From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f175.google.com (mail-wi0-f175.google.com [209.85.212.175]) by dpdk.org (Postfix) with ESMTP id 610A558D6 for ; Sat, 21 Dec 2013 00:36:40 +0100 (CET) Received: by mail-wi0-f175.google.com with SMTP id hi5so9082910wib.2 for ; Fri, 20 Dec 2013 15:37:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=d3LR5Tt6h3/pl9qYzwa0ZRP9UuVUy4xqvM8wN3GKHC8=; b=gGCRqR+mMSK1FbsY7pEkbkGpJsiPGmEyLDibvvCv2K8d3N5nTXhnpgb476zP3OtDOM EK5cjVXukW1KV4/yPbO8H1P5aprFu/g0dEmizj1QqA/0q7Q673Tc6/KHHTMMYzpITOb3 gvG1EMW39/o6RbjPbhspFWcdypmbsaL6CoLIhNbj00vpvQenIDZBRBKE9lK8bLW2xj4k mqby4V9IkeKlSB8wO1qAMtU4NduvfOUPpDQrKkXUyVEQO+QdKmVz837RAVJH0IPNUFul kDvol+W9eWckA3LemrebQPnK8woYpECXhVKE70NLuuuALSWihq0RhWbNfpjSguf3iXjZ wxxg== X-Gm-Message-State: ALoCoQkCQh+PjCr8fLsXP+1UPYervL/DKZmdoUXVQ2w0mJjolN1A6Zgcgchkgciufc0ztIc1WQqg X-Received: by 10.194.57.243 with SMTP id l19mr282051wjq.54.1387582667174; Fri, 20 Dec 2013 15:37:47 -0800 (PST) Received: from 6wind.com (6wind.net2.nerim.net. [213.41.180.237]) by mx.google.com with ESMTPSA id j3sm17065353wiy.3.2013.12.20.15.37.44 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 20 Dec 2013 15:37:46 -0800 (PST) Received: by 6wind.com (sSMTP sendmail emulation); Sat, 21 Dec 2013 00:37:42 +0100 From: Thomas Monjalon To: dev@dpdk.org Date: Sat, 21 Dec 2013 00:37:36 +0100 Message-Id: <1387582656-1892-1-git-send-email-thomas.monjalon@6wind.com> X-Mailer: git-send-email 1.7.10.4 Subject: [dpdk-dev] [PATCH] spinlock: fix atomic and out of order execution X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Dec 2013 23:36:40 -0000 From: Damien Millescamps Add lock prefix before xchg instructions in order to be atomic and flush speculative values to ensure effective execution order (as an acquire barrier). MPLOCKED is a "lock" in multicore case. Signed-off-by: Damien Millescamps Signed-off-by: Thomas Monjalon --- lib/librte_eal/common/include/rte_spinlock.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/librte_eal/common/include/rte_spinlock.h b/lib/librte_eal/common/include/rte_spinlock.h index f7a245a..8edb971 100644 --- a/lib/librte_eal/common/include/rte_spinlock.h +++ b/lib/librte_eal/common/include/rte_spinlock.h @@ -51,6 +51,7 @@ extern "C" { #endif +#include #include #ifdef RTE_FORCE_INTRINSICS #include @@ -93,7 +94,7 @@ rte_spinlock_lock(rte_spinlock_t *sl) int lock_val = 1; asm volatile ( "1:\n" - "xchg %[locked], %[lv]\n" + MPLOCKED "xchg %[locked], %[lv]\n" "test %[lv], %[lv]\n" "jz 3f\n" "2:\n" @@ -124,7 +125,7 @@ rte_spinlock_unlock (rte_spinlock_t *sl) #ifndef RTE_FORCE_INTRINSICS int unlock_val = 0; asm volatile ( - "xchg %[locked], %[ulv]\n" + MPLOCKED "xchg %[locked], %[ulv]\n" : [locked] "=m" (sl->locked), [ulv] "=q" (unlock_val) : "[ulv]" (unlock_val) : "memory"); @@ -148,7 +149,7 @@ rte_spinlock_trylock (rte_spinlock_t *sl) int lockval = 1; asm volatile ( - "xchg %[locked], %[lockval]" + MPLOCKED "xchg %[locked], %[lockval]" : [locked] "=m" (sl->locked), [lockval] "=q" (lockval) : "[lockval]" (lockval) : "memory"); -- 1.7.10.4