From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-we0-f174.google.com (mail-we0-f174.google.com [74.125.82.174]) by dpdk.org (Postfix) with ESMTP id A0CF35907 for ; Wed, 19 Feb 2014 13:06:23 +0100 (CET) Received: by mail-we0-f174.google.com with SMTP id w61so247028wes.19 for ; Wed, 19 Feb 2014 04:07:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:resent-from:resent-to:resent-date :resent-message-id:delivered-to:from:to:subject:date:message-id :in-reply-to:references; bh=YmJK9J85YwL5u77OdcJ+l1uQx7sd6e5cWBRL8sUtulo=; b=dlZ3MvQUsK/XPspnYouua6snDx+TO8hwQGiHYYi1hOYO54NFlO9cQlVwP3PJnxx3MI pHXqNm6OpbjczixvEp5++pqNIVF4ySpxjzDEdolQssAyKVLQ2Gb+vFhPb2QF7/I9QHmT R/1fljwCo6UXTKiJv0KhcaoNMGimK9jo8Up65JwaztKyFpUZwd5aLPDSvE4gduC3q0g8 KAM/urPZb2IitHVpBTq3Bshtxw/x6E4d3glNIIrKwy74neWi4vAY7Pu4o1prXW3YiTW9 WFpabQZTeSByovE5vocto4xf+/98S9nRw1LvJ/y51zUnt3jLr6U4qjvzJqCvhmxNnEZc LSBg== X-Gm-Message-State: ALoCoQnPO8Gx6ey1npc7J8LQPO0p69DYlzUqAcUpEaum7oeNbvn2UXHCXPHfCUpqK6f78tGZE0EB X-Received: by 10.194.240.41 with SMTP id vx9mr1498386wjc.70.1392811668059; Wed, 19 Feb 2014 04:07:48 -0800 (PST) Received: from angus.localnet (6wind.net2.nerim.net. [213.41.180.237]) by mx.google.com with ESMTPSA id bj3sm53402675wjb.14.2014.02.19.04.07.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Feb 2014 04:07:47 -0800 (PST) Resent-From: Thomas Monjalon Resent-To: dev@dpdk.org Resent-Date: Wed, 19 Feb 2014 13:07:45 +0100 Resent-Message-ID: <201402191307.45458.didier.pallard@6wind.com> Received: by 10.76.82.162 with SMTP id j2csp5775oay; Wed, 19 Feb 2014 03:39:30 -0800 (PST) X-Received: by 10.194.236.9 with SMTP id uq9mr27568326wjc.31.1392809970048; Wed, 19 Feb 2014 03:39:30 -0800 (PST) Received: from mail-we0-f180.google.com (mail-we0-f180.google.com [74.125.82.180]) by mx.google.com with ESMTPS id fk8si354477wib.80.2014.02.19.03.39.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 19 Feb 2014 03:39:29 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.180 is neither permitted nor denied by best guess record for domain of didier.pallard@6wind.com) client-ip=74.125.82.180; Received: by mail-we0-f180.google.com with SMTP id u57so218503wes.25 for ; Wed, 19 Feb 2014 03:39:29 -0800 (PST) X-Received: by 10.194.2.168 with SMTP id 8mr27677461wjv.8.1392809969348; Wed, 19 Feb 2014 03:39:29 -0800 (PST) Received: from pala.dev.6wind.com (6wind.net2.nerim.net. [213.41.180.237]) by mx.google.com with ESMTPSA id bj3sm53208108wjb.14.2014.02.19.03.39.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Feb 2014 03:39:28 -0800 (PST) From: Didier Pallard To: thomas.monjalon@6wind.com Date: Wed, 19 Feb 2014 12:39:05 +0100 Message-Id: <1392809945-28025-1-git-send-email-didier.pallard@6wind.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390562134-24720-1-git-send-email-didier.pallard@6wind.com> References: <1390562134-24720-1-git-send-email-didier.pallard@6wind.com> X-Length: 4992 X-UID: 25244 Subject: [dpdk-dev] [PATCH v2] timer: add lfence before TSC read X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Feb 2014 12:06:23 -0000 According to Intel Developer's Manual: "The RDTSC instruction is not a serializing instruction. It does not necessarily wait until all previous instructions have been executed before reading the counter. Simi- larly, subsequent instructions may begin execution before the read operation is performed. If software requires RDTSC to be executed only after all previous instruc- tions have completed locally, it can either use RDTSCP (if the processor supports that instruction) or execute the sequence LFENCE;RDTSC." So add a rte_rdtsc_precise function that do a lfence instruction before rdtsc to synchronize read operations and ensure that the TSC read is done at the expected place. Signed-off-by: Didier Pallard --- Introduce a rte_rdtsc_precise function that adds lfence before reading tsc counter. lib/librte_eal/common/include/rte_cycles.h | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/lib/librte_eal/common/include/rte_cycles.h b/lib/librte_eal/common/include/rte_cycles.h index cc6fe71..662f62d 100644 --- a/lib/librte_eal/common/include/rte_cycles.h +++ b/lib/librte_eal/common/include/rte_cycles.h @@ -128,6 +128,43 @@ rte_rdtsc(void) } /** + * Read the TSC register precisely where function is called. + * + * @return + * The TSC for this lcore. + */ +static inline uint64_t +rte_rdtsc_precise(void) +{ + union { + uint64_t tsc_64; + struct { + uint32_t lo_32; + uint32_t hi_32; + }; + } tsc; + + /* serialize previous load instructions in pipe */ + asm volatile("lfence"); + +#ifdef RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT + if (unlikely(rte_cycles_vmware_tsc_map)) { + /* ecx = 0x10000 corresponds to the physical TSC for VMware */ + asm volatile("rdpmc" : + "=a" (tsc.lo_32), + "=d" (tsc.hi_32) : + "c"(0x10000)); + return tsc.tsc_64; + } +#endif + + asm volatile("rdtsc" : + "=a" (tsc.lo_32), + "=d" (tsc.hi_32)); + return tsc.tsc_64; +} + +/** * Get the measured frequency of the RDTSC counter * * @return -- 1.7.10.4