From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 519D230D for ; Thu, 5 Jun 2014 07:11:52 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 04 Jun 2014 22:12:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.98,978,1392192000"; d="scan'208";a="550032135" Received: from shilc102.sh.intel.com ([10.239.39.44]) by fmsmga002.fm.intel.com with ESMTP; 04 Jun 2014 22:12:02 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shilc102.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s555BvOR025198; Thu, 5 Jun 2014 13:11:59 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s555BrrK024070; Thu, 5 Jun 2014 13:11:55 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s555Bra5024066; Thu, 5 Jun 2014 13:11:53 +0800 From: Helin Zhang To: dev@dpdk.org Date: Thu, 5 Jun 2014 13:09:09 +0800 Message-Id: <1401944951-23783-26-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1401944951-23783-1-git-send-email-helin.zhang@intel.com> References: <1401944951-23783-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 25/27] igb_uio: add sys files to read/write specific bits in pci config space X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jun 2014 05:11:55 -0000 Enabling 'Extended Tag' and resetting 'Max Read Request Size' in PCI config space have big impacts to i40e performance. They cannot be changed on some BIOS implementations, though can on others. Two sys files of 'extended_tag' and 'max_read_request_size' are added to support changing them by 'echo' in user space. Signed-off-by: Helin Zhang Signed-off-by: Jing Chen Acked-by: Cunming Liang Acked-by: Jijiang Liu Acked-by: Jingjing Wu Tested-by: Waterman Cao --- lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 105 ++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c index 79fe97d..55e801d 100644 --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c @@ -47,6 +47,15 @@ #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 #endif +#ifdef RTE_PCI_CONFIG +#define PCI_SYS_FILE_BUF_SIZE 10 +#define PCI_DEV_CAP_REG 0xA4 +#define PCI_DEV_CTRL_REG 0xA8 +#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 +#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 +#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) +#endif + #define IGBUIO_NUM_MSI_VECTORS 1 /* interrupt mode */ @@ -151,9 +160,105 @@ store_max_vfs(struct device *dev, struct device_attribute *attr, return err ? err : count; } +#ifdef RTE_PCI_CONFIG +static ssize_t +show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev); + uint32_t val = 0; + + pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val); + if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */ + return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid"); + + val = 0; + pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, + PCI_DEV_CTRL_REG, &val); + + return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", + (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off"); +} + +static ssize_t +store_extended_tag(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev); + uint32_t val = 0, enable; + + if (strncmp(buf, "on", 2) == 0) + enable = 1; + else if (strncmp(buf, "off", 3) == 0) + enable = 0; + else + return -EINVAL; + + pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, + PCI_DEV_CAP_REG, &val); + if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */ + return -EPERM; + + val = 0; + pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn, + PCI_DEV_CTRL_REG, &val); + if (enable) + val |= PCI_DEV_CTRL_EXT_TAG_MASK; + else + val &= ~PCI_DEV_CTRL_EXT_TAG_MASK; + pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn, + PCI_DEV_CTRL_REG, val); + + return count; +} + +static ssize_t +show_max_read_request_size(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev); + int val = pcie_get_readrq(pci_dev); + + return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val); +} + +static ssize_t +store_max_read_request_size(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev); + unsigned long size = 0; + int ret; + + if (strict_strtoul(buf, 0, &size) != 0) + return -EINVAL; + + ret = pcie_set_readrq(pci_dev, (int)size); + if (ret < 0) + return ret; + + return count; +} +#endif + static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs); +#ifdef RTE_PCI_CONFIG +static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag, \ + store_extended_tag); +static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR, \ + show_max_read_request_size, store_max_read_request_size); +#endif + static struct attribute *dev_attrs[] = { &dev_attr_max_vfs.attr, +#ifdef RTE_PCI_CONFIG + &dev_attr_extended_tag.attr, + &dev_attr_max_read_request_size.attr, +#endif NULL, }; -- 1.8.1.4