From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [119.145.14.65]) by dpdk.org (Postfix) with ESMTP id 601B8AFCD for ; Wed, 18 Jun 2014 06:19:16 +0200 (CEST) Received: from 172.24.2.119 (EHLO szxeml205-edg.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BVG53491; Wed, 18 Jun 2014 12:19:28 +0800 (CST) Received: from SZXEML463-HUB.china.huawei.com (10.82.67.206) by szxeml205-edg.china.huawei.com (172.24.2.58) with Microsoft SMTP Server (TLS) id 14.3.158.1; Wed, 18 Jun 2014 12:19:24 +0800 Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml463-hub.china.huawei.com (10.82.67.206) with Microsoft SMTP Server id 14.3.158.1; Wed, 18 Jun 2014 12:19:22 +0800 From: Shannon Zhao To: Date: Wed, 18 Jun 2014 12:18:15 +0800 Message-ID: <1403065095-11092-1-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <2140757.fj3Ic02JMu@xps13> References: <2140757.fj3Ic02JMu@xps13> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v3] cpu_layout.py: adjust output format to align X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jun 2014 04:19:18 -0000 Bug: when "core id" is greater than 9, the cpu_layout.py output doesn't align. Socket 0 Socket 1 --------- --------- Core 9 [4, 16] [10, 22] Core 10 [5, 17] [11, 23] Solution: adjust output format to align based on the maximum length of the "core id" and "processor" Socket 0 Socket 1 -------- -------- Core 9 [4, 16] [10, 22] Core 10 [5, 17] [11, 23] Signed-off-by: Shannon Zhao --- tools/cpu_layout.py | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tools/cpu_layout.py b/tools/cpu_layout.py index 623fad9..20a409d 100755 --- a/tools/cpu_layout.py +++ b/tools/cpu_layout.py @@ -75,15 +75,21 @@ print "cores = ",cores print "sockets = ", sockets print "" +max_processor_len = len(str(len(cores) * len(sockets) * 2 - 1)) +max_core_map_len = max_processor_len * 2 + len('[, ]') + len('Socket ') +max_core_id_len = len(str(max(cores))) + +print " ".ljust(max_core_id_len + len('Core ')), for s in sockets: - print "\tSocket %s" % s, + print "Socket %s" % str(s).ljust(max_core_map_len - len('Socket ')), print "" +print " ".ljust(max_core_id_len + len('Core ')), for s in sockets: - print "\t---------", + print "--------".ljust(max_core_map_len), print "" for c in cores: - print "Core %s" % c, - for s in sockets: - print "\t", core_map[(s,c)], - print "\n" + print "Core %s" % str(c).ljust(max_core_id_len), + for s in sockets: + print str(core_map[(s,c)]).ljust(max_core_map_len), + print "\n" -- 1.9.0.msysgit.0