From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id AA664B381 for ; Mon, 25 Aug 2014 04:06:09 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 24 Aug 2014 19:01:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,393,1406617200"; d="scan'208";a="581150010" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 24 Aug 2014 19:09:43 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s7P29fWd025029; Mon, 25 Aug 2014 10:09:41 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s7P29caI010451; Mon, 25 Aug 2014 10:09:40 +0800 Received: (from couyang@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s7P29cjB010447; Mon, 25 Aug 2014 10:09:38 +0800 From: Ouyang Changchun To: dev@dpdk.org Date: Mon, 25 Aug 2014 10:09:28 +0800 Message-Id: <1408932572-10343-2-git-send-email-changchun.ouyang@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1408932572-10343-1-git-send-email-changchun.ouyang@intel.com> References: <1408932572-10343-1-git-send-email-changchun.ouyang@intel.com> Subject: [dpdk-dev] [PATCH 1/5] ethdev: Add new config field to config VMDQ offload register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Aug 2014 02:06:10 -0000 This patch adds new field of rx mode in VMDQ config; and set the register PFVML2FLT for IXGBE PMD, this makes VMDQ receive multicast and broadcast packets. Signed-off-by: Changchun Ouyang Acked-by: Huawei Xie Acked-by: Cunming Liang --- lib/librte_ether/rte_ethdev.h | 1 + lib/librte_pmd_ixgbe/ixgbe_rxtx.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h index 50df654..f44dd2d 100644 --- a/lib/librte_ether/rte_ethdev.h +++ b/lib/librte_ether/rte_ethdev.h @@ -575,6 +575,7 @@ struct rte_eth_vmdq_rx_conf { uint8_t default_pool; /**< The default pool, if applicable */ uint8_t enable_loop_back; /**< Enable VT loop back */ uint8_t nb_pool_maps; /**< We can have up to 64 filters/mappings */ + uint32_t rx_mode; /**< RX mode for vmdq */ struct { uint16_t vlan_id; /**< The vlan id of the received frame */ uint64_t pools; /**< Bitmask of pools for packet rx */ diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c index dfc2076..9efdbfb 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c +++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c @@ -3084,6 +3084,7 @@ ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev) struct ixgbe_hw *hw; enum rte_eth_nb_pools num_pools; uint32_t mrqc, vt_ctl, vlanctrl; + uint32_t vmolr = 0; int i; PMD_INIT_FUNC_TRACE(); @@ -3106,6 +3107,21 @@ ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev) IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl); + for (i = 0; i < (int)num_pools; i++) { + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG) + vmolr |= IXGBE_VMOLR_AUPE; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC) + vmolr |= IXGBE_VMOLR_ROMPE; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC) + vmolr |= IXGBE_VMOLR_ROPE; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST) + vmolr |= IXGBE_VMOLR_BAM; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST) + vmolr |= IXGBE_VMOLR_MPE; + + IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr); + } + /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */ -- 1.8.4.2