From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by dpdk.org (Postfix) with ESMTP id 5D560B378 for ; Tue, 26 Aug 2014 09:27:57 +0200 (CEST) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 26 Aug 2014 00:31:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,402,1406617200"; d="scan'208";a="472638979" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by azsmga001.ch.intel.com with ESMTP; 26 Aug 2014 00:31:54 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s7Q7VrkE027288; Tue, 26 Aug 2014 15:31:53 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s7Q7VneZ021848; Tue, 26 Aug 2014 15:31:51 +0800 Received: (from jijiangl@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s7Q7VnXE021844; Tue, 26 Aug 2014 15:31:49 +0800 From: Jijiang Liu To: dev@dpdk.org Date: Tue, 26 Aug 2014 15:31:33 +0800 Message-Id: <1409038294-21693-7-git-send-email-jijiang.liu@intel.com> X-Mailer: git-send-email 1.7.0.7 In-Reply-To: <1409038294-21693-1-git-send-email-jijiang.liu@intel.com> References: <1409038294-21693-1-git-send-email-jijiang.liu@intel.com> Subject: [dpdk-dev] [PATCH v2 6/7]i40e:support VxLAN Tx checksum offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Aug 2014 07:27:58 -0000 Support VxLAN Tx checksum offload, which include - outer L3(IP) checksum offload - inner L3(IP) checksum offload - inner L4(UDP, TCP and SCTP) checksum offload Signed-off-by: jijiangl --- lib/librte_mbuf/rte_mbuf.h | 4 +++ lib/librte_pmd_i40e/i40e_rxtx.c | 58 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 59 insertions(+), 3 deletions(-) diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h index 2735f37..212ac3a 100644 --- a/lib/librte_mbuf/rte_mbuf.h +++ b/lib/librte_mbuf/rte_mbuf.h @@ -97,6 +97,8 @@ struct rte_ctrlmbuf { #define PKT_RX_IEEE1588_PTP 0x0200 /**< RX IEEE1588 L2 Ethernet PT Packet. */ #define PKT_RX_IEEE1588_TMST 0x0400 /**< RX IEEE1588 L2/L4 timestamped packet.*/ +#define PKT_TX_VXLAN_CKSUM 0x0001 /**< Checksum of TX VxLAN pkt. computed by NIC.. */ +#define PKT_TX_IVLAN_PKT 0x0002 /**< TX packet is VxLAN packet with an inner VLAN. */ #define PKT_TX_VLAN_PKT 0x0800 /**< TX packet is a 802.1q VLAN packet. */ #define PKT_TX_IP_CKSUM 0x1000 /**< IP cksum of TX pkt. computed by NIC. */ #define PKT_TX_IPV4_CSUM 0x1000 /**< Alias of PKT_TX_IP_CKSUM. */ @@ -594,6 +596,7 @@ static inline void rte_pktmbuf_reset(struct rte_mbuf *m) m->pkt.in_port = 0xff; m->ol_flags = 0; + m->reserved = 0; buf_ofs = (RTE_PKTMBUF_HEADROOM <= m->buf_len) ? RTE_PKTMBUF_HEADROOM : m->buf_len; m->pkt.data = (char*) m->buf_addr + buf_ofs; @@ -658,6 +661,7 @@ static inline void rte_pktmbuf_attach(struct rte_mbuf *mi, struct rte_mbuf *md) mi->pkt.pkt_len = mi->pkt.data_len; mi->pkt.nb_segs = 1; mi->ol_flags = md->ol_flags; + mi->reserved = md->reserved; __rte_mbuf_sanity_check(mi, RTE_MBUF_PKT, 1); __rte_mbuf_sanity_check(md, RTE_MBUF_PKT, 0); diff --git a/lib/librte_pmd_i40e/i40e_rxtx.c b/lib/librte_pmd_i40e/i40e_rxtx.c index f153844..a382d74 100644 --- a/lib/librte_pmd_i40e/i40e_rxtx.c +++ b/lib/librte_pmd_i40e/i40e_rxtx.c @@ -412,12 +412,16 @@ i40e_rxd_ptype_to_pkt_flags(uint64_t qword) return ip_ptype_map[ptype]; } +#define L4TUN_LEN (sizeof(struct udp_hdr) + sizeof(struct vxlan_hdr)\ + + sizeof(struct ether_hdr)) static inline void i40e_txd_enable_checksum(uint32_t ol_flags, uint32_t *td_cmd, uint32_t *td_offset, uint8_t l2_len, - uint8_t l3_len) + uint8_t l3_len, + uint8_t inner_l3_len, + uint32_t *cd_tunneling) { if (!l2_len) { PMD_DRV_LOG(DEBUG, "L2 length set to 0\n"); @@ -430,6 +434,31 @@ i40e_txd_enable_checksum(uint32_t ol_flags, return; } + /* VxLAN packet TX checksum offload */ + if (unlikely(ol_flags & PKT_TX_VXLAN_CKSUM)) { + uint8_t l4tun_len; + + /* packet with inner VLAN */ + if (ol_flags & PKT_TX_IVLAN_PKT) + l4tun_len = L4TUN_LEN + sizeof(struct vlan_hdr); + else + l4tun_len = L4TUN_LEN; + + if (ol_flags & PKT_TX_IPV4_CSUM) + *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4; + else if (ol_flags & PKT_TX_IPV6) + *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6; + + /* Now set the ctx descriptor fields */ + *cd_tunneling |= (l3_len >> 2) << + I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT | + I40E_TXD_CTX_UDP_TUNNELING | + (l4tun_len >> 1) << + I40E_TXD_CTX_QW0_NATLEN_SHIFT; + + l3_len = inner_l3_len; + } + /* Enable L3 checksum offloads */ if (ol_flags & PKT_TX_IPV4_CSUM) { *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM; @@ -611,6 +640,12 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) I40E_RXD_QW1_STATUS_SHIFT; pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len; + + /* reserved is used to store packet type for RX side */ + mb->reserved = (uint8_t)((qword1 & + I40E_RXD_QW1_PTYPE_MASK) >> + I40E_RXD_QW1_PTYPE_SHIFT); + mb->pkt.data_len = pkt_len; mb->pkt.pkt_len = pkt_len; mb->pkt.vlan_macip.f.vlan_tci = rx_status & @@ -857,6 +892,8 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) pkt_flags = i40e_rxd_status_to_pkt_flags(qword1); pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1); pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1); + rxm->reserved = (uint8_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >> + I40E_RXD_QW1_PTYPE_SHIFT); rxm->ol_flags = pkt_flags; if (pkt_flags & PKT_RX_RSS_HASH) rxm->pkt.hash.rss = @@ -1010,6 +1047,9 @@ i40e_recv_scattered_pkts(void *rx_queue, pkt_flags = i40e_rxd_status_to_pkt_flags(qword1); pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1); pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1); + first_seg->reserved = (uint8_t)((qword1 & + I40E_RXD_QW1_PTYPE_MASK) >> + I40E_RXD_QW1_PTYPE_SHIFT); first_seg->ol_flags = pkt_flags; if (pkt_flags & PKT_RX_RSS_HASH) rxm->pkt.hash.rss = @@ -1052,6 +1092,9 @@ i40e_calc_context_desc(uint16_t flags) { uint16_t mask = 0; + if (flags | PKT_TX_VXLAN_CKSUM) + mask |= PKT_TX_VXLAN_CKSUM; + #ifdef RTE_LIBRTE_IEEE1588 mask |= PKT_TX_IEEE1588_TMST; #endif @@ -1071,6 +1114,7 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) volatile struct i40e_tx_desc *txr; struct rte_mbuf *tx_pkt; struct rte_mbuf *m_seg; + uint32_t cd_tunneling_params; uint16_t tx_id; uint16_t nb_tx; uint32_t td_cmd; @@ -1080,6 +1124,7 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) uint16_t ol_flags; uint8_t l2_len; uint8_t l3_len; + uint8_t inner_l3_len; uint16_t nb_used; uint16_t nb_ctx; uint16_t tx_last; @@ -1109,6 +1154,12 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) l2_len = tx_pkt->pkt.vlan_macip.f.l2_len; l3_len = tx_pkt->pkt.vlan_macip.f.l3_len; + /** + * the reserved in mbuf is used to store innel L3 + * header length. + */ + inner_l3_len = tx_pkt->reserved; + /* Calculate the number of context descriptors needed. */ nb_ctx = i40e_calc_context_desc(ol_flags); @@ -1155,15 +1206,16 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) td_cmd |= I40E_TX_DESC_CMD_ICRC; /* Enable checksum offloading */ + cd_tunneling_params = 0; i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset, - l2_len, l3_len); + l2_len, l3_len, inner_l3_len, + &cd_tunneling_params); if (unlikely(nb_ctx)) { /* Setup TX context descriptor if required */ volatile struct i40e_tx_context_desc *ctx_txd = (volatile struct i40e_tx_context_desc *)\ &txr[tx_id]; - uint32_t cd_tunneling_params = 0; uint16_t cd_l2tag2 = 0; uint64_t cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; -- 1.7.7.6