From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id C80FEB3D1 for ; Thu, 25 Sep 2014 10:35:11 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 25 Sep 2014 01:35:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,595,1406617200"; d="scan'208";a="578729312" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 25 Sep 2014 01:40:57 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s8P8eu4V002330; Thu, 25 Sep 2014 16:40:56 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s8P8erDB000859; Thu, 25 Sep 2014 16:40:55 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8P8erKe000855; Thu, 25 Sep 2014 16:40:53 +0800 From: Helin Zhang To: dev@dpdk.org Date: Thu, 25 Sep 2014 16:40:25 +0800 Message-Id: <1411634427-746-12-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1411634427-746-1-git-send-email-helin.zhang@intel.com> References: <1411634427-746-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 11/13] i40e: rework of updating/querying reta X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Sep 2014 08:35:12 -0000 As ethdev has been changed to support multiple sizes of reta, updating/querying reta should be reworked to support that change. v2 changes: * Put rework of updating/querying i40e reta to a single patch. Signed-off-by: Helin Zhang Reviewed-by: Jijiang Liu Reviewed-by: Cunming Liang Reviewed-by: Jingjing Wu --- lib/librte_pmd_i40e/i40e_ethdev.c | 93 ++++++++++++++++++++++----------------- lib/librte_pmd_i40e/i40e_ethdev.h | 12 +++++ 2 files changed, 65 insertions(+), 40 deletions(-) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index 9fe3f7a..6338e1b 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -72,14 +72,6 @@ /* Maximun number of VSI */ #define I40E_MAX_NUM_VSIS (384UL) -/* Bit shift and mask */ -#define I40E_16_BIT_SHIFT 16 -#define I40E_16_BIT_MASK 0xFFFF -#define I40E_32_BIT_SHIFT 32 -#define I40E_32_BIT_MASK 0xFFFFFFFF -#define I40E_48_BIT_SHIFT 48 -#define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL - /* Default queue interrupt throttling time in microseconds*/ #define I40E_ITR_INDEX_DEFAULT 0 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ @@ -160,9 +152,11 @@ static void i40e_macaddr_add(struct rte_eth_dev *dev, uint32_t pool); static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index); static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf); + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf); + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); static int i40e_get_cap(struct i40e_hw *hw); static int i40e_pf_parameter_init(struct rte_eth_dev *dev); @@ -1590,32 +1584,41 @@ i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index) static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf) + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) { + struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t lut, l; - uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2; - - for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) { - if (i < max) - mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF); - else - mask = (uint8_t)((reta_conf->mask_hi >> - (i - max)) & 0xF); + uint16_t i, j, lut_size = pf->hash_lut_size; + uint16_t idx, shift; + uint8_t mask; + + if (reta_size != lut_size || + reta_size > ETH_RSS_RETA_SIZE_512) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number hardware can supported " + "(%d)\n", reta_size, lut_size); + return -EINVAL; + } + for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) { + idx = i / RTE_BIT_WIDTH_64; + shift = i % RTE_BIT_WIDTH_64; + mask = (uint8_t)((reta_conf[idx].mask >> shift) & + I40E_4_BIT_MASK); if (!mask) continue; - - if (mask == 0xF) + if (mask == I40E_4_BIT_MASK) l = 0; else l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2)); - - for (j = 0, lut = 0; j < 4; j++) { + for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) { if (mask & (0x1 << j)) - lut |= reta_conf->reta[i + j] << (8 * j); + lut |= reta_conf[idx].reta[shift + j] << + (CHAR_BIT * j); else - lut |= l & (0xFF << (8 * j)); + lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j)); } I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut); } @@ -1625,27 +1628,37 @@ i40e_dev_rss_reta_update(struct rte_eth_dev *dev, static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev, - struct rte_eth_rss_reta *reta_conf) + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) { + struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t lut; - uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2; - - for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) { - if (i < max) - mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF); - else - mask = (uint8_t)((reta_conf->mask_hi >> - (i - max)) & 0xF); + uint16_t i, j, lut_size = pf->hash_lut_size; + uint16_t idx, shift; + uint8_t mask; + + if (reta_size != lut_size || + reta_size > ETH_RSS_RETA_SIZE_512) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number hardware can supported " + "(%d)\n", reta_size, lut_size); + return -EINVAL; + } + for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) { + idx = i / RTE_BIT_WIDTH_64; + shift = i % RTE_BIT_WIDTH_64; + mask = (uint8_t)((reta_conf[idx].mask >> shift) & + I40E_4_BIT_MASK); if (!mask) continue; lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2)); - for (j = 0; j < 4; j++) { + for (j = 0; j < I40E_4_BIT_WIDTH; j++) { if (mask & (0x1 << j)) - reta_conf->reta[i + j] = - (uint8_t)((lut >> (8 * j)) & 0xFF); + reta_conf[idx].reta[shift] = ((lut >> + (CHAR_BIT * j)) & I40E_8_BIT_MASK); } } @@ -3225,7 +3238,7 @@ i40e_stat_update_32(struct i40e_hw *hw, *stat = (uint64_t)(new_data - *offset); else *stat = (uint64_t)((new_data + - ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset); + ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset); } static void @@ -3240,7 +3253,7 @@ i40e_stat_update_48(struct i40e_hw *hw, new_data = (uint64_t)I40E_READ_REG(hw, loreg); new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & - I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT; + I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; if (!offset_loaded) *offset = new_data; @@ -3249,7 +3262,7 @@ i40e_stat_update_48(struct i40e_hw *hw, *stat = new_data - *offset; else *stat = (uint64_t)((new_data + - ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset); + ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset); *stat &= I40E_48_BIT_MASK; } diff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h index a1a2e75..336e936 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.h +++ b/lib/librte_pmd_i40e/i40e_ethdev.h @@ -52,6 +52,18 @@ /* Default TC traffic in case DCB is not enabled */ #define I40E_DEFAULT_TCMAP 0x1 +/* Bit shift and mask */ +#define I40E_4_BIT_WIDTH (CHAR_BIT / 2) +#define I40E_4_BIT_MASK ((1 << I40E_4_BIT_WIDTH) - 1) +#define I40E_8_BIT_WIDTH CHAR_BIT +#define I40E_8_BIT_MASK ((1 << I40E_8_BIT_WIDTH) - 1) +#define I40E_16_BIT_WIDTH (CHAR_BIT * 2) +#define I40E_16_BIT_MASK ((1 << I40E_16_BIT_WIDTH) - 1) +#define I40E_32_BIT_WIDTH (CHAR_BIT * 4) +#define I40E_32_BIT_MASK ((1 << I40E_32_BIT_WIDTH) - 1) +#define I40E_48_BIT_WIDTH (CHAR_BIT * 6) +#define I40E_48_BIT_MASK ((1ULL << I40E_48_BIT_WIDTH) - 1) + /* i40e flags */ #define I40E_FLAG_RSS (1ULL << 0) #define I40E_FLAG_DCB (1ULL << 1) -- 1.8.1.4