From: Ouyang Changchun <changchun.ouyang@intel.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH 12/18] ixgbe: Use hardware MAC type for I2C control
Date: Thu, 25 Sep 2014 22:18:58 +0800 [thread overview]
Message-ID: <1411654744-9460-13-git-send-email-changchun.ouyang@intel.com> (raw)
In-Reply-To: <1411654744-9460-1-git-send-email-changchun.ouyang@intel.com>
This patch uses hardware MAC type to determine I2C control, clock
in/out, and data in/out in IXGBE base code.
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
---
lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c | 58 ++++++++++++++++-----------------
lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 12 ++++---
2 files changed, 37 insertions(+), 33 deletions(-)
diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
index 462e884..2e8fe93 100644
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
@@ -2075,7 +2075,7 @@ write_byte_out:
**/
STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
DEBUGFUNC("ixgbe_i2c_start");
@@ -2106,7 +2106,7 @@ STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
**/
STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
DEBUGFUNC("ixgbe_i2c_stop");
@@ -2170,9 +2170,9 @@ STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
}
/* Release SDA line (set high) */
- i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- i2cctl |= IXGBE_I2C_DATA_OUT;
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
+ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
IXGBE_WRITE_FLUSH(hw);
return status;
@@ -2188,7 +2188,7 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u32 i = 0;
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
u32 timeout = 10;
bool ack = 1;
@@ -2203,17 +2203,16 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
/* Poll for ACK. Note that ACK in I2C spec is
* transition from 1 to 0 */
for (i = 0; i < timeout; i++) {
- i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- ack = ixgbe_get_i2c_data(&i2cctl);
+ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ ack = ixgbe_get_i2c_data(hw, &i2cctl);
usec_delay(1);
if (!ack)
break;
}
- if (ack == 1) {
- ERROR_REPORT1(IXGBE_ERROR_POLLING,
- "I2C ack was not received.\n");
+ if (ack) {
+ DEBUGOUT("I2C ack was not received.\n");
status = IXGBE_ERR_I2C;
}
@@ -2234,7 +2233,7 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
**/
STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
DEBUGFUNC("ixgbe_clock_in_i2c_bit");
@@ -2243,8 +2242,8 @@ STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
/* Minimum high period of clock is 4us */
usec_delay(IXGBE_I2C_T_HIGH);
- i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- *data = ixgbe_get_i2c_data(&i2cctl);
+ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ *data = ixgbe_get_i2c_data(hw, &i2cctl);
ixgbe_lower_i2c_clk(hw, &i2cctl);
@@ -2264,7 +2263,7 @@ STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
{
s32 status;
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
DEBUGFUNC("ixgbe_clock_out_i2c_bit");
@@ -2306,15 +2305,15 @@ STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
DEBUGFUNC("ixgbe_raise_i2c_clk");
for (i = 0; i < timeout; i++) {
- *i2cctl |= IXGBE_I2C_CLK_OUT;
+ *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
IXGBE_WRITE_FLUSH(hw);
/* SCL rise time (1000ns) */
usec_delay(IXGBE_I2C_T_RISE);
- i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- if (i2cctl_r & IXGBE_I2C_CLK_IN)
+ i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
break;
}
}
@@ -2331,9 +2330,9 @@ STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
DEBUGFUNC("ixgbe_lower_i2c_clk");
- *i2cctl &= ~IXGBE_I2C_CLK_OUT;
+ *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
IXGBE_WRITE_FLUSH(hw);
/* SCL fall time (300ns) */
@@ -2355,19 +2354,19 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
DEBUGFUNC("ixgbe_set_i2c_data");
if (data)
- *i2cctl |= IXGBE_I2C_DATA_OUT;
+ *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
else
- *i2cctl &= ~IXGBE_I2C_DATA_OUT;
+ *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
- IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
IXGBE_WRITE_FLUSH(hw);
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
/* Verify data was set correctly */
- *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
- if (data != ixgbe_get_i2c_data(i2cctl)) {
+ *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
status = IXGBE_ERR_I2C;
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
"Error - I2C data was not set to %X.\n",
@@ -2384,13 +2383,14 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
*
* Returns the I2C data bit value
**/
-STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
+STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
{
bool data;
+ UNREFERENCED_1PARAMETER(hw);
DEBUGFUNC("ixgbe_get_i2c_data");
- if (*i2cctl & IXGBE_I2C_DATA_IN)
+ if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
data = 1;
else
data = 0;
@@ -2407,7 +2407,7 @@ STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
**/
void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+ u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
u32 i;
DEBUGFUNC("ixgbe_i2c_bus_clear");
diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index bfe1235..48f25d1 100644
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -171,10 +171,14 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_VPDDIAG1 0x10208
/* I2CCTL Bit Masks */
-#define IXGBE_I2C_CLK_IN 0x00000001
-#define IXGBE_I2C_CLK_OUT 0x00000002
-#define IXGBE_I2C_DATA_IN 0x00000004
-#define IXGBE_I2C_DATA_OUT 0x00000008
+#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+ 0x00004000 : 0x00000001)
+#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+ 0x00000200 : 0x00000002)
+#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+ 0x00001000 : 0x00000004)
+#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+ 0x00000400 : 0x00000008)
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
--
1.8.4.2
next prev parent reply other threads:[~2014-09-25 14:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-25 14:18 [dpdk-dev] [PATCH 00/18] Update IXGBE base code Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 01/18] ixgbe: Update comments and fix some comments typo in " Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 02/18] ixgbe: Clean up IXGBE base codes Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 03/18] ixgbe: New function to check command complete in IXGBE base code Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 04/18] ixgbe: Support cloud mode " Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 05/18] ixgbe: eeprom checksum calculation return new value " Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 06/18] ixgbe: New argument in host interface command function Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 07/18] ixgbe: Extend mask for SWFW semaphore Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 08/18] ixgbe: New function to read and write I2C bytes Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 09/18] ixgbe: Support new device id 82599_QSFP and 82599_LS Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 10/18] ixgbe: Modify time to wait in polling flash update Ouyang Changchun
2014-09-25 14:18 ` [dpdk-dev] [PATCH 11/18] ixgbe: New error type Ouyang Changchun
2014-09-25 14:18 ` Ouyang Changchun [this message]
2014-09-25 14:18 ` [dpdk-dev] [PATCH 13/18] ixgbe: semaphore mask move into hardware physical information Ouyang Changchun
2014-09-25 14:19 ` [dpdk-dev] [PATCH 14/18] ixgbe: Remove unnecessary delay Ouyang Changchun
2014-09-25 14:19 ` [dpdk-dev] [PATCH 15/18] ixgbe: New function for resetting VF register Ouyang Changchun
2014-09-25 14:19 ` [dpdk-dev] [PATCH 16/18] ixgbe: New functionalities in IXGBE base code Ouyang Changchun
2014-09-25 14:19 ` [dpdk-dev] [PATCH 17/18] ixgbe: Support X550 " Ouyang Changchun
2014-09-25 14:19 ` [dpdk-dev] [PATCH 18/18] ixgbe: Support X550 in IXGBE poll mode driver Ouyang Changchun
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1411654744-9460-13-git-send-email-changchun.ouyang@intel.com \
--to=changchun.ouyang@intel.com \
--cc=dev@dpdk.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).