From: Chao Zhu <bjzhuc@cn.ibm.com> To: dev@dpdk.org Subject: [dpdk-dev] [PATCH 4/7] Split prefetch operations to architecture specific Date: Fri, 26 Sep 2014 05:33:35 -0400 Message-ID: <1411724018-7738-5-git-send-email-bjzhuc@cn.ibm.com> (raw) In-Reply-To: <1411724018-7738-1-git-send-email-bjzhuc@cn.ibm.com> This patch splits the prefetch operations from DPDK and push them to architecture specific arch directories, so that other processor architecture to support DPDK can be easily adopted. Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com> --- lib/librte_eal/common/Makefile | 2 +- .../common/include/i686/arch/rte_prefetch_arch.h | 68 ++++++++++++++++++++ lib/librte_eal/common/include/rte_prefetch.h | 7 +- .../common/include/x86_64/arch/rte_prefetch_arch.h | 68 ++++++++++++++++++++ 4 files changed, 141 insertions(+), 4 deletions(-) create mode 100644 lib/librte_eal/common/include/i686/arch/rte_prefetch_arch.h create mode 100644 lib/librte_eal/common/include/x86_64/arch/rte_prefetch_arch.h diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index 0863aeb..bb175ca 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -46,7 +46,7 @@ ifeq ($(CONFIG_RTE_INSECURE_FUNCTION_WARNING),y) INC += rte_warnings.h endif -ARCH_INC := rte_atomic.h rte_atomic_arch.h rte_byteorder_arch.h rte_cycles_arch.h +ARCH_INC := rte_atomic.h rte_atomic_arch.h rte_byteorder_arch.h rte_cycles_arch.h rte_prefetch_arch.h SYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include := $(addprefix include/,$(INC)) SYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include/arch := \ diff --git a/lib/librte_eal/common/include/i686/arch/rte_prefetch_arch.h b/lib/librte_eal/common/include/i686/arch/rte_prefetch_arch.h new file mode 100644 index 0000000..48cfaf5 --- /dev/null +++ b/lib/librte_eal/common/include/i686/arch/rte_prefetch_arch.h @@ -0,0 +1,68 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_PREFETCH_ARCH_H_ +#define _RTE_PREFETCH_ARCH_H_ + +/** + * Prefetch a cache line into all cache levels. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch0(volatile void *p) +{ + asm volatile ("prefetcht0 %[p]" : [p] "+m" (*(volatile char *)p)); +} + +/** + * Prefetch a cache line into all cache levels except the 0th cache level. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch1(volatile void *p) +{ + asm volatile ("prefetcht1 %[p]" : [p] "+m" (*(volatile char *)p)); +} + +/** + * Prefetch a cache line into all cache levels except the 0th and 1th cache + * levels. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch2(volatile void *p) +{ + asm volatile ("prefetcht2 %[p]" : [p] "+m" (*(volatile char *)p)); +} + +#endif /* _RTE_PREFETCH_ARCH_H_ */ diff --git a/lib/librte_eal/common/include/rte_prefetch.h b/lib/librte_eal/common/include/rte_prefetch.h index 8a691ef..0a45176 100644 --- a/lib/librte_eal/common/include/rte_prefetch.h +++ b/lib/librte_eal/common/include/rte_prefetch.h @@ -34,6 +34,7 @@ #ifndef _RTE_PREFETCH_H_ #define _RTE_PREFETCH_H_ +#include <arch/rte_prefetch_arch.h> /** * @file * @@ -57,7 +58,7 @@ extern "C" { */ static inline void rte_prefetch0(volatile void *p) { - asm volatile ("prefetcht0 %[p]" : [p] "+m" (*(volatile char *)p)); + rte_arch_prefetch0(p); } /** @@ -67,7 +68,7 @@ static inline void rte_prefetch0(volatile void *p) */ static inline void rte_prefetch1(volatile void *p) { - asm volatile ("prefetcht1 %[p]" : [p] "+m" (*(volatile char *)p)); + rte_arch_prefetch1(p); } /** @@ -78,7 +79,7 @@ static inline void rte_prefetch1(volatile void *p) */ static inline void rte_prefetch2(volatile void *p) { - asm volatile ("prefetcht2 %[p]" : [p] "+m" (*(volatile char *)p)); + rte_arch_prefetch2(p); } #ifdef __cplusplus diff --git a/lib/librte_eal/common/include/x86_64/arch/rte_prefetch_arch.h b/lib/librte_eal/common/include/x86_64/arch/rte_prefetch_arch.h new file mode 100644 index 0000000..48cfaf5 --- /dev/null +++ b/lib/librte_eal/common/include/x86_64/arch/rte_prefetch_arch.h @@ -0,0 +1,68 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_PREFETCH_ARCH_H_ +#define _RTE_PREFETCH_ARCH_H_ + +/** + * Prefetch a cache line into all cache levels. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch0(volatile void *p) +{ + asm volatile ("prefetcht0 %[p]" : [p] "+m" (*(volatile char *)p)); +} + +/** + * Prefetch a cache line into all cache levels except the 0th cache level. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch1(volatile void *p) +{ + asm volatile ("prefetcht1 %[p]" : [p] "+m" (*(volatile char *)p)); +} + +/** + * Prefetch a cache line into all cache levels except the 0th and 1th cache + * levels. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch2(volatile void *p) +{ + asm volatile ("prefetcht2 %[p]" : [p] "+m" (*(volatile char *)p)); +} + +#endif /* _RTE_PREFETCH_ARCH_H_ */ -- 1.7.1
next prev parent reply other threads:[~2014-09-26 9:27 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-26 9:33 [dpdk-dev] [PATCH 0/7] Patches to split architecture specific operations from DPDK Chao Zhu 2014-09-26 9:33 ` [dpdk-dev] [PATCH 1/7] Split atomic operations to architecture specific Chao Zhu 2014-09-29 11:05 ` Bruce Richardson 2014-09-29 15:24 ` Neil Horman 2014-09-30 2:18 ` Chao CH Zhu 2014-09-26 9:33 ` [dpdk-dev] [PATCH 2/7] Split byte order " Chao Zhu 2014-09-26 9:33 ` [dpdk-dev] [PATCH 3/7] Split CPU cycle operation " Chao Zhu 2014-09-26 9:33 ` Chao Zhu [this message] 2014-09-26 9:33 ` [dpdk-dev] [PATCH 5/7] Split spinlock operations " Chao Zhu 2014-09-26 9:33 ` [dpdk-dev] [PATCH 6/7] Split memcpy operation " Chao Zhu 2014-09-26 9:33 ` [dpdk-dev] [PATCH 7/7] Split CPU flags operations " Chao Zhu 2014-10-03 13:21 ` [dpdk-dev] [PATCH 0/7] Patches to split architecture specific operations from DPDK David Marchand 2014-10-03 13:29 ` Bruce Richardson 2014-10-13 2:36 ` Chao CH Zhu 2014-10-06 21:46 ` Cyril Chemparathy 2014-10-12 9:14 ` Chao CH Zhu
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