From: Chao Zhu <bjzhuc@cn.ibm.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH 12/12] Add memory support for IBM Power Architecture
Date: Fri, 26 Sep 2014 05:36:26 -0400 [thread overview]
Message-ID: <1411724186-8036-13-git-send-email-bjzhuc@cn.ibm.com> (raw)
In-Reply-To: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com>
IBM Power architecture has different memory architecture with x86. When
the physical memory address is in ascending order, the mmaped virtual
address is in descending order. This patch modified the memory segment
detection code to make it work for Power.
Signed-off-by: Chao Zhu <bjzhuc@cn.ibm.com>
---
config/defconfig_ppc_64-native-linuxapp-gcc | 1 +
config/defconfig_x86_64-native-linuxapp-clang | 1 +
config/defconfig_x86_64-native-linuxapp-gcc | 1 +
config/defconfig_x86_64-native-linuxapp-icc | 1 +
lib/librte_eal/linuxapp/eal/eal_memory.c | 19 +++++++++++++++++--
5 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/config/defconfig_ppc_64-native-linuxapp-gcc b/config/defconfig_ppc_64-native-linuxapp-gcc
index cc11cfc..c29888c 100644
--- a/config/defconfig_ppc_64-native-linuxapp-gcc
+++ b/config/defconfig_ppc_64-native-linuxapp-gcc
@@ -34,6 +34,7 @@ CONFIG_RTE_MACHINE="powerpc"
CONFIG_RTE_ARCH="powerpc"
CONFIG_RTE_ARCH_PPC_64=y
+CONFIG_RTE_ARCH_64=y
CONFIG_RTE_ARCH_BIG_ENDIAN=y
CONFIG_RTE_TOOLCHAIN="gcc"
diff --git a/config/defconfig_x86_64-native-linuxapp-clang b/config/defconfig_x86_64-native-linuxapp-clang
index bbda080..5f3074e 100644
--- a/config/defconfig_x86_64-native-linuxapp-clang
+++ b/config/defconfig_x86_64-native-linuxapp-clang
@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native"
CONFIG_RTE_ARCH="x86_64"
CONFIG_RTE_ARCH_X86_64=y
+CONFIG_RTE_ARCH_64=y
CONFIG_RTE_TOOLCHAIN="clang"
CONFIG_RTE_TOOLCHAIN_CLANG=y
diff --git a/config/defconfig_x86_64-native-linuxapp-gcc b/config/defconfig_x86_64-native-linuxapp-gcc
index 3de818a..60baf5b 100644
--- a/config/defconfig_x86_64-native-linuxapp-gcc
+++ b/config/defconfig_x86_64-native-linuxapp-gcc
@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native"
CONFIG_RTE_ARCH="x86_64"
CONFIG_RTE_ARCH_X86_64=y
+CONFIG_RTE_ARCH_64=y
CONFIG_RTE_TOOLCHAIN="gcc"
CONFIG_RTE_TOOLCHAIN_GCC=y
diff --git a/config/defconfig_x86_64-native-linuxapp-icc b/config/defconfig_x86_64-native-linuxapp-icc
index 795333b..71d1e28 100644
--- a/config/defconfig_x86_64-native-linuxapp-icc
+++ b/config/defconfig_x86_64-native-linuxapp-icc
@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="native"
CONFIG_RTE_ARCH="x86_64"
CONFIG_RTE_ARCH_X86_64=y
+CONFIG_RTE_ARCH_64=y
CONFIG_RTE_TOOLCHAIN="icc"
CONFIG_RTE_TOOLCHAIN_ICC=y
diff --git a/lib/librte_eal/linuxapp/eal/eal_memory.c b/lib/librte_eal/linuxapp/eal/eal_memory.c
index f2454f4..6694e08 100644
--- a/lib/librte_eal/linuxapp/eal/eal_memory.c
+++ b/lib/librte_eal/linuxapp/eal/eal_memory.c
@@ -316,7 +316,7 @@ map_all_hugepages(struct hugepage_file *hugepg_tbl,
#endif
hugepg_tbl[i].filepath[sizeof(hugepg_tbl[i].filepath) - 1] = '\0';
}
-#ifndef RTE_ARCH_X86_64
+#ifndef RTE_ARCH_64
/* for 32-bit systems, don't remap 1G pages, just reuse original
* map address as final map address.
*/
@@ -412,7 +412,7 @@ remap_all_hugepages(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)
while (i < hpi->num_pages[0]) {
-#ifndef RTE_ARCH_X86_64
+#ifndef RTE_ARCH_64
/* for 32-bit systems, don't remap 1G pages, just reuse original
* map address as final map address.
*/
@@ -1263,9 +1263,18 @@ rte_eal_hugepage_init(void)
else if ((hugepage[i].physaddr - hugepage[i-1].physaddr) !=
hugepage[i].size)
new_memseg = 1;
+#ifdef RTE_ARCH_PPC_64
+ /* IBM Power architecture has different memory layout.
+ * If the physical address is lower address first, the mmaped virtual
+ * address will be higher address first */
+ else if (((unsigned long)hugepage[i-1].final_va -
+ (unsigned long)hugepage[i].final_va) != hugepage[i].size)
+ new_memseg = 1;
+#else
else if (((unsigned long)hugepage[i].final_va -
(unsigned long)hugepage[i-1].final_va) != hugepage[i].size)
new_memseg = 1;
+#endif
if (new_memseg) {
j += 1;
@@ -1284,6 +1293,12 @@ rte_eal_hugepage_init(void)
}
/* continuation of previous memseg */
else {
+#ifdef RTE_ARCH_PPC_64
+ /* Use the phy and virt address of the last page as segment address
+ * for IBM Power architecture */
+ mcfg->memseg[j].phys_addr = hugepage[i].physaddr;
+ mcfg->memseg[j].addr = hugepage[i].final_va;
+#endif
mcfg->memseg[j].len += mcfg->memseg[j].hugepage_sz;
}
hugepage[i].memseg_id = j;
--
1.7.1
next prev parent reply other threads:[~2014-09-26 9:30 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-26 9:36 [dpdk-dev] [PATCH 00/12] Patches for DPDK to support Power architecture Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 01/12] Add compiling definations for IBM " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 02/12] Add atomic operations " Chao Zhu
2014-09-29 6:16 ` Hemant
2014-09-29 6:41 ` Chao CH Zhu
2014-10-16 0:39 ` Ananyev, Konstantin
2014-10-16 3:14 ` Chao CH Zhu
2014-10-16 9:42 ` Richardson, Bruce
2014-10-16 11:04 ` Ananyev, Konstantin
[not found] ` <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com>
2014-10-16 10:59 ` Ananyev, Konstantin
2014-09-26 9:36 ` [dpdk-dev] [PATCH 03/12] Add byte order " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 04/12] Add CPU cycle " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 05/12] Add prefetch operation " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 06/12] Add spinlock " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 07/12] Add vector memcpy " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 08/12] Add CPU flag checking " Chao Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 09/12] Remove iopl operation " Chao Zhu
2014-10-06 22:03 ` Cyril Chemparathy
2014-10-07 14:46 ` Ananyev, Konstantin
2014-10-13 2:33 ` Chao CH Zhu
2014-09-26 9:36 ` [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture Chao Zhu
2014-09-29 6:21 ` Hemant
2014-09-26 9:36 ` [dpdk-dev] [PATCH 11/12] Add huge page sizes for IBM Power architecture Chao Zhu
2014-09-26 9:36 ` Chao Zhu [this message]
2014-11-13 10:24 ` [dpdk-dev] [PATCH 00/12] Patches for DPDK to support " Thomas Monjalon
2014-11-13 10:31 ` Chao Zhu
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