From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e39.co.us.ibm.com (e39.co.us.ibm.com [32.97.110.160]) by dpdk.org (Postfix) with ESMTP id 0B0957E30 for ; Fri, 26 Sep 2014 11:30:21 +0200 (CEST) Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 26 Sep 2014 03:36:42 -0600 Received: from d01dlp03.pok.ibm.com (9.56.250.168) by e39.co.us.ibm.com (192.168.1.139) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 26 Sep 2014 03:36:40 -0600 Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 39B32C90042 for ; Fri, 26 Sep 2014 05:25:24 -0400 (EDT) Received: from d01av05.pok.ibm.com (d01av05.pok.ibm.com [9.56.224.195]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id s8Q9aVed5243284 for ; Fri, 26 Sep 2014 09:36:39 GMT Received: from d01av05.pok.ibm.com (localhost [127.0.0.1]) by d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s8Q9a7LG002933 for ; Fri, 26 Sep 2014 05:36:07 -0400 Received: from d01hub02.pok.ibm.com (d01hub02.pok.ibm.com [9.63.10.236]) by d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s8Q9a7wI002655 for ; Fri, 26 Sep 2014 05:36:07 -0400 Received: from localhost.localdomain ([9.186.57.14]) by rescrl1.research.ibm.com (IBM Domino Release 9.0.1) with ESMTP id 2014092617352226-312551 ; Fri, 26 Sep 2014 17:35:22 +0800 From: Chao Zhu To: dev@dpdk.org Date: Fri, 26 Sep 2014 05:36:19 -0400 Message-Id: <1411724186-8036-6-git-send-email-bjzhuc@cn.ibm.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com> References: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com> X-MIMETrack: Itemize by SMTP Server on rescrl1/Research/Affiliated/IBM(Release 9.0.1|October 14, 2013) at 2014/09/26 17:35:22, Serialize by Router on D01HUB02/01/H/IBM(Release 8.5.3FP2 ZX853FP2HF5|February, 2013) at 09/26/2014 05:36:06, Serialize complete at 09/26/2014 05:36:06 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14092609-9332-0000-0000-000002250F95 Subject: [dpdk-dev] [PATCH 05/12] Add prefetch operation for IBM Power architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Sep 2014 09:30:25 -0000 The prefetch operations implemented with assembly code in DPDK only support x86. This patch add architecture specific prefetch operations for IBM Power architecture. Signed-off-by: Chao Zhu --- .../include/powerpc/arch/rte_prefetch_arch.h | 67 ++++++++++++++++++++ 1 files changed, 67 insertions(+), 0 deletions(-) create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h b/lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h new file mode 100644 index 0000000..32f18b4 --- /dev/null +++ b/lib/librte_eal/common/include/powerpc/arch/rte_prefetch_arch.h @@ -0,0 +1,67 @@ +/* + * BSD LICENSE + * + * Copyright (C) IBM Corporation 2014. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of IBM Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _RTE_PREFETCH_ARCH_H_ +#define _RTE_PREFETCH_ARCH_H_ + +/** + * Prefetch a cache line into all cache levels. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch0(volatile void *p) +{ + asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); +} + +/** + * Prefetch a cache line into all cache levels except the 0th cache level. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch1(volatile void *p) +{ + asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); +} + +/** + * Prefetch a cache line into all cache levels except the 0th and 1th cache + * levels. + * @param p + * Address to prefetch + */ +static inline void rte_arch_prefetch2(volatile void *p) +{ + asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p)); +} + +#endif /* _RTE_PREFETCH_ARCH_H_ */ -- 1.7.1