From: Helin Zhang <helin.zhang@intel.com> To: dev@dpdk.org Subject: [dpdk-dev] [PATCH v4 4/7] i40e: add hash filter control implementation Date: Mon, 13 Oct 2014 14:12:43 +0800 Message-ID: <1413180766-12211-5-git-send-email-helin.zhang@intel.com> (raw) In-Reply-To: <1413180766-12211-1-git-send-email-helin.zhang@intel.com> Hash filter control has been implemented for i40e. It includes getting/setting - hash function type - symmetric hash enable per pctype (packet classification type) - symmetric hash enable per port - filter swap configuration Signed-off-by: Helin Zhang <helin.zhang@intel.com> --- lib/librte_pmd_i40e/i40e_ethdev.c | 402 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 402 insertions(+) diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index 46c43a7..60b619b 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -216,6 +216,10 @@ static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); +static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, + enum rte_filter_type filter_type, + enum rte_filter_op filter_op, + void *arg); /* Default hash key buffer for RSS */ static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1]; @@ -267,6 +271,7 @@ static struct eth_dev_ops i40e_eth_dev_ops = { .reta_query = i40e_dev_rss_reta_query, .rss_hash_update = i40e_dev_rss_hash_update, .rss_hash_conf_get = i40e_dev_rss_hash_conf_get, + .filter_ctrl = i40e_dev_filter_ctrl, }; static struct eth_driver rte_i40e_pmd = { @@ -4162,3 +4167,400 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf) return 0; } + +/* Get the symmetric hash enable configurations per PCTYPE */ +static int +i40e_get_symmetric_hash_enable_per_pctype(struct i40e_hw *hw, + struct rte_eth_sym_hash_ena_info *info) +{ + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(info->pctype)); + info->enable = reg & I40E_GLQF_HSYM_SYMH_ENA_MASK ? 1 : 0; + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Set the symmetric hash enable configurations per PCTYPE */ +static int +i40e_set_symmetric_hash_enable_per_pctype(struct i40e_hw *hw, + const struct rte_eth_sym_hash_ena_info *info) +{ + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + reg = info->enable ? I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; + I40E_WRITE_REG(hw, I40E_GLQF_HSYM(info->pctype), reg); + I40E_WRITE_FLUSH(hw); + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Get the symmetric hash enable configurations per port */ +static void +i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0); + + *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0; +} + +/* Set the symmetric hash enable configurations per port */ +static void +i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0); + + if (enable > 0) { + if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) { + PMD_DRV_LOG(INFO, "Symmetric hash has already " + "been enabled"); + return; + } + reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK; + } else { + if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) { + PMD_DRV_LOG(INFO, "Symmetric hash has already " + "been disabled"); + return; + } + reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK; + } + I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg); + I40E_WRITE_FLUSH(hw); +} + +/* Get filter swap configurations */ +static int +i40e_get_filter_swap(struct i40e_hw *hw, struct rte_eth_filter_swap_info *info) +{ + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + reg = I40E_READ_REG(hw, I40E_GLQF_SWAP(0, info->pctype)); + PMD_DRV_LOG(DEBUG, "Value read from I40E_GLQF_SWAP[0,%d]: " + "0x%x", info->pctype, reg); + + /** + * The offset and length read from register in word unit, + * which need to be converted in byte unit before being saved. + */ + info->off0_src0 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC0_MASK) >> + I40E_GLQF_SWAP_OFF0_SRC0_SHIFT) << 1; + info->off0_src1 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF0_SRC1_MASK) >> + I40E_GLQF_SWAP_OFF0_SRC1_SHIFT) << 1; + info->len0 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN0_MASK) >> + I40E_GLQF_SWAP_FLEN0_SHIFT) << 1; + info->off1_src0 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC0_MASK) >> + I40E_GLQF_SWAP_OFF1_SRC0_SHIFT) << 1; + info->off1_src1 = + (uint8_t)((reg & I40E_GLQF_SWAP_OFF1_SRC1_MASK) >> + I40E_GLQF_SWAP_OFF1_SRC1_SHIFT) << 1; + info->len1 = (uint8_t)((reg & I40E_GLQF_SWAP_FLEN1_MASK) >> + I40E_GLQF_SWAP_FLEN1_SHIFT) << 1; + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Set filter swap configurations */ +static int +i40e_set_filter_swap(struct i40e_hw *hw, + const struct rte_eth_filter_swap_info *info) +{ +#define I40E_FIELD_LEN_MAX 0x1f +#define I40E_FIELD_OFFSET_MAX 0x7f + uint32_t reg; + + switch (info->pctype) { + case ETH_RSS_NONF_IPV4_UDP_SHIFT: + case ETH_RSS_NONF_IPV4_TCP_SHIFT: + case ETH_RSS_NONF_IPV4_SCTP_SHIFT: + case ETH_RSS_NONF_IPV4_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV4_SHIFT: + case ETH_RSS_NONF_IPV6_UDP_SHIFT: + case ETH_RSS_NONF_IPV6_TCP_SHIFT: + case ETH_RSS_NONF_IPV6_SCTP_SHIFT: + case ETH_RSS_NONF_IPV6_OTHER_SHIFT: + case ETH_RSS_FRAG_IPV6_SHIFT: + case ETH_RSS_L2_PAYLOAD_SHIFT: + if (info->off0_src0 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off0_src0 (0x%x) exceeds the " + "maximum of 0x%x", info->off0_src0, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->off0_src1 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off0_src1 (0x%x) exceeds the " + "maximum of 0x%x", info->off0_src1, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->len0 > I40E_FIELD_LEN_MAX) { + PMD_DRV_LOG(ERR, "len0 (0x%x) exceeds the maximum " + "of 0x%x", info->len0, I40E_FIELD_LEN_MAX); + return I40E_ERR_PARAM; + } else if (info->off1_src0 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off1_src0 (0x%x) exceeds the " + "maximum of 0x%x", info->off1_src0, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->off1_src1 > I40E_FIELD_OFFSET_MAX) { + PMD_DRV_LOG(ERR, "off1_src1 (0x%x) exceeds the " + "maximum of 0x%x", info->off1_src1, + I40E_FIELD_OFFSET_MAX); + return I40E_ERR_PARAM; + } else if (info->len1 > I40E_FIELD_LEN_MAX) { + PMD_DRV_LOG(ERR, "len1 (0x%x) exceeds the maximum " + "of 0x%x", info->len1, I40E_FIELD_LEN_MAX); + return I40E_ERR_PARAM; + } + + /** + * The offset and length given in byte unit, which need to be + * converted in word unit before being written to the register, + * as hardware requires it in word unit. + */ + reg = (info->off0_src0 >> 1) << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT; + reg |= (info->off0_src1 >> 1) << + I40E_GLQF_SWAP_OFF0_SRC1_SHIFT; + reg |= (info->len0 >> 1) << I40E_GLQF_SWAP_FLEN0_SHIFT; + reg |= (info->off1_src0 >> 1) << + I40E_GLQF_SWAP_OFF1_SRC0_SHIFT; + reg |= (info->off1_src1 >> 1) << + I40E_GLQF_SWAP_OFF1_SRC1_SHIFT; + reg |= (info->len1 >> 1) << I40E_GLQF_SWAP_FLEN1_SHIFT; + + PMD_DRV_LOG(DEBUG, "Value to be written to " + "I40E_GLQF_SWAP[0,%d]: 0x%x", info->pctype, reg); + I40E_WRITE_REG(hw, I40E_GLQF_SWAP(0, info->pctype), reg); + I40E_WRITE_FLUSH(hw); + break; + default: + PMD_DRV_LOG(ERR, "PCTYPE[%u] not supported", info->pctype); + return -EINVAL; + } + + return 0; +} + +/* Get hash function type */ +static void +i40e_get_hash_function(struct i40e_hw *hw, enum rte_eth_hash_function *hf) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_GLQF_CTL); + + if (reg & I40E_GLQF_CTL_HTOEP_MASK) + *hf = RTE_ETH_HASH_FUNCTION_TOEPLITZ; + else + *hf = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR; + + PMD_DRV_LOG(INFO, "Hash function is %s", + (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); +} + +/* Set hash function type */ +static int +i40e_set_hash_function(struct i40e_hw *hw, enum rte_eth_hash_function hf) +{ + uint32_t reg = I40E_READ_REG(hw, I40E_GLQF_CTL); + + if (hf == RTE_ETH_HASH_FUNCTION_TOEPLITZ) { + if (reg & I40E_GLQF_CTL_HTOEP_MASK) { + PMD_DRV_LOG(DEBUG, "Hash function already set to " + "Toeplitz"); + return 0; + } + reg |= I40E_GLQF_CTL_HTOEP_MASK; + } else if (hf == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) { + if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) { + PMD_DRV_LOG(DEBUG, "Hash function already set to " + "Simple XOR"); + return 0; + } + reg &= ~I40E_GLQF_CTL_HTOEP_MASK; + } else { + PMD_DRV_LOG(ERR, "Unknown hash function type"); + return -EINVAL; + } + + PMD_DRV_LOG(INFO, "Hash function set to %s", + (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); + I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg); + I40E_WRITE_FLUSH(hw); + + return 0; +} + +static int +i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) +{ + int ret = 0; + + if (!hw || !info) { + PMD_DRV_LOG(ERR, "Invalid pointer"); + return -EFAULT; + } + + switch (info->info_type) { + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PCTYPE: + ret = i40e_get_symmetric_hash_enable_per_pctype(hw, + &(info->info.sym_hash_ena)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PORT: + i40e_get_symmetric_hash_enable_per_port(hw, + &(info->info.enable)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_FILTER_SWAP: + ret = i40e_get_filter_swap(hw, &(info->info.filter_swap)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_HASH_FUNCTION: + i40e_get_hash_function(hw, &(info->info.hash_function)); + break; + default: + PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", + info->info_type); + ret = -EINVAL; + break; + } + + return ret; +} + +static int +i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info) +{ + int ret = 0; + + if (!hw || !info) { + PMD_DRV_LOG(ERR, "Invalid pointer"); + return -EFAULT; + } + + switch (info->info_type) { + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PCTYPE: + ret = i40e_set_symmetric_hash_enable_per_pctype(hw, + &(info->info.sym_hash_ena)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_SYM_HASH_ENA_PER_PORT: + i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_FILTER_SWAP: + ret = i40e_set_filter_swap(hw, &(info->info.filter_swap)); + break; + case RTE_ETH_HASH_FILTER_INFO_TYPE_HASH_FUNCTION: + ret = i40e_set_hash_function(hw, info->info.hash_function); + break; + default: + PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported", + info->info_type); + ret = -EINVAL; + break; + } + + return ret; +} + +/* Operations for hash function */ +static int +i40e_hash_filter_ctrl(struct rte_eth_dev *dev, + enum rte_filter_op filter_op, + void *arg) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int ret = 0; + + switch (filter_op) { + case RTE_ETH_FILTER_OP_NONE: + break; + case RTE_ETH_FILTER_OP_GET: + ret = i40e_hash_filter_get(hw, + (struct rte_eth_hash_filter_info *)arg); + break; + case RTE_ETH_FILTER_OP_SET: + ret = i40e_hash_filter_set(hw, + (struct rte_eth_hash_filter_info *)arg); + break; + default: + PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported", + filter_op); + ret = -ENOTSUP; + break; + } + + return ret; +} + +static int +i40e_dev_filter_ctrl(struct rte_eth_dev *dev, + enum rte_filter_type filter_type, + enum rte_filter_op filter_op, + void *arg) +{ + int ret = -ENOTSUP; + + switch (filter_type) { + case RTE_ETH_FILTER_HASH: + ret = i40e_hash_filter_ctrl(dev, filter_op, arg); + break; + case RTE_ETH_FILTER_FDIR: + break; + case RTE_ETH_FILTER_TUNNEL: + break; + default: + PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", + filter_type); + break; + } + + return ret; +} -- 1.8.1.4
next prev parent reply other threads:[~2014-10-13 6:05 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-30 6:20 [dpdk-dev] [PATCH v3 0/7] Support configuring hash functions Helin Zhang 2014-09-30 6:20 ` [dpdk-dev] [PATCH v3 1/7] ethdev: add more annotations Helin Zhang 2014-10-13 6:12 ` [dpdk-dev] [PATCH v4 0/7] Support configuring hash functions Helin Zhang 2014-10-13 6:12 ` [dpdk-dev] [PATCH v4 1/7] ethdev: add more annotations Helin Zhang 2014-10-13 6:12 ` [dpdk-dev] [PATCH v4 2/7] ethdev: add interfaces and relevant for filter control Helin Zhang 2014-10-13 6:12 ` [dpdk-dev] [PATCH v4 3/7] ethdev: add structures and enum for hash " Helin Zhang 2014-10-13 6:12 ` Helin Zhang [this message] 2014-10-13 10:23 ` [dpdk-dev] [PATCH v4 4/7] i40e: add hash filter control implementation Chilikin, Andrey 2014-10-14 0:42 ` Zhang, Helin 2014-10-13 6:12 ` [dpdk-dev] [PATCH v4 5/7] i40e: add hardware initialization Helin Zhang 2014-10-13 6:12 ` [dpdk-dev] [PATCH v4 6/7] i40e: Use constant random hash keys Helin Zhang 2014-10-13 6:12 ` [dpdk-dev] [PATCH v4 7/7] app/testpmd: add commands to support hash filter control Helin Zhang 2014-10-13 12:27 ` [dpdk-dev] [PATCH v4 0/7] Support configuring hash functions Zhan, Zhaochen 2014-10-14 3:32 ` Wu, Jingjing 2014-10-21 3:14 ` [dpdk-dev] [PATCH v5 0/5] " Helin Zhang 2014-10-21 3:14 ` [dpdk-dev] [PATCH v5 1/5] i40e: Use constant random hash keys Helin Zhang 2014-11-03 7:49 ` Thomas Monjalon 2014-11-03 8:18 ` Zhang, Helin 2014-11-03 8:59 ` Thomas Monjalon 2014-11-06 7:52 ` Zhang, Helin 2014-11-11 3:30 ` Zhang, Helin 2014-10-21 3:14 ` [dpdk-dev] [PATCH v5 2/5] ethdev: add enum type and relevant structures for hash filter control Helin Zhang 2014-11-03 7:57 ` Thomas Monjalon 2014-11-06 3:41 ` Zhang, Helin 2014-11-06 8:43 ` Thomas Monjalon 2014-11-06 8:54 ` Zhang, Helin 2014-11-11 3:27 ` Zhang, Helin 2014-11-11 6:46 ` Zhang, Helin 2014-11-11 21:08 ` Thomas Monjalon 2014-11-12 5:52 ` Zhang, Helin 2014-11-12 9:30 ` Thomas Monjalon 2014-11-12 14:22 ` Zhang, Helin 2014-10-21 3:14 ` [dpdk-dev] [PATCH v5 3/5] i40e: add hash filter control implementation Helin Zhang 2014-10-21 3:14 ` [dpdk-dev] [PATCH v5 4/5] i40e: add hardware initialization Helin Zhang 2014-10-21 3:14 ` [dpdk-dev] [PATCH v5 5/5] app/testpmd: add commands to support hash filter Helin Zhang 2014-11-07 3:45 ` [dpdk-dev] [PATCH v5 0/5] Support configuring hash functions Chen, Erlu 2014-11-07 6:12 ` Chen, Erlu 2014-11-19 14:58 ` [dpdk-dev] [PATCH v6 0/3] " Helin Zhang 2014-11-19 14:58 ` [dpdk-dev] [PATCH v6 1/3] i40e: Use constant as the default hash keys Helin Zhang 2014-11-19 14:58 ` [dpdk-dev] [PATCH v6 2/3] i40e: support of controlling hash functions Helin Zhang 2014-11-19 14:58 ` [dpdk-dev] [PATCH v6 3/3] app/testpmd: add commands to support " Helin Zhang 2014-11-27 15:45 ` [dpdk-dev] [PATCH v6 0/3] Support configuring " Thomas Monjalon 2014-11-27 16:17 ` Zhang, Helin 2014-11-28 12:14 ` [dpdk-dev] [PATCH v7 0/4] " Helin Zhang 2014-11-28 12:14 ` [dpdk-dev] [PATCH v7 1/4] ethdev: code style fixes Helin Zhang 2014-11-28 12:14 ` [dpdk-dev] [PATCH v7 2/4] i40e: use constant as the default hash keys Helin Zhang 2014-11-28 12:14 ` [dpdk-dev] [PATCH v7 3/4] i40e: support of controlling hash functions Helin Zhang 2014-11-28 12:52 ` Ananyev, Konstantin 2014-11-28 12:14 ` [dpdk-dev] [PATCH v7 4/4] app/testpmd: app/testpmd: add commands to support " Helin Zhang 2014-12-02 2:19 ` [dpdk-dev] [PATCH v8 0/4] Support configuring " Helin Zhang 2014-12-02 2:19 ` [dpdk-dev] [PATCH v8 1/4] ethdev: code style fixes Helin Zhang 2014-12-02 2:19 ` [dpdk-dev] [PATCH v8 2/4] i40e: use constant as the default hash keys Helin Zhang 2014-12-02 2:19 ` [dpdk-dev] [PATCH v8 3/4] i40e: support of controlling hash functions Helin Zhang 2015-01-20 7:54 ` Thomas Monjalon 2015-01-21 0:13 ` Zhang, Helin 2015-01-22 7:44 ` Zhang, Helin 2014-12-02 2:19 ` [dpdk-dev] [PATCH v8 4/4] app/testpmd: add commands to support " Helin Zhang 2014-12-02 13:15 ` [dpdk-dev] [PATCH v8 0/4] Support configuring " Ananyev, Konstantin 2015-01-22 7:36 ` [dpdk-dev] [PATCH v9 0/5] " Helin Zhang 2015-01-22 7:36 ` [dpdk-dev] [PATCH v9 1/5] i40e: use constant as the default hash keys Helin Zhang 2015-01-22 7:36 ` [dpdk-dev] [PATCH v9 2/5] ethdev: code style fixes Helin Zhang 2015-01-22 7:36 ` [dpdk-dev] [PATCH v9 3/5] ethdev: support of configuring hash functions Helin Zhang 2015-01-22 7:36 ` [dpdk-dev] [PATCH v9 4/5] i40e: support of controlling " Helin Zhang 2015-01-22 7:36 ` [dpdk-dev] [PATCH v9 5/5] app/testpmd: add commands to support " Helin Zhang [not found] ` <5028514.8nkR6oWFO2@xps13> 2015-02-03 2:35 ` Zhang, Helin 2014-09-30 6:20 ` [dpdk-dev] [PATCH v3 2/7] ethdev: add interfaces and relevant for filter control Helin Zhang 2014-09-30 6:20 ` [dpdk-dev] [PATCH v3 3/7] ethdev: add structures and enum for hash " Helin Zhang 2014-09-30 6:20 ` [dpdk-dev] [PATCH v3 4/7] i40e: add hash filter control implementation Helin Zhang 2014-09-30 6:20 ` [dpdk-dev] [PATCH v3 5/7] i40e: add hardware initialization Helin Zhang 2014-09-30 6:20 ` [dpdk-dev] [PATCH v3 6/7] i40e: Use constant random hash keys Helin Zhang 2014-09-30 6:20 ` [dpdk-dev] [PATCH v3 7/7] app/testpmd: add commands to support hash filter control Helin Zhang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1413180766-12211-5-git-send-email-helin.zhang@intel.com \ --to=helin.zhang@intel.com \ --cc=dev@dpdk.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
DPDK patches and discussions This inbox may be cloned and mirrored by anyone: git clone --mirror https://inbox.dpdk.org/dev/0 dev/git/0.git # If you have public-inbox 1.1+ installed, you may # initialize and index your mirror using the following commands: public-inbox-init -V2 dev dev/ https://inbox.dpdk.org/dev \ dev@dpdk.org public-inbox-index dev Example config snippet for mirrors. Newsgroup available over NNTP: nntp://inbox.dpdk.org/inbox.dpdk.dev AGPL code for this site: git clone https://public-inbox.org/public-inbox.git