From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 322A37E93 for ; Fri, 31 Oct 2014 06:10:34 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 30 Oct 2014 22:19:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,292,1413270000"; d="scan'208";a="623936079" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 30 Oct 2014 22:19:31 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s9V5JT9U020945; Fri, 31 Oct 2014 13:19:29 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s9V5JRLw007295; Fri, 31 Oct 2014 13:19:29 +0800 Received: (from couyang@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s9V5JRu0007291; Fri, 31 Oct 2014 13:19:27 +0800 From: Ouyang Changchun To: dev@dpdk.org Date: Fri, 31 Oct 2014 13:19:15 +0800 Message-Id: <1414732757-7241-4-git-send-email-changchun.ouyang@intel.com> X-Mailer: git-send-email 1.7.12.2 In-Reply-To: <1414732757-7241-1-git-send-email-changchun.ouyang@intel.com> References: <1414381533-30370-1-git-send-email-changchun.ouyang@intel.com> <1414732757-7241-1-git-send-email-changchun.ouyang@intel.com> Subject: [dpdk-dev] [PATCH v3 3/5] ixgbe: Config PFVML2FLT register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 31 Oct 2014 05:10:34 -0000 Config PFVML2FLT register in ixgbe PMD to enable it receive broadcast and multicast packets. Signed-off-by: Changchun Ouyang --- lib/librte_pmd_ixgbe/ixgbe_rxtx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c index 3a5a8ff..96276a7 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c +++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c @@ -3123,6 +3123,7 @@ ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev) struct ixgbe_hw *hw; enum rte_eth_nb_pools num_pools; uint32_t mrqc, vt_ctl, vlanctrl; + uint32_t vmolr = 0; int i; PMD_INIT_FUNC_TRACE(); @@ -3145,6 +3146,21 @@ ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev) IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl); + for (i = 0; i < (int)num_pools; i++) { + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG) + vmolr |= IXGBE_VMOLR_AUPE; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC) + vmolr |= IXGBE_VMOLR_ROMPE; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC) + vmolr |= IXGBE_VMOLR_ROPE; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST) + vmolr |= IXGBE_VMOLR_BAM; + if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST) + vmolr |= IXGBE_VMOLR_MPE; + + IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr); + } + /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */ -- 1.8.4.2