From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 835DD7F0D for ; Fri, 31 Oct 2014 09:54:53 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 31 Oct 2014 02:03:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,293,1413270000"; d="scan'208";a="624018033" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 31 Oct 2014 02:03:48 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s9V93kId031165; Fri, 31 Oct 2014 17:03:46 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s9V93if1017382; Fri, 31 Oct 2014 17:03:46 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s9V93iVn017378; Fri, 31 Oct 2014 17:03:44 +0800 From: Helin Zhang To: dev@dpdk.org Date: Fri, 31 Oct 2014 17:03:30 +0800 Message-Id: <1414746215-17327-4-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1414746215-17327-1-git-send-email-helin.zhang@intel.com> References: <1413978810-24610-1-git-send-email-helin.zhang@intel.com> <1414746215-17327-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH v4 3/8] i40e: support of setting hash lookup table size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 31 Oct 2014 08:54:56 -0000 Add support of setting hash lookup table size according to the hardawre capability. Signed-off-by: Helin Zhang --- lib/librte_ether/rte_ethdev.h | 3 +++ lib/librte_pmd_i40e/i40e_ethdev.c | 14 +++++++++++++- lib/librte_pmd_i40e/i40e_ethdev.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h index 8bf274d..cdfa579 100644 --- a/lib/librte_ether/rte_ethdev.h +++ b/lib/librte_ether/rte_ethdev.h @@ -430,6 +430,9 @@ struct rte_eth_rss_conf { /* Definitions used for redirection table entry size */ #define ETH_RSS_RETA_NUM_ENTRIES 128 #define ETH_RSS_RETA_MAX_QUEUE 16 +#define ETH_RSS_RETA_SIZE_64 64 +#define ETH_RSS_RETA_SIZE_128 128 +#define ETH_RSS_RETA_SIZE_512 512 /* Definitions used for VMDQ and DCB functionality */ #define ETH_VMDQ_MAX_VLAN_FILTERS 64 /**< Maximum nb. of VMDQ vlan filters. */ diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c index d768a08..0efbcd8 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.c +++ b/lib/librte_pmd_i40e/i40e_ethdev.c @@ -3081,7 +3081,19 @@ i40e_pf_setup(struct i40e_pf *pf) /* Configure filter control */ memset(&settings, 0, sizeof(settings)); - settings.hash_lut_size = I40E_HASH_LUT_SIZE_128; + if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128) + settings.hash_lut_size = I40E_HASH_LUT_SIZE_128; + else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512) + settings.hash_lut_size = I40E_HASH_LUT_SIZE_512; + else { + PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n", + hw->func_caps.rss_table_size); + return I40E_ERR_PARAM; + } + PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table " + "size: %u\n", hw->func_caps.rss_table_size); + pf->hash_lut_size = hw->func_caps.rss_table_size; + /* Enable ethtype and macvlan filters */ settings.enable_ethtype = TRUE; settings.enable_macvlan = TRUE; diff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h index e61d258..ce72720 100644 --- a/lib/librte_pmd_i40e/i40e_ethdev.h +++ b/lib/librte_pmd_i40e/i40e_ethdev.h @@ -260,6 +260,7 @@ struct i40e_pf { uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ uint16_t vf_nb_qps; /* The number of queue pairs of VF */ uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ + uint16_t hash_lut_size; /* The size of hash lookup table */ /* store VXLAN UDP ports */ uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; -- 1.8.1.4