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From: Chao Zhu <chaozhu@linux.vnet.ibm.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH v2 04/12] Add CPU cycle operations for IBM Power architecture
Date: Sun, 16 Nov 2014 23:48:17 -0500	[thread overview]
Message-ID: <1416199705-24150-5-git-send-email-chaozhu@linux.vnet.ibm.com> (raw)
In-Reply-To: <1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com>

IBM Power architecture doesn't have TSC register to get CPU cycles. This
patch implements the time base register read instead of TSC register of
x86 on IBM Power architecture.

Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
---
 .../common/include/arch/ppc_64/rte_cycles.h        |   86 ++++++++++++++++++++
 1 files changed, 86 insertions(+), 0 deletions(-)
 create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h

diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h
new file mode 100644
index 0000000..ed66b48
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h
@@ -0,0 +1,86 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_CYCLES_PPC_64_H_
+#define _RTE_CYCLES_PPC_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static inline uint64_t
+rte_rdtsc(void)
+{
+	union {
+		uint64_t tsc_64;
+		struct {
+			uint32_t hi_32;
+			uint32_t lo_32;
+		};
+	} tsc;
+	uint32_t tmp;
+	asm volatile(
+			"0:\n"
+			"mftbu   %[hi32]\n"
+			"mftb    %[lo32]\n"
+			"mftbu   %[tmp]\n"
+			"cmpw    %[tmp],%[hi32]\n"
+			"bne     0b\n"
+			: [hi32] "=r"(tsc.hi_32), [lo32] "=r"(tsc.lo_32), [tmp] "=r"(tmp)
+		    );
+	return tsc.tsc_64;
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+	rte_mb();
+	return rte_rdtsc();
+}
+
+static inline uint64_t
+rte_get_tsc_cycles(void) { return rte_rdtsc(); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CYCLES_PPC_64_H_ */
+
-- 
1.7.1

  parent reply	other threads:[~2014-11-16 16:37 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-17  4:48 [dpdk-dev] [PATCH v2 00/12] Patches for DPDK to support " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 01/12] Add compiling definations for IBM " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 02/12] Add atomic operations " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 03/12] Add byte order " Chao Zhu
2014-11-17  4:48 ` Chao Zhu [this message]
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 05/12] Add prefetch operation " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 06/12] Add spinlock " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 07/12] Add vector memcpy " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 08/12] Add CPU flag checking " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 09/12] Remove iopl operation " Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 10/12] Add cache size define for IBM Power Architecture Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 11/12] Add huge page size define for IBM Power architecture Chao Zhu
2014-11-17  4:48 ` [dpdk-dev] [PATCH v2 12/12] Add eal memory support for IBM Power Architecture Chao Zhu

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