From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e28smtp08.in.ibm.com (e28smtp08.in.ibm.com [122.248.162.8]) by dpdk.org (Postfix) with ESMTP id 5240D2E8B for ; Tue, 25 Nov 2014 11:05:30 +0100 (CET) Received: from /spool/local by e28smtp08.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 25 Nov 2014 15:46:21 +0530 Received: from d28dlp01.in.ibm.com (9.184.220.126) by e28smtp08.in.ibm.com (192.168.1.138) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Tue, 25 Nov 2014 15:46:19 +0530 Received: from d28relay03.in.ibm.com (d28relay03.in.ibm.com [9.184.220.60]) by d28dlp01.in.ibm.com (Postfix) with ESMTP id 17BFAE004C for ; Tue, 25 Nov 2014 15:46:40 +0530 (IST) Received: from d28av05.in.ibm.com (d28av05.in.ibm.com [9.184.220.67]) by d28relay03.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id sAPAIRLF59048024 for ; Tue, 25 Nov 2014 15:48:27 +0530 Received: from d28av05.in.ibm.com (localhost [127.0.0.1]) by d28av05.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id sAPAGGfK021422 for ; Tue, 25 Nov 2014 15:46:16 +0530 Received: from os_controller.crl.ibm.com ([9.186.57.58]) by d28av05.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id sAPAG3kt020283 for ; Tue, 25 Nov 2014 15:46:16 +0530 From: Chao Zhu To: dev@dpdk.org Date: Tue, 25 Nov 2014 17:17:13 -0500 Message-Id: <1416953837-15894-11-git-send-email-chaozhu@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1416953837-15894-1-git-send-email-chaozhu@linux.vnet.ibm.com> References: <1416953837-15894-1-git-send-email-chaozhu@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14112510-0029-0000-0000-000003221AFC Subject: [dpdk-dev] [PATCH v5 10/14] Add cache size define for IBM Power Architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Nov 2014 10:05:33 -0000 IBM Power architecture has different cache line size (128 bytes) than x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to override the default value 64 bytes to support IBM Power Architecture. Signed-off-by: Chao Zhu --- app/test/test_malloc.c | 8 ++++---- mk/arch/ppc_64/rte.vars.mk | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/app/test/test_malloc.c b/app/test/test_malloc.c index ee34ca3..63e6b32 100644 --- a/app/test/test_malloc.c +++ b/app/test/test_malloc.c @@ -300,9 +300,9 @@ test_big_alloc(void) size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2; int align = 0; #ifndef RTE_LIBRTE_MALLOC_DEBUG - int overhead = 64 + 64; + int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE; #else - int overhead = 64 + 64 + 64; + int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE + CACHE_LINE_SIZE; #endif rte_malloc_get_socket_stats(socket, &pre_stats); @@ -356,9 +356,9 @@ test_multi_alloc_statistics(void) #ifndef RTE_LIBRTE_MALLOC_DEBUG int trailer_size = 0; #else - int trailer_size = 64; + int trailer_size = CACHE_LINE_SIZE; #endif - int overhead = 64 + trailer_size; + int overhead = CACHE_LINE_SIZE + trailer_size; rte_malloc_get_socket_stats(socket, &pre_stats); diff --git a/mk/arch/ppc_64/rte.vars.mk b/mk/arch/ppc_64/rte.vars.mk index 363fcd1..dfdeaea 100644 --- a/mk/arch/ppc_64/rte.vars.mk +++ b/mk/arch/ppc_64/rte.vars.mk @@ -32,7 +32,7 @@ ARCH ?= powerpc CROSS ?= -CPU_CFLAGS ?= -m64 +CPU_CFLAGS ?= -m64 -DCACHE_LINE_SIZE=128 CPU_LDFLAGS ?= CPU_ASFLAGS ?= -felf64 -- 1.7.1