From: Zhigang Lu <zlu@ezchip.com> To: <dev@dpdk.org> Subject: [dpdk-dev] [PATCH v2 03/12] eal/tile: add spinlock operations for TileGx Date: Tue, 6 Jan 2015 14:53:41 +0800 Message-ID: <1420527230-17037-4-git-send-email-zlu@ezchip.com> (raw) In-Reply-To: <1420527230-17037-1-git-send-email-zlu@ezchip.com> TileGx uses generic spinlock operations. Signed-off-by: Zhigang Lu <zlu@ezchip.com> Signed-off-by: Cyril Chemparathy <cchemparathy@ezchip.com> --- .../common/include/arch/tile/rte_spinlock.h | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/tile/rte_spinlock.h diff --git a/lib/librte_eal/common/include/arch/tile/rte_spinlock.h b/lib/librte_eal/common/include/arch/tile/rte_spinlock.h new file mode 100644 index 0000000..1dc224e --- /dev/null +++ b/lib/librte_eal/common/include/arch/tile/rte_spinlock.h @@ -0,0 +1,47 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2014 Tilera Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Tilera Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_SPINLOCK_TILE_H_ +#define _RTE_SPINLOCK_TILE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_spinlock.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_SPINLOCK_TILE_H_ */ -- 2.1.2
next prev parent reply other threads:[~2015-01-06 6:58 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <1420527230-17037-1-git-send-email-zlu@ezchip.com> 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 01/12] eal/tile: add atomic " Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 02/12] eal/tile: add byte order " Zhigang Lu 2015-01-06 6:53 ` Zhigang Lu [this message] 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 04/12] eal/tile: add prefetch " Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 05/12] eal/tile: add memcpy " Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 06/12] eal/tile: add cycle " Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 07/12] eal: split vector operations to architecture specific Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 08/12] eal/tile: add vector operations for TileGx Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 09/12] eal/tile: add CPU flags " Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 10/12] app/test: remove architecture specific code from cpuflags test Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 11/12] eal: allow empty set of compile time cpuflags Zhigang Lu 2015-01-06 6:53 ` [dpdk-dev] [PATCH v2 12/12] mk: introduce Tilera Tile architecture Zhigang Lu 2015-05-22 16:03 ` Thomas Monjalon 2015-05-22 16:42 ` Cyril Chemparathy
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