From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 12024ADC2 for ; Wed, 4 Feb 2015 08:16:50 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 03 Feb 2015 23:13:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,517,1418112000"; d="scan'208";a="672463653" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 03 Feb 2015 23:16:48 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t147GjXw012943; Wed, 4 Feb 2015 15:16:45 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t147Gi2w027028; Wed, 4 Feb 2015 15:16:46 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t147GiZT027024; Wed, 4 Feb 2015 15:16:44 +0800 From: Helin Zhang To: dev@dpdk.org Date: Wed, 4 Feb 2015 15:16:30 +0800 Message-Id: <1423034193-26966-5-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1423034193-26966-1-git-send-email-helin.zhang@intel.com> References: <1421650577-25969-1-git-send-email-helin.zhang@intel.com> <1423034193-26966-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 4/7] ethdev: fix of calculating the size of flow type mask array X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Feb 2015 07:16:51 -0000 It wrongly calculates the size of the flow type mask array. The fix is to align the flow type maximum index ID with the number of element bit width, and then divide the number of element bit width. Signed-off-by: Helin Zhang --- lib/librte_ether/rte_eth_ctrl.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h index e936f3a..cbd36ea 100644 --- a/lib/librte_ether/rte_eth_ctrl.h +++ b/lib/librte_ether/rte_eth_ctrl.h @@ -398,6 +398,10 @@ enum rte_fdir_mode { RTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode. */ }; +#define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) +#define RTE_FLOW_MASK_ARRAY_SIZE \ +(RTE_ALIGN(RTE_ETH_FLOW_TYPE_MAX, UINT32_BIT)/UINT32_BIT) + /** * A structure used to get the information of flow director filter. * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_INFO operation. @@ -412,7 +416,7 @@ struct rte_eth_fdir_info { uint32_t guarant_spc; /**< Guaranteed spaces.*/ uint32_t best_spc; /**< Best effort spaces.*/ /** Bit mask for every supported flow type. */ - uint32_t flow_types_mask[RTE_ETH_FLOW_TYPE_MAX / sizeof(uint32_t)]; + uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]; uint32_t max_flexpayload; /**< Total flex payload in bytes. */ /** Flexible payload unit in bytes. Size and alignments of all flex payload segments should be multiplies of this value. */ @@ -477,7 +481,6 @@ enum rte_eth_hash_function { RTE_ETH_HASH_FUNCTION_MAX, }; -#define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ (RTE_ALIGN(RTE_ETH_FLOW_TYPE_MAX, UINT32_BIT)/UINT32_BIT) /** -- 1.9.3