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From: Stephen Hemminger <stephen@networkplumber.org>
To: dev@dpdk.org
Cc: Stephen Hemminger <shemming@brocade.com>
Subject: [dpdk-dev] [PATCH 3/4] bcm: new poll mode driver
Date: Fri,  6 Feb 2015 10:36:34 -0800
Message-ID: <1423247795-22399-4-git-send-email-stephen@networkplumber.org> (raw)
In-Reply-To: <1423247795-22399-1-git-send-email-stephen@networkplumber.org>

From: Stephen Hemminger <shemming@brocade.com>

Add driver for the Broadcom NetXtremeII 10 gigabit devices.

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 lib/Makefile                        |     1 +
 lib/librte_pmd_bcm/Makefile         |    28 +
 lib/librte_pmd_bcm/bcm.c            | 11817 ++++++++++++++++++++++++++++++
 lib/librte_pmd_bcm/bcm.h            |  1998 +++++
 lib/librte_pmd_bcm/bcm_ethdev.c     |   544 ++
 lib/librte_pmd_bcm/bcm_ethdev.h     |    79 +
 lib/librte_pmd_bcm/bcm_logs.h       |    51 +
 lib/librte_pmd_bcm/bcm_rxtx.c       |   487 ++
 lib/librte_pmd_bcm/bcm_rxtx.h       |    85 +
 lib/librte_pmd_bcm/bcm_stats.c      |  1619 ++++
 lib/librte_pmd_bcm/bcm_stats.h      |   633 ++
 lib/librte_pmd_bcm/bcm_vfpf.c       |   597 ++
 lib/librte_pmd_bcm/bcm_vfpf.h       |   315 +
 lib/librte_pmd_bcm/debug.c          |   113 +
 lib/librte_pmd_bcm/ecore_fw_defs.h  |   423 ++
 lib/librte_pmd_bcm/ecore_hsi.h      |  6349 ++++++++++++++++
 lib/librte_pmd_bcm/ecore_init.h     |   842 +++
 lib/librte_pmd_bcm/ecore_init_ops.h |   886 +++
 lib/librte_pmd_bcm/ecore_mfw_req.h  |   207 +
 lib/librte_pmd_bcm/ecore_reg.h      |  3664 ++++++++++
 lib/librte_pmd_bcm/ecore_sp.c       |  5455 ++++++++++++++
 lib/librte_pmd_bcm/ecore_sp.h       |  1796 +++++
 lib/librte_pmd_bcm/elink.c          | 13378 ++++++++++++++++++++++++++++++++++
 lib/librte_pmd_bcm/elink.h          |   610 ++
 24 files changed, 51977 insertions(+)
 create mode 100644 lib/librte_pmd_bcm/Makefile
 create mode 100644 lib/librte_pmd_bcm/bcm.c
 create mode 100644 lib/librte_pmd_bcm/bcm.h
 create mode 100644 lib/librte_pmd_bcm/bcm_ethdev.c
 create mode 100644 lib/librte_pmd_bcm/bcm_ethdev.h
 create mode 100644 lib/librte_pmd_bcm/bcm_logs.h
 create mode 100644 lib/librte_pmd_bcm/bcm_rxtx.c
 create mode 100644 lib/librte_pmd_bcm/bcm_rxtx.h
 create mode 100644 lib/librte_pmd_bcm/bcm_stats.c
 create mode 100644 lib/librte_pmd_bcm/bcm_stats.h
 create mode 100644 lib/librte_pmd_bcm/bcm_vfpf.c
 create mode 100644 lib/librte_pmd_bcm/bcm_vfpf.h
 create mode 100644 lib/librte_pmd_bcm/debug.c
 create mode 100644 lib/librte_pmd_bcm/ecore_fw_defs.h
 create mode 100644 lib/librte_pmd_bcm/ecore_hsi.h
 create mode 100644 lib/librte_pmd_bcm/ecore_init.h
 create mode 100644 lib/librte_pmd_bcm/ecore_init_ops.h
 create mode 100644 lib/librte_pmd_bcm/ecore_mfw_req.h
 create mode 100644 lib/librte_pmd_bcm/ecore_reg.h
 create mode 100644 lib/librte_pmd_bcm/ecore_sp.c
 create mode 100644 lib/librte_pmd_bcm/ecore_sp.h
 create mode 100644 lib/librte_pmd_bcm/elink.c
 create mode 100644 lib/librte_pmd_bcm/elink.h

diff --git a/lib/Makefile b/lib/Makefile
index d617d81..023fc9c 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -45,6 +45,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += librte_pmd_e1000
 DIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += librte_pmd_ixgbe
 DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += librte_pmd_i40e
 DIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += librte_pmd_enic
+DIRS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += librte_pmd_bcm
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += librte_pmd_bond
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += librte_pmd_ring
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += librte_pmd_pcap
diff --git a/lib/librte_pmd_bcm/Makefile b/lib/librte_pmd_bcm/Makefile
new file mode 100644
index 0000000..2f3df65
--- /dev/null
+++ b/lib/librte_pmd_bcm/Makefile
@@ -0,0 +1,28 @@
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_pmd_bcm.a
+
+CFLAGS += -O3 -g
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DZLIB_CONST
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += bcm.c
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += bcm_rxtx.c
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += bcm_stats.c
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += bcm_ethdev.c
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += ecore_sp.c
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += elink.c
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += bcm_vfpf.c
+SRCS-$(CONFIG_RTE_LIBRTE_BCM_DEBUG) += debug.c
+
+# this lib depends upon:
+DEPDIRS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += lib/librte_eal lib/librte_ether lib/librte_hash
+DEPDIRS-$(CONFIG_RTE_LIBRTE_BCM_PMD) += lib/librte_mempool lib/librte_mbuf
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/lib/librte_pmd_bcm/bcm.c b/lib/librte_pmd_bcm/bcm.c
new file mode 100644
index 0000000..26f190e
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm.c
@@ -0,0 +1,11817 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define BCM_DRIVER_VERSION "1.78.18"
+
+#include "bcm.h"
+#include "bcm_vfpf.h"
+#include "ecore_sp.h"
+#include "ecore_init.h"
+#include "ecore_init_ops.h"
+
+#include "rte_pci_dev_ids.h"
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <zlib.h>
+
+static z_stream zlib_stream;
+
+#define EVL_VLID_MASK 0x0FFF
+
+#define BCM_DEF_SB_ATT_IDX 0x0001
+#define BCM_DEF_SB_IDX     0x0002
+
+/*
+ * FLR Support - bcm_pf_flr_clnup() is called during nic_load in the per
+ * function HW initialization.
+ */
+#define FLR_WAIT_USEC     10000	/* 10 msecs */
+#define FLR_WAIT_INTERVAL 50	/* usecs */
+#define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)	/* 200 */
+
+struct pbf_pN_buf_regs {
+	int pN;
+	uint32_t init_crd;
+	uint32_t crd;
+	uint32_t crd_freed;
+};
+
+struct pbf_pN_cmd_regs {
+	int pN;
+	uint32_t lines_occup;
+	uint32_t lines_freed;
+};
+
+/* resources needed for unloading a previously loaded device */
+
+#define BCM_PREV_WAIT_NEEDED 1
+rte_spinlock_t bcm_prev_mtx;
+struct bcm_prev_list_node {
+	LIST_ENTRY(bcm_prev_list_node) node;
+	uint8_t bus;
+	uint8_t slot;
+	uint8_t path;
+	uint8_t aer;
+	uint8_t undi;
+};
+static LIST_HEAD(, bcm_prev_list_node) bcm_prev_list =
+LIST_HEAD_INITIALIZER(bcm_prev_list);
+
+static int load_count[2][3] = { {0} };	/* per-path: 0-common, 1-port0, 2-port1 */
+
+static void bcm_cmng_fns_init(struct bcm_softc *sc, uint8_t read_cfg,
+			      uint8_t cmng_type);
+static int bcm_get_cmng_fns_mode(struct bcm_softc *sc);
+static void storm_memset_cmng(struct bcm_softc *sc, struct cmng_init *cmng,
+			      uint8_t port);
+static void bcm_set_reset_global(struct bcm_softc *sc);
+static void bcm_set_reset_in_progress(struct bcm_softc *sc);
+static uint8_t bcm_reset_is_done(struct bcm_softc *sc, int engine);
+static uint8_t bcm_clear_pf_load(struct bcm_softc *sc);
+static uint8_t bcm_chk_parity_attn(struct bcm_softc *sc, uint8_t * global,
+				   uint8_t print);
+static void bcm_int_disable(struct bcm_softc *sc);
+static int bcm_release_leader_lock(struct bcm_softc *sc);
+static void bcm_pf_disable(struct bcm_softc *sc);
+static void bcm_update_rx_prod(struct bcm_softc *sc, struct bcm_fastpath *fp,
+			       uint16_t rx_bd_prod, uint16_t rx_cq_prod);
+static void bcm_link_report(struct bcm_softc *sc);
+void bcm_link_status_update(struct bcm_softc *sc);
+static int bcm_alloc_mem(struct bcm_softc *sc);
+static void bcm_free_mem(struct bcm_softc *sc);
+static int bcm_alloc_fw_stats_mem(struct bcm_softc *sc);
+static void bcm_free_fw_stats_mem(struct bcm_softc *sc);
+static __attribute__ ((noinline))
+int bcm_nic_load(struct bcm_softc *sc);
+
+static int bcm_handle_sp_tq(struct bcm_softc *sc);
+static void bcm_handle_fp_tq(struct bcm_fastpath *fp, int scan_fp);
+static void bcm_periodic_stop(struct bcm_softc *sc);
+static void bcm_ack_sb(struct bcm_softc *sc, uint8_t igu_sb_id, uint8_t storm,
+		       uint16_t index, uint8_t op, uint8_t update);
+
+int bcm_test_bit(int nr, volatile unsigned long *addr)
+{
+	int res;
+	mb();
+	res = ((*addr) & (1UL << nr)) != 0;
+	mb();
+	return res;
+}
+
+void bcm_set_bit(unsigned int nr, volatile unsigned long *addr)
+{
+	__sync_fetch_and_or(addr, (1UL << nr));
+}
+
+void bcm_clear_bit(int nr, volatile unsigned long *addr)
+{
+	__sync_fetch_and_and(addr, ~(1UL << nr));
+}
+
+int bcm_test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = (1UL << nr);
+	return __sync_fetch_and_and(addr, ~mask) & mask;
+}
+
+int bcm_cmpxchg(volatile int *addr, int old, int new)
+{
+	return __sync_val_compare_and_swap(addr, old, new);
+}
+
+int
+bcm_dma_alloc(struct bcm_softc *sc, size_t size, struct bcm_dma *dma,
+	      const char *msg, uint32_t align)
+{
+	char mz_name[RTE_MEMZONE_NAMESIZE];
+	const struct rte_memzone *z;
+
+	dma->sc = sc;
+	if (IS_PF(sc))
+		sprintf(mz_name, "bcm%d_%s_%lx", SC_ABS_FUNC(sc), msg,
+			rte_get_timer_cycles());
+	else
+		sprintf(mz_name, "bcm%d_%s_%lx", sc->pcie_device, msg,
+			rte_get_timer_cycles());
+
+	/* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
+	z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
+					rte_lcore_to_socket_id(rte_lcore_id()),
+					0, align);
+	if (z == NULL) {
+		PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
+		return -ENOMEM;
+	}
+	dma->paddr = (uint64_t) z->phys_addr;
+	dma->vaddr = z->addr;
+
+	PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%lx", msg, dma->vaddr, dma->paddr);
+
+	return 0;
+}
+
+static int bcm_acquire_hw_lock(struct bcm_softc *sc, uint32_t resource)
+{
+	uint32_t lock_status;
+	uint32_t resource_bit = (1 << resource);
+	int func = SC_FUNC(sc);
+	uint32_t hw_lock_control_reg;
+	int cnt;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/* validate the resource is within range */
+	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
+		PMD_DRV_LOG(NOTICE,
+			    "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
+			    resource);
+		return -1;
+	}
+
+	if (func <= 5) {
+		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
+	} else {
+		hw_lock_control_reg =
+		    (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
+	}
+
+	/* validate the resource is not already taken */
+	lock_status = REG_RD(sc, hw_lock_control_reg);
+	if (lock_status & resource_bit) {
+		PMD_DRV_LOG(NOTICE,
+			    "resource in use (status 0x%x bit 0x%x)",
+			    lock_status, resource_bit);
+		return -1;
+	}
+
+	/* try every 5ms for 5 seconds */
+	for (cnt = 0; cnt < 1000; cnt++) {
+		REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
+		lock_status = REG_RD(sc, hw_lock_control_reg);
+		if (lock_status & resource_bit) {
+			return 0;
+		}
+		DELAY(5000);
+	}
+
+	PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
+	return -1;
+}
+
+static int bcm_release_hw_lock(struct bcm_softc *sc, uint32_t resource)
+{
+	uint32_t lock_status;
+	uint32_t resource_bit = (1 << resource);
+	int func = SC_FUNC(sc);
+	uint32_t hw_lock_control_reg;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/* validate the resource is within range */
+	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
+		PMD_DRV_LOG(NOTICE,
+			    "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
+			    resource);
+		return -1;
+	}
+
+	if (func <= 5) {
+		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
+	} else {
+		hw_lock_control_reg =
+		    (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
+	}
+
+	/* validate the resource is currently taken */
+	lock_status = REG_RD(sc, hw_lock_control_reg);
+	if (!(lock_status & resource_bit)) {
+		PMD_DRV_LOG(NOTICE,
+			    "resource not in use (status 0x%x bit 0x%x)",
+			    lock_status, resource_bit);
+		return -1;
+	}
+
+	REG_WR(sc, hw_lock_control_reg, resource_bit);
+	return 0;
+}
+
+/* copy command into DMAE command memory and set DMAE command Go */
+void bcm_post_dmae(struct bcm_softc *sc, struct dmae_command *dmae, int idx)
+{
+	uint32_t cmd_offset;
+	uint32_t i;
+
+	cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
+	for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
+		REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
+	}
+
+	REG_WR(sc, dmae_reg_go_c[idx], 1);
+}
+
+uint32_t bcm_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
+{
+	return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
+			  DMAE_COMMAND_C_TYPE_ENABLE));
+}
+
+uint32_t bcm_dmae_opcode_clr_src_reset(uint32_t opcode)
+{
+	return (opcode & ~DMAE_COMMAND_SRC_RESET);
+}
+
+uint32_t
+bcm_dmae_opcode(struct bcm_softc * sc, uint8_t src_type, uint8_t dst_type,
+		uint8_t with_comp, uint8_t comp_type)
+{
+	uint32_t opcode = 0;
+
+	opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
+		   (dst_type << DMAE_COMMAND_DST_SHIFT));
+
+	opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
+
+	opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
+
+	opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
+		   (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
+
+	opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
+
+#ifdef __BIG_ENDIAN
+	opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
+#else
+	opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
+#endif
+
+	if (with_comp) {
+		opcode = bcm_dmae_opcode_add_comp(opcode, comp_type);
+	}
+
+	return opcode;
+}
+
+static void
+bcm_prep_dmae_with_comp(struct bcm_softc *sc, struct dmae_command *dmae,
+			uint8_t src_type, uint8_t dst_type)
+{
+	memset(dmae, 0, sizeof(struct dmae_command));
+
+	/* set the opcode */
+	dmae->opcode = bcm_dmae_opcode(sc, src_type, dst_type,
+				       TRUE, DMAE_COMP_PCI);
+
+	/* fill in the completion parameters */
+	dmae->comp_addr_lo = U64_LO(BCM_SP_MAPPING(sc, wb_comp));
+	dmae->comp_addr_hi = U64_HI(BCM_SP_MAPPING(sc, wb_comp));
+	dmae->comp_val = DMAE_COMP_VAL;
+}
+
+/* issue a DMAE command over the init channel and wait for completion */
+static int
+bcm_issue_dmae_with_comp(struct bcm_softc *sc, struct dmae_command *dmae)
+{
+	uint32_t *wb_comp = BCM_SP(sc, wb_comp);
+	int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
+
+	/* reset completion */
+	*wb_comp = 0;
+
+	/* post the command on the channel used for initializations */
+	bcm_post_dmae(sc, dmae, INIT_DMAE_C(sc));
+
+	/* wait for completion */
+	DELAY(500);
+
+	while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
+		if (!timeout ||
+		    (sc->recovery_state != BCM_RECOVERY_DONE &&
+		     sc->recovery_state != BCM_RECOVERY_NIC_LOADING)) {
+			PMD_DRV_LOG(INFO, "DMAE timeout!");
+			return DMAE_TIMEOUT;
+		}
+
+		timeout--;
+		DELAY(50);
+	}
+
+	if (*wb_comp & DMAE_PCI_ERR_FLAG) {
+		PMD_DRV_LOG(INFO, "DMAE PCI error!");
+		return DMAE_PCI_ERROR;
+	}
+
+	return 0;
+}
+
+void bcm_read_dmae(struct bcm_softc *sc, uint32_t src_addr, uint32_t len32)
+{
+	struct dmae_command dmae;
+	uint32_t *data;
+	uint32_t i;
+	int rc;
+
+	if (!sc->dmae_ready) {
+		data = BCM_SP(sc, wb_data[0]);
+
+		for (i = 0; i < len32; i++) {
+			data[i] = REG_RD(sc, (src_addr + (i * 4)));
+		}
+
+		return;
+	}
+
+	/* set opcode and fixed command fields */
+	bcm_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
+
+	/* fill in addresses and len */
+	dmae.src_addr_lo = (src_addr >> 2);	/* GRC addr has dword resolution */
+	dmae.src_addr_hi = 0;
+	dmae.dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, wb_data));
+	dmae.dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, wb_data));
+	dmae.len = len32;
+
+	/* issue the command and wait for completion */
+	if ((rc = bcm_issue_dmae_with_comp(sc, &dmae)) != 0) {
+		rte_panic("DMAE failed (%d)", rc);
+	};
+}
+
+void
+bcm_write_dmae(struct bcm_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
+	       uint32_t len32)
+{
+	struct dmae_command dmae;
+	int rc;
+
+	if (!sc->dmae_ready) {
+		ecore_init_str_wr(sc, dst_addr, BCM_SP(sc, wb_data[0]), len32);
+		return;
+	}
+
+	/* set opcode and fixed command fields */
+	bcm_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
+
+	/* fill in addresses and len */
+	dmae.src_addr_lo = U64_LO(dma_addr);
+	dmae.src_addr_hi = U64_HI(dma_addr);
+	dmae.dst_addr_lo = (dst_addr >> 2);	/* GRC addr has dword resolution */
+	dmae.dst_addr_hi = 0;
+	dmae.len = len32;
+
+	/* issue the command and wait for completion */
+	if ((rc = bcm_issue_dmae_with_comp(sc, &dmae)) != 0) {
+		rte_panic("DMAE failed (%d)", rc);
+	}
+}
+
+static void
+bcm_write_dmae_phys_len(struct bcm_softc *sc, phys_addr_t phys_addr,
+			uint32_t addr, uint32_t len)
+{
+	uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
+	uint32_t offset = 0;
+
+	while (len > dmae_wr_max) {
+		bcm_write_dmae(sc, (phys_addr + offset),	/* src DMA address */
+			       (addr + offset),	/* dst GRC address */
+			       dmae_wr_max);
+		offset += (dmae_wr_max * 4);
+		len -= dmae_wr_max;
+	}
+
+	bcm_write_dmae(sc, (phys_addr + offset),	/* src DMA address */
+		       (addr + offset),	/* dst GRC address */
+		       len);
+}
+
+void
+bcm_set_ctx_validation(struct bcm_softc *sc, struct eth_context *cxt,
+		       uint32_t cid)
+{
+	/* ustorm cxt validation */
+	cxt->ustorm_ag_context.cdu_usage =
+	    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
+				   CDU_REGION_NUMBER_UCM_AG,
+				   ETH_CONNECTION_TYPE);
+	/* xcontext validation */
+	cxt->xstorm_ag_context.cdu_reserved =
+	    CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
+				   CDU_REGION_NUMBER_XCM_AG,
+				   ETH_CONNECTION_TYPE);
+}
+
+static void
+bcm_storm_memset_hc_timeout(struct bcm_softc *sc, uint8_t fw_sb_id,
+			    uint8_t sb_index, uint8_t ticks)
+{
+	uint32_t addr =
+	    (BAR_CSTRORM_INTMEM +
+	     CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
+
+	REG_WR8(sc, addr, ticks);
+}
+
+static void
+bcm_storm_memset_hc_disable(struct bcm_softc *sc, uint16_t fw_sb_id,
+			    uint8_t sb_index, uint8_t disable)
+{
+	uint32_t enable_flag =
+	    (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
+	uint32_t addr =
+	    (BAR_CSTRORM_INTMEM +
+	     CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
+	uint8_t flags;
+
+	/* clear and set */
+	flags = REG_RD8(sc, addr);
+	flags &= ~HC_INDEX_DATA_HC_ENABLED;
+	flags |= enable_flag;
+	REG_WR8(sc, addr, flags);
+}
+
+void
+bcm_update_coalesce_sb_index(struct bcm_softc *sc, uint8_t fw_sb_id,
+			     uint8_t sb_index, uint8_t disable, uint16_t usec)
+{
+	uint8_t ticks = (usec / 4);
+
+	bcm_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
+
+	disable = (disable) ? 1 : ((usec) ? 0 : 1);
+	bcm_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
+}
+
+uint32_t elink_cb_reg_read(struct bcm_softc *sc, uint32_t reg_addr)
+{
+	return REG_RD(sc, reg_addr);
+}
+
+void elink_cb_reg_write(struct bcm_softc *sc, uint32_t reg_addr, uint32_t val)
+{
+	REG_WR(sc, reg_addr, val);
+}
+
+void
+elink_cb_event_log(__rte_unused struct bcm_softc *sc,
+		   __rte_unused const elink_log_id_t elink_log_id, ...)
+{
+	PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
+}
+
+static int bcm_set_spio(struct bcm_softc *sc, int spio, uint32_t mode)
+{
+	uint32_t spio_reg;
+
+	/* Only 2 SPIOs are configurable */
+	if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
+		PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
+		return -1;
+	}
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
+
+	/* read SPIO and mask except the float bits */
+	spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
+
+	switch (mode) {
+	case MISC_SPIO_OUTPUT_LOW:
+		/* clear FLOAT and set CLR */
+		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
+		spio_reg |= (spio << MISC_SPIO_CLR_POS);
+		break;
+
+	case MISC_SPIO_OUTPUT_HIGH:
+		/* clear FLOAT and set SET */
+		spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
+		spio_reg |= (spio << MISC_SPIO_SET_POS);
+		break;
+
+	case MISC_SPIO_INPUT_HI_Z:
+		/* set FLOAT */
+		spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
+		break;
+
+	default:
+		break;
+	}
+
+	REG_WR(sc, MISC_REG_SPIO, spio_reg);
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
+
+	return 0;
+}
+
+static int bcm_gpio_read(struct bcm_softc *sc, int gpio_num, uint8_t port)
+{
+	/* The GPIO should be swapped if swap register is set and active */
+	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
+			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
+	int gpio_shift = gpio_num;
+	if (gpio_port)
+		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
+
+	uint32_t gpio_mask = (1 << gpio_shift);
+	uint32_t gpio_reg;
+
+	if (gpio_num > MISC_REGISTERS_GPIO_3) {
+		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
+		return -1;
+	}
+
+	/* read GPIO value */
+	gpio_reg = REG_RD(sc, MISC_REG_GPIO);
+
+	/* get the requested pin value */
+	return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
+}
+
+static int
+bcm_gpio_write(struct bcm_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
+{
+	/* The GPIO should be swapped if swap register is set and active */
+	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
+			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
+	int gpio_shift = gpio_num;
+	if (gpio_port)
+		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
+
+	uint32_t gpio_mask = (1 << gpio_shift);
+	uint32_t gpio_reg;
+
+	if (gpio_num > MISC_REGISTERS_GPIO_3) {
+		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
+		return -1;
+	}
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+
+	/* read GPIO and mask except the float bits */
+	gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
+
+	switch (mode) {
+	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
+		/* clear FLOAT and set CLR */
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
+		break;
+
+	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
+		/* clear FLOAT and set SET */
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
+		break;
+
+	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
+		/* set FLOAT */
+		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
+		break;
+
+	default:
+		break;
+	}
+
+	REG_WR(sc, MISC_REG_GPIO, gpio_reg);
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+
+	return 0;
+}
+
+static int
+bcm_gpio_mult_write(struct bcm_softc *sc, uint8_t pins, uint32_t mode)
+{
+	uint32_t gpio_reg;
+
+	/* any port swapping should be handled by caller */
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+
+	/* read GPIO and mask except the float bits */
+	gpio_reg = REG_RD(sc, MISC_REG_GPIO);
+	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
+	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
+	gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
+
+	switch (mode) {
+	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
+		/* set CLR */
+		gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
+		break;
+
+	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
+		/* set SET */
+		gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
+		break;
+
+	case MISC_REGISTERS_GPIO_INPUT_HI_Z:
+		/* set FLOAT */
+		gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
+		break;
+
+	default:
+		PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
+		bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+		return -1;
+	}
+
+	REG_WR(sc, MISC_REG_GPIO, gpio_reg);
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+
+	return 0;
+}
+
+static int
+bcm_gpio_int_write(struct bcm_softc *sc, int gpio_num, uint32_t mode,
+		   uint8_t port)
+{
+	/* The GPIO should be swapped if swap register is set and active */
+	int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
+			  REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
+	int gpio_shift = gpio_num;
+	if (gpio_port)
+		gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
+
+	uint32_t gpio_mask = (1 << gpio_shift);
+	uint32_t gpio_reg;
+
+	if (gpio_num > MISC_REGISTERS_GPIO_3) {
+		PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
+		return -1;
+	}
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+
+	/* read GPIO int */
+	gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
+
+	switch (mode) {
+	case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
+		/* clear SET and set CLR */
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
+		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
+		break;
+
+	case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
+		/* clear CLR and set SET */
+		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
+		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
+		break;
+
+	default:
+		break;
+	}
+
+	REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
+
+	return 0;
+}
+
+uint32_t
+elink_cb_gpio_read(struct bcm_softc * sc, uint16_t gpio_num, uint8_t port)
+{
+	return bcm_gpio_read(sc, gpio_num, port);
+}
+
+uint8_t elink_cb_gpio_write(struct bcm_softc * sc, uint16_t gpio_num, uint8_t mode,	/* 0=low 1=high */
+			    uint8_t port)
+{
+	return bcm_gpio_write(sc, gpio_num, mode, port);
+}
+
+uint8_t
+elink_cb_gpio_mult_write(struct bcm_softc * sc, uint8_t pins,
+			 uint8_t mode /* 0=low 1=high */ )
+{
+	return bcm_gpio_mult_write(sc, pins, mode);
+}
+
+uint8_t elink_cb_gpio_int_write(struct bcm_softc * sc, uint16_t gpio_num, uint8_t mode,	/* 0=low 1=high */
+				uint8_t port)
+{
+	return bcm_gpio_int_write(sc, gpio_num, mode, port);
+}
+
+void elink_cb_notify_link_changed(struct bcm_softc *sc)
+{
+	REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
+		    (SC_FUNC(sc) * sizeof(uint32_t))), 1);
+}
+
+/* send the MCP a request, block until there is a reply */
+uint32_t
+elink_cb_fw_command(struct bcm_softc *sc, uint32_t command, uint32_t param)
+{
+	int mb_idx = SC_FW_MB_IDX(sc);
+	uint32_t seq;
+	uint32_t rc = 0;
+	uint32_t cnt = 1;
+	uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
+
+	seq = ++sc->fw_seq;
+	SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
+	SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
+
+	PMD_DRV_LOG(DEBUG,
+		    "wrote command 0x%08x to FW MB param 0x%08x",
+		    (command | seq), param);
+
+	/* Let the FW do it's magic. GIve it up to 5 seconds... */
+	do {
+		DELAY(delay * 1000);
+		rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
+	} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
+
+	/* is this a reply to our command? */
+	if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
+		rc &= FW_MSG_CODE_MASK;
+	} else {
+		/* Ruh-roh! */
+		PMD_DRV_LOG(NOTICE, "FW failed to respond!");
+		rc = 0;
+	}
+
+	return rc;
+}
+
+static uint32_t
+bcm_fw_command(struct bcm_softc *sc, uint32_t command, uint32_t param)
+{
+	return elink_cb_fw_command(sc, command, param);
+}
+
+static void
+__storm_memset_dma_mapping(struct bcm_softc *sc, uint32_t addr,
+			   phys_addr_t mapping)
+{
+	REG_WR(sc, addr, U64_LO(mapping));
+	REG_WR(sc, (addr + 4), U64_HI(mapping));
+}
+
+static void
+storm_memset_spq_addr(struct bcm_softc *sc, phys_addr_t mapping,
+		      uint16_t abs_fid)
+{
+	uint32_t addr = (XSEM_REG_FAST_MEMORY +
+			 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
+	__storm_memset_dma_mapping(sc, addr, mapping);
+}
+
+static void
+storm_memset_vf_to_pf(struct bcm_softc *sc, uint16_t abs_fid, uint16_t pf_id)
+{
+	REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
+		pf_id);
+	REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
+		pf_id);
+	REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
+		pf_id);
+	REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
+		pf_id);
+}
+
+static void
+storm_memset_func_en(struct bcm_softc *sc, uint16_t abs_fid, uint8_t enable)
+{
+	REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
+		enable);
+	REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
+		enable);
+	REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
+		enable);
+	REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
+		enable);
+}
+
+static void
+storm_memset_eq_data(struct bcm_softc *sc, struct event_ring_data *eq_data,
+		     uint16_t pfid)
+{
+	uint32_t addr;
+	size_t size;
+
+	addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
+	size = sizeof(struct event_ring_data);
+	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
+}
+
+static void
+storm_memset_eq_prod(struct bcm_softc *sc, uint16_t eq_prod, uint16_t pfid)
+{
+	uint32_t addr = (BAR_CSTRORM_INTMEM +
+			 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
+	REG_WR16(sc, addr, eq_prod);
+}
+
+/*
+ * Post a slowpath command.
+ *
+ * A slowpath command is used to propogate a configuration change through
+ * the controller in a controlled manner, allowing each STORM processor and
+ * other H/W blocks to phase in the change.  The commands sent on the
+ * slowpath are referred to as ramrods.  Depending on the ramrod used the
+ * completion of the ramrod will occur in different ways.  Here's a
+ * breakdown of ramrods and how they complete:
+ *
+ * RAMROD_CMD_ID_ETH_PORT_SETUP
+ *   Used to setup the leading connection on a port.  Completes on the
+ *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
+ *
+ * RAMROD_CMD_ID_ETH_CLIENT_SETUP
+ *   Used to setup an additional connection on a port.  Completes on the
+ *   RCQ of the multi-queue/RSS connection being initialized.
+ *
+ * RAMROD_CMD_ID_ETH_STAT_QUERY
+ *   Used to force the storm processors to update the statistics database
+ *   in host memory.  This ramrod is send on the leading connection CID and
+ *   completes as an index increment of the CSTORM on the default status
+ *   block.
+ *
+ * RAMROD_CMD_ID_ETH_UPDATE
+ *   Used to update the state of the leading connection, usually to udpate
+ *   the RSS indirection table.  Completes on the RCQ of the leading
+ *   connection. (Not currently used under FreeBSD until OS support becomes
+ *   available.)
+ *
+ * RAMROD_CMD_ID_ETH_HALT
+ *   Used when tearing down a connection prior to driver unload.  Completes
+ *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
+ *   use this on the leading connection.
+ *
+ * RAMROD_CMD_ID_ETH_SET_MAC
+ *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
+ *   the RCQ of the leading connection.
+ *
+ * RAMROD_CMD_ID_ETH_CFC_DEL
+ *   Used when tearing down a conneciton prior to driver unload.  Completes
+ *   on the RCQ of the leading connection (since the current connection
+ *   has been completely removed from controller memory).
+ *
+ * RAMROD_CMD_ID_ETH_PORT_DEL
+ *   Used to tear down the leading connection prior to driver unload,
+ *   typically fp[0].  Completes as an index increment of the CSTORM on the
+ *   default status block.
+ *
+ * RAMROD_CMD_ID_ETH_FORWARD_SETUP
+ *   Used for connection offload.  Completes on the RCQ of the multi-queue
+ *   RSS connection that is being offloaded.  (Not currently used under
+ *   FreeBSD.)
+ *
+ * There can only be one command pending per function.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure.
+ */
+
+/* must be called under the spq lock */
+static inline struct eth_spe *bcm_sp_get_next(struct bcm_softc *sc)
+{
+	struct eth_spe *next_spe = sc->spq_prod_bd;
+
+	if (sc->spq_prod_bd == sc->spq_last_bd) {
+		/* wrap back to the first eth_spq */
+		sc->spq_prod_bd = sc->spq;
+		sc->spq_prod_idx = 0;
+	} else {
+		sc->spq_prod_bd++;
+		sc->spq_prod_idx++;
+	}
+
+	return next_spe;
+}
+
+/* must be called under the spq lock */
+static void bcm_sp_prod_update(struct bcm_softc *sc)
+{
+	int func = SC_FUNC(sc);
+
+	/*
+	 * Make sure that BD data is updated before writing the producer.
+	 * BD data is written to the memory, the producer is read from the
+	 * memory, thus we need a full memory barrier to ensure the ordering.
+	 */
+	mb();
+
+	REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
+		 sc->spq_prod_idx);
+
+	mb();
+}
+
+/**
+ * bcm_is_contextless_ramrod - check if the current command ends on EQ
+ *
+ * @cmd:      command to check
+ * @cmd_type: command type
+ */
+static int bcm_is_contextless_ramrod(int cmd, int cmd_type)
+{
+	if ((cmd_type == NONE_CONNECTION_TYPE) ||
+	    (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
+	    (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
+	    (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
+	    (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
+	    (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
+	    (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
+		return TRUE;
+	} else {
+		return FALSE;
+	}
+}
+
+/**
+ * bcm_sp_post - place a single command on an SP ring
+ *
+ * @sc:         driver handle
+ * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
+ * @cid:        SW CID the command is related to
+ * @data_hi:    command private data address (high 32 bits)
+ * @data_lo:    command private data address (low 32 bits)
+ * @cmd_type:   command type (e.g. NONE, ETH)
+ *
+ * SP data is handled as if it's always an address pair, thus data fields are
+ * not swapped to little endian in upper functions. Instead this function swaps
+ * data as if it's two uint32 fields.
+ */
+int
+bcm_sp_post(struct bcm_softc *sc, int command, int cid, uint32_t data_hi,
+	    uint32_t data_lo, int cmd_type)
+{
+	struct eth_spe *spe;
+	uint16_t type;
+	int common;
+
+	common = bcm_is_contextless_ramrod(command, cmd_type);
+
+	if (common) {
+		if (!atomic_load_acq_long(&sc->eq_spq_left)) {
+			PMD_DRV_LOG(INFO, "EQ ring is full!");
+			return -1;
+		}
+	} else {
+		if (!atomic_load_acq_long(&sc->cq_spq_left)) {
+			PMD_DRV_LOG(INFO, "SPQ ring is full!");
+			return -1;
+		}
+	}
+
+	spe = bcm_sp_get_next(sc);
+
+	/* CID needs port number to be encoded int it */
+	spe->hdr.conn_and_cmd_data =
+	    htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
+
+	type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
+
+	/* TBD: Check if it works for VFs */
+	type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
+		 SPE_HDR_FUNCTION_ID);
+
+	spe->hdr.type = htole16(type);
+
+	spe->data.update_data_addr.hi = htole32(data_hi);
+	spe->data.update_data_addr.lo = htole32(data_lo);
+
+	/*
+	 * It's ok if the actual decrement is issued towards the memory
+	 * somewhere between the lock and unlock. Thus no more explict
+	 * memory barrier is needed.
+	 */
+	if (common) {
+		atomic_subtract_acq_long(&sc->eq_spq_left, 1);
+	} else {
+		atomic_subtract_acq_long(&sc->cq_spq_left, 1);
+	}
+
+	PMD_DRV_LOG(DEBUG,
+		    "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
+		    "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
+		    sc->spq_prod_idx,
+		    (uint32_t) U64_HI(sc->spq_dma.paddr),
+		    (uint32_t) (U64_LO(sc->spq_dma.paddr) +
+				(uint8_t *) sc->spq_prod_bd -
+				(uint8_t *) sc->spq), command, common,
+		    HW_CID(sc, cid), data_hi, data_lo, type,
+		    atomic_load_acq_long(&sc->cq_spq_left),
+		    atomic_load_acq_long(&sc->eq_spq_left));
+
+	bcm_sp_prod_update(sc);
+
+	return 0;
+}
+
+static void bcm_drv_pulse(struct bcm_softc *sc)
+{
+	SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
+		 sc->fw_drv_pulse_wr_seq);
+}
+
+static int bcm_tx_queue_has_work(const struct bcm_fastpath *fp)
+{
+	uint16_t hw_cons;
+	struct bcm_tx_queue *txq = fp->sc->tx_queues[fp->index];
+
+	if (unlikely(!txq)) {
+		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
+		return 0;
+	}
+
+	mb();			/* status block fields can change */
+	hw_cons = le16toh(*fp->tx_cons_sb);
+	return (hw_cons != txq->tx_pkt_head);
+}
+
+static uint8_t bcm_has_tx_work(struct bcm_fastpath *fp)
+{
+	/* expand this for multi-cos if ever supported */
+	return bcm_tx_queue_has_work(fp);
+}
+
+static int bcm_has_rx_work(struct bcm_fastpath *fp)
+{
+	uint16_t rx_cq_cons_sb;
+	struct bcm_rx_queue *rxq;
+	rxq = fp->sc->rx_queues[fp->index];
+	if (unlikely(!rxq)) {
+		PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
+		return 0;
+	}
+
+	mb();			/* status block fields can change */
+	rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
+	if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
+		     MAX_RCQ_ENTRIES(rxq)))
+		rx_cq_cons_sb++;
+	return (rxq->rx_cq_head != rx_cq_cons_sb);
+}
+
+static void
+bcm_sp_event(struct bcm_softc *sc, struct bcm_fastpath *fp,
+	     union eth_rx_cqe *rr_cqe)
+{
+#ifdef RTE_LIBRTE_BCM_DEBUG
+	int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+#endif
+	int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+	enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
+	struct ecore_queue_sp_obj *q_obj = &BCM_SP_OBJ(sc, fp).q_obj;
+
+	PMD_DRV_LOG(DEBUG,
+		    "fp=%d cid=%d got ramrod #%d state is %x type is %d",
+		    fp->index, cid, command, sc->state,
+		    rr_cqe->ramrod_cqe.ramrod_type);
+
+	switch (command) {
+	case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
+		PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
+		drv_cmd = ECORE_Q_CMD_UPDATE;
+		break;
+
+	case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
+		PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
+		drv_cmd = ECORE_Q_CMD_SETUP;
+		break;
+
+	case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
+		PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
+		drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
+		break;
+
+	case (RAMROD_CMD_ID_ETH_HALT):
+		PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
+		drv_cmd = ECORE_Q_CMD_HALT;
+		break;
+
+	case (RAMROD_CMD_ID_ETH_TERMINATE):
+		PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
+		drv_cmd = ECORE_Q_CMD_TERMINATE;
+		break;
+
+	case (RAMROD_CMD_ID_ETH_EMPTY):
+		PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
+		drv_cmd = ECORE_Q_CMD_EMPTY;
+		break;
+
+	default:
+		PMD_DRV_LOG(DEBUG,
+			    "ERROR: unexpected MC reply (%d)"
+			    "on fp[%d]", command, fp->index);
+		return;
+	}
+
+	if ((drv_cmd != ECORE_Q_CMD_MAX) &&
+	    q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
+		/*
+		 * q_obj->complete_cmd() failure means that this was
+		 * an unexpected completion.
+		 *
+		 * In this case we don't want to increase the sc->spq_left
+		 * because apparently we haven't sent this command the first
+		 * place.
+		 */
+		// rte_panic("Unexpected SP completion");
+		return;
+	}
+
+	atomic_add_acq_long(&sc->cq_spq_left, 1);
+
+	PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
+		    atomic_load_acq_long(&sc->cq_spq_left));
+}
+
+static uint8_t bcm_rxeof(struct bcm_softc *sc, struct bcm_fastpath *fp)
+{
+	struct bcm_rx_queue *rxq;
+	uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
+	uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
+
+	rxq = sc->rx_queues[fp->index];
+	if (!rxq) {
+		PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
+		return 0;
+	}
+
+	/* CQ "next element" is of the size of the regular element */
+	hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
+	if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
+		     USABLE_RCQ_ENTRIES_PER_PAGE)) {
+		hw_cq_cons++;
+	}
+
+	bd_cons = rxq->rx_bd_head;
+	bd_prod = rxq->rx_bd_tail;
+	bd_prod_fw = bd_prod;
+	sw_cq_cons = rxq->rx_cq_head;
+	sw_cq_prod = rxq->rx_cq_tail;
+
+	/*
+	 * Memory barrier necessary as speculative reads of the rx
+	 * buffer can be ahead of the index in the status block
+	 */
+	rmb();
+
+	while (sw_cq_cons != hw_cq_cons) {
+		union eth_rx_cqe *cqe;
+		struct eth_fast_path_rx_cqe *cqe_fp;
+		uint8_t cqe_fp_flags;
+		enum eth_rx_cqe_type cqe_fp_type;
+
+		comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
+		bd_prod = RX_BD(bd_prod, rxq);
+		bd_cons = RX_BD(bd_cons, rxq);
+
+		cqe = &rxq->cq_ring[comp_ring_cons];
+		cqe_fp = &cqe->fast_path_cqe;
+		cqe_fp_flags = cqe_fp->type_error_flags;
+		cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
+
+		/* is this a slowpath msg? */
+		if (CQE_TYPE_SLOW(cqe_fp_type)) {
+			bcm_sp_event(sc, fp, cqe);
+			goto next_cqe;
+		}
+
+		/* is this an error packet? */
+		if (unlikely(cqe_fp_flags &
+			     ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
+			PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
+				   cqe_fp_flags, sw_cq_cons);
+			goto next_rx;
+		}
+
+		PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
+
+next_rx:
+		bd_cons = NEXT_RX_BD(bd_cons);
+		bd_prod = NEXT_RX_BD(bd_prod);
+		bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
+
+next_cqe:
+		sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
+		sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
+
+	}			/* while work to do */
+
+	rxq->rx_bd_head = bd_cons;
+	rxq->rx_bd_tail = bd_prod_fw;
+	rxq->rx_cq_head = sw_cq_cons;
+	rxq->rx_cq_tail = sw_cq_prod;
+
+	/* Update producers */
+	bcm_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
+
+	return (sw_cq_cons != hw_cq_cons);
+}
+
+static uint16_t
+bcm_free_tx_pkt(__rte_unused struct bcm_fastpath *fp, struct bcm_tx_queue *txq,
+		uint16_t pkt_idx, uint16_t bd_idx)
+{
+	struct eth_tx_start_bd *tx_start_bd =
+	    &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
+	uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
+	struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
+
+	if (likely(tx_mbuf != NULL)) {
+		rte_pktmbuf_free(tx_mbuf);
+	} else {
+		PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
+			   fp->index, TX_BD(pkt_idx, txq));
+	}
+
+	txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
+	txq->nb_tx_avail += nbd;
+
+	while (nbd--)
+		bd_idx = NEXT_TX_BD(bd_idx);
+
+	return bd_idx;
+}
+
+/* processes transmit completions */
+uint8_t bcm_txeof(__rte_unused struct bcm_softc * sc, struct bcm_fastpath * fp)
+{
+	uint16_t bd_cons, hw_cons, sw_cons;
+	__rte_unused uint16_t tx_bd_avail;
+
+	struct bcm_tx_queue *txq = fp->sc->tx_queues[fp->index];
+
+	if (unlikely(!txq)) {
+		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
+		return 0;
+	}
+
+	bd_cons = txq->tx_bd_head;
+	hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
+	sw_cons = txq->tx_pkt_head;
+
+	while (sw_cons != hw_cons) {
+		bd_cons = bcm_free_tx_pkt(fp, txq, sw_cons, bd_cons);
+		sw_cons++;
+	}
+
+	txq->tx_pkt_head = sw_cons;
+	txq->tx_bd_head = bd_cons;
+
+	tx_bd_avail = txq->nb_tx_avail;
+
+	PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
+		   "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
+		   fp->index, tx_bd_avail, hw_cons,
+		   txq->tx_pkt_head, txq->tx_pkt_tail,
+		   txq->tx_bd_head, txq->tx_bd_tail);
+	return TRUE;
+}
+
+static void bcm_drain_tx_queues(struct bcm_softc *sc)
+{
+	struct bcm_fastpath *fp;
+	int i, count;
+
+	/* wait until all TX fastpath tasks have completed */
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+
+		count = 1000;
+
+		while (bcm_has_tx_work(fp)) {
+			bcm_txeof(sc, fp);
+
+			if (count == 0) {
+				PMD_TX_LOG(ERR,
+					   "Timeout waiting for fp[%d] "
+					   "transmits to complete!", i);
+				rte_panic("tx drain failure");
+				return;
+			}
+
+			count--;
+			DELAY(1000);
+			rmb();
+		}
+	}
+
+	return;
+}
+
+static int
+bcm_del_all_macs(struct bcm_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
+		 int mac_type, uint8_t wait_for_comp)
+{
+	unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
+	int rc;
+
+	/* wait for completion of requested */
+	if (wait_for_comp) {
+		bcm_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
+	}
+
+	/* Set the mac type of addresses we want to clear */
+	bcm_set_bit(mac_type, &vlan_mac_flags);
+
+	rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
+	if (rc < 0)
+		PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
+
+	return rc;
+}
+
+int
+bcm_fill_accept_flags(struct bcm_softc *sc, uint32_t rx_mode,
+		      unsigned long *rx_accept_flags,
+		      unsigned long *tx_accept_flags)
+{
+	/* Clear the flags first */
+	*rx_accept_flags = 0;
+	*tx_accept_flags = 0;
+
+	switch (rx_mode) {
+	case BCM_RX_MODE_NONE:
+		/*
+		 * 'drop all' supersedes any accept flags that may have been
+		 * passed to the function.
+		 */
+		break;
+
+	case BCM_RX_MODE_NORMAL:
+		bcm_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
+
+		/* internal switching mode */
+		bcm_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
+
+		break;
+
+	case BCM_RX_MODE_ALLMULTI:
+		bcm_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
+
+		/* internal switching mode */
+		bcm_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
+
+		break;
+
+	case BCM_RX_MODE_PROMISC:
+		/*
+		 * According to deffinition of SI mode, iface in promisc mode
+		 * should receive matched and unmatched (in resolution of port)
+		 * unicast packets.
+		 */
+		bcm_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
+
+		/* internal switching mode */
+		bcm_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
+
+		if (IS_MF_SI(sc)) {
+			bcm_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
+		} else {
+			bcm_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
+		}
+
+		break;
+
+	default:
+		PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
+		return -1;
+	}
+
+	/* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
+	if (rx_mode != BCM_RX_MODE_NONE) {
+		bcm_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
+		bcm_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
+	}
+
+	return 0;
+}
+
+static int
+bcm_set_q_rx_mode(struct bcm_softc *sc, uint8_t cl_id,
+		  unsigned long rx_mode_flags,
+		  unsigned long rx_accept_flags,
+		  unsigned long tx_accept_flags, unsigned long ramrod_flags)
+{
+	struct ecore_rx_mode_ramrod_params ramrod_param;
+	int rc;
+
+	memset(&ramrod_param, 0, sizeof(ramrod_param));
+
+	/* Prepare ramrod parameters */
+	ramrod_param.cid = 0;
+	ramrod_param.cl_id = cl_id;
+	ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
+	ramrod_param.func_id = SC_FUNC(sc);
+
+	ramrod_param.pstate = &sc->sp_state;
+	ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
+
+	ramrod_param.rdata = BCM_SP(sc, rx_mode_rdata);
+	ramrod_param.rdata_mapping =
+	    (phys_addr_t) ((void *)BCM_SP_MAPPING(sc, rx_mode_rdata)),
+	    bcm_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
+
+	ramrod_param.ramrod_flags = ramrod_flags;
+	ramrod_param.rx_mode_flags = rx_mode_flags;
+
+	ramrod_param.rx_accept_flags = rx_accept_flags;
+	ramrod_param.tx_accept_flags = tx_accept_flags;
+
+	rc = ecore_config_rx_mode(sc, &ramrod_param);
+	if (rc < 0) {
+		PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
+		return rc;
+	}
+
+	return 0;
+}
+
+int bcm_set_storm_rx_mode(struct bcm_softc *sc)
+{
+	unsigned long rx_mode_flags = 0, ramrod_flags = 0;
+	unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
+	int rc;
+
+	rc = bcm_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
+				   &tx_accept_flags);
+	if (rc) {
+		return rc;
+	}
+
+	bcm_set_bit(RAMROD_RX, &ramrod_flags);
+	bcm_set_bit(RAMROD_TX, &ramrod_flags);
+	bcm_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
+
+	return bcm_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
+				 rx_accept_flags, tx_accept_flags,
+				 ramrod_flags);
+}
+
+/* returns the "mcp load_code" according to global load_count array */
+static int bcm_nic_load_no_mcp(struct bcm_softc *sc)
+{
+	int path = SC_PATH(sc);
+	int port = SC_PORT(sc);
+
+	PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
+		    path, load_count[path][0], load_count[path][1],
+		    load_count[path][2]);
+
+	load_count[path][0]++;
+	load_count[path][1 + port]++;
+	PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
+		    path, load_count[path][0], load_count[path][1],
+		    load_count[path][2]);
+	if (load_count[path][0] == 1)
+		return FW_MSG_CODE_DRV_LOAD_COMMON;
+	else if (load_count[path][1 + port] == 1)
+		return FW_MSG_CODE_DRV_LOAD_PORT;
+	else
+		return FW_MSG_CODE_DRV_LOAD_FUNCTION;
+}
+
+/* returns the "mcp load_code" according to global load_count array */
+static int bcm_nic_unload_no_mcp(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	int path = SC_PATH(sc);
+
+	PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
+		    path, load_count[path][0], load_count[path][1],
+		    load_count[path][2]);
+	load_count[path][0]--;
+	load_count[path][1 + port]--;
+	PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
+		    path, load_count[path][0], load_count[path][1],
+		    load_count[path][2]);
+	if (load_count[path][0] == 0) {
+		return FW_MSG_CODE_DRV_UNLOAD_COMMON;
+	} else if (load_count[path][1 + port] == 0) {
+		return FW_MSG_CODE_DRV_UNLOAD_PORT;
+	} else {
+		return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
+	}
+}
+
+/* request unload mode from the MCP: COMMON, PORT or FUNCTION */
+static uint32_t bcm_send_unload_req(struct bcm_softc *sc, int unload_mode)
+{
+	uint32_t reset_code = 0;
+
+	/* Select the UNLOAD request mode */
+	if (unload_mode == UNLOAD_NORMAL) {
+		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+	} else {
+		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+	}
+
+	/* Send the request to the MCP */
+	if (!BCM_NOMCP(sc)) {
+		reset_code = bcm_fw_command(sc, reset_code, 0);
+	} else {
+		reset_code = bcm_nic_unload_no_mcp(sc);
+	}
+
+	return reset_code;
+}
+
+/* send UNLOAD_DONE command to the MCP */
+static void bcm_send_unload_done(struct bcm_softc *sc, uint8_t keep_link)
+{
+	uint32_t reset_param =
+	    keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
+
+	/* Report UNLOAD_DONE to MCP */
+	if (!BCM_NOMCP(sc)) {
+		bcm_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
+	}
+}
+
+static int bcm_func_wait_started(struct bcm_softc *sc)
+{
+	int tout = 50;
+
+	if (!sc->port.pmf) {
+		return 0;
+	}
+
+	/*
+	 * (assumption: No Attention from MCP at this stage)
+	 * PMF probably in the middle of TX disable/enable transaction
+	 * 1. Sync IRS for default SB
+	 * 2. Sync SP queue - this guarantees us that attention handling started
+	 * 3. Wait, that TX disable/enable transaction completes
+	 *
+	 * 1+2 guarantee that if DCBX attention was scheduled it already changed
+	 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
+	 * received completion for the transaction the state is TX_STOPPED.
+	 * State will return to STARTED after completion of TX_STOPPED-->STARTED
+	 * transaction.
+	 */
+
+	while (ecore_func_get_state(sc, &sc->func_obj) !=
+	       ECORE_F_STATE_STARTED && tout--) {
+		DELAY(20000);
+	}
+
+	if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
+		/*
+		 * Failed to complete the transaction in a "good way"
+		 * Force both transactions with CLR bit.
+		 */
+		struct ecore_func_state_params func_params = { NULL };
+
+		PMD_DRV_LOG(NOTICE, "Unexpected function state! "
+			    "Forcing STARTED-->TX_STOPPED-->STARTED");
+
+		func_params.f_obj = &sc->func_obj;
+		bcm_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
+
+		/* STARTED-->TX_STOPPED */
+		func_params.cmd = ECORE_F_CMD_TX_STOP;
+		ecore_func_state_change(sc, &func_params);
+
+		/* TX_STOPPED-->STARTED */
+		func_params.cmd = ECORE_F_CMD_TX_START;
+		return ecore_func_state_change(sc, &func_params);
+	}
+
+	return 0;
+}
+
+static int bcm_stop_queue(struct bcm_softc *sc, int index)
+{
+	struct bcm_fastpath *fp = &sc->fp[index];
+	struct ecore_queue_state_params q_params = { NULL };
+	int rc;
+
+	PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
+
+	q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
+	/* We want to wait for completion in this context */
+	bcm_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
+
+	/* Stop the primary connection: */
+
+	/* ...halt the connection */
+	q_params.cmd = ECORE_Q_CMD_HALT;
+	rc = ecore_queue_state_change(sc, &q_params);
+	if (rc) {
+		return rc;
+	}
+
+	/* ...terminate the connection */
+	q_params.cmd = ECORE_Q_CMD_TERMINATE;
+	memset(&q_params.params.terminate, 0,
+	       sizeof(q_params.params.terminate));
+	q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
+	rc = ecore_queue_state_change(sc, &q_params);
+	if (rc) {
+		return rc;
+	}
+
+	/* ...delete cfc entry */
+	q_params.cmd = ECORE_Q_CMD_CFC_DEL;
+	memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
+	q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
+	return ecore_queue_state_change(sc, &q_params);
+}
+
+/* wait for the outstanding SP commands */
+static uint8_t bcm_wait_sp_comp(struct bcm_softc *sc, unsigned long mask)
+{
+	unsigned long tmp;
+	int tout = 5000;	/* wait for 5 secs tops */
+
+	while (tout--) {
+		mb();
+		if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
+			return TRUE;
+		}
+
+		DELAY(1000);
+	}
+
+	mb();
+
+	tmp = atomic_load_acq_long(&sc->sp_state);
+	if (tmp & mask) {
+		PMD_DRV_LOG(INFO, "Filtering completion timed out: "
+			    "sp_state 0x%lx, mask 0x%lx", tmp, mask);
+		return FALSE;
+	}
+
+	return FALSE;
+}
+
+static int bcm_func_stop(struct bcm_softc *sc)
+{
+	struct ecore_func_state_params func_params = { NULL };
+	int rc;
+
+	/* prepare parameters for function state transitions */
+	bcm_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
+	func_params.f_obj = &sc->func_obj;
+	func_params.cmd = ECORE_F_CMD_STOP;
+
+	/*
+	 * Try to stop the function the 'good way'. If it fails (in case
+	 * of a parity error during bcm_chip_cleanup()) and we are
+	 * not in a debug mode, perform a state transaction in order to
+	 * enable further HW_RESET transaction.
+	 */
+	rc = ecore_func_state_change(sc, &func_params);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
+			    "Running a dry transaction");
+		bcm_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
+		return ecore_func_state_change(sc, &func_params);
+	}
+
+	return 0;
+}
+
+static int bcm_reset_hw(struct bcm_softc *sc, uint32_t load_code)
+{
+	struct ecore_func_state_params func_params = { NULL };
+
+	/* Prepare parameters for function state transitions */
+	bcm_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
+
+	func_params.f_obj = &sc->func_obj;
+	func_params.cmd = ECORE_F_CMD_HW_RESET;
+
+	func_params.params.hw_init.load_phase = load_code;
+
+	return ecore_func_state_change(sc, &func_params);
+}
+
+static void bcm_int_disable_sync(struct bcm_softc *sc, int disable_hw)
+{
+	if (disable_hw) {
+		/* prevent the HW from sending interrupts */
+		bcm_int_disable(sc);
+	}
+}
+
+static void
+bcm_chip_cleanup(struct bcm_softc *sc, uint32_t unload_mode, uint8_t keep_link)
+{
+	int port = SC_PORT(sc);
+	struct ecore_mcast_ramrod_params rparam = { NULL };
+	uint32_t reset_code;
+	int i, rc = 0;
+
+	bcm_drain_tx_queues(sc);
+
+	/* give HW time to discard old tx messages */
+	DELAY(1000);
+
+	/* Clean all ETH MACs */
+	rc = bcm_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
+			      FALSE);
+	if (rc < 0) {
+		PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
+	}
+
+	/* Clean up UC list  */
+	rc = bcm_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
+			      TRUE);
+	if (rc < 0) {
+		PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
+	}
+
+	/* Disable LLH */
+	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
+
+	/* Set "drop all" to stop Rx */
+
+	/*
+	 * We need to take the if_maddr_lock() here in order to prevent
+	 * a race between the completion code and this code.
+	 */
+
+	if (bcm_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
+		bcm_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
+	} else {
+		bcm_set_storm_rx_mode(sc);
+	}
+
+	/* Clean up multicast configuration */
+	rparam.mcast_obj = &sc->mcast_obj;
+	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
+	if (rc < 0) {
+		PMD_DRV_LOG(NOTICE,
+			    "Failed to send DEL MCAST command (%d)", rc);
+	}
+
+	/*
+	 * Send the UNLOAD_REQUEST to the MCP. This will return if
+	 * this function should perform FUNCTION, PORT, or COMMON HW
+	 * reset.
+	 */
+	reset_code = bcm_send_unload_req(sc, unload_mode);
+
+	/*
+	 * (assumption: No Attention from MCP at this stage)
+	 * PMF probably in the middle of TX disable/enable transaction
+	 */
+	rc = bcm_func_wait_started(sc);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "bcm_func_wait_started failed");
+	}
+
+	/*
+	 * Close multi and leading connections
+	 * Completions for ramrods are collected in a synchronous way
+	 */
+	for (i = 0; i < sc->num_queues; i++) {
+		if (bcm_stop_queue(sc, i)) {
+			goto unload_error;
+		}
+	}
+
+	/*
+	 * If SP settings didn't get completed so far - something
+	 * very wrong has happen.
+	 */
+	if (!bcm_wait_sp_comp(sc, ~0x0UL)) {
+		PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
+	}
+
+unload_error:
+
+	rc = bcm_func_stop(sc);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "Function stop failed!");
+	}
+
+	/* disable HW interrupts */
+	bcm_int_disable_sync(sc, TRUE);
+
+	/* Reset the chip */
+	rc = bcm_reset_hw(sc, reset_code);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "Hardware reset failed");
+	}
+
+	/* Report UNLOAD_DONE to MCP */
+	bcm_send_unload_done(sc, keep_link);
+}
+
+static void bcm_disable_close_the_gate(struct bcm_softc *sc)
+{
+	uint32_t val;
+
+	PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
+
+	val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
+	val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
+		 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
+	REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
+}
+
+/*
+ * Cleans the object that have internal lists without sending
+ * ramrods. Should be run when interrutps are disabled.
+ */
+static void bcm_squeeze_objects(struct bcm_softc *sc)
+{
+	unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
+	struct ecore_mcast_ramrod_params rparam = { NULL };
+	struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
+	int rc;
+
+	/* Cleanup MACs' object first... */
+
+	/* Wait for completion of requested */
+	bcm_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
+	/* Perform a dry cleanup */
+	bcm_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
+
+	/* Clean ETH primary MAC */
+	bcm_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
+	rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
+				 &ramrod_flags);
+	if (rc != 0) {
+		PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
+	}
+
+	/* Cleanup UC list */
+	vlan_mac_flags = 0;
+	bcm_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
+	rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
+	if (rc != 0) {
+		PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
+	}
+
+	/* Now clean mcast object... */
+
+	rparam.mcast_obj = &sc->mcast_obj;
+	bcm_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
+
+	/* Add a DEL command... */
+	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
+	if (rc < 0) {
+		PMD_DRV_LOG(NOTICE,
+			    "Failed to send DEL MCAST command (%d)", rc);
+	}
+
+	/* now wait until all pending commands are cleared */
+
+	rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
+	while (rc != 0) {
+		if (rc < 0) {
+			PMD_DRV_LOG(NOTICE,
+				    "Failed to clean MCAST object (%d)", rc);
+			return;
+		}
+
+		rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
+	}
+}
+
+/* stop the controller */
+__attribute__ ((noinline))
+int
+bcm_nic_unload(struct bcm_softc *sc, uint32_t unload_mode, uint8_t keep_link)
+{
+	uint8_t global = FALSE;
+	uint32_t val;
+
+	PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
+
+	/* stop the periodic callout */
+	bcm_periodic_stop(sc);
+
+	/* mark driver as unloaded in shmem2 */
+	if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
+		val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
+		SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
+			  val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
+	}
+
+	if (IS_PF(sc) && sc->recovery_state != BCM_RECOVERY_DONE &&
+	    (sc->state == BCM_STATE_CLOSED || sc->state == BCM_STATE_ERROR)) {
+		/*
+		 * We can get here if the driver has been unloaded
+		 * during parity error recovery and is either waiting for a
+		 * leader to complete or for other functions to unload and
+		 * then ifconfig down has been issued. In this case we want to
+		 * unload and let other functions to complete a recovery
+		 * process.
+		 */
+		sc->recovery_state = BCM_RECOVERY_DONE;
+		sc->is_leader = 0;
+		bcm_release_leader_lock(sc);
+		mb();
+
+		PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
+		return -1;
+	}
+
+	/*
+	 * Nothing to do during unload if previous bcm_nic_load()
+	 * did not completed succesfully - all resourses are released.
+	 */
+	if ((sc->state == BCM_STATE_CLOSED) || (sc->state == BCM_STATE_ERROR)) {
+		return 0;
+	}
+
+	sc->state = BCM_STATE_CLOSING_WAITING_HALT;
+	mb();
+
+	sc->rx_mode = BCM_RX_MODE_NONE;
+	bcm_set_rx_mode(sc);
+	mb();
+
+	if (IS_PF(sc)) {
+		/* set ALWAYS_ALIVE bit in shmem */
+		sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
+
+		bcm_drv_pulse(sc);
+
+		bcm_stats_handle(sc, STATS_EVENT_STOP);
+		bcm_save_statistics(sc);
+	}
+
+	/* wait till consumers catch up with producers in all queues */
+	bcm_drain_tx_queues(sc);
+
+	/* if VF indicate to PF this function is going down (PF will delete sp
+	 * elements and clear initializations
+	 */
+	if (IS_VF(sc)) {
+		bcm_vf_unload(sc);
+	} else if (unload_mode != UNLOAD_RECOVERY) {
+		/* if this is a normal/close unload need to clean up chip */
+		bcm_chip_cleanup(sc, unload_mode, keep_link);
+	} else {
+		/* Send the UNLOAD_REQUEST to the MCP */
+		bcm_send_unload_req(sc, unload_mode);
+
+		/*
+		 * Prevent transactions to host from the functions on the
+		 * engine that doesn't reset global blocks in case of global
+		 * attention once gloabl blocks are reset and gates are opened
+		 * (the engine which leader will perform the recovery
+		 * last).
+		 */
+		if (!CHIP_IS_E1x(sc)) {
+			bcm_pf_disable(sc);
+		}
+
+		/* disable HW interrupts */
+		bcm_int_disable_sync(sc, TRUE);
+
+		/* Report UNLOAD_DONE to MCP */
+		bcm_send_unload_done(sc, FALSE);
+	}
+
+	/*
+	 * At this stage no more interrupts will arrive so we may safely clean
+	 * the queue'able objects here in case they failed to get cleaned so far.
+	 */
+	if (IS_PF(sc)) {
+		bcm_squeeze_objects(sc);
+	}
+
+	/* There should be no more pending SP commands at this stage */
+	sc->sp_state = 0;
+
+	sc->port.pmf = 0;
+
+	if (IS_PF(sc)) {
+		bcm_free_mem(sc);
+	}
+
+	bcm_free_fw_stats_mem(sc);
+
+	sc->state = BCM_STATE_CLOSED;
+
+	/*
+	 * Check if there are pending parity attentions. If there are - set
+	 * RECOVERY_IN_PROGRESS.
+	 */
+	if (IS_PF(sc) && bcm_chk_parity_attn(sc, &global, FALSE)) {
+		bcm_set_reset_in_progress(sc);
+
+		/* Set RESET_IS_GLOBAL if needed */
+		if (global) {
+			bcm_set_reset_global(sc);
+		}
+	}
+
+	/*
+	 * The last driver must disable a "close the gate" if there is no
+	 * parity attention or "process kill" pending.
+	 */
+	if (IS_PF(sc) && !bcm_clear_pf_load(sc) &&
+	    bcm_reset_is_done(sc, SC_PATH(sc))) {
+		bcm_disable_close_the_gate(sc);
+	}
+
+	PMD_DRV_LOG(DEBUG, "Ended NIC unload");
+
+	return 0;
+}
+
+/*
+ * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
+ * visible to the controller.
+ *
+ * If an mbuf is submitted to this routine and cannot be given to the
+ * controller (e.g. it has too many fragments) then the function may free
+ * the mbuf and return to the caller.
+ *
+ * Returns:
+ *   0 = Success, !0 = Failure
+ *   Note the side effect that an mbuf may be freed if it causes a problem.
+ */
+int bcm_tx_encap(struct bcm_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts)
+{
+	struct rte_mbuf *m0;
+	struct eth_tx_start_bd *tx_start_bd;
+	uint16_t bd_prod, pkt_prod;
+	int m_tx;
+	struct bcm_softc *sc;
+	uint32_t nbds = 0;
+	struct bcm_fastpath *fp;
+
+	sc = txq->sc;
+	fp = &sc->fp[txq->queue_id];
+
+	bd_prod = txq->tx_bd_tail;
+	pkt_prod = txq->tx_pkt_tail;
+
+	for (m_tx = 0; m_tx < m_pkts; m_tx++) {
+
+		m0 = *m_head++;
+
+		if (unlikely(txq->nb_tx_avail < 3)) {
+			PMD_TX_LOG(ERR, "no enough bds %d/%d",
+				   bd_prod, txq->nb_tx_avail);
+			return -ENOMEM;
+		}
+
+		txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
+
+		tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
+
+		tx_start_bd->addr =
+		    rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR(m0));
+		tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
+		tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
+		tx_start_bd->general_data =
+		    (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
+
+		tx_start_bd->nbd = rte_cpu_to_le_16(2);
+
+		if (m0->ol_flags & PKT_TX_VLAN_PKT) {
+			tx_start_bd->vlan_or_ethertype =
+			    rte_cpu_to_le_16(m0->vlan_tci);
+			tx_start_bd->bd_flags.as_bitfield |=
+			    (X_ETH_OUTBAND_VLAN <<
+			     ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
+		} else {
+			if (IS_PF(sc))
+				tx_start_bd->vlan_or_ethertype =
+				    rte_cpu_to_le_16(pkt_prod);
+			else {
+				struct ether_hdr *eh
+				    = rte_pktmbuf_mtod(m0, struct ether_hdr *);
+
+				tx_start_bd->vlan_or_ethertype = eh->ether_type;
+			}
+		}
+
+		bd_prod = NEXT_TX_BD(bd_prod);
+		if (IS_VF(sc)) {
+			struct eth_tx_parse_bd_e2 *tx_parse_bd;
+			uint8_t *data = rte_pktmbuf_mtod(m0, uint8_t *);
+
+			tx_parse_bd =
+			    &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
+			tx_parse_bd->parsing_data =
+			    (1 << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
+
+			rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
+				   &data[0], 2);
+			rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
+				   &data[2], 2);
+			rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
+				   &data[4], 2);
+			rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
+				   &data[6], 2);
+			rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
+				   &data[8], 2);
+			rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
+				   &data[10], 2);
+
+			tx_parse_bd->data.mac_addr.dst_hi =
+			    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
+			tx_parse_bd->data.mac_addr.dst_mid =
+			    rte_cpu_to_be_16(tx_parse_bd->data.
+					     mac_addr.dst_mid);
+			tx_parse_bd->data.mac_addr.dst_lo =
+			    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
+			tx_parse_bd->data.mac_addr.src_hi =
+			    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
+			tx_parse_bd->data.mac_addr.src_mid =
+			    rte_cpu_to_be_16(tx_parse_bd->data.
+					     mac_addr.src_mid);
+			tx_parse_bd->data.mac_addr.src_lo =
+			    rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
+
+			PMD_TX_LOG(DEBUG,
+				   "PBD dst %x %x %x src %x %x %x p_data %x",
+				   tx_parse_bd->data.mac_addr.dst_hi,
+				   tx_parse_bd->data.mac_addr.dst_mid,
+				   tx_parse_bd->data.mac_addr.dst_lo,
+				   tx_parse_bd->data.mac_addr.src_hi,
+				   tx_parse_bd->data.mac_addr.src_mid,
+				   tx_parse_bd->data.mac_addr.src_lo,
+				   tx_parse_bd->parsing_data);
+		}
+
+		PMD_TX_LOG(DEBUG,
+			   "start bd: nbytes %d flags %x vlan %x\n",
+			   tx_start_bd->nbytes,
+			   tx_start_bd->bd_flags.as_bitfield,
+			   tx_start_bd->vlan_or_ethertype);
+
+		bd_prod = NEXT_TX_BD(bd_prod);
+		pkt_prod++;
+
+		if (TX_IDX(bd_prod) < 2) {
+			nbds++;
+		}
+	}
+
+	txq->nb_tx_avail -= m_pkts << 1;
+	txq->tx_bd_tail = bd_prod;
+	txq->tx_pkt_tail = pkt_prod;
+
+	mb();
+	fp->tx_db.data.prod += (m_pkts << 1) + nbds;
+	DOORBELL(sc, txq->queue_id, fp->tx_db.raw);
+	mb();
+
+	return 0;
+}
+
+static uint16_t bcm_cid_ilt_lines(struct bcm_softc *sc)
+{
+	return L2_ILT_LINES(sc);
+}
+
+static void bcm_ilt_set_info(struct bcm_softc *sc)
+{
+	struct ilt_client_info *ilt_client;
+	struct ecore_ilt *ilt = sc->ilt;
+	uint16_t line = 0;
+
+	PMD_INIT_FUNC_TRACE();
+
+	ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
+
+	/* CDU */
+	ilt_client = &ilt->clients[ILT_CLIENT_CDU];
+	ilt_client->client_num = ILT_CLIENT_CDU;
+	ilt_client->page_size = CDU_ILT_PAGE_SZ;
+	ilt_client->flags = ILT_CLIENT_SKIP_MEM;
+	ilt_client->start = line;
+	line += bcm_cid_ilt_lines(sc);
+
+	if (CNIC_SUPPORT(sc)) {
+		line += CNIC_ILT_LINES;
+	}
+
+	ilt_client->end = (line - 1);
+
+	/* QM */
+	if (QM_INIT(sc->qm_cid_count)) {
+		ilt_client = &ilt->clients[ILT_CLIENT_QM];
+		ilt_client->client_num = ILT_CLIENT_QM;
+		ilt_client->page_size = QM_ILT_PAGE_SZ;
+		ilt_client->flags = 0;
+		ilt_client->start = line;
+
+		/* 4 bytes for each cid */
+		line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
+				     QM_ILT_PAGE_SZ);
+
+		ilt_client->end = (line - 1);
+	}
+
+	if (CNIC_SUPPORT(sc)) {
+		/* SRC */
+		ilt_client = &ilt->clients[ILT_CLIENT_SRC];
+		ilt_client->client_num = ILT_CLIENT_SRC;
+		ilt_client->page_size = SRC_ILT_PAGE_SZ;
+		ilt_client->flags = 0;
+		ilt_client->start = line;
+		line += SRC_ILT_LINES;
+		ilt_client->end = (line - 1);
+
+		/* TM */
+		ilt_client = &ilt->clients[ILT_CLIENT_TM];
+		ilt_client->client_num = ILT_CLIENT_TM;
+		ilt_client->page_size = TM_ILT_PAGE_SZ;
+		ilt_client->flags = 0;
+		ilt_client->start = line;
+		line += TM_ILT_LINES;
+		ilt_client->end = (line - 1);
+	}
+
+	assert((line <= ILT_MAX_LINES));
+}
+
+static void bcm_set_fp_rx_buf_size(struct bcm_softc *sc)
+{
+	int i;
+
+	for (i = 0; i < sc->num_queues; i++) {
+		/* get the Rx buffer size for RX frames */
+		sc->fp[i].rx_buf_size =
+		    (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
+
+		/* get the mbuf allocation size for RX frames */
+		if (sc->fp[i].rx_buf_size <= MCLBYTES) {
+			sc->fp[i].mbuf_alloc_size = MCLBYTES;
+		} else if (sc->fp[i].rx_buf_size <= BCM_PAGE_SIZE) {
+			sc->fp[i].mbuf_alloc_size = PAGE_SIZE;
+		} else {
+			sc->fp[i].mbuf_alloc_size = MJUM9BYTES;
+		}
+	}
+}
+
+int bcm_alloc_ilt_mem(struct bcm_softc *sc)
+{
+
+	sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
+
+	return sc->ilt == NULL;
+}
+
+static int bcm_alloc_ilt_lines_mem(struct bcm_softc *sc)
+{
+	sc->ilt->lines = rte_calloc("",
+				    sizeof(struct ilt_line), ILT_MAX_LINES,
+				    RTE_CACHE_LINE_SIZE);
+	return sc->ilt->lines == NULL;
+}
+
+void bcm_free_ilt_mem(struct bcm_softc *sc)
+{
+	rte_free(sc->ilt);
+	sc->ilt = NULL;
+}
+
+static void bcm_free_ilt_lines_mem(struct bcm_softc *sc)
+{
+	if (sc->ilt->lines != NULL) {
+		rte_free(sc->ilt->lines);
+		sc->ilt->lines = NULL;
+	}
+}
+
+static void bcm_free_mem(struct bcm_softc *sc)
+{
+	uint32_t i;
+
+	for (i = 0; i < L2_ILT_LINES(sc); i++) {
+		sc->context[i].vcxt = NULL;
+		sc->context[i].size = 0;
+	}
+
+	ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
+
+	bcm_free_ilt_lines_mem(sc);
+}
+
+static int bcm_alloc_mem(struct bcm_softc *sc)
+{
+	int context_size;
+	int allocated;
+	int i;
+	char cdu_name[RTE_MEMZONE_NAMESIZE];
+
+	/*
+	 * Allocate memory for CDU context:
+	 * This memory is allocated separately and not in the generic ILT
+	 * functions because CDU differs in few aspects:
+	 * 1. There can be multiple entities allocating memory for context -
+	 * regular L2, CNIC, and SRIOV drivers. Each separately controls
+	 * its own ILT lines.
+	 * 2. Since CDU page-size is not a single 4KB page (which is the case
+	 * for the other ILT clients), to be efficient we want to support
+	 * allocation of sub-page-size in the last entry.
+	 * 3. Context pointers are used by the driver to pass to FW / update
+	 * the context (for the other ILT clients the pointers are used just to
+	 * free the memory during unload).
+	 */
+	context_size = (sizeof(union cdu_context) * BCM_L2_CID_COUNT(sc));
+	for (i = 0, allocated = 0; allocated < context_size; i++) {
+		sc->context[i].size = min(CDU_ILT_PAGE_SZ,
+					  (context_size - allocated));
+
+		snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
+		if (bcm_dma_alloc(sc, sc->context[i].size,
+				  &sc->context[i].vcxt_dma,
+				  cdu_name, BCM_PAGE_SIZE) != 0) {
+			bcm_free_mem(sc);
+			return -1;
+		}
+
+		sc->context[i].vcxt =
+		    (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
+
+		allocated += sc->context[i].size;
+	}
+
+	bcm_alloc_ilt_lines_mem(sc);
+
+	if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
+		PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
+		bcm_free_mem(sc);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void bcm_free_fw_stats_mem(struct bcm_softc *sc)
+{
+	sc->fw_stats_num = 0;
+
+	sc->fw_stats_req_size = 0;
+	sc->fw_stats_req = NULL;
+	sc->fw_stats_req_mapping = 0;
+
+	sc->fw_stats_data_size = 0;
+	sc->fw_stats_data = NULL;
+	sc->fw_stats_data_mapping = 0;
+}
+
+static int bcm_alloc_fw_stats_mem(struct bcm_softc *sc)
+{
+	uint8_t num_queue_stats;
+	int num_groups, vf_headroom = 0;
+
+	/* number of queues for statistics is number of eth queues */
+	num_queue_stats = BCM_NUM_ETH_QUEUES(sc);
+
+	/*
+	 * Total number of FW statistics requests =
+	 *   1 for port stats + 1 for PF stats + num of queues
+	 */
+	sc->fw_stats_num = (2 + num_queue_stats);
+
+	/*
+	 * Request is built from stats_query_header and an array of
+	 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
+	 * rules. The real number or requests is configured in the
+	 * stats_query_header.
+	 */
+	num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
+	if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
+		num_groups++;
+
+	sc->fw_stats_req_size =
+	    (sizeof(struct stats_query_header) +
+	     (num_groups * sizeof(struct stats_query_cmd_group)));
+
+	/*
+	 * Data for statistics requests + stats_counter.
+	 * stats_counter holds per-STORM counters that are incremented when
+	 * STORM has finished with the current request. Memory for FCoE
+	 * offloaded statistics are counted anyway, even if they will not be sent.
+	 * VF stats are not accounted for here as the data of VF stats is stored
+	 * in memory allocated by the VF, not here.
+	 */
+	sc->fw_stats_data_size =
+	    (sizeof(struct stats_counter) +
+	     sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
+	     /* sizeof(struct fcoe_statistics_params) + */
+	     (sizeof(struct per_queue_stats) * num_queue_stats));
+
+	if (bcm_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
+			  &sc->fw_stats_dma, "fw_stats",
+			  RTE_CACHE_LINE_SIZE) != 0) {
+		bcm_free_fw_stats_mem(sc);
+		return -1;
+	}
+
+	/* set up the shortcuts */
+
+	sc->fw_stats_req = (struct bcm_fw_stats_req *)sc->fw_stats_dma.vaddr;
+	sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
+
+	sc->fw_stats_data =
+	    (struct bcm_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
+					 sc->fw_stats_req_size);
+	sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
+				     sc->fw_stats_req_size);
+
+	return 0;
+}
+
+/*
+ * Bits map:
+ * 0-7  - Engine0 load counter.
+ * 8-15 - Engine1 load counter.
+ * 16   - Engine0 RESET_IN_PROGRESS bit.
+ * 17   - Engine1 RESET_IN_PROGRESS bit.
+ * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
+ *        function on the engine
+ * 19   - Engine1 ONE_IS_LOADED.
+ * 20   - Chip reset flow bit. When set none-leader must wait for both engines
+ *        leader to complete (check for both RESET_IN_PROGRESS bits and not
+ *        for just the one belonging to its engine).
+ */
+#define BCM_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
+#define BCM_PATH0_LOAD_CNT_MASK   0x000000ff
+#define BCM_PATH0_LOAD_CNT_SHIFT  0
+#define BCM_PATH1_LOAD_CNT_MASK   0x0000ff00
+#define BCM_PATH1_LOAD_CNT_SHIFT  8
+#define BCM_PATH0_RST_IN_PROG_BIT 0x00010000
+#define BCM_PATH1_RST_IN_PROG_BIT 0x00020000
+#define BCM_GLOBAL_RESET_BIT      0x00040000
+
+/* set the GLOBAL_RESET bit, should be run under rtnl lock */
+static void bcm_set_reset_global(struct bcm_softc *sc)
+{
+	uint32_t val;
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+	val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+	REG_WR(sc, BCM_RECOVERY_GLOB_REG, val | BCM_GLOBAL_RESET_BIT);
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+}
+
+/* clear the GLOBAL_RESET bit, should be run under rtnl lock */
+static void bcm_clear_reset_global(struct bcm_softc *sc)
+{
+	uint32_t val;
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+	val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+	REG_WR(sc, BCM_RECOVERY_GLOB_REG, val & (~BCM_GLOBAL_RESET_BIT));
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+}
+
+/* checks the GLOBAL_RESET bit, should be run under rtnl lock */
+static uint8_t bcm_reset_is_global(struct bcm_softc *sc)
+{
+	return (REG_RD(sc, BCM_RECOVERY_GLOB_REG) & BCM_GLOBAL_RESET_BIT);
+}
+
+/* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
+static void bcm_set_reset_done(struct bcm_softc *sc)
+{
+	uint32_t val;
+	uint32_t bit = SC_PATH(sc) ? BCM_PATH1_RST_IN_PROG_BIT :
+	    BCM_PATH0_RST_IN_PROG_BIT;
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+
+	val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+	/* Clear the bit */
+	val &= ~bit;
+	REG_WR(sc, BCM_RECOVERY_GLOB_REG, val);
+
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+}
+
+/* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
+static void bcm_set_reset_in_progress(struct bcm_softc *sc)
+{
+	uint32_t val;
+	uint32_t bit = SC_PATH(sc) ? BCM_PATH1_RST_IN_PROG_BIT :
+	    BCM_PATH0_RST_IN_PROG_BIT;
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+
+	val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+	/* Set the bit */
+	val |= bit;
+	REG_WR(sc, BCM_RECOVERY_GLOB_REG, val);
+
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+}
+
+/* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
+static uint8_t bcm_reset_is_done(struct bcm_softc *sc, int engine)
+{
+	uint32_t val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+	uint32_t bit = engine ? BCM_PATH1_RST_IN_PROG_BIT :
+	    BCM_PATH0_RST_IN_PROG_BIT;
+
+	/* return false if bit is set */
+	return (val & bit) ? FALSE : TRUE;
+}
+
+/* get the load status for an engine, should be run under rtnl lock */
+static uint8_t bcm_get_load_status(struct bcm_softc *sc, int engine)
+{
+	uint32_t mask = engine ? BCM_PATH1_LOAD_CNT_MASK :
+	    BCM_PATH0_LOAD_CNT_MASK;
+	uint32_t shift = engine ? BCM_PATH1_LOAD_CNT_SHIFT :
+	    BCM_PATH0_LOAD_CNT_SHIFT;
+	uint32_t val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+
+	val = ((val & mask) >> shift);
+
+	return (val != 0);
+}
+
+/* set pf load mark */
+static void bcm_set_pf_load(struct bcm_softc *sc)
+{
+	uint32_t val;
+	uint32_t val1;
+	uint32_t mask = SC_PATH(sc) ? BCM_PATH1_LOAD_CNT_MASK :
+	    BCM_PATH0_LOAD_CNT_MASK;
+	uint32_t shift = SC_PATH(sc) ? BCM_PATH1_LOAD_CNT_SHIFT :
+	    BCM_PATH0_LOAD_CNT_SHIFT;
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+
+	PMD_INIT_FUNC_TRACE();
+
+	val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+
+	/* get the current counter value */
+	val1 = ((val & mask) >> shift);
+
+	/* set bit of this PF */
+	val1 |= (1 << SC_ABS_FUNC(sc));
+
+	/* clear the old value */
+	val &= ~mask;
+
+	/* set the new one */
+	val |= ((val1 << shift) & mask);
+
+	REG_WR(sc, BCM_RECOVERY_GLOB_REG, val);
+
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+}
+
+/* clear pf load mark */
+static uint8_t bcm_clear_pf_load(struct bcm_softc *sc)
+{
+	uint32_t val1, val;
+	uint32_t mask = SC_PATH(sc) ? BCM_PATH1_LOAD_CNT_MASK :
+	    BCM_PATH0_LOAD_CNT_MASK;
+	uint32_t shift = SC_PATH(sc) ? BCM_PATH1_LOAD_CNT_SHIFT :
+	    BCM_PATH0_LOAD_CNT_SHIFT;
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+	val = REG_RD(sc, BCM_RECOVERY_GLOB_REG);
+
+	/* get the current counter value */
+	val1 = (val & mask) >> shift;
+
+	/* clear bit of that PF */
+	val1 &= ~(1 << SC_ABS_FUNC(sc));
+
+	/* clear the old value */
+	val &= ~mask;
+
+	/* set the new one */
+	val |= ((val1 << shift) & mask);
+
+	REG_WR(sc, BCM_RECOVERY_GLOB_REG, val);
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
+	return val1 != 0;
+}
+
+/* send load requrest to mcp and analyze response */
+static int bcm_nic_load_request(struct bcm_softc *sc, uint32_t * load_code)
+{
+	PMD_INIT_FUNC_TRACE();
+
+	/* init fw_seq */
+	sc->fw_seq =
+	    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
+	     DRV_MSG_SEQ_NUMBER_MASK);
+
+	PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
+
+#ifdef BCM_PULSE
+	/* get the current FW pulse sequence */
+	sc->fw_drv_pulse_wr_seq =
+	    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
+	     DRV_PULSE_SEQ_MASK);
+#else
+	/* set ALWAYS_ALIVE bit in shmem */
+	sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
+	bcm_drv_pulse(sc);
+#endif
+
+	/* load request */
+	(*load_code) = bcm_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
+				      DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
+
+	/* if the MCP fails to respond we must abort */
+	if (!(*load_code)) {
+		PMD_DRV_LOG(NOTICE, "MCP response failure!");
+		return -1;
+	}
+
+	/* if MCP refused then must abort */
+	if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
+		PMD_DRV_LOG(NOTICE, "MCP refused load request");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * Check whether another PF has already loaded FW to chip. In virtualized
+ * environments a pf from anoth VM may have already initialized the device
+ * including loading FW.
+ */
+static int bcm_nic_load_analyze_req(struct bcm_softc *sc, uint32_t load_code)
+{
+	uint32_t my_fw, loaded_fw;
+
+	/* is another pf loaded on this engine? */
+	if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
+	    (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
+		/* build my FW version dword */
+		my_fw = (BCM_5710_FW_MAJOR_VERSION +
+			 (BCM_5710_FW_MINOR_VERSION << 8) +
+			 (BCM_5710_FW_REVISION_VERSION << 16) +
+			 (BCM_5710_FW_ENGINEERING_VERSION << 24));
+
+		/* read loaded FW from chip */
+		loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
+		PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
+			    loaded_fw, my_fw);
+
+		/* abort nic load if version mismatch */
+		if (my_fw != loaded_fw) {
+			PMD_DRV_LOG(NOTICE,
+				    "FW 0x%08x already loaded (mine is 0x%08x)",
+				    loaded_fw, my_fw);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/* mark PMF if applicable */
+static void bcm_nic_load_pmf(struct bcm_softc *sc, uint32_t load_code)
+{
+	uint32_t ncsi_oem_data_addr;
+
+	PMD_INIT_FUNC_TRACE();
+
+	if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
+	    (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
+	    (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
+		/*
+		 * Barrier here for ordering between the writing to sc->port.pmf here
+		 * and reading it from the periodic task.
+		 */
+		sc->port.pmf = 1;
+		mb();
+	} else {
+		sc->port.pmf = 0;
+	}
+
+	PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
+
+	if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
+		if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
+			ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
+			if (ncsi_oem_data_addr) {
+				REG_WR(sc,
+				       (ncsi_oem_data_addr +
+					offsetof(struct glob_ncsi_oem_data,
+						 driver_version)), 0);
+			}
+		}
+	}
+}
+
+static void bcm_read_mf_cfg(struct bcm_softc *sc)
+{
+	int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
+	int abs_func;
+	int vn;
+
+	if (BCM_NOMCP(sc)) {
+		return;		/* what should be the default bvalue in this case */
+	}
+
+	/*
+	 * The formula for computing the absolute function number is...
+	 * For 2 port configuration (4 functions per port):
+	 *   abs_func = 2 * vn + SC_PORT + SC_PATH
+	 * For 4 port configuration (2 functions per port):
+	 *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
+	 */
+	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
+		abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
+		if (abs_func >= E1H_FUNC_MAX) {
+			break;
+		}
+		sc->devinfo.mf_info.mf_config[vn] =
+		    MFCFG_RD(sc, func_mf_config[abs_func].config);
+	}
+
+	if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
+	    FUNC_MF_CFG_FUNC_DISABLED) {
+		PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
+		sc->flags |= BCM_MF_FUNC_DIS;
+	} else {
+		PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
+		sc->flags &= ~BCM_MF_FUNC_DIS;
+	}
+}
+
+/* acquire split MCP access lock register */
+static int bcm_acquire_alr(struct bcm_softc *sc)
+{
+	uint32_t j, val;
+
+	for (j = 0; j < 1000; j++) {
+		val = (1UL << 31);
+		REG_WR(sc, GRCBASE_MCP + 0x9c, val);
+		val = REG_RD(sc, GRCBASE_MCP + 0x9c);
+		if (val & (1L << 31))
+			break;
+
+		DELAY(5000);
+	}
+
+	if (!(val & (1L << 31))) {
+		PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
+		return -1;
+	}
+
+	return 0;
+}
+
+/* release split MCP access lock register */
+static void bcm_release_alr(struct bcm_softc *sc)
+{
+	REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
+}
+
+static void bcm_fan_failure(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	uint32_t ext_phy_config;
+
+	/* mark the failure */
+	ext_phy_config =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
+
+	ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
+	ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
+	SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
+		 ext_phy_config);
+
+	/* log the failure */
+	PMD_DRV_LOG(INFO,
+		    "Fan Failure has caused the driver to shutdown "
+		    "the card to prevent permanent damage. "
+		    "Please contact OEM Support for assistance");
+
+	rte_panic("Schedule task to handle fan failure");
+}
+
+/* this function is called upon a link interrupt */
+static void bcm_link_attn(struct bcm_softc *sc)
+{
+	uint32_t pause_enabled = 0;
+	struct host_port_stats *pstats;
+	int cmng_fns;
+
+	/* Make sure that we are synced with the current statistics */
+	bcm_stats_handle(sc, STATS_EVENT_STOP);
+
+	elink_link_update(&sc->link_params, &sc->link_vars);
+
+	if (sc->link_vars.link_up) {
+
+		/* dropless flow control */
+		if (sc->dropless_fc) {
+			pause_enabled = 0;
+
+			if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
+				pause_enabled = 1;
+			}
+
+			REG_WR(sc,
+			       (BAR_USTRORM_INTMEM +
+				USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
+			       pause_enabled);
+		}
+
+		if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
+			pstats = BCM_SP(sc, port_stats);
+			/* reset old mac stats */
+			memset(&(pstats->mac_stx[0]), 0,
+			       sizeof(struct mac_stx));
+		}
+
+		if (sc->state == BCM_STATE_OPEN) {
+			bcm_stats_handle(sc, STATS_EVENT_LINK_UP);
+		}
+	}
+
+	if (sc->link_vars.link_up && sc->link_vars.line_speed) {
+		cmng_fns = bcm_get_cmng_fns_mode(sc);
+
+		if (cmng_fns != CMNG_FNS_NONE) {
+			bcm_cmng_fns_init(sc, FALSE, cmng_fns);
+			storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
+		}
+	}
+
+	bcm_link_report(sc);
+
+	if (IS_MF(sc)) {
+		bcm_link_sync_notify(sc);
+	}
+}
+
+static void bcm_attn_int_asserted(struct bcm_softc *sc, uint32_t asserted)
+{
+	int port = SC_PORT(sc);
+	uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
+	uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
+	    NIG_REG_MASK_INTERRUPT_PORT0;
+	uint32_t aeu_mask;
+	uint32_t nig_mask = 0;
+	uint32_t reg_addr;
+	uint32_t igu_acked;
+	uint32_t cnt;
+
+	if (sc->attn_state & asserted) {
+		PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
+	}
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+
+	aeu_mask = REG_RD(sc, aeu_addr);
+
+	aeu_mask &= ~(asserted & 0x3ff);
+
+	REG_WR(sc, aeu_addr, aeu_mask);
+
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+
+	sc->attn_state |= asserted;
+
+	if (asserted & ATTN_HARD_WIRED_MASK) {
+		if (asserted & ATTN_NIG_FOR_FUNC) {
+
+			/* save nig interrupt mask */
+			nig_mask = REG_RD(sc, nig_int_mask_addr);
+
+			/* If nig_mask is not set, no need to call the update function */
+			if (nig_mask) {
+				REG_WR(sc, nig_int_mask_addr, 0);
+
+				bcm_link_attn(sc);
+			}
+
+			/* handle unicore attn? */
+		}
+
+		if (asserted & ATTN_SW_TIMER_4_FUNC) {
+			PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
+		}
+
+		if (asserted & GPIO_2_FUNC) {
+			PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
+		}
+
+		if (asserted & GPIO_3_FUNC) {
+			PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
+		}
+
+		if (asserted & GPIO_4_FUNC) {
+			PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
+		}
+
+		if (port == 0) {
+			if (asserted & ATTN_GENERAL_ATTN_1) {
+				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
+			}
+			if (asserted & ATTN_GENERAL_ATTN_2) {
+				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
+			}
+			if (asserted & ATTN_GENERAL_ATTN_3) {
+				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
+			}
+		} else {
+			if (asserted & ATTN_GENERAL_ATTN_4) {
+				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
+			}
+			if (asserted & ATTN_GENERAL_ATTN_5) {
+				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
+			}
+			if (asserted & ATTN_GENERAL_ATTN_6) {
+				PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
+				REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
+			}
+		}
+	}
+	/* hardwired */
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		reg_addr =
+		    (HC_REG_COMMAND_REG + port * 32 +
+		     COMMAND_REG_ATTN_BITS_SET);
+	} else {
+		reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
+	}
+
+	PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
+		    asserted,
+		    (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
+		    reg_addr);
+	REG_WR(sc, reg_addr, asserted);
+
+	/* now set back the mask */
+	if (asserted & ATTN_NIG_FOR_FUNC) {
+		/*
+		 * Verify that IGU ack through BAR was written before restoring
+		 * NIG mask. This loop should exit after 2-3 iterations max.
+		 */
+		if (sc->devinfo.int_block != INT_BLOCK_HC) {
+			cnt = 0;
+
+			do {
+				igu_acked =
+				    REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
+			} while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
+				 && (++cnt < MAX_IGU_ATTN_ACK_TO));
+
+			if (!igu_acked) {
+				PMD_DRV_LOG(ERR,
+					    "Failed to verify IGU ack on time");
+			}
+
+			mb();
+		}
+
+		REG_WR(sc, nig_int_mask_addr, nig_mask);
+
+	}
+}
+
+static void
+bcm_print_next_block(__rte_unused struct bcm_softc *sc, __rte_unused int idx,
+		     __rte_unused const char *blk)
+{
+	PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
+}
+
+static int
+bcm_check_blocks_with_parity0(struct bcm_softc *sc, uint32_t sig, int par_num,
+			      uint8_t print)
+{
+	uint32_t cur_bit = 0;
+	int i = 0;
+
+	for (i = 0; sig; i++) {
+		cur_bit = ((uint32_t) 0x1 << i);
+		if (sig & cur_bit) {
+			switch (cur_bit) {
+			case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "BRB");
+				break;
+			case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "PARSER");
+				break;
+			case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "TSDM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "SEARCHER");
+				break;
+			case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "TCM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "TSEMI");
+				break;
+			case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "XPB");
+				break;
+			}
+
+			/* Clear the bit */
+			sig &= ~cur_bit;
+		}
+	}
+
+	return par_num;
+}
+
+static int
+bcm_check_blocks_with_parity1(struct bcm_softc *sc, uint32_t sig, int par_num,
+			      uint8_t * global, uint8_t print)
+{
+	int i = 0;
+	uint32_t cur_bit = 0;
+	for (i = 0; sig; i++) {
+		cur_bit = ((uint32_t) 0x1 << i);
+		if (sig & cur_bit) {
+			switch (cur_bit) {
+			case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "PBF");
+				break;
+			case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "QM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "TM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "XSDM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "XCM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "XSEMI");
+				break;
+			case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "DOORBELLQ");
+				break;
+			case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "NIG");
+				break;
+			case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "VAUX PCI CORE");
+				*global = TRUE;
+				break;
+			case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "DEBUG");
+				break;
+			case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "USDM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "UCM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "USEMI");
+				break;
+			case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "UPB");
+				break;
+			case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "CSDM");
+				break;
+			case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "CCM");
+				break;
+			}
+
+			/* Clear the bit */
+			sig &= ~cur_bit;
+		}
+	}
+
+	return par_num;
+}
+
+static int
+bcm_check_blocks_with_parity2(struct bcm_softc *sc, uint32_t sig, int par_num,
+			      uint8_t print)
+{
+	uint32_t cur_bit = 0;
+	int i = 0;
+
+	for (i = 0; sig; i++) {
+		cur_bit = ((uint32_t) 0x1 << i);
+		if (sig & cur_bit) {
+			switch (cur_bit) {
+			case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "CSEMI");
+				break;
+			case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "PXP");
+				break;
+			case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "PXPPCICLOCKCLIENT");
+				break;
+			case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "CFC");
+				break;
+			case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "CDU");
+				break;
+			case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "DMAE");
+				break;
+			case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "IGU");
+				break;
+			case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "MISC");
+				break;
+			}
+
+			/* Clear the bit */
+			sig &= ~cur_bit;
+		}
+	}
+
+	return par_num;
+}
+
+static int
+bcm_check_blocks_with_parity3(struct bcm_softc *sc, uint32_t sig, int par_num,
+			      uint8_t * global, uint8_t print)
+{
+	uint32_t cur_bit = 0;
+	int i = 0;
+
+	for (i = 0; sig; i++) {
+		cur_bit = ((uint32_t) 0x1 << i);
+		if (sig & cur_bit) {
+			switch (cur_bit) {
+			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "MCP ROM");
+				*global = TRUE;
+				break;
+			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "MCP UMP RX");
+				*global = TRUE;
+				break;
+			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "MCP UMP TX");
+				*global = TRUE;
+				break;
+			case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "MCP SCPAD");
+				*global = TRUE;
+				break;
+			}
+
+			/* Clear the bit */
+			sig &= ~cur_bit;
+		}
+	}
+
+	return par_num;
+}
+
+static int
+bcm_check_blocks_with_parity4(struct bcm_softc *sc, uint32_t sig, int par_num,
+			      uint8_t print)
+{
+	uint32_t cur_bit = 0;
+	int i = 0;
+
+	for (i = 0; sig; i++) {
+		cur_bit = ((uint32_t) 0x1 << i);
+		if (sig & cur_bit) {
+			switch (cur_bit) {
+			case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "PGLUE_B");
+				break;
+			case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
+				if (print)
+					bcm_print_next_block(sc, par_num++,
+							     "ATC");
+				break;
+			}
+
+			/* Clear the bit */
+			sig &= ~cur_bit;
+		}
+	}
+
+	return par_num;
+}
+
+static uint8_t
+bcm_parity_attn(struct bcm_softc *sc, uint8_t * global, uint8_t print,
+		uint32_t * sig)
+{
+	int par_num = 0;
+
+	if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
+	    (sig[1] & HW_PRTY_ASSERT_SET_1) ||
+	    (sig[2] & HW_PRTY_ASSERT_SET_2) ||
+	    (sig[3] & HW_PRTY_ASSERT_SET_3) ||
+	    (sig[4] & HW_PRTY_ASSERT_SET_4)) {
+		PMD_DRV_LOG(ERR,
+			    "Parity error: HW block parity attention:"
+			    "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
+			    (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
+			    (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
+			    (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
+			    (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
+			    (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
+
+		if (print)
+			PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
+
+		par_num =
+		    bcm_check_blocks_with_parity0(sc, sig[0] &
+						  HW_PRTY_ASSERT_SET_0,
+						  par_num, print);
+		par_num =
+		    bcm_check_blocks_with_parity1(sc, sig[1] &
+						  HW_PRTY_ASSERT_SET_1,
+						  par_num, global, print);
+		par_num =
+		    bcm_check_blocks_with_parity2(sc, sig[2] &
+						  HW_PRTY_ASSERT_SET_2,
+						  par_num, print);
+		par_num =
+		    bcm_check_blocks_with_parity3(sc, sig[3] &
+						  HW_PRTY_ASSERT_SET_3,
+						  par_num, global, print);
+		par_num =
+		    bcm_check_blocks_with_parity4(sc, sig[4] &
+						  HW_PRTY_ASSERT_SET_4,
+						  par_num, print);
+
+		if (print)
+			PMD_DRV_LOG(INFO, "");
+
+		return TRUE;
+	}
+
+	return FALSE;
+}
+
+static uint8_t
+bcm_chk_parity_attn(struct bcm_softc *sc, uint8_t * global, uint8_t print)
+{
+	struct attn_route attn = { {0} };
+	int port = SC_PORT(sc);
+
+	attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
+	attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
+	attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
+	attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
+
+	if (!CHIP_IS_E1x(sc))
+		attn.sig[4] =
+		    REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
+
+	return bcm_parity_attn(sc, global, print, attn.sig);
+}
+
+static void bcm_attn_int_deasserted4(struct bcm_softc *sc, uint32_t attn)
+{
+	uint32_t val;
+
+	if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
+		val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
+		PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
+		if (val &
+		    PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
+		if (val &
+		    PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
+	}
+
+	if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
+		val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
+		PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
+		if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
+		if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
+		if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
+		if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
+		if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
+		if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
+			PMD_DRV_LOG(INFO,
+				    "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
+	}
+
+	if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
+		    AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
+		PMD_DRV_LOG(INFO,
+			    "ERROR: FATAL parity attention set4 0x%08x",
+			    (uint32_t) (attn &
+					(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
+					 |
+					 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
+	}
+}
+
+static void bcm_e1h_disable(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+
+	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
+}
+
+static void bcm_e1h_enable(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+
+	REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
+}
+
+/*
+ * called due to MCP event (on pmf):
+ *   reread new bandwidth configuration
+ *   configure FW
+ *   notify others function about the change
+ */
+static void bcm_config_mf_bw(struct bcm_softc *sc)
+{
+	if (sc->link_vars.link_up) {
+		bcm_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
+		bcm_link_sync_notify(sc);
+	}
+
+	storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
+}
+
+static void bcm_set_mf_bw(struct bcm_softc *sc)
+{
+	bcm_config_mf_bw(sc);
+	bcm_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
+}
+
+static void bcm_handle_eee_event(struct bcm_softc *sc)
+{
+	bcm_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
+}
+
+#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
+
+static void bcm_drv_info_ether_stat(struct bcm_softc *sc)
+{
+	struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
+
+	strncpy(ether_stat->version, BCM_DRIVER_VERSION,
+		ETH_STAT_INFO_VERSION_LEN);
+
+	sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
+					      DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
+					      ether_stat->mac_local + MAC_PAD,
+					      MAC_PAD, ETH_ALEN);
+
+	ether_stat->mtu_size = sc->mtu;
+
+	ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
+	ether_stat->promiscuous_mode = 0;	// (flags & PROMISC) ? 1 : 0;
+
+	ether_stat->txq_size = sc->tx_ring_size;
+	ether_stat->rxq_size = sc->rx_ring_size;
+}
+
+static void bcm_handle_drv_info_req(struct bcm_softc *sc)
+{
+	enum drv_info_opcode op_code;
+	uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
+
+	/* if drv_info version supported by MFW doesn't match - send NACK */
+	if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
+		bcm_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
+		return;
+	}
+
+	op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
+		   DRV_INFO_CONTROL_OP_CODE_SHIFT);
+
+	memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
+
+	switch (op_code) {
+	case ETH_STATS_OPCODE:
+		bcm_drv_info_ether_stat(sc);
+		break;
+	case FCOE_STATS_OPCODE:
+	case ISCSI_STATS_OPCODE:
+	default:
+		/* if op code isn't supported - send NACK */
+		bcm_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
+		return;
+	}
+
+	/*
+	 * If we got drv_info attn from MFW then these fields are defined in
+	 * shmem2 for sure
+	 */
+	SHMEM2_WR(sc, drv_info_host_addr_lo,
+		  U64_LO(BCM_SP_MAPPING(sc, drv_info_to_mcp)));
+	SHMEM2_WR(sc, drv_info_host_addr_hi,
+		  U64_HI(BCM_SP_MAPPING(sc, drv_info_to_mcp)));
+
+	bcm_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
+}
+
+static void bcm_dcc_event(struct bcm_softc *sc, uint32_t dcc_event)
+{
+	if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
+/*
+ * This is the only place besides the function initialization
+ * where the sc->flags can change so it is done without any
+ * locks
+ */
+		if (sc->devinfo.
+		    mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
+			PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
+			sc->flags |= BCM_MF_FUNC_DIS;
+			bcm_e1h_disable(sc);
+		} else {
+			PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
+			sc->flags &= ~BCM_MF_FUNC_DIS;
+			bcm_e1h_enable(sc);
+		}
+		dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
+	}
+
+	if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
+		bcm_config_mf_bw(sc);
+		dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
+	}
+
+	/* Report results to MCP */
+	if (dcc_event)
+		bcm_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
+	else
+		bcm_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
+}
+
+static void bcm_pmf_update(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	uint32_t val;
+
+	sc->port.pmf = 1;
+
+	/*
+	 * We need the mb() to ensure the ordering between the writing to
+	 * sc->port.pmf here and reading it from the bcm_periodic_task().
+	 */
+	mb();
+
+	/* enable nig attention */
+	val = (0xff0f | (1 << (SC_VN(sc) + 4)));
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
+		REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
+	} else if (!CHIP_IS_E1x(sc)) {
+		REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
+		REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
+	}
+
+	bcm_stats_handle(sc, STATS_EVENT_PMF);
+}
+
+static int bcm_mc_assert(struct bcm_softc *sc)
+{
+	char last_idx;
+	int i, rc = 0;
+	__rte_unused uint32_t row0, row1, row2, row3;
+
+	/* XSTORM */
+	last_idx =
+	    REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
+	if (last_idx)
+		PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+
+	/* print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 =
+		    REG_RD(sc,
+			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
+		row1 =
+		    REG_RD(sc,
+			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
+			   4);
+		row2 =
+		    REG_RD(sc,
+			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
+			   8);
+		row3 =
+		    REG_RD(sc,
+			   BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
+			   12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			PMD_DRV_LOG(ERR,
+				    "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
+				    i, row3, row2, row1, row0);
+			rc++;
+		} else {
+			break;
+		}
+	}
+
+	/* TSTORM */
+	last_idx =
+	    REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
+	if (last_idx) {
+		PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+	}
+
+	/* print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 =
+		    REG_RD(sc,
+			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
+		row1 =
+		    REG_RD(sc,
+			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
+			   4);
+		row2 =
+		    REG_RD(sc,
+			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
+			   8);
+		row3 =
+		    REG_RD(sc,
+			   BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
+			   12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			PMD_DRV_LOG(ERR,
+				    "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
+				    i, row3, row2, row1, row0);
+			rc++;
+		} else {
+			break;
+		}
+	}
+
+	/* CSTORM */
+	last_idx =
+	    REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
+	if (last_idx) {
+		PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+	}
+
+	/* print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 =
+		    REG_RD(sc,
+			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
+		row1 =
+		    REG_RD(sc,
+			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
+			   4);
+		row2 =
+		    REG_RD(sc,
+			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
+			   8);
+		row3 =
+		    REG_RD(sc,
+			   BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
+			   12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			PMD_DRV_LOG(ERR,
+				    "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
+				    i, row3, row2, row1, row0);
+			rc++;
+		} else {
+			break;
+		}
+	}
+
+	/* USTORM */
+	last_idx =
+	    REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
+	if (last_idx) {
+		PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
+	}
+
+	/* print the asserts */
+	for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
+
+		row0 =
+		    REG_RD(sc,
+			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
+		row1 =
+		    REG_RD(sc,
+			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
+			   4);
+		row2 =
+		    REG_RD(sc,
+			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
+			   8);
+		row3 =
+		    REG_RD(sc,
+			   BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
+			   12);
+
+		if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+			PMD_DRV_LOG(ERR,
+				    "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
+				    i, row3, row2, row1, row0);
+			rc++;
+		} else {
+			break;
+		}
+	}
+
+	return rc;
+}
+
+static void bcm_attn_int_deasserted3(struct bcm_softc *sc, uint32_t attn)
+{
+	int func = SC_FUNC(sc);
+	uint32_t val;
+
+	if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
+
+		if (attn & BCM_PMF_LINK_ASSERT(sc)) {
+
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
+			bcm_read_mf_cfg(sc);
+			sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
+			    MFCFG_RD(sc,
+				     func_mf_config[SC_ABS_FUNC(sc)].config);
+			val =
+			    SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
+
+			if (val & DRV_STATUS_DCC_EVENT_MASK)
+				bcm_dcc_event(sc,
+					      (val &
+					       DRV_STATUS_DCC_EVENT_MASK));
+
+			if (val & DRV_STATUS_SET_MF_BW)
+				bcm_set_mf_bw(sc);
+
+			if (val & DRV_STATUS_DRV_INFO_REQ)
+				bcm_handle_drv_info_req(sc);
+
+			if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
+				bcm_pmf_update(sc);
+
+			if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
+				bcm_handle_eee_event(sc);
+
+			if (sc->link_vars.periodic_flags &
+			    ELINK_PERIODIC_FLAGS_LINK_EVENT) {
+				/* sync with link */
+				sc->link_vars.periodic_flags &=
+				    ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
+				if (IS_MF(sc)) {
+					bcm_link_sync_notify(sc);
+				}
+				bcm_link_report(sc);
+			}
+
+			/*
+			 * Always call it here: bcm_link_report() will
+			 * prevent the link indication duplication.
+			 */
+			bcm_link_status_update(sc);
+
+		} else if (attn & BCM_MC_ASSERT_BITS) {
+
+			PMD_DRV_LOG(ERR, "MC assert!");
+			bcm_mc_assert(sc);
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
+			rte_panic("MC assert!");
+
+		} else if (attn & BCM_MCP_ASSERT) {
+
+			PMD_DRV_LOG(ERR, "MCP assert!");
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
+
+		} else {
+			PMD_DRV_LOG(ERR,
+				    "Unknown HW assert! (attn 0x%08x)", attn);
+		}
+	}
+
+	if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
+		PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
+		if (attn & BCM_GRC_TIMEOUT) {
+			val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
+			PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
+		}
+		if (attn & BCM_GRC_RSV) {
+			val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
+			PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
+		}
+		REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
+	}
+}
+
+static void bcm_attn_int_deasserted2(struct bcm_softc *sc, uint32_t attn)
+{
+	int port = SC_PORT(sc);
+	int reg_offset;
+	uint32_t val0, mask0, val1, mask1;
+	uint32_t val;
+
+	if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
+		val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
+		PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
+/* CFC error attention */
+		if (val & 0x2) {
+			PMD_DRV_LOG(ERR, "FATAL error from CFC");
+		}
+	}
+
+	if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
+		val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
+		PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
+/* RQ_USDMDP_FIFO_OVERFLOW */
+		if (val & 0x18000) {
+			PMD_DRV_LOG(ERR, "FATAL error from PXP");
+		}
+
+		if (!CHIP_IS_E1x(sc)) {
+			val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
+			PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
+		}
+	}
+#define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
+#define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
+
+	if (attn & AEU_PXP2_HW_INT_BIT) {
+/*  CQ47854 workaround do not panic on
+ *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
+ */
+		if (!CHIP_IS_E1x(sc)) {
+			mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
+			val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
+			mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
+			val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
+			/*
+			 * If the olny PXP2_EOP_ERROR_BIT is set in
+			 * STS0 and STS1 - clear it
+			 *
+			 * probably we lose additional attentions between
+			 * STS0 and STS_CLR0, in this case user will not
+			 * be notified about them
+			 */
+			if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
+			    !(val1 & mask1))
+				val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
+
+			/* print the register, since no one can restore it */
+			PMD_DRV_LOG(ERR,
+				    "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
+
+			/*
+			 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
+			 * then notify
+			 */
+			if (val0 & PXP2_EOP_ERROR_BIT) {
+				PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
+
+				/*
+				 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
+				 * set then clear attention from PXP2 block without panic
+				 */
+				if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
+				    ((val1 & mask1) == 0))
+					attn &= ~AEU_PXP2_HW_INT_BIT;
+			}
+		}
+	}
+
+	if (attn & HW_INTERRUT_ASSERT_SET_2) {
+		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
+			      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
+
+		val = REG_RD(sc, reg_offset);
+		val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
+		REG_WR(sc, reg_offset, val);
+
+		PMD_DRV_LOG(ERR,
+			    "FATAL HW block attention set2 0x%x",
+			    (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
+		rte_panic("HW block attention set2");
+	}
+}
+
+static void bcm_attn_int_deasserted1(struct bcm_softc *sc, uint32_t attn)
+{
+	int port = SC_PORT(sc);
+	int reg_offset;
+	uint32_t val;
+
+	if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
+		val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
+		PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
+/* DORQ discard attention */
+		if (val & 0x2) {
+			PMD_DRV_LOG(ERR, "FATAL error from DORQ");
+		}
+	}
+
+	if (attn & HW_INTERRUT_ASSERT_SET_1) {
+		reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
+			      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
+
+		val = REG_RD(sc, reg_offset);
+		val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
+		REG_WR(sc, reg_offset, val);
+
+		PMD_DRV_LOG(ERR,
+			    "FATAL HW block attention set1 0x%08x",
+			    (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
+		rte_panic("HW block attention set1");
+	}
+}
+
+static void bcm_attn_int_deasserted0(struct bcm_softc *sc, uint32_t attn)
+{
+	int port = SC_PORT(sc);
+	int reg_offset;
+	uint32_t val;
+
+	reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
+
+	if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
+		val = REG_RD(sc, reg_offset);
+		val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
+		REG_WR(sc, reg_offset, val);
+
+		PMD_DRV_LOG(WARN, "SPIO5 hw attention");
+
+/* Fan failure attention */
+		elink_hw_reset_phy(&sc->link_params);
+		bcm_fan_failure(sc);
+	}
+
+	if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
+		elink_handle_module_detect_int(&sc->link_params);
+	}
+
+	if (attn & HW_INTERRUT_ASSERT_SET_0) {
+		val = REG_RD(sc, reg_offset);
+		val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
+		REG_WR(sc, reg_offset, val);
+
+		rte_panic("FATAL HW block attention set0 0x%lx",
+			  (attn & HW_INTERRUT_ASSERT_SET_0));
+	}
+}
+
+static void bcm_attn_int_deasserted(struct bcm_softc *sc, uint32_t deasserted)
+{
+	struct attn_route attn;
+	struct attn_route *group_mask;
+	int port = SC_PORT(sc);
+	int index;
+	uint32_t reg_addr;
+	uint32_t val;
+	uint32_t aeu_mask;
+	uint8_t global = FALSE;
+
+	/*
+	 * Need to take HW lock because MCP or other port might also
+	 * try to handle this event.
+	 */
+	bcm_acquire_alr(sc);
+
+	if (bcm_chk_parity_attn(sc, &global, TRUE)) {
+		sc->recovery_state = BCM_RECOVERY_INIT;
+
+/* disable HW interrupts */
+		bcm_int_disable(sc);
+		bcm_release_alr(sc);
+		return;
+	}
+
+	attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
+	attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
+	attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
+	attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
+	if (!CHIP_IS_E1x(sc)) {
+		attn.sig[4] =
+		    REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
+	} else {
+		attn.sig[4] = 0;
+	}
+
+	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
+		if (deasserted & (1 << index)) {
+			group_mask = &sc->attn_group[index];
+
+			bcm_attn_int_deasserted4(sc,
+						 attn.
+						 sig[4] & group_mask->sig[4]);
+			bcm_attn_int_deasserted3(sc,
+						 attn.
+						 sig[3] & group_mask->sig[3]);
+			bcm_attn_int_deasserted1(sc,
+						 attn.
+						 sig[1] & group_mask->sig[1]);
+			bcm_attn_int_deasserted2(sc,
+						 attn.
+						 sig[2] & group_mask->sig[2]);
+			bcm_attn_int_deasserted0(sc,
+						 attn.
+						 sig[0] & group_mask->sig[0]);
+		}
+	}
+
+	bcm_release_alr(sc);
+
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		reg_addr = (HC_REG_COMMAND_REG + port * 32 +
+			    COMMAND_REG_ATTN_BITS_CLR);
+	} else {
+		reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
+	}
+
+	val = ~deasserted;
+	PMD_DRV_LOG(DEBUG,
+		    "about to mask 0x%08x at %s addr 0x%08x", val,
+		    (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
+		    reg_addr);
+	REG_WR(sc, reg_addr, val);
+
+	if (~sc->attn_state & deasserted) {
+		PMD_DRV_LOG(ERR, "IGU error");
+	}
+
+	reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
+	    MISC_REG_AEU_MASK_ATTN_FUNC_0;
+
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+
+	aeu_mask = REG_RD(sc, reg_addr);
+
+	aeu_mask |= (deasserted & 0x3ff);
+
+	REG_WR(sc, reg_addr, aeu_mask);
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
+
+	sc->attn_state &= ~deasserted;
+}
+
+static void bcm_attn_int(struct bcm_softc *sc)
+{
+	/* read local copy of bits */
+	uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
+	uint32_t attn_ack =
+	    le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
+	uint32_t attn_state = sc->attn_state;
+
+	/* look for changed bits */
+	uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
+	uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
+
+	PMD_DRV_LOG(DEBUG,
+		    "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
+		    attn_bits, attn_ack, asserted, deasserted);
+
+	if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
+		PMD_DRV_LOG(ERR, "BAD attention state");
+	}
+
+	/* handle bits that were raised */
+	if (asserted) {
+		bcm_attn_int_asserted(sc, asserted);
+	}
+
+	if (deasserted) {
+		bcm_attn_int_deasserted(sc, deasserted);
+	}
+}
+
+static uint16_t bcm_update_dsb_idx(struct bcm_softc *sc)
+{
+	struct host_sp_status_block *def_sb = sc->def_sb;
+	uint16_t rc = 0;
+
+	mb();			/* status block is written to by the chip */
+
+	if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
+		sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
+		rc |= BCM_DEF_SB_ATT_IDX;
+	}
+
+	if (sc->def_idx != def_sb->sp_sb.running_index) {
+		sc->def_idx = def_sb->sp_sb.running_index;
+		rc |= BCM_DEF_SB_IDX;
+	}
+
+	mb();
+
+	return rc;
+}
+
+static struct ecore_queue_sp_obj *bcm_cid_to_q_obj(struct bcm_softc *sc,
+							  uint32_t cid)
+{
+	return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
+}
+
+static void bcm_handle_mcast_eqe(struct bcm_softc *sc)
+{
+	struct ecore_mcast_ramrod_params rparam;
+	int rc;
+
+	memset(&rparam, 0, sizeof(rparam));
+
+	rparam.mcast_obj = &sc->mcast_obj;
+
+	/* clear pending state for the last command */
+	sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
+
+	/* if there are pending mcast commands - send them */
+	if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
+		rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
+		if (rc < 0) {
+			PMD_DRV_LOG(INFO,
+				    "Failed to send pending mcast commands (%d)",
+				    rc);
+		}
+	}
+}
+
+static void
+bcm_handle_classification_eqe(struct bcm_softc *sc, union event_ring_elem *elem)
+{
+	unsigned long ramrod_flags = 0;
+	int rc = 0;
+	uint32_t cid = elem->message.data.eth_event.echo & BCM_SWCID_MASK;
+	struct ecore_vlan_mac_obj *vlan_mac_obj;
+
+	/* always push next commands out, don't wait here */
+	bcm_set_bit(RAMROD_CONT, &ramrod_flags);
+
+	switch (le32toh(elem->message.data.eth_event.echo) >> BCM_SWCID_SHIFT) {
+	case ECORE_FILTER_MAC_PENDING:
+		PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
+		vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
+		break;
+
+	case ECORE_FILTER_MCAST_PENDING:
+		PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
+		bcm_handle_mcast_eqe(sc);
+		return;
+
+	default:
+		PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
+			    elem->message.data.eth_event.echo);
+		return;
+	}
+
+	rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
+
+	if (rc < 0) {
+		PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
+	} else if (rc > 0) {
+		PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
+	}
+}
+
+static void bcm_handle_rx_mode_eqe(struct bcm_softc *sc)
+{
+	bcm_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
+
+	/* send rx_mode command again if was requested */
+	if (bcm_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
+		bcm_set_storm_rx_mode(sc);
+	}
+}
+
+static void bcm_update_eq_prod(struct bcm_softc *sc, uint16_t prod)
+{
+	storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
+	wmb();			/* keep prod updates ordered */
+}
+
+static void bcm_eq_int(struct bcm_softc *sc)
+{
+	uint16_t hw_cons, sw_cons, sw_prod;
+	union event_ring_elem *elem;
+	uint8_t echo;
+	uint32_t cid;
+	uint8_t opcode;
+	int spqe_cnt = 0;
+	struct ecore_queue_sp_obj *q_obj;
+	struct ecore_func_sp_obj *f_obj = &sc->func_obj;
+	struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
+
+	hw_cons = le16toh(*sc->eq_cons_sb);
+
+	/*
+	 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
+	 * when we get to the next-page we need to adjust so the loop
+	 * condition below will be met. The next element is the size of a
+	 * regular element and hence incrementing by 1
+	 */
+	if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
+		hw_cons++;
+	}
+
+	/*
+	 * This function may never run in parallel with itself for a
+	 * specific sc and no need for a read memory barrier here.
+	 */
+	sw_cons = sc->eq_cons;
+	sw_prod = sc->eq_prod;
+
+	for (;
+	     sw_cons != hw_cons;
+	     sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
+
+		elem = &sc->eq[EQ_DESC(sw_cons)];
+
+/* elem CID originates from FW, actually LE */
+		cid = SW_CID(elem->message.data.cfc_del_event.cid);
+		opcode = elem->message.opcode;
+
+/* handle eq element */
+		switch (opcode) {
+		case EVENT_RING_OPCODE_STAT_QUERY:
+			PMD_DRV_LOG(DEBUG, "got statistics completion event %d",
+				    sc->stats_comp++);
+			/* nothing to do with stats comp */
+			goto next_spqe;
+
+		case EVENT_RING_OPCODE_CFC_DEL:
+			/* handle according to cid range */
+			/* we may want to verify here that the sc state is HALTING */
+			PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
+				    cid);
+			q_obj = bcm_cid_to_q_obj(sc, cid);
+			if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
+				break;
+			}
+			goto next_spqe;
+
+		case EVENT_RING_OPCODE_STOP_TRAFFIC:
+			PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
+			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
+				break;
+			}
+			goto next_spqe;
+
+		case EVENT_RING_OPCODE_START_TRAFFIC:
+			PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
+			if (f_obj->complete_cmd
+			    (sc, f_obj, ECORE_F_CMD_TX_START)) {
+				break;
+			}
+			goto next_spqe;
+
+		case EVENT_RING_OPCODE_FUNCTION_UPDATE:
+			echo = elem->message.data.function_update_event.echo;
+			if (echo == SWITCH_UPDATE) {
+				PMD_DRV_LOG(DEBUG,
+					    "got FUNC_SWITCH_UPDATE ramrod");
+				if (f_obj->complete_cmd(sc, f_obj,
+							ECORE_F_CMD_SWITCH_UPDATE))
+				{
+					break;
+				}
+			} else {
+				PMD_DRV_LOG(DEBUG,
+					    "AFEX: ramrod completed FUNCTION_UPDATE");
+				f_obj->complete_cmd(sc, f_obj,
+						    ECORE_F_CMD_AFEX_UPDATE);
+			}
+			goto next_spqe;
+
+		case EVENT_RING_OPCODE_FORWARD_SETUP:
+			q_obj = &bcm_fwd_sp_obj(sc, q_obj);
+			if (q_obj->complete_cmd(sc, q_obj,
+						ECORE_Q_CMD_SETUP_TX_ONLY)) {
+				break;
+			}
+			goto next_spqe;
+
+		case EVENT_RING_OPCODE_FUNCTION_START:
+			PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
+			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
+				break;
+			}
+			goto next_spqe;
+
+		case EVENT_RING_OPCODE_FUNCTION_STOP:
+			PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
+			if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
+				break;
+			}
+			goto next_spqe;
+		}
+
+		switch (opcode | sc->state) {
+		case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BCM_STATE_OPEN):
+		case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BCM_STATE_OPENING_WAITING_PORT):
+			cid =
+			    elem->message.data.eth_event.echo & BCM_SWCID_MASK;
+			PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
+				    cid);
+			rss_raw->clear_pending(rss_raw);
+			break;
+
+		case (EVENT_RING_OPCODE_SET_MAC | BCM_STATE_OPEN):
+		case (EVENT_RING_OPCODE_SET_MAC | BCM_STATE_DIAG):
+		case (EVENT_RING_OPCODE_SET_MAC | BCM_STATE_CLOSING_WAITING_HALT):
+		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BCM_STATE_OPEN):
+		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BCM_STATE_DIAG):
+		case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BCM_STATE_CLOSING_WAITING_HALT):
+			PMD_DRV_LOG(DEBUG,
+				    "got (un)set mac ramrod");
+			bcm_handle_classification_eqe(sc, elem);
+			break;
+
+		case (EVENT_RING_OPCODE_MULTICAST_RULES | BCM_STATE_OPEN):
+		case (EVENT_RING_OPCODE_MULTICAST_RULES | BCM_STATE_DIAG):
+		case (EVENT_RING_OPCODE_MULTICAST_RULES | BCM_STATE_CLOSING_WAITING_HALT):
+			PMD_DRV_LOG(DEBUG,
+				    "got mcast ramrod");
+			bcm_handle_mcast_eqe(sc);
+			break;
+
+		case (EVENT_RING_OPCODE_FILTERS_RULES | BCM_STATE_OPEN):
+		case (EVENT_RING_OPCODE_FILTERS_RULES | BCM_STATE_DIAG):
+		case (EVENT_RING_OPCODE_FILTERS_RULES | BCM_STATE_CLOSING_WAITING_HALT):
+			PMD_DRV_LOG(DEBUG,
+				    "got rx_mode ramrod");
+			bcm_handle_rx_mode_eqe(sc);
+			break;
+
+		default:
+			/* unknown event log error and continue */
+			PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
+				    elem->message.opcode, sc->state);
+		}
+
+next_spqe:
+		spqe_cnt++;
+	}			/* for */
+
+	mb();
+	atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
+
+	sc->eq_cons = sw_cons;
+	sc->eq_prod = sw_prod;
+
+	/* make sure that above mem writes were issued towards the memory */
+	wmb();
+
+	/* update producer */
+	bcm_update_eq_prod(sc, sc->eq_prod);
+}
+
+static int bcm_handle_sp_tq(struct bcm_softc *sc)
+{
+	uint16_t status;
+	int rc = 0;
+
+	/* what work needs to be performed? */
+	status = bcm_update_dsb_idx(sc);
+
+	/* HW attentions */
+	if (status & BCM_DEF_SB_ATT_IDX) {
+		PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
+		bcm_attn_int(sc);
+		status &= ~BCM_DEF_SB_ATT_IDX;
+		rc = 1;
+	}
+
+	/* SP events: STAT_QUERY and others */
+	if (status & BCM_DEF_SB_IDX) {
+/* handle EQ completions */
+		PMD_DRV_LOG(DEBUG, "---> EQ INTR <---");
+		bcm_eq_int(sc);
+		bcm_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
+			   le16toh(sc->def_idx), IGU_INT_NOP, 1);
+		status &= ~BCM_DEF_SB_IDX;
+	}
+
+	/* if status is non zero then something went wrong */
+	if (unlikely(status)) {
+		PMD_DRV_LOG(INFO,
+			    "Got an unknown SP interrupt! (0x%04x)", status);
+	}
+
+	/* ack status block only if something was actually handled */
+	bcm_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
+		   le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
+
+	return rc;
+}
+
+static void bcm_handle_fp_tq(struct bcm_fastpath *fp, int scan_fp)
+{
+	struct bcm_softc *sc = fp->sc;
+	uint8_t more_rx = FALSE;
+
+	/* update the fastpath index */
+	bcm_update_fp_sb_idx(fp);
+
+	if (scan_fp) {
+		if (bcm_has_rx_work(fp)) {
+			more_rx = bcm_rxeof(sc, fp);
+		}
+
+		if (more_rx) {
+			/* still more work to do */
+			bcm_handle_fp_tq(fp, scan_fp);
+			return;
+		}
+	}
+
+	bcm_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
+		   le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
+}
+
+/*
+ * Legacy interrupt entry point.
+ *
+ * Verifies that the controller generated the interrupt and
+ * then calls a separate routine to handle the various
+ * interrupt causes: link, RX, and TX.
+ */
+int bcm_intr_legacy(struct bcm_softc *sc, int scan_fp)
+{
+	struct bcm_fastpath *fp;
+	uint32_t status, mask;
+	int i, rc = 0;
+
+	/*
+	 * 0 for ustorm, 1 for cstorm
+	 * the bits returned from ack_int() are 0-15
+	 * bit 0 = attention status block
+	 * bit 1 = fast path status block
+	 * a mask of 0x2 or more = tx/rx event
+	 * a mask of 1 = slow path event
+	 */
+
+	status = bcm_ack_int(sc);
+
+	/* the interrupt is not for us */
+	if (unlikely(status == 0)) {
+		return 0;
+	}
+
+	PMD_DRV_LOG(DEBUG, "Interrupt status 0x%04x", status);
+	//bcm_dump_status_block(sc);
+
+	FOR_EACH_ETH_QUEUE(sc, i) {
+		fp = &sc->fp[i];
+		mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
+		if (status & mask) {
+			bcm_handle_fp_tq(fp, scan_fp);
+			status &= ~mask;
+		}
+	}
+
+	if (unlikely(status & 0x1)) {
+		rc = bcm_handle_sp_tq(sc);
+		status &= ~0x1;
+	}
+
+	if (unlikely(status)) {
+		PMD_DRV_LOG(WARN,
+			    "Unexpected fastpath status (0x%08x)!", status);
+	}
+
+	return rc;
+}
+
+static int bcm_init_hw_common_chip(struct bcm_softc *sc);
+static int bcm_init_hw_common(struct bcm_softc *sc);
+static int bcm_init_hw_port(struct bcm_softc *sc);
+static int bcm_init_hw_func(struct bcm_softc *sc);
+static void bcm_reset_common(struct bcm_softc *sc);
+static void bcm_reset_port(struct bcm_softc *sc);
+static void bcm_reset_func(struct bcm_softc *sc);
+static int bcm_init_firmware(struct bcm_softc *sc);
+static void bcm_release_firmware(struct bcm_softc *sc);
+
+static struct
+ecore_func_sp_drv_ops bcm_func_sp_drv = {
+	.init_hw_cmn_chip = bcm_init_hw_common_chip,
+	.init_hw_cmn = bcm_init_hw_common,
+	.init_hw_port = bcm_init_hw_port,
+	.init_hw_func = bcm_init_hw_func,
+
+	.reset_hw_cmn = bcm_reset_common,
+	.reset_hw_port = bcm_reset_port,
+	.reset_hw_func = bcm_reset_func,
+
+	.init_fw = bcm_init_firmware,
+	.release_fw = bcm_release_firmware,
+};
+
+static void bcm_init_func_obj(struct bcm_softc *sc)
+{
+	sc->dmae_ready = 0;
+
+	PMD_INIT_FUNC_TRACE();
+
+	ecore_init_func_obj(sc,
+			    &sc->func_obj,
+			    BCM_SP(sc, func_rdata), (phys_addr_t) ((void *)
+								   BCM_SP_MAPPING(sc, func_rdata)), BCM_SP(sc, func_afex_rdata), (phys_addr_t) ((void *)
+																		BCM_SP_MAPPING(sc, func_afex_rdata)), &bcm_func_sp_drv);
+}
+
+static int bcm_init_hw(struct bcm_softc *sc, uint32_t load_code)
+{
+	struct ecore_func_state_params func_params = { NULL };
+	int rc;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/* prepare the parameters for function state transitions */
+	bcm_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
+
+	func_params.f_obj = &sc->func_obj;
+	func_params.cmd = ECORE_F_CMD_HW_INIT;
+
+	func_params.params.hw_init.load_phase = load_code;
+
+	/*
+	 * Via a plethora of function pointers, we will eventually reach
+	 * bcm_init_hw_common(), bcm_init_hw_port(), or bcm_init_hw_func().
+	 */
+	rc = ecore_func_state_change(sc, &func_params);
+
+	return rc;
+}
+
+static void
+bcm_fill(struct bcm_softc *sc, uint32_t addr, int fill, uint32_t len)
+{
+	uint32_t i;
+
+	if (!(len % 4) && !(addr % 4)) {
+		for (i = 0; i < len; i += 4) {
+			REG_WR(sc, (addr + i), fill);
+		}
+	} else {
+		for (i = 0; i < len; i++) {
+			REG_WR8(sc, (addr + i), fill);
+		}
+	}
+}
+
+/* writes FP SP data to FW - data_size in dwords */
+static void
+bcm_wr_fp_sb_data(struct bcm_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
+		  uint32_t data_size)
+{
+	uint32_t index;
+
+	for (index = 0; index < data_size; index++) {
+		REG_WR(sc,
+		       (BAR_CSTRORM_INTMEM +
+			CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
+			(sizeof(uint32_t) * index)), *(sb_data_p + index));
+	}
+}
+
+static void bcm_zero_fp_sb(struct bcm_softc *sc, int fw_sb_id)
+{
+	struct hc_status_block_data_e2 sb_data_e2;
+	struct hc_status_block_data_e1x sb_data_e1x;
+	uint32_t *sb_data_p;
+	uint32_t data_size = 0;
+
+	if (!CHIP_IS_E1x(sc)) {
+		memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
+		sb_data_e2.common.state = SB_DISABLED;
+		sb_data_e2.common.p_func.vf_valid = FALSE;
+		sb_data_p = (uint32_t *) & sb_data_e2;
+		data_size = (sizeof(struct hc_status_block_data_e2) /
+			     sizeof(uint32_t));
+	} else {
+		memset(&sb_data_e1x, 0,
+		       sizeof(struct hc_status_block_data_e1x));
+		sb_data_e1x.common.state = SB_DISABLED;
+		sb_data_e1x.common.p_func.vf_valid = FALSE;
+		sb_data_p = (uint32_t *) & sb_data_e1x;
+		data_size = (sizeof(struct hc_status_block_data_e1x) /
+			     sizeof(uint32_t));
+	}
+
+	bcm_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
+
+	bcm_fill(sc,
+		 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
+		 CSTORM_STATUS_BLOCK_SIZE);
+	bcm_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
+		 0, CSTORM_SYNC_BLOCK_SIZE);
+}
+
+static void
+bcm_wr_sp_sb_data(struct bcm_softc *sc,
+		  struct hc_sp_status_block_data *sp_sb_data)
+{
+	uint32_t i;
+
+	for (i = 0;
+	     i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
+	     i++) {
+		REG_WR(sc,
+		       (BAR_CSTRORM_INTMEM +
+			CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
+			(i * sizeof(uint32_t))),
+		       *((uint32_t *) sp_sb_data + i));
+	}
+}
+
+static void bcm_zero_sp_sb(struct bcm_softc *sc)
+{
+	struct hc_sp_status_block_data sp_sb_data;
+
+	memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
+
+	sp_sb_data.state = SB_DISABLED;
+	sp_sb_data.p_func.vf_valid = FALSE;
+
+	bcm_wr_sp_sb_data(sc, &sp_sb_data);
+
+	bcm_fill(sc,
+		 (BAR_CSTRORM_INTMEM +
+		  CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
+		 0, CSTORM_SP_STATUS_BLOCK_SIZE);
+	bcm_fill(sc,
+		 (BAR_CSTRORM_INTMEM +
+		  CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
+		 0, CSTORM_SP_SYNC_BLOCK_SIZE);
+}
+
+static void
+bcm_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
+			     int igu_seg_id)
+{
+	hc_sm->igu_sb_id = igu_sb_id;
+	hc_sm->igu_seg_id = igu_seg_id;
+	hc_sm->timer_value = 0xFF;
+	hc_sm->time_to_expire = 0xFFFFFFFF;
+}
+
+static void bcm_map_sb_state_machines(struct hc_index_data *index_data)
+{
+	/* zero out state machine indices */
+
+	/* rx indices */
+	index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
+
+	/* tx indices */
+	index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
+	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
+	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
+	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
+
+	/* map indices */
+
+	/* rx indices */
+	index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
+	    (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
+
+	/* tx indices */
+	index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
+	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
+	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
+	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
+	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
+	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
+	index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
+	    (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
+}
+
+static void
+bcm_init_sb(struct bcm_softc *sc, phys_addr_t busaddr, int vfid,
+	    uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
+{
+	struct hc_status_block_data_e2 sb_data_e2;
+	struct hc_status_block_data_e1x sb_data_e1x;
+	struct hc_status_block_sm *hc_sm_p;
+	uint32_t *sb_data_p;
+	int igu_seg_id;
+	int data_size;
+
+	if (CHIP_INT_MODE_IS_BC(sc)) {
+		igu_seg_id = HC_SEG_ACCESS_NORM;
+	} else {
+		igu_seg_id = IGU_SEG_ACCESS_NORM;
+	}
+
+	bcm_zero_fp_sb(sc, fw_sb_id);
+
+	if (!CHIP_IS_E1x(sc)) {
+		memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
+		sb_data_e2.common.state = SB_ENABLED;
+		sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
+		sb_data_e2.common.p_func.vf_id = vfid;
+		sb_data_e2.common.p_func.vf_valid = vf_valid;
+		sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
+		sb_data_e2.common.same_igu_sb_1b = TRUE;
+		sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
+		sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
+		hc_sm_p = sb_data_e2.common.state_machine;
+		sb_data_p = (uint32_t *) & sb_data_e2;
+		data_size = (sizeof(struct hc_status_block_data_e2) /
+			     sizeof(uint32_t));
+		bcm_map_sb_state_machines(sb_data_e2.index_data);
+	} else {
+		memset(&sb_data_e1x, 0,
+		       sizeof(struct hc_status_block_data_e1x));
+		sb_data_e1x.common.state = SB_ENABLED;
+		sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
+		sb_data_e1x.common.p_func.vf_id = 0xff;
+		sb_data_e1x.common.p_func.vf_valid = FALSE;
+		sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
+		sb_data_e1x.common.same_igu_sb_1b = TRUE;
+		sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
+		sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
+		hc_sm_p = sb_data_e1x.common.state_machine;
+		sb_data_p = (uint32_t *) & sb_data_e1x;
+		data_size = (sizeof(struct hc_status_block_data_e1x) /
+			     sizeof(uint32_t));
+		bcm_map_sb_state_machines(sb_data_e1x.index_data);
+	}
+
+	bcm_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
+	bcm_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
+
+	/* write indices to HW - PCI guarantees endianity of regpairs */
+	bcm_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
+}
+
+static uint8_t bcm_fp_qzone_id(struct bcm_fastpath *fp)
+{
+	if (CHIP_IS_E1x(fp->sc)) {
+		return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
+	} else {
+		return (fp->cl_id);
+	}
+}
+
+static uint32_t
+bcm_rx_ustorm_prods_offset(struct bcm_softc *sc, struct bcm_fastpath *fp)
+{
+	uint32_t offset = BAR_USTRORM_INTMEM;
+
+	if (IS_VF(sc)) {
+		return (PXP_VF_ADDR_USDM_QUEUES_START +
+			(sc->acquire_resp.resc.hw_qid[fp->index] *
+			 sizeof(struct ustorm_queue_zone_data)));
+	} else if (!CHIP_IS_E1x(sc)) {
+		offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
+	} else {
+		offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
+	}
+
+	return offset;
+}
+
+static void bcm_init_eth_fp(struct bcm_softc *sc, int idx)
+{
+	struct bcm_fastpath *fp = &sc->fp[idx];
+	uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
+	unsigned long q_type = 0;
+	int cos;
+
+	fp->sc = sc;
+	fp->index = idx;
+
+	fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
+	fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
+
+	if (CHIP_IS_E1x(sc))
+		fp->cl_id = SC_L_ID(sc) + idx;
+	else
+/* want client ID same as IGU SB ID for non-E1 */
+		fp->cl_id = fp->igu_sb_id;
+	fp->cl_qzone_id = bcm_fp_qzone_id(fp);
+
+	/* setup sb indices */
+	if (!CHIP_IS_E1x(sc)) {
+		fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
+		fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
+	} else {
+		fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
+		fp->sb_running_index =
+		    fp->status_block.e1x_sb->sb.running_index;
+	}
+
+	/* init shortcut */
+	fp->ustorm_rx_prods_offset = bcm_rx_ustorm_prods_offset(sc, fp);
+
+	fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
+
+	for (cos = 0; cos < sc->max_cos; cos++) {
+		cids[cos] = idx;
+	}
+	fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
+
+	/* nothing more for a VF to do */
+	if (IS_VF(sc)) {
+		return;
+	}
+
+	bcm_init_sb(sc, fp->sb_dma.paddr, BCM_VF_ID_INVALID, FALSE,
+		    fp->fw_sb_id, fp->igu_sb_id);
+
+	bcm_update_fp_sb_idx(fp);
+
+	/* Configure Queue State object */
+	bcm_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
+	bcm_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
+
+	ecore_init_queue_obj(sc,
+			     &sc->sp_objs[idx].q_obj,
+			     fp->cl_id,
+			     cids,
+			     sc->max_cos,
+			     SC_FUNC(sc),
+			     BCM_SP(sc, q_rdata), (phys_addr_t) ((void *)
+								 BCM_SP_MAPPING
+								 (sc, q_rdata)),
+			     q_type);
+
+	/* configure classification DBs */
+	ecore_init_mac_obj(sc,
+			   &sc->sp_objs[idx].mac_obj,
+			   fp->cl_id,
+			   idx,
+			   SC_FUNC(sc),
+			   BCM_SP(sc, mac_rdata), (phys_addr_t) ((void *)
+								 BCM_SP_MAPPING
+								 (sc,
+								  mac_rdata)),
+			   ECORE_FILTER_MAC_PENDING, &sc->sp_state,
+			   ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
+}
+
+static void
+bcm_update_rx_prod(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		   uint16_t rx_bd_prod, uint16_t rx_cq_prod)
+{
+	union ustorm_eth_rx_producers rx_prods;
+	uint32_t i;
+
+	/* update producers */
+	rx_prods.prod.bd_prod = rx_bd_prod;
+	rx_prods.prod.cqe_prod = rx_cq_prod;
+	rx_prods.prod.reserved = 0;
+
+	/*
+	 * Make sure that the BD and SGE data is updated before updating the
+	 * producers since FW might read the BD/SGE right after the producer
+	 * is updated.
+	 * This is only applicable for weak-ordered memory model archs such
+	 * as IA-64. The following barrier is also mandatory since FW will
+	 * assumes BDs must have buffers.
+	 */
+	wmb();
+
+	for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
+		REG_WR(sc,
+		       (fp->ustorm_rx_prods_offset + (i * 4)),
+		       rx_prods.raw_data[i]);
+	}
+
+	wmb();			/* keep prod updates ordered */
+}
+
+static void bcm_init_rx_rings(struct bcm_softc *sc)
+{
+	struct bcm_fastpath *fp;
+	int i;
+	struct bcm_rx_queue *rxq;
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		rxq = sc->rx_queues[fp->index];
+		if (!rxq) {
+			PMD_RX_LOG(ERR, "RX queue is NULL");
+			return;
+		}
+
+/*
+ * Activate the BD ring...
+ * Warning, this will generate an interrupt (to the TSTORM)
+ * so this can only be done after the chip is initialized
+ */
+		bcm_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
+
+		if (i != 0) {
+			continue;
+		}
+	}
+}
+
+static void bcm_init_tx_ring_one(struct bcm_fastpath *fp)
+{
+	struct bcm_tx_queue *txq = fp->sc->tx_queues[fp->index];
+
+	fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
+	fp->tx_db.data.zero_fill1 = 0;
+	fp->tx_db.data.prod = 0;
+
+	if (!txq) {
+		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
+		return;
+	}
+
+	txq->tx_pkt_tail = 0;
+	txq->tx_pkt_head = 0;
+	txq->tx_bd_tail = 0;
+	txq->tx_bd_head = 0;
+}
+
+static void bcm_init_tx_rings(struct bcm_softc *sc)
+{
+	int i;
+
+	for (i = 0; i < sc->num_queues; i++) {
+		bcm_init_tx_ring_one(&sc->fp[i]);
+	}
+}
+
+static void bcm_init_def_sb(struct bcm_softc *sc)
+{
+	struct host_sp_status_block *def_sb = sc->def_sb;
+	phys_addr_t mapping = sc->def_sb_dma.paddr;
+	int igu_sp_sb_index;
+	int igu_seg_id;
+	int port = SC_PORT(sc);
+	int func = SC_FUNC(sc);
+	int reg_offset, reg_offset_en5;
+	uint64_t section;
+	int index, sindex;
+	struct hc_sp_status_block_data sp_sb_data;
+
+	memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
+
+	if (CHIP_INT_MODE_IS_BC(sc)) {
+		igu_sp_sb_index = DEF_SB_IGU_ID;
+		igu_seg_id = HC_SEG_ACCESS_DEF;
+	} else {
+		igu_sp_sb_index = sc->igu_dsb_id;
+		igu_seg_id = IGU_SEG_ACCESS_DEF;
+	}
+
+	/* attentions */
+	section = ((uint64_t) mapping +
+		   offsetof(struct host_sp_status_block, atten_status_block));
+	def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
+	sc->attn_state = 0;
+
+	reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+	    MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
+
+	reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
+	    MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
+
+	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
+/* take care of sig[0]..sig[4] */
+		for (sindex = 0; sindex < 4; sindex++) {
+			sc->attn_group[index].sig[sindex] =
+			    REG_RD(sc,
+				   (reg_offset + (sindex * 0x4) +
+				    (0x10 * index)));
+		}
+
+		if (!CHIP_IS_E1x(sc)) {
+			/*
+			 * enable5 is separate from the rest of the registers,
+			 * and the address skip is 4 and not 16 between the
+			 * different groups
+			 */
+			sc->attn_group[index].sig[4] =
+			    REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
+		} else {
+			sc->attn_group[index].sig[4] = 0;
+		}
+	}
+
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		reg_offset =
+		    port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
+		REG_WR(sc, reg_offset, U64_LO(section));
+		REG_WR(sc, (reg_offset + 4), U64_HI(section));
+	} else if (!CHIP_IS_E1x(sc)) {
+		REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
+		REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
+	}
+
+	section = ((uint64_t) mapping +
+		   offsetof(struct host_sp_status_block, sp_sb));
+
+	bcm_zero_sp_sb(sc);
+
+	/* PCI guarantees endianity of regpair */
+	sp_sb_data.state = SB_ENABLED;
+	sp_sb_data.host_sb_addr.lo = U64_LO(section);
+	sp_sb_data.host_sb_addr.hi = U64_HI(section);
+	sp_sb_data.igu_sb_id = igu_sp_sb_index;
+	sp_sb_data.igu_seg_id = igu_seg_id;
+	sp_sb_data.p_func.pf_id = func;
+	sp_sb_data.p_func.vnic_id = SC_VN(sc);
+	sp_sb_data.p_func.vf_id = 0xff;
+
+	bcm_wr_sp_sb_data(sc, &sp_sb_data);
+
+	bcm_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
+}
+
+static void bcm_init_sp_ring(struct bcm_softc *sc)
+{
+	atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
+	sc->spq_prod_idx = 0;
+	sc->dsb_sp_prod =
+	    &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
+	sc->spq_prod_bd = sc->spq;
+	sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
+}
+
+static void bcm_init_eq_ring(struct bcm_softc *sc)
+{
+	union event_ring_elem *elem;
+	int i;
+
+	for (i = 1; i <= NUM_EQ_PAGES; i++) {
+		elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
+
+		elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
+							 BCM_PAGE_SIZE *
+							 (i % NUM_EQ_PAGES)));
+		elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
+							 BCM_PAGE_SIZE *
+							 (i % NUM_EQ_PAGES)));
+	}
+
+	sc->eq_cons = 0;
+	sc->eq_prod = NUM_EQ_DESC;
+	sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
+
+	atomic_store_rel_long(&sc->eq_spq_left,
+			      (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
+				   NUM_EQ_DESC) - 1));
+}
+
+static void bcm_init_internal_common(struct bcm_softc *sc)
+{
+	int i;
+
+	if (IS_MF_SI(sc)) {
+/*
+ * In switch independent mode, the TSTORM needs to accept
+ * packets that failed classification, since approximate match
+ * mac addresses aren't written to NIG LLH.
+ */
+		REG_WR8(sc,
+			(BAR_TSTRORM_INTMEM +
+			 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
+	} else
+		REG_WR8(sc,
+			(BAR_TSTRORM_INTMEM +
+			 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
+
+	/*
+	 * Zero this manually as its initialization is currently missing
+	 * in the initTool.
+	 */
+	for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
+		REG_WR(sc,
+		       (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
+		       0);
+	}
+
+	if (!CHIP_IS_E1x(sc)) {
+		REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
+			CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
+			HC_IGU_NBC_MODE);
+	}
+}
+
+static void bcm_init_internal(struct bcm_softc *sc, uint32_t load_code)
+{
+	switch (load_code) {
+	case FW_MSG_CODE_DRV_LOAD_COMMON:
+	case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
+		bcm_init_internal_common(sc);
+		/* no break */
+
+	case FW_MSG_CODE_DRV_LOAD_PORT:
+		/* nothing to do */
+		/* no break */
+
+	case FW_MSG_CODE_DRV_LOAD_FUNCTION:
+		/* internal memory per function is initialized inside bcm_pf_init */
+		break;
+
+	default:
+		PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
+			    load_code);
+		break;
+	}
+}
+
+static void
+storm_memset_func_cfg(struct bcm_softc *sc,
+		      struct tstorm_eth_function_common_config *tcfg,
+		      uint16_t abs_fid)
+{
+	uint32_t addr;
+	size_t size;
+
+	addr = (BAR_TSTRORM_INTMEM +
+		TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
+	size = sizeof(struct tstorm_eth_function_common_config);
+	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
+}
+
+static void bcm_func_init(struct bcm_softc *sc, struct bcm_func_init_params *p)
+{
+	struct tstorm_eth_function_common_config tcfg = { 0 };
+
+	if (CHIP_IS_E1x(sc)) {
+		storm_memset_func_cfg(sc, &tcfg, p->func_id);
+	}
+
+	/* Enable the function in the FW */
+	storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
+	storm_memset_func_en(sc, p->func_id, 1);
+
+	/* spq */
+	if (p->func_flgs & FUNC_FLG_SPQ) {
+		storm_memset_spq_addr(sc, p->spq_map, p->func_id);
+		REG_WR(sc,
+		       (XSEM_REG_FAST_MEMORY +
+			XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
+	}
+}
+
+/*
+ * Calculates the sum of vn_min_rates.
+ * It's needed for further normalizing of the min_rates.
+ * Returns:
+ *   sum of vn_min_rates.
+ *     or
+ *   0 - if all the min_rates are 0.
+ * In the later case fainess algorithm should be deactivated.
+ * If all min rates are not zero then those that are zeroes will be set to 1.
+ */
+static void bcm_calc_vn_min(struct bcm_softc *sc, struct cmng_init_input *input)
+{
+	uint32_t vn_cfg;
+	uint32_t vn_min_rate;
+	int all_zero = 1;
+	int vn;
+
+	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
+		vn_cfg = sc->devinfo.mf_info.mf_config[vn];
+		vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
+				FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
+
+		if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
+			/* skip hidden VNs */
+			vn_min_rate = 0;
+		} else if (!vn_min_rate) {
+			/* If min rate is zero - set it to 100 */
+			vn_min_rate = DEF_MIN_RATE;
+		} else {
+			all_zero = 0;
+		}
+
+		input->vnic_min_rate[vn] = vn_min_rate;
+	}
+
+	/* if ETS or all min rates are zeros - disable fairness */
+	if (all_zero) {
+		input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
+	} else {
+		input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
+	}
+}
+
+static uint16_t
+bcm_extract_max_cfg(__rte_unused struct bcm_softc *sc, uint32_t mf_cfg)
+{
+	uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
+			    FUNC_MF_CFG_MAX_BW_SHIFT);
+
+	if (!max_cfg) {
+		PMD_DRV_LOG(DEBUG,
+			    "Max BW configured to 0 - using 100 instead");
+		max_cfg = 100;
+	}
+
+	return max_cfg;
+}
+
+static void
+bcm_calc_vn_max(struct bcm_softc *sc, int vn, struct cmng_init_input *input)
+{
+	uint16_t vn_max_rate;
+	uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
+	uint32_t max_cfg;
+
+	if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
+		vn_max_rate = 0;
+	} else {
+		max_cfg = bcm_extract_max_cfg(sc, vn_cfg);
+
+		if (IS_MF_SI(sc)) {
+			/* max_cfg in percents of linkspeed */
+			vn_max_rate =
+			    ((sc->link_vars.line_speed * max_cfg) / 100);
+		} else {	/* SD modes */
+			/* max_cfg is absolute in 100Mb units */
+			vn_max_rate = (max_cfg * 100);
+		}
+	}
+
+	input->vnic_max_rate[vn] = vn_max_rate;
+}
+
+static void
+bcm_cmng_fns_init(struct bcm_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
+{
+	struct cmng_init_input input;
+	int vn;
+
+	memset(&input, 0, sizeof(struct cmng_init_input));
+
+	input.port_rate = sc->link_vars.line_speed;
+
+	if (cmng_type == CMNG_FNS_MINMAX) {
+/* read mf conf from shmem */
+		if (read_cfg) {
+			bcm_read_mf_cfg(sc);
+		}
+
+/* get VN min rate and enable fairness if not 0 */
+		bcm_calc_vn_min(sc, &input);
+
+/* get VN max rate */
+		if (sc->port.pmf) {
+			for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
+				bcm_calc_vn_max(sc, vn, &input);
+			}
+		}
+
+/* always enable rate shaping and fairness */
+		input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
+
+		ecore_init_cmng(&input, &sc->cmng);
+		return;
+	}
+}
+
+static int bcm_get_cmng_fns_mode(struct bcm_softc *sc)
+{
+	if (CHIP_REV_IS_SLOW(sc)) {
+		return CMNG_FNS_NONE;
+	}
+
+	if (IS_MF(sc)) {
+		return CMNG_FNS_MINMAX;
+	}
+
+	return CMNG_FNS_NONE;
+}
+
+static void
+storm_memset_cmng(struct bcm_softc *sc, struct cmng_init *cmng, uint8_t port)
+{
+	int vn;
+	int func;
+	uint32_t addr;
+	size_t size;
+
+	addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
+	size = sizeof(struct cmng_struct_per_port);
+	ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
+
+	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
+		func = func_by_vn(sc, vn);
+
+		addr = (BAR_XSTRORM_INTMEM +
+			XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
+		size = sizeof(struct rate_shaping_vars_per_vn);
+		ecore_storm_memset_struct(sc, addr, size,
+					  (uint32_t *) & cmng->
+					  vnic.vnic_max_rate[vn]);
+
+		addr = (BAR_XSTRORM_INTMEM +
+			XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
+		size = sizeof(struct fairness_vars_per_vn);
+		ecore_storm_memset_struct(sc, addr, size,
+					  (uint32_t *) & cmng->
+					  vnic.vnic_min_rate[vn]);
+	}
+}
+
+static void bcm_pf_init(struct bcm_softc *sc)
+{
+	struct bcm_func_init_params func_init;
+	struct event_ring_data eq_data;
+	uint16_t flags;
+
+	memset(&eq_data, 0, sizeof(struct event_ring_data));
+	memset(&func_init, 0, sizeof(struct bcm_func_init_params));
+
+	if (!CHIP_IS_E1x(sc)) {
+/* reset IGU PF statistics: MSIX + ATTN */
+/* PF */
+		REG_WR(sc,
+		       (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
+			(BCM_IGU_STAS_MSG_VF_CNT * 4) +
+			((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
+			 4)), 0);
+/* ATTN */
+		REG_WR(sc,
+		       (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
+			(BCM_IGU_STAS_MSG_VF_CNT * 4) +
+			(BCM_IGU_STAS_MSG_PF_CNT * 4) +
+			((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
+			 4)), 0);
+	}
+
+	/* function setup flags */
+	flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
+
+	func_init.func_flgs = flags;
+	func_init.pf_id = SC_FUNC(sc);
+	func_init.func_id = SC_FUNC(sc);
+	func_init.spq_map = sc->spq_dma.paddr;
+	func_init.spq_prod = sc->spq_prod_idx;
+
+	bcm_func_init(sc, &func_init);
+
+	memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
+
+	/*
+	 * Congestion management values depend on the link rate.
+	 * There is no active link so initial link rate is set to 10Gbps.
+	 * When the link comes up the congestion management values are
+	 * re-calculated according to the actual link rate.
+	 */
+	sc->link_vars.line_speed = SPEED_10000;
+	bcm_cmng_fns_init(sc, TRUE, bcm_get_cmng_fns_mode(sc));
+
+	/* Only the PMF sets the HW */
+	if (sc->port.pmf) {
+		storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
+	}
+
+	/* init Event Queue - PCI bus guarantees correct endainity */
+	eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
+	eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
+	eq_data.producer = sc->eq_prod;
+	eq_data.index_id = HC_SP_INDEX_EQ_CONS;
+	eq_data.sb_id = DEF_SB_ID;
+	storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
+}
+
+static void bcm_hc_int_enable(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
+	uint32_t val = REG_RD(sc, addr);
+	uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
+	    || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
+	uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
+	uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
+
+	if (msix) {
+		val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+			 HC_CONFIG_0_REG_INT_LINE_EN_0);
+		val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+		if (single_msix) {
+			val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
+		}
+	} else if (msi) {
+		val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
+		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+	} else {
+		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+			HC_CONFIG_0_REG_INT_LINE_EN_0 |
+			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+
+		REG_WR(sc, addr, val);
+
+		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
+	}
+
+	REG_WR(sc, addr, val);
+
+	/* ensure that HC_CONFIG is written before leading/trailing edge config */
+	mb();
+
+	/* init leading/trailing edge */
+	if (IS_MF(sc)) {
+		val = (0xee0f | (1 << (SC_VN(sc) + 4)));
+		if (sc->port.pmf) {
+			/* enable nig and gpio3 attention */
+			val |= 0x1100;
+		}
+	} else {
+		val = 0xffff;
+	}
+
+	REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
+	REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
+
+	/* make sure that interrupts are indeed enabled from here on */
+	mb();
+}
+
+static void bcm_igu_int_enable(struct bcm_softc *sc)
+{
+	uint32_t val;
+	uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
+	    || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
+	uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
+	uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
+
+	val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
+
+	if (msix) {
+		val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
+		val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
+		if (single_msix) {
+			val |= IGU_PF_CONF_SINGLE_ISR_EN;
+		}
+	} else if (msi) {
+		val &= ~IGU_PF_CONF_INT_LINE_EN;
+		val |= (IGU_PF_CONF_MSI_MSIX_EN |
+			IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
+	} else {
+		val &= ~IGU_PF_CONF_MSI_MSIX_EN;
+		val |= (IGU_PF_CONF_INT_LINE_EN |
+			IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
+	}
+
+	/* clean previous status - need to configure igu prior to ack */
+	if ((!msix) || single_msix) {
+		REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
+		bcm_ack_int(sc);
+	}
+
+	val |= IGU_PF_CONF_FUNC_EN;
+
+	PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
+		    val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
+
+	REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
+
+	mb();
+
+	/* init leading/trailing edge */
+	if (IS_MF(sc)) {
+		val = (0xee0f | (1 << (SC_VN(sc) + 4)));
+		if (sc->port.pmf) {
+			/* enable nig and gpio3 attention */
+			val |= 0x1100;
+		}
+	} else {
+		val = 0xffff;
+	}
+
+	REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
+	REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
+
+	/* make sure that interrupts are indeed enabled from here on */
+	mb();
+}
+
+static void bcm_int_enable(struct bcm_softc *sc)
+{
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		bcm_hc_int_enable(sc);
+	} else {
+		bcm_igu_int_enable(sc);
+	}
+}
+
+static void bcm_hc_int_disable(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
+	uint32_t val = REG_RD(sc, addr);
+
+	val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+		 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+		 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+	/* flush all outstanding writes */
+	mb();
+
+	REG_WR(sc, addr, val);
+	if (REG_RD(sc, addr) != val) {
+		PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
+	}
+}
+
+static void bcm_igu_int_disable(struct bcm_softc *sc)
+{
+	uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
+
+	val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
+		 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
+
+	PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
+
+	/* flush all outstanding writes */
+	mb();
+
+	REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
+	if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
+		PMD_DRV_LOG(ERR, "proper val not read from IGU!");
+	}
+}
+
+static void bcm_int_disable(struct bcm_softc *sc)
+{
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		bcm_hc_int_disable(sc);
+	} else {
+		bcm_igu_int_disable(sc);
+	}
+}
+
+static void bcm_nic_init(struct bcm_softc *sc, int load_code)
+{
+	int i;
+
+	PMD_INIT_FUNC_TRACE();
+
+	for (i = 0; i < sc->num_queues; i++) {
+		bcm_init_eth_fp(sc, i);
+	}
+
+	rmb();			/* ensure status block indices were read */
+
+	bcm_init_rx_rings(sc);
+	bcm_init_tx_rings(sc);
+
+	if (IS_VF(sc)) {
+		bcm_memset_stats(sc);
+		return;
+	}
+
+	/* initialize MOD_ABS interrupts */
+	elink_init_mod_abs_int(sc, &sc->link_vars,
+			       sc->devinfo.chip_id,
+			       sc->devinfo.shmem_base,
+			       sc->devinfo.shmem2_base, SC_PORT(sc));
+
+	bcm_init_def_sb(sc);
+	bcm_update_dsb_idx(sc);
+	bcm_init_sp_ring(sc);
+	bcm_init_eq_ring(sc);
+	bcm_init_internal(sc, load_code);
+	bcm_pf_init(sc);
+	bcm_stats_init(sc);
+
+	/* flush all before enabling interrupts */
+	mb();
+
+	bcm_int_enable(sc);
+
+	/* check for SPIO5 */
+	bcm_attn_int_deasserted0(sc,
+				 REG_RD(sc,
+					(MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
+					 SC_PORT(sc) * 4)) &
+				 AEU_INPUTS_ATTN_BITS_SPIO5);
+}
+
+static void bcm_init_objs(struct bcm_softc *sc)
+{
+	/* mcast rules must be added to tx if tx switching is enabled */
+	ecore_obj_type o_type;
+	if (sc->flags & BCM_TX_SWITCHING)
+		o_type = ECORE_OBJ_TYPE_RX_TX;
+	else
+		o_type = ECORE_OBJ_TYPE_RX;
+
+	/* RX_MODE controlling object */
+	ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
+
+	/* multicast configuration controlling object */
+	ecore_init_mcast_obj(sc,
+			     &sc->mcast_obj,
+			     sc->fp[0].cl_id,
+			     sc->fp[0].index,
+			     SC_FUNC(sc),
+			     SC_FUNC(sc),
+			     BCM_SP(sc, mcast_rdata), (phys_addr_t) ((void *)
+								     BCM_SP_MAPPING(sc, mcast_rdata)), ECORE_FILTER_MCAST_PENDING, &sc->sp_state, o_type);
+
+	/* Setup CAM credit pools */
+	ecore_init_mac_credit_pool(sc,
+				   &sc->macs_pool,
+				   SC_FUNC(sc),
+				   CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
+				   VNICS_PER_PATH(sc));
+
+	ecore_init_vlan_credit_pool(sc,
+				    &sc->vlans_pool,
+				    SC_ABS_FUNC(sc) >> 1,
+				    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
+				    VNICS_PER_PATH(sc));
+
+	/* RSS configuration object */
+	ecore_init_rss_config_obj(&sc->rss_conf_obj,
+				  sc->fp[0].cl_id,
+				  sc->fp[0].index,
+				  SC_FUNC(sc),
+				  SC_FUNC(sc),
+				  BCM_SP(sc, rss_rdata), (phys_addr_t) ((void *)
+									BCM_SP_MAPPING(sc, rss_rdata)), ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state, ECORE_OBJ_TYPE_RX);
+}
+
+/*
+ * Initialize the function. This must be called before sending CLIENT_SETUP
+ * for the first client.
+ */
+static int bcm_func_start(struct bcm_softc *sc)
+{
+	struct ecore_func_state_params func_params = { NULL };
+	struct ecore_func_start_params *start_params =
+	    &func_params.params.start;
+
+	/* Prepare parameters for function state transitions */
+	bcm_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
+
+	func_params.f_obj = &sc->func_obj;
+	func_params.cmd = ECORE_F_CMD_START;
+
+	/* Function parameters */
+	start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
+	start_params->sd_vlan_tag = OVLAN(sc);
+
+	if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
+		start_params->network_cos_mode = STATIC_COS;
+	} else {		/* CHIP_IS_E1X */
+		start_params->network_cos_mode = FW_WRR;
+	}
+
+	start_params->gre_tunnel_mode = 0;
+	start_params->gre_tunnel_rss = 0;
+
+	return ecore_func_state_change(sc, &func_params);
+}
+
+static int bcm_set_power_state(struct bcm_softc *sc, uint8_t state)
+{
+	uint16_t pmcsr;
+
+	/* If there is no power capability, silently succeed */
+	if (!(sc->devinfo.pcie_cap_flags & BCM_PM_CAPABLE_FLAG)) {
+		PMD_DRV_LOG(WARN, "No power capability");
+		return 0;
+	}
+
+	pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
+		 2);
+
+	switch (state) {
+	case PCI_PM_D0:
+		pci_write_word(sc,
+			       (sc->devinfo.pcie_pm_cap_reg +
+				PCIR_POWER_STATUS),
+			       ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
+
+		if (pmcsr & PCIM_PSTAT_DMASK) {
+			/* delay required during transition out of D3hot */
+			DELAY(20000);
+		}
+
+		break;
+
+	case PCI_PM_D3hot:
+		/* don't shut down the power for emulation and FPGA */
+		if (CHIP_REV_IS_SLOW(sc)) {
+			return 0;
+		}
+
+		pmcsr &= ~PCIM_PSTAT_DMASK;
+		pmcsr |= PCIM_PSTAT_D3;
+
+		if (sc->wol) {
+			pmcsr |= PCIM_PSTAT_PMEENABLE;
+		}
+
+		pci_write_long(sc,
+			       (sc->devinfo.pcie_pm_cap_reg +
+				PCIR_POWER_STATUS), pmcsr);
+
+		/*
+		 * No more memory access after this point until device is brought back
+		 * to D0 state.
+		 */
+		break;
+
+	default:
+		PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
+			    state);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* return true if succeeded to acquire the lock */
+static uint8_t bcm_trylock_hw_lock(struct bcm_softc *sc, uint32_t resource)
+{
+	uint32_t lock_status;
+	uint32_t resource_bit = (1 << resource);
+	int func = SC_FUNC(sc);
+	uint32_t hw_lock_control_reg;
+
+	/* Validating that the resource is within range */
+	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
+		PMD_DRV_LOG(INFO,
+			    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
+			    resource, HW_LOCK_MAX_RESOURCE_VALUE);
+		return FALSE;
+	}
+
+	if (func <= 5) {
+		hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
+	} else {
+		hw_lock_control_reg =
+		    (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
+	}
+
+	/* try to acquire the lock */
+	REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
+	lock_status = REG_RD(sc, hw_lock_control_reg);
+	if (lock_status & resource_bit) {
+		return TRUE;
+	}
+
+	PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
+
+	return FALSE;
+}
+
+/*
+ * Get the recovery leader resource id according to the engine this function
+ * belongs to. Currently only only 2 engines is supported.
+ */
+static int bcm_get_leader_lock_resource(struct bcm_softc *sc)
+{
+	if (SC_PATH(sc)) {
+		return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
+	} else {
+		return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
+	}
+}
+
+/* try to acquire a leader lock for current engine */
+static uint8_t bcm_trylock_leader_lock(struct bcm_softc *sc)
+{
+	return bcm_trylock_hw_lock(sc, bcm_get_leader_lock_resource(sc));
+}
+
+static int bcm_release_leader_lock(struct bcm_softc *sc)
+{
+	return bcm_release_hw_lock(sc, bcm_get_leader_lock_resource(sc));
+}
+
+/* close gates #2, #3 and #4 */
+static void bcm_set_234_gates(struct bcm_softc *sc, uint8_t close)
+{
+	uint32_t val;
+
+	/* gates #2 and #4a are closed/opened */
+	/* #4 */
+	REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
+	/* #2 */
+	REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
+
+	/* #3 */
+	if (CHIP_IS_E1x(sc)) {
+/* prevent interrupts from HC on both ports */
+		val = REG_RD(sc, HC_REG_CONFIG_1);
+		if (close)
+			REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
+						     HC_CONFIG_1_REG_BLOCK_DISABLE_1));
+		else
+			REG_WR(sc, HC_REG_CONFIG_1,
+			       (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
+
+		val = REG_RD(sc, HC_REG_CONFIG_0);
+		if (close)
+			REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
+						     HC_CONFIG_0_REG_BLOCK_DISABLE_0));
+		else
+			REG_WR(sc, HC_REG_CONFIG_0,
+			       (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
+
+	} else {
+/* Prevent incomming interrupts in IGU */
+		val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
+
+		if (close)
+			REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
+			       (val & ~(uint32_t)
+				IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
+		else
+			REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
+			       (val |
+				IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
+	}
+
+	wmb();
+}
+
+/* poll for pending writes bit, it should get cleared in no more than 1s */
+static int bcm_er_poll_igu_vq(struct bcm_softc *sc)
+{
+	uint32_t cnt = 1000;
+	uint32_t pend_bits = 0;
+
+	do {
+		pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
+
+		if (pend_bits == 0) {
+			break;
+		}
+
+		DELAY(1000);
+	} while (cnt-- > 0);
+
+	if (cnt <= 0) {
+		PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
+			    pend_bits);
+		return -1;
+	}
+
+	return 0;
+}
+
+#define SHARED_MF_CLP_MAGIC  0x80000000	/* 'magic' bit */
+
+static void bcm_clp_reset_prep(struct bcm_softc *sc, uint32_t * magic_val)
+{
+	/* Do some magic... */
+	uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
+	*magic_val = val & SHARED_MF_CLP_MAGIC;
+	MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
+}
+
+/* restore the value of the 'magic' bit */
+static void bcm_clp_reset_done(struct bcm_softc *sc, uint32_t magic_val)
+{
+	/* Restore the 'magic' bit value... */
+	uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
+	MFCFG_WR(sc, shared_mf_config.clp_mb,
+		 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
+}
+
+/* prepare for MCP reset, takes care of CLP configurations */
+static void bcm_reset_mcp_prep(struct bcm_softc *sc, uint32_t * magic_val)
+{
+	uint32_t shmem;
+	uint32_t validity_offset;
+
+	/* set `magic' bit in order to save MF config */
+	bcm_clp_reset_prep(sc, magic_val);
+
+	/* get shmem offset */
+	shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
+	validity_offset =
+	    offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
+
+	/* Clear validity map flags */
+	if (shmem > 0) {
+		REG_WR(sc, shmem + validity_offset, 0);
+	}
+}
+
+#define MCP_TIMEOUT      5000	/* 5 seconds (in ms) */
+#define MCP_ONE_TIMEOUT  100	/* 100 ms */
+
+static void bcm_mcp_wait_one(struct bcm_softc *sc)
+{
+	/* special handling for emulation and FPGA (10 times longer) */
+	if (CHIP_REV_IS_SLOW(sc)) {
+		DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
+	} else {
+		DELAY((MCP_ONE_TIMEOUT) * 1000);
+	}
+}
+
+/* initialize shmem_base and waits for validity signature to appear */
+static int bcm_init_shmem(struct bcm_softc *sc)
+{
+	int cnt = 0;
+	uint32_t val = 0;
+
+	do {
+		sc->devinfo.shmem_base =
+		    sc->link_params.shmem_base =
+		    REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
+
+		if (sc->devinfo.shmem_base) {
+			val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
+			if (val & SHR_MEM_VALIDITY_MB)
+				return 0;
+		}
+
+		bcm_mcp_wait_one(sc);
+
+	} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
+
+	PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
+
+	return -1;
+}
+
+static int bcm_reset_mcp_comp(struct bcm_softc *sc, uint32_t magic_val)
+{
+	int rc = bcm_init_shmem(sc);
+
+	/* Restore the `magic' bit value */
+	bcm_clp_reset_done(sc, magic_val);
+
+	return rc;
+}
+
+static void bcm_pxp_prep(struct bcm_softc *sc)
+{
+	REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
+	REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
+	wmb();
+}
+
+/*
+ * Reset the whole chip except for:
+ *      - PCIE core
+ *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
+ *      - IGU
+ *      - MISC (including AEU)
+ *      - GRC
+ *      - RBCN, RBCP
+ */
+static void bcm_process_kill_chip_reset(struct bcm_softc *sc, uint8_t global)
+{
+	uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
+	uint32_t global_bits2, stay_reset2;
+
+	/*
+	 * Bits that have to be set in reset_mask2 if we want to reset 'global'
+	 * (per chip) blocks.
+	 */
+	global_bits2 =
+	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
+	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
+
+	/*
+	 * Don't reset the following blocks.
+	 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
+	 *            reset, as in 4 port device they might still be owned
+	 *            by the MCP (there is only one leader per path).
+	 */
+	not_reset_mask1 =
+	    MISC_REGISTERS_RESET_REG_1_RST_HC |
+	    MISC_REGISTERS_RESET_REG_1_RST_PXPV |
+	    MISC_REGISTERS_RESET_REG_1_RST_PXP;
+
+	not_reset_mask2 =
+	    MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
+	    MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
+	    MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
+	    MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
+	    MISC_REGISTERS_RESET_REG_2_RST_RBCN |
+	    MISC_REGISTERS_RESET_REG_2_RST_GRC |
+	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
+	    MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
+	    MISC_REGISTERS_RESET_REG_2_RST_ATC |
+	    MISC_REGISTERS_RESET_REG_2_PGLC |
+	    MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
+	    MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
+	    MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
+	    MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
+	    MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
+
+	/*
+	 * Keep the following blocks in reset:
+	 *  - all xxMACs are handled by the elink code.
+	 */
+	stay_reset2 =
+	    MISC_REGISTERS_RESET_REG_2_XMAC |
+	    MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
+
+	/* Full reset masks according to the chip */
+	reset_mask1 = 0xffffffff;
+
+	if (CHIP_IS_E1H(sc))
+		reset_mask2 = 0x1ffff;
+	else if (CHIP_IS_E2(sc))
+		reset_mask2 = 0xfffff;
+	else			/* CHIP_IS_E3 */
+		reset_mask2 = 0x3ffffff;
+
+	/* Don't reset global blocks unless we need to */
+	if (!global)
+		reset_mask2 &= ~global_bits2;
+
+	/*
+	 * In case of attention in the QM, we need to reset PXP
+	 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
+	 * because otherwise QM reset would release 'close the gates' shortly
+	 * before resetting the PXP, then the PSWRQ would send a write
+	 * request to PGLUE. Then when PXP is reset, PGLUE would try to
+	 * read the payload data from PSWWR, but PSWWR would not
+	 * respond. The write queue in PGLUE would stuck, dmae commands
+	 * would not return. Therefore it's important to reset the second
+	 * reset register (containing the
+	 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
+	 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
+	 * bit).
+	 */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
+	       reset_mask2 & (~not_reset_mask2));
+
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
+	       reset_mask1 & (~not_reset_mask1));
+
+	mb();
+	wmb();
+
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
+	       reset_mask2 & (~stay_reset2));
+
+	mb();
+	wmb();
+
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
+	wmb();
+}
+
+static int bcm_process_kill(struct bcm_softc *sc, uint8_t global)
+{
+	int cnt = 1000;
+	uint32_t val = 0;
+	uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
+	uint32_t tags_63_32 = 0;
+
+	/* Empty the Tetris buffer, wait for 1s */
+	do {
+		sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
+		blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
+		port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
+		port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
+		pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
+		if (CHIP_IS_E3(sc)) {
+			tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
+		}
+
+		if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
+		    ((port_is_idle_0 & 0x1) == 0x1) &&
+		    ((port_is_idle_1 & 0x1) == 0x1) &&
+		    (pgl_exp_rom2 == 0xffffffff) &&
+		    (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
+			break;
+		DELAY(1000);
+	} while (cnt-- > 0);
+
+	if (cnt <= 0) {
+		PMD_DRV_LOG(NOTICE,
+			    "ERROR: Tetris buffer didn't get empty or there "
+			    "are still outstanding read requests after 1s! "
+			    "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
+			    "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
+			    sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
+			    pgl_exp_rom2);
+		return -1;
+	}
+
+	mb();
+
+	/* Close gates #2, #3 and #4 */
+	bcm_set_234_gates(sc, TRUE);
+
+	/* Poll for IGU VQs for 57712 and newer chips */
+	if (!CHIP_IS_E1x(sc) && bcm_er_poll_igu_vq(sc)) {
+		return -1;
+	}
+
+	/* clear "unprepared" bit */
+	REG_WR(sc, MISC_REG_UNPREPARED, 0);
+	mb();
+
+	/* Make sure all is written to the chip before the reset */
+	wmb();
+
+	/*
+	 * Wait for 1ms to empty GLUE and PCI-E core queues,
+	 * PSWHST, GRC and PSWRD Tetris buffer.
+	 */
+	DELAY(1000);
+
+	/* Prepare to chip reset: */
+	/* MCP */
+	if (global) {
+		bcm_reset_mcp_prep(sc, &val);
+	}
+
+	/* PXP */
+	bcm_pxp_prep(sc);
+	mb();
+
+	/* reset the chip */
+	bcm_process_kill_chip_reset(sc, global);
+	mb();
+
+	/* Recover after reset: */
+	/* MCP */
+	if (global &&bcm_reset_mcp_comp(sc, val)) {
+		return -1;
+	}
+
+	/* Open the gates #2, #3 and #4 */
+	bcm_set_234_gates(sc, FALSE);
+
+	return 0;
+}
+
+static int bcm_leader_reset(struct bcm_softc *sc)
+{
+	int rc = 0;
+	uint8_t global = bcm_reset_is_global(sc);
+	uint32_t load_code;
+
+	/*
+	 * If not going to reset MCP, load "fake" driver to reset HW while
+	 * driver is owner of the HW.
+	 */
+	if (!global &&!BCM_NOMCP(sc)) {
+		load_code = bcm_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
+					   DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
+		if (!load_code) {
+			PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+			rc = -1;
+			goto exit_leader_reset;
+		}
+
+		if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
+		    (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
+			PMD_DRV_LOG(NOTICE,
+				    "MCP unexpected response, aborting");
+			rc = -1;
+			goto exit_leader_reset2;
+		}
+
+		load_code = bcm_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
+		if (!load_code) {
+			PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+			rc = -1;
+			goto exit_leader_reset2;
+		}
+	}
+
+	/* try to recover after the failure */
+	if (bcm_process_kill(sc, global)) {
+		PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
+			    SC_PATH(sc));
+		rc = -1;
+		goto exit_leader_reset2;
+	}
+
+	/*
+	 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
+	 * state.
+	 */
+	bcm_set_reset_done(sc);
+	if (global) {
+		bcm_clear_reset_global(sc);
+	}
+
+exit_leader_reset2:
+
+	/* unload "fake driver" if it was loaded */
+	if (!global &&!BCM_NOMCP(sc)) {
+		bcm_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
+		bcm_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
+	}
+
+exit_leader_reset:
+
+	sc->is_leader = 0;
+	bcm_release_leader_lock(sc);
+
+	mb();
+	return rc;
+}
+
+/*
+ * prepare INIT transition, parameters configured:
+ *   - HC configuration
+ *   - Queue's CDU context
+ */
+static void
+bcm_pf_q_prep_init(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		   struct ecore_queue_init_params *init_params)
+{
+	uint8_t cos;
+	int cxt_index, cxt_offset;
+
+	bcm_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
+	bcm_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
+
+	bcm_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
+	bcm_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
+
+	/* HC rate */
+	init_params->rx.hc_rate =
+	    sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
+	init_params->tx.hc_rate =
+	    sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
+
+	/* FW SB ID */
+	init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
+
+	/* CQ index among the SB indices */
+	init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
+	init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
+
+	/* set maximum number of COSs supported by this queue */
+	init_params->max_cos = sc->max_cos;
+
+	/* set the context pointers queue object */
+	for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
+		cxt_index = fp->index / ILT_PAGE_CIDS;
+		cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
+		init_params->cxts[cos] =
+		    &sc->context[cxt_index].vcxt[cxt_offset].eth;
+	}
+}
+
+/* set flags that are common for the Tx-only and not normal connections */
+static unsigned long
+bcm_get_common_flags(struct bcm_softc *sc, uint8_t zero_stats)
+{
+	unsigned long flags = 0;
+
+	/* PF driver will always initialize the Queue to an ACTIVE state */
+	bcm_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
+
+	/*
+	 * tx only connections collect statistics (on the same index as the
+	 * parent connection). The statistics are zeroed when the parent
+	 * connection is initialized.
+	 */
+
+	bcm_set_bit(ECORE_Q_FLG_STATS, &flags);
+	if (zero_stats) {
+		bcm_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
+	}
+
+	/*
+	 * tx only connections can support tx-switching, though their
+	 * CoS-ness doesn't survive the loopback
+	 */
+	if (sc->flags & BCM_TX_SWITCHING) {
+		bcm_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
+	}
+
+	bcm_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
+
+	return flags;
+}
+
+static unsigned long bcm_get_q_flags(struct bcm_softc *sc, uint8_t leading)
+{
+	unsigned long flags = 0;
+
+	if (IS_MF_SD(sc)) {
+		bcm_set_bit(ECORE_Q_FLG_OV, &flags);
+	}
+
+	if (leading) {
+		bcm_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
+		bcm_set_bit(ECORE_Q_FLG_MCAST, &flags);
+	}
+
+	bcm_set_bit(ECORE_Q_FLG_VLAN, &flags);
+
+	/* merge with common flags */
+	return flags | bcm_get_common_flags(sc, TRUE);
+}
+
+static void
+bcm_pf_q_prep_general(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		      struct ecore_general_setup_params *gen_init, uint8_t cos)
+{
+	gen_init->stat_id = bcm_stats_id(fp);
+	gen_init->spcl_id = fp->cl_id;
+	gen_init->mtu = sc->mtu;
+	gen_init->cos = cos;
+}
+
+static void
+bcm_pf_rx_q_prep(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		 struct rxq_pause_params *pause,
+		 struct ecore_rxq_setup_params *rxq_init)
+{
+	struct bcm_rx_queue *rxq;
+
+	rxq = sc->rx_queues[fp->index];
+	if (!rxq) {
+		PMD_RX_LOG(ERR, "RX queue is NULL");
+		return;
+	}
+	/* pause */
+	pause->bd_th_lo = BD_TH_LO(sc);
+	pause->bd_th_hi = BD_TH_HI(sc);
+
+	pause->rcq_th_lo = RCQ_TH_LO(sc);
+	pause->rcq_th_hi = RCQ_TH_HI(sc);
+
+	/* validate rings have enough entries to cross high thresholds */
+	if (sc->dropless_fc &&
+	    pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
+		PMD_DRV_LOG(WARN, "rx bd ring threshold limit");
+	}
+
+	if (sc->dropless_fc &&
+	    pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
+		PMD_DRV_LOG(WARN, "rcq ring threshold limit");
+	}
+
+	pause->pri_map = 1;
+
+	/* rxq setup */
+	rxq_init->dscr_map = (phys_addr_t) ((void *)rxq->rx_ring_phys_addr);
+	rxq_init->rcq_map = (phys_addr_t) ((void *)rxq->cq_ring_phys_addr);
+	rxq_init->rcq_np_map = (phys_addr_t) ((void *)(rxq->cq_ring_phys_addr +
+						       BCM_PAGE_SIZE));
+
+	/*
+	 * This should be a maximum number of data bytes that may be
+	 * placed on the BD (not including paddings).
+	 */
+	rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
+
+	rxq_init->cl_qzone_id = fp->cl_qzone_id;
+	rxq_init->rss_engine_id = SC_FUNC(sc);
+	rxq_init->mcast_engine_id = SC_FUNC(sc);
+
+	rxq_init->cache_line_log = BCM_RX_ALIGN_SHIFT;
+	rxq_init->fw_sb_id = fp->fw_sb_id;
+
+	rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
+
+	/*
+	 * configure silent vlan removal
+	 * if multi function mode is afex, then mask default vlan
+	 */
+	if (IS_MF_AFEX(sc)) {
+		rxq_init->silent_removal_value =
+		    sc->devinfo.mf_info.afex_def_vlan_tag;
+		rxq_init->silent_removal_mask = EVL_VLID_MASK;
+	}
+}
+
+static void
+bcm_pf_tx_q_prep(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		 struct ecore_txq_setup_params *txq_init, uint8_t cos)
+{
+	struct bcm_tx_queue *txq = fp->sc->tx_queues[fp->index];
+
+	if (!txq) {
+		PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
+		return;
+	}
+	txq_init->dscr_map = (phys_addr_t) ((void *)txq->tx_ring_phys_addr);
+	txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
+	txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
+	txq_init->fw_sb_id = fp->fw_sb_id;
+
+	/*
+	 * set the TSS leading client id for TX classfication to the
+	 * leading RSS client id
+	 */
+	txq_init->tss_leading_cl_id = BCM_FP(sc, 0, cl_id);
+}
+
+/*
+ * This function performs 2 steps in a queue state machine:
+ *   1) RESET->INIT
+ *   2) INIT->SETUP
+ */
+static int
+bcm_setup_queue(struct bcm_softc *sc, struct bcm_fastpath *fp, uint8_t leading)
+{
+	struct ecore_queue_state_params q_params = { NULL };
+	struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
+	int rc;
+
+	PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
+
+	bcm_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+	q_params.q_obj = &BCM_SP_OBJ(sc, fp).q_obj;
+
+	/* we want to wait for completion in this context */
+	bcm_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
+
+	/* prepare the INIT parameters */
+	bcm_pf_q_prep_init(sc, fp, &q_params.params.init);
+
+	/* Set the command */
+	q_params.cmd = ECORE_Q_CMD_INIT;
+
+	/* Change the state to INIT */
+	rc = ecore_queue_state_change(sc, &q_params);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
+		return rc;
+	}
+
+	PMD_DRV_LOG(DEBUG, "init complete");
+
+	/* now move the Queue to the SETUP state */
+	memset(setup_params, 0, sizeof(*setup_params));
+
+	/* set Queue flags */
+	setup_params->flags = bcm_get_q_flags(sc, leading);
+
+	/* set general SETUP parameters */
+	bcm_pf_q_prep_general(sc, fp, &setup_params->gen_params,
+			      FIRST_TX_COS_INDEX);
+
+	bcm_pf_rx_q_prep(sc, fp,
+			 &setup_params->pause_params,
+			 &setup_params->rxq_params);
+
+	bcm_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
+
+	/* Set the command */
+	q_params.cmd = ECORE_Q_CMD_SETUP;
+
+	/* change the state to SETUP */
+	rc = ecore_queue_state_change(sc, &q_params);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
+		return rc;
+	}
+
+	return rc;
+}
+
+static int bcm_setup_leading(struct bcm_softc *sc)
+{
+	if (IS_PF(sc))
+		return bcm_setup_queue(sc, &sc->fp[0], TRUE);
+	else			/* VF */
+		return bcm_vf_setup_queue(sc, &sc->fp[0], TRUE);
+}
+
+static int
+bcm_config_rss_pf(struct bcm_softc *sc, struct ecore_rss_config_obj *rss_obj,
+		  uint8_t config_hash)
+{
+	struct ecore_config_rss_params params = { NULL };
+	uint32_t i;
+
+	/*
+	 * Although RSS is meaningless when there is a single HW queue we
+	 * still need it enabled in order to have HW Rx hash generated.
+	 */
+
+	params.rss_obj = rss_obj;
+
+	bcm_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
+
+	bcm_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
+
+	/* RSS configuration */
+	bcm_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
+	bcm_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
+	bcm_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
+	bcm_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
+	if (rss_obj->udp_rss_v4) {
+		bcm_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
+	}
+	if (rss_obj->udp_rss_v6) {
+		bcm_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
+	}
+
+	/* Hash bits */
+	params.rss_result_mask = MULTI_MASK;
+
+	(void)rte_memcpy(params.ind_table, rss_obj->ind_table,
+			 sizeof(params.ind_table));
+
+	if (config_hash) {
+/* RSS keys */
+		for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
+			params.rss_key[i] = (uint32_t) rte_rand();
+		}
+
+		bcm_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
+	}
+
+	if (IS_PF(sc))
+		return ecore_config_rss(sc, &params);
+	else
+		return bcm_vf_config_rss(sc, &params);
+}
+
+static int bcm_config_rss_eth(struct bcm_softc *sc, uint8_t config_hash)
+{
+	return bcm_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
+}
+
+static int bcm_init_rss_pf(struct bcm_softc *sc)
+{
+	uint8_t num_eth_queues = BCM_NUM_ETH_QUEUES(sc);
+	uint32_t i;
+
+	/*
+	 * Prepare the initial contents of the indirection table if
+	 * RSS is enabled
+	 */
+	for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
+		sc->rss_conf_obj.ind_table[i] =
+		    (sc->fp->cl_id + (i % num_eth_queues));
+	}
+
+	if (sc->udp_rss) {
+		sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
+	}
+
+	/*
+	 * For 57711 SEARCHER configuration (rss_keys) is
+	 * per-port, so if explicit configuration is needed, do it only
+	 * for a PMF.
+	 *
+	 * For 57712 and newer it's a per-function configuration.
+	 */
+	return bcm_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
+}
+
+static int
+bcm_set_mac_one(struct bcm_softc *sc, uint8_t * mac,
+		struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
+		unsigned long *ramrod_flags)
+{
+	struct ecore_vlan_mac_ramrod_params ramrod_param;
+	int rc;
+
+	memset(&ramrod_param, 0, sizeof(ramrod_param));
+
+	/* fill in general parameters */
+	ramrod_param.vlan_mac_obj = obj;
+	ramrod_param.ramrod_flags = *ramrod_flags;
+
+	/* fill a user request section if needed */
+	if (!bcm_test_bit(RAMROD_CONT, ramrod_flags)) {
+		(void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
+				 ETH_ALEN);
+
+		bcm_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
+
+/* Set the command: ADD or DEL */
+		ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
+		    ECORE_VLAN_MAC_DEL;
+	}
+
+	rc = ecore_config_vlan_mac(sc, &ramrod_param);
+
+	if (rc == ECORE_EXISTS) {
+		PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
+/* do not treat adding same MAC as error */
+		rc = 0;
+	} else if (rc < 0) {
+		PMD_DRV_LOG(ERR,
+			    "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
+	}
+
+	return rc;
+}
+
+static int bcm_set_eth_mac(struct bcm_softc *sc, uint8_t set)
+{
+	unsigned long ramrod_flags = 0;
+
+	PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
+
+	bcm_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
+
+	/* Eth MAC is set on RSS leading client (fp[0]) */
+	return bcm_set_mac_one(sc, sc->link_params.mac_addr,
+			       &sc->sp_objs->mac_obj,
+			       set, ECORE_ETH_MAC, &ramrod_flags);
+}
+
+static int bcm_get_cur_phy_idx(struct bcm_softc *sc)
+{
+	uint32_t sel_phy_idx = 0;
+
+	if (sc->link_params.num_phys <= 1) {
+		return ELINK_INT_PHY;
+	}
+
+	if (sc->link_vars.link_up) {
+		sel_phy_idx = ELINK_EXT_PHY1;
+/* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
+		if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
+		    (sc->link_params.phy[ELINK_EXT_PHY2].supported &
+		     ELINK_SUPPORTED_FIBRE))
+			sel_phy_idx = ELINK_EXT_PHY2;
+	} else {
+		switch (elink_phy_selection(&sc->link_params)) {
+		case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
+		case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
+		case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
+			sel_phy_idx = ELINK_EXT_PHY1;
+			break;
+		case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
+		case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
+			sel_phy_idx = ELINK_EXT_PHY2;
+			break;
+		}
+	}
+
+	return sel_phy_idx;
+}
+
+static int bcm_get_link_cfg_idx(struct bcm_softc *sc)
+{
+	uint32_t sel_phy_idx = bcm_get_cur_phy_idx(sc);
+
+	/*
+	 * The selected activated PHY is always after swapping (in case PHY
+	 * swapping is enabled). So when swapping is enabled, we need to reverse
+	 * the configuration
+	 */
+
+	if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
+		if (sel_phy_idx == ELINK_EXT_PHY1)
+			sel_phy_idx = ELINK_EXT_PHY2;
+		else if (sel_phy_idx == ELINK_EXT_PHY2)
+			sel_phy_idx = ELINK_EXT_PHY1;
+	}
+
+	return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
+}
+
+static void bcm_set_requested_fc(struct bcm_softc *sc)
+{
+	/*
+	 * Initialize link parameters structure variables
+	 * It is recommended to turn off RX FC for jumbo frames
+	 * for better performance
+	 */
+	if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
+		sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
+	} else {
+		sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
+	}
+}
+
+static void bcm_calc_fc_adv(struct bcm_softc *sc)
+{
+	uint8_t cfg_idx = bcm_get_link_cfg_idx(sc);
+	switch (sc->link_vars.ieee_fc &
+		MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
+	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
+	default:
+		sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
+						   ADVERTISED_Pause);
+		break;
+
+	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
+		sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
+						  ADVERTISED_Pause);
+		break;
+
+	case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
+		sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
+		break;
+	}
+}
+
+static uint16_t bcm_get_mf_speed(struct bcm_softc *sc)
+{
+	uint16_t line_speed = sc->link_vars.line_speed;
+	if (IS_MF(sc)) {
+		uint16_t maxCfg = bcm_extract_max_cfg(sc,
+						      sc->devinfo.
+						      mf_info.mf_config[SC_VN
+									(sc)]);
+
+/* calculate the current MAX line speed limit for the MF devices */
+		if (IS_MF_SI(sc)) {
+			line_speed = (line_speed * maxCfg) / 100;
+		} else {	/* SD mode */
+			uint16_t vn_max_rate = maxCfg * 100;
+
+			if (vn_max_rate < line_speed) {
+				line_speed = vn_max_rate;
+			}
+		}
+	}
+
+	return line_speed;
+}
+
+static void
+bcm_fill_report_data(struct bcm_softc *sc, struct bcm_link_report_data *data)
+{
+	uint16_t line_speed = bcm_get_mf_speed(sc);
+
+	memset(data, 0, sizeof(*data));
+
+	/* fill the report data with the effective line speed */
+	data->line_speed = line_speed;
+
+	/* Link is down */
+	if (!sc->link_vars.link_up || (sc->flags & BCM_MF_FUNC_DIS)) {
+		bcm_set_bit(BCM_LINK_REPORT_LINK_DOWN,
+			    &data->link_report_flags);
+	}
+
+	/* Full DUPLEX */
+	if (sc->link_vars.duplex == DUPLEX_FULL) {
+		bcm_set_bit(BCM_LINK_REPORT_FULL_DUPLEX,
+			    &data->link_report_flags);
+	}
+
+	/* Rx Flow Control is ON */
+	if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
+		bcm_set_bit(BCM_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
+	}
+
+	/* Tx Flow Control is ON */
+	if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
+		bcm_set_bit(BCM_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
+	}
+}
+
+/* report link status to OS, should be called under phy_lock */
+static void bcm_link_report(struct bcm_softc *sc)
+{
+	struct bcm_link_report_data cur_data;
+
+	/* reread mf_cfg */
+	if (IS_PF(sc)) {
+		bcm_read_mf_cfg(sc);
+	}
+
+	/* Read the current link report info */
+	bcm_fill_report_data(sc, &cur_data);
+
+	/* Don't report link down or exactly the same link status twice */
+	if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
+	    (bcm_test_bit(BCM_LINK_REPORT_LINK_DOWN,
+			  &sc->last_reported_link.link_report_flags) &&
+	     bcm_test_bit(BCM_LINK_REPORT_LINK_DOWN,
+			  &cur_data.link_report_flags))) {
+		return;
+	}
+
+	sc->link_cnt++;
+
+	/* report new link params and remember the state for the next time */
+	(void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
+
+	if (bcm_test_bit(BCM_LINK_REPORT_LINK_DOWN,
+			 &cur_data.link_report_flags)) {
+		PMD_DRV_LOG(INFO, "NIC Link is Down");
+	} else {
+		__rte_unused const char *duplex;
+		__rte_unused const char *flow;
+
+		if (bcm_test_and_clear_bit(BCM_LINK_REPORT_FULL_DUPLEX,
+					   &cur_data.link_report_flags)) {
+			duplex = "full";
+		} else {
+			duplex = "half";
+		}
+
+/*
+ * Handle the FC at the end so that only these flags would be
+ * possibly set. This way we may easily check if there is no FC
+ * enabled.
+ */
+		if (cur_data.link_report_flags) {
+			if (bcm_test_bit(BCM_LINK_REPORT_RX_FC_ON,
+					 &cur_data.link_report_flags) &&
+			    bcm_test_bit(BCM_LINK_REPORT_TX_FC_ON,
+					 &cur_data.link_report_flags)) {
+				flow = "ON - receive & transmit";
+			} else if (bcm_test_bit(BCM_LINK_REPORT_RX_FC_ON,
+						&cur_data.link_report_flags) &&
+				   !bcm_test_bit(BCM_LINK_REPORT_TX_FC_ON,
+						 &cur_data.link_report_flags)) {
+				flow = "ON - receive";
+			} else if (!bcm_test_bit(BCM_LINK_REPORT_RX_FC_ON,
+						 &cur_data.link_report_flags) &&
+				   bcm_test_bit(BCM_LINK_REPORT_TX_FC_ON,
+						&cur_data.link_report_flags)) {
+				flow = "ON - transmit";
+			} else {
+				flow = "none";	/* possible? */
+			}
+		} else {
+			flow = "none";
+		}
+
+		PMD_DRV_LOG(INFO,
+			    "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
+			    cur_data.line_speed, duplex, flow);
+	}
+}
+
+void bcm_link_status_update(struct bcm_softc *sc)
+{
+	if (sc->state != BCM_STATE_OPEN) {
+		return;
+	}
+
+	if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
+		elink_link_status_update(&sc->link_params, &sc->link_vars);
+	} else {
+		sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
+					  ELINK_SUPPORTED_10baseT_Full |
+					  ELINK_SUPPORTED_100baseT_Half |
+					  ELINK_SUPPORTED_100baseT_Full |
+					  ELINK_SUPPORTED_1000baseT_Full |
+					  ELINK_SUPPORTED_2500baseX_Full |
+					  ELINK_SUPPORTED_10000baseT_Full |
+					  ELINK_SUPPORTED_TP |
+					  ELINK_SUPPORTED_FIBRE |
+					  ELINK_SUPPORTED_Autoneg |
+					  ELINK_SUPPORTED_Pause |
+					  ELINK_SUPPORTED_Asym_Pause);
+		sc->port.advertising[0] = sc->port.supported[0];
+
+		sc->link_params.sc = sc;
+		sc->link_params.port = SC_PORT(sc);
+		sc->link_params.req_duplex[0] = DUPLEX_FULL;
+		sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
+		sc->link_params.req_line_speed[0] = SPEED_10000;
+		sc->link_params.speed_cap_mask[0] = 0x7f0000;
+		sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
+
+		if (CHIP_REV_IS_FPGA(sc)) {
+			sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
+			sc->link_vars.line_speed = ELINK_SPEED_1000;
+			sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
+						     LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
+		} else {
+			sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
+			sc->link_vars.line_speed = ELINK_SPEED_10000;
+			sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
+						     LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
+		}
+
+		sc->link_vars.link_up = 1;
+
+		sc->link_vars.duplex = DUPLEX_FULL;
+		sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
+
+		if (IS_PF(sc)) {
+			REG_WR(sc,
+			       NIG_REG_EGRESS_DRAIN0_MODE +
+			       sc->link_params.port * 4, 0);
+			bcm_stats_handle(sc, STATS_EVENT_LINK_UP);
+			bcm_link_report(sc);
+		}
+	}
+
+	if (IS_PF(sc)) {
+		if (sc->link_vars.link_up) {
+			bcm_stats_handle(sc, STATS_EVENT_LINK_UP);
+		} else {
+			bcm_stats_handle(sc, STATS_EVENT_STOP);
+		}
+		bcm_link_report(sc);
+	} else {
+		bcm_link_report(sc);
+		bcm_stats_handle(sc, STATS_EVENT_LINK_UP);
+	}
+}
+
+static void bcm_periodic_start(struct bcm_softc *sc)
+{
+	atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
+}
+
+static void bcm_periodic_stop(struct bcm_softc *sc)
+{
+	atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
+}
+
+static int bcm_initial_phy_init(struct bcm_softc *sc, int load_mode)
+{
+	int rc, cfg_idx = bcm_get_link_cfg_idx(sc);
+	uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
+	struct elink_params *lp = &sc->link_params;
+
+	bcm_set_requested_fc(sc);
+
+	if (CHIP_REV_IS_SLOW(sc)) {
+		uint32_t bond = CHIP_BOND_ID(sc);
+		uint32_t feat = 0;
+
+		if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
+			feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
+		} else if (bond & 0x4) {
+			if (CHIP_IS_E3(sc)) {
+				feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
+			} else {
+				feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
+			}
+		} else if (bond & 0x8) {
+			if (CHIP_IS_E3(sc)) {
+				feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
+			} else {
+				feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
+			}
+		}
+
+/* disable EMAC for E3 and above */
+		if (bond & 0x2) {
+			feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
+		}
+
+		sc->link_params.feature_config_flags |= feat;
+	}
+
+	if (load_mode == LOAD_DIAG) {
+		lp->loopback_mode = ELINK_LOOPBACK_XGXS;
+/* Prefer doing PHY loopback at 10G speed, if possible */
+		if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
+			if (lp->speed_cap_mask[cfg_idx] &
+			    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
+				lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
+			} else {
+				lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
+			}
+		}
+	}
+
+	if (load_mode == LOAD_LOOPBACK_EXT) {
+		lp->loopback_mode = ELINK_LOOPBACK_EXT;
+	}
+
+	rc = elink_phy_init(&sc->link_params, &sc->link_vars);
+
+	bcm_calc_fc_adv(sc);
+
+	if (sc->link_vars.link_up) {
+		bcm_stats_handle(sc, STATS_EVENT_LINK_UP);
+		bcm_link_report(sc);
+	}
+
+	if (!CHIP_REV_IS_SLOW(sc)) {
+		bcm_periodic_start(sc);
+	}
+
+	sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
+	return rc;
+}
+
+/* update flags in shmem */
+static void
+bcm_update_drv_flags(struct bcm_softc *sc, uint32_t flags, uint32_t set)
+{
+	uint32_t drv_flags;
+
+	if (SHMEM2_HAS(sc, drv_flags)) {
+		bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
+		drv_flags = SHMEM2_RD(sc, drv_flags);
+
+		if (set) {
+			drv_flags |= flags;
+		} else {
+			drv_flags &= ~flags;
+		}
+
+		SHMEM2_WR(sc, drv_flags, drv_flags);
+
+		bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
+	}
+}
+
+/* periodic timer callout routine, only runs when the interface is up */
+void bcm_periodic_callout(struct bcm_softc *sc)
+{
+	if ((sc->state != BCM_STATE_OPEN) ||
+	    (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
+		PMD_DRV_LOG(WARN, "periodic callout exit (state=0x%x)",
+			    sc->state);
+		return;
+	}
+	if (!CHIP_REV_IS_SLOW(sc)) {
+/*
+ * This barrier is needed to ensure the ordering between the writing
+ * to the sc->port.pmf in the bcm_nic_load() or bcm_pmf_update() and
+ * the reading here.
+ */
+		mb();
+		if (sc->port.pmf) {
+			elink_period_func(&sc->link_params, &sc->link_vars);
+		}
+	}
+#ifdef BCM_PULSE
+	if (IS_PF(sc) && !BCM_NOMCP(sc)) {
+		int mb_idx = SC_FW_MB_IDX(sc);
+		uint32_t drv_pulse;
+		uint32_t mcp_pulse;
+
+		++sc->fw_drv_pulse_wr_seq;
+		sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
+
+		drv_pulse = sc->fw_drv_pulse_wr_seq;
+		bcm_drv_pulse(sc);
+
+		mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
+			     MCP_PULSE_SEQ_MASK);
+
+/*
+ * The delta between driver pulse and mcp response should
+ * be 1 (before mcp response) or 0 (after mcp response).
+ */
+		if ((drv_pulse != mcp_pulse) &&
+		    (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
+			/* someone lost a heartbeat... */
+			PMD_DRV_LOG(ERR,
+				    "drv_pulse (0x%x) != mcp_pulse (0x%x)",
+				    drv_pulse, mcp_pulse);
+		}
+	}
+#endif
+}
+
+/* start the controller */
+static __attribute__ ((noinline))
+int bcm_nic_load(struct bcm_softc *sc)
+{
+	uint32_t val;
+	uint32_t load_code = 0;
+	int i, rc = 0;
+
+	PMD_INIT_FUNC_TRACE();
+
+	sc->state = BCM_STATE_OPENING_WAITING_LOAD;
+
+	if (IS_PF(sc)) {
+/* must be called before memory allocation and HW init */
+		bcm_ilt_set_info(sc);
+	}
+
+	bcm_set_fp_rx_buf_size(sc);
+
+	if (IS_PF(sc)) {
+		if (bcm_alloc_mem(sc) != 0) {
+			sc->state = BCM_STATE_CLOSED;
+			rc = -ENOMEM;
+			goto bcm_nic_load_error0;
+		}
+	}
+
+	if (bcm_alloc_fw_stats_mem(sc) != 0) {
+		sc->state = BCM_STATE_CLOSED;
+		rc = -ENOMEM;
+		goto bcm_nic_load_error0;
+	}
+
+	if (IS_VF(sc)) {
+		rc = bcm_vf_init(sc);
+		if (rc) {
+			sc->state = BCM_STATE_ERROR;
+			goto bcm_nic_load_error0;
+		}
+	}
+
+	if (IS_PF(sc)) {
+/* set pf load just before approaching the MCP */
+		bcm_set_pf_load(sc);
+
+/* if MCP exists send load request and analyze response */
+		if (!BCM_NOMCP(sc)) {
+			/* attempt to load pf */
+			if (bcm_nic_load_request(sc, &load_code) != 0) {
+				sc->state = BCM_STATE_CLOSED;
+				rc = -ENXIO;
+				goto bcm_nic_load_error1;
+			}
+
+			/* what did the MCP say? */
+			if (bcm_nic_load_analyze_req(sc, load_code) != 0) {
+				bcm_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
+				sc->state = BCM_STATE_CLOSED;
+				rc = -ENXIO;
+				goto bcm_nic_load_error2;
+			}
+		} else {
+			PMD_DRV_LOG(INFO, "Device has no MCP!");
+			load_code = bcm_nic_load_no_mcp(sc);
+		}
+
+/* mark PMF if applicable */
+		bcm_nic_load_pmf(sc, load_code);
+
+/* Init Function state controlling object */
+		bcm_init_func_obj(sc);
+
+/* Initialize HW */
+		if (bcm_init_hw(sc, load_code) != 0) {
+			PMD_DRV_LOG(NOTICE, "HW init failed");
+			bcm_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
+			sc->state = BCM_STATE_CLOSED;
+			rc = -ENXIO;
+			goto bcm_nic_load_error2;
+		}
+	}
+
+	bcm_nic_init(sc, load_code);
+
+	/* Init per-function objects */
+	if (IS_PF(sc)) {
+		bcm_init_objs(sc);
+
+/* set AFEX default VLAN tag to an invalid value */
+		sc->devinfo.mf_info.afex_def_vlan_tag = -1;
+
+		sc->state = BCM_STATE_OPENING_WAITING_PORT;
+		rc = bcm_func_start(sc);
+		if (rc) {
+			PMD_DRV_LOG(NOTICE, "Function start failed!");
+			bcm_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
+			sc->state = BCM_STATE_ERROR;
+			goto bcm_nic_load_error3;
+		}
+
+/* send LOAD_DONE command to MCP */
+		if (!BCM_NOMCP(sc)) {
+			load_code =
+			    bcm_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
+			if (!load_code) {
+				PMD_DRV_LOG(NOTICE,
+					    "MCP response failure, aborting");
+				sc->state = BCM_STATE_ERROR;
+				rc = -ENXIO;
+				goto bcm_nic_load_error3;
+			}
+		}
+	}
+
+	rc = bcm_setup_leading(sc);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "Setup leading failed!");
+		sc->state = BCM_STATE_ERROR;
+		goto bcm_nic_load_error3;
+	}
+
+	FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
+		if (IS_PF(sc))
+			rc = bcm_setup_queue(sc, &sc->fp[i], FALSE);
+		else		/* IS_VF(sc) */
+			rc = bcm_vf_setup_queue(sc, &sc->fp[i], FALSE);
+
+		if (rc) {
+			PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
+			sc->state = BCM_STATE_ERROR;
+			goto bcm_nic_load_error3;
+		}
+	}
+
+	rc = bcm_init_rss_pf(sc);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "PF RSS init failed");
+		sc->state = BCM_STATE_ERROR;
+		goto bcm_nic_load_error3;
+	}
+
+	/* now when Clients are configured we are ready to work */
+	sc->state = BCM_STATE_OPEN;
+
+	/* Configure a ucast MAC */
+	if (IS_PF(sc)) {
+		rc = bcm_set_eth_mac(sc, TRUE);
+	} else {		/* IS_VF(sc) */
+		rc = bcm_vf_set_mac(sc, TRUE);
+	}
+
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
+		sc->state = BCM_STATE_ERROR;
+		goto bcm_nic_load_error3;
+	}
+
+	if (sc->port.pmf) {
+		rc = bcm_initial_phy_init(sc, LOAD_OPEN);
+		if (rc) {
+			sc->state = BCM_STATE_ERROR;
+			goto bcm_nic_load_error3;
+		}
+	}
+
+	sc->link_params.feature_config_flags &=
+	    ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
+
+	/* start the Tx */
+	switch (LOAD_OPEN) {
+	case LOAD_NORMAL:
+	case LOAD_OPEN:
+		break;
+
+	case LOAD_DIAG:
+	case LOAD_LOOPBACK_EXT:
+		sc->state = BCM_STATE_DIAG;
+		break;
+
+	default:
+		break;
+	}
+
+	if (sc->port.pmf) {
+		bcm_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
+	} else {
+		bcm_link_status_update(sc);
+	}
+
+	if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
+/* mark driver is loaded in shmem2 */
+		val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
+		SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
+			  (val |
+			   DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
+			   DRV_FLAGS_CAPABILITIES_LOADED_L2));
+	}
+
+	/* start fast path */
+	/* Initialize Rx filter */
+	bcm_set_rx_mode(sc);
+
+	/* wait for all pending SP commands to complete */
+	if (IS_PF(sc) && !bcm_wait_sp_comp(sc, ~0x0UL)) {
+		PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
+		bcm_periodic_stop(sc);
+		bcm_nic_unload(sc, UNLOAD_CLOSE, FALSE);
+		return -ENXIO;
+	}
+
+	PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
+
+	return 0;
+
+bcm_nic_load_error3:
+
+	if (IS_PF(sc)) {
+		bcm_int_disable_sync(sc, 1);
+
+/* clean out queued objects */
+		bcm_squeeze_objects(sc);
+	}
+
+bcm_nic_load_error2:
+
+	if (IS_PF(sc) && !BCM_NOMCP(sc)) {
+		bcm_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
+		bcm_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
+	}
+
+	sc->port.pmf = 0;
+
+bcm_nic_load_error1:
+
+	/* clear pf_load status, as it was already set */
+	if (IS_PF(sc)) {
+		bcm_clear_pf_load(sc);
+	}
+
+bcm_nic_load_error0:
+
+	bcm_free_fw_stats_mem(sc);
+	bcm_free_mem(sc);
+
+	return rc;
+}
+
+/*
+* Handles controller initialization.
+*/
+int bcm_init(struct bcm_softc *sc)
+{
+	int other_engine = SC_PATH(sc) ? 0 : 1;
+	uint8_t other_load_status, load_status;
+	uint8_t global = FALSE;
+	int rc;
+
+	/* Check if the driver is still running and bail out if it is. */
+	if (sc->link_vars.link_up) {
+		PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
+		rc = 0;
+		goto bcm_init_done;
+	}
+
+	bcm_set_power_state(sc, PCI_PM_D0);
+
+	/*
+	 * If parity occurred during the unload, then attentions and/or
+	 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
+	 * loaded on the current engine to complete the recovery. Parity recovery
+	 * is only relevant for PF driver.
+	 */
+	if (IS_PF(sc)) {
+		other_load_status = bcm_get_load_status(sc, other_engine);
+		load_status = bcm_get_load_status(sc, SC_PATH(sc));
+
+		if (!bcm_reset_is_done(sc, SC_PATH(sc)) ||
+		    bcm_chk_parity_attn(sc, &global, TRUE)) {
+			do {
+				/*
+				 * If there are attentions and they are in global blocks, set
+				 * the GLOBAL_RESET bit regardless whether it will be this
+				 * function that will complete the recovery or not.
+				 */
+				if (global) {
+					bcm_set_reset_global(sc);
+				}
+
+				/*
+				 * Only the first function on the current engine should try
+				 * to recover in open. In case of attentions in global blocks
+				 * only the first in the chip should try to recover.
+				 */
+				if ((!load_status
+				     && (!global ||!other_load_status))
+				    && bcm_trylock_leader_lock(sc)
+				    && !bcm_leader_reset(sc)) {
+					PMD_DRV_LOG(INFO,
+						    "Recovered during init");
+					break;
+				}
+
+				/* recovery has failed... */
+				bcm_set_power_state(sc, PCI_PM_D3hot);
+
+				sc->recovery_state = BCM_RECOVERY_FAILED;
+
+				PMD_DRV_LOG(NOTICE,
+					    "Recovery flow hasn't properly "
+					    "completed yet, try again later. "
+					    "If you still see this message after a "
+					    "few retries then power cycle is required.");
+
+				rc = -ENXIO;
+				goto bcm_init_done;
+			} while (0);
+		}
+	}
+
+	sc->recovery_state = BCM_RECOVERY_DONE;
+
+	rc = bcm_nic_load(sc);
+
+bcm_init_done:
+
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "Initialization failed, "
+			    "stack notified driver is NOT running!");
+	}
+
+	return rc;
+}
+
+static void bcm_get_function_num(struct bcm_softc *sc)
+{
+	uint32_t val = 0;
+
+	/*
+	 * Read the ME register to get the function number. The ME register
+	 * holds the relative-function number and absolute-function number. The
+	 * absolute-function number appears only in E2 and above. Before that
+	 * these bits always contained zero, therefore we cannot blindly use them.
+	 */
+
+	val = REG_RD(sc, BAR_ME_REGISTER);
+
+	sc->pfunc_rel =
+	    (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
+	sc->path_id =
+	    (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
+	    1;
+
+	if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
+		sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
+	} else {
+		sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
+	}
+
+	PMD_DRV_LOG(DEBUG,
+		    "Relative function %d, Absolute function %d, Path %d",
+		    sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
+}
+
+static uint32_t bcm_get_shmem_mf_cfg_base(struct bcm_softc *sc)
+{
+	uint32_t shmem2_size;
+	uint32_t offset;
+	uint32_t mf_cfg_offset_value;
+
+	/* Non 57712 */
+	offset = (SHMEM_ADDR(sc, func_mb) +
+		  (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
+
+	/* 57712 plus */
+	if (sc->devinfo.shmem2_base != 0) {
+		shmem2_size = SHMEM2_RD(sc, size);
+		if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
+			mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
+			if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
+				offset = mf_cfg_offset_value;
+			}
+		}
+	}
+
+	return offset;
+}
+
+static uint32_t bcm_pcie_capability_read(struct bcm_softc *sc, int reg)
+{
+	uint32_t ret;
+	struct bcm_pci_cap *caps;
+
+	/* ensure PCIe capability is enabled */
+	caps = pci_find_cap(sc, PCIY_EXPRESS, BCM_PCI_CAP);
+	if (NULL != caps) {
+		PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
+			    "id=0x%04X type=0x%04X addr=0x%08X",
+			    caps->id, caps->type, caps->addr);
+		pci_read(sc, (caps->addr + reg), &ret, 2);
+		return ret;
+	}
+
+	PMD_DRV_LOG(WARN, "PCIe capability NOT FOUND!!!");
+
+	return 0;
+}
+
+static uint8_t bcm_is_pcie_pending(struct bcm_softc *sc)
+{
+	return (bcm_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
+		PCIM_EXP_STA_TRANSACTION_PND);
+}
+
+/*
+* Walk the PCI capabiites list for the device to find what features are
+* supported. These capabilites may be enabled/disabled by firmware so it's
+* best to walk the list rather than make assumptions.
+*/
+static void bcm_probe_pci_caps(struct bcm_softc *sc)
+{
+	PMD_INIT_FUNC_TRACE();
+
+	struct bcm_pci_cap *caps;
+	uint16_t link_status;
+#ifdef RTE_LIBRTE_BCM_DEBUG
+	int reg = 0;
+#endif
+
+	/* check if PCI Power Management is enabled */
+	caps = pci_find_cap(sc, PCIY_PMG, BCM_PCI_CAP);
+	if (NULL != caps) {
+		PMD_DRV_LOG(DEBUG, "Found PM capability: "
+			    "id=0x%04X type=0x%04X addr=0x%08X",
+			    caps->id, caps->type, caps->addr);
+
+		sc->devinfo.pcie_cap_flags |= BCM_PM_CAPABLE_FLAG;
+		sc->devinfo.pcie_pm_cap_reg = caps->addr;
+	}
+
+	link_status = bcm_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
+
+	sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
+	sc->devinfo.pcie_link_width =
+	    ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
+
+	PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
+		    sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
+
+	sc->devinfo.pcie_cap_flags |= BCM_PCIE_CAPABLE_FLAG;
+
+	/* check if MSI capability is enabled */
+	caps = pci_find_cap(sc, PCIY_MSI, BCM_PCI_CAP);
+	if (NULL != caps) {
+		PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
+
+		sc->devinfo.pcie_cap_flags |= BCM_MSI_CAPABLE_FLAG;
+		sc->devinfo.pcie_msi_cap_reg = caps->addr;
+	}
+
+	/* check if MSI-X capability is enabled */
+	caps = pci_find_cap(sc, PCIY_MSIX, BCM_PCI_CAP);
+	if (NULL != caps) {
+		PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
+
+		sc->devinfo.pcie_cap_flags |= BCM_MSIX_CAPABLE_FLAG;
+		sc->devinfo.pcie_msix_cap_reg = caps->addr;
+	}
+}
+
+static int bcm_get_shmem_mf_cfg_info_sd(struct bcm_softc *sc)
+{
+	struct bcm_mf_info *mf_info = &sc->devinfo.mf_info;
+	uint32_t val;
+
+	/* get the outer vlan if we're in switch-dependent mode */
+
+	val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
+	mf_info->ext_id = (uint16_t) val;
+
+	mf_info->multi_vnics_mode = 1;
+
+	if (!VALID_OVLAN(mf_info->ext_id)) {
+		PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
+		return 1;
+	}
+
+	/* get the capabilities */
+	if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
+	    FUNC_MF_CFG_PROTOCOL_ISCSI) {
+		mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
+	} else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
+		   == FUNC_MF_CFG_PROTOCOL_FCOE) {
+		mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
+	} else {
+		mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
+	}
+
+	mf_info->vnics_per_port =
+	    (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
+
+	return 0;
+}
+
+static uint32_t bcm_get_shmem_ext_proto_support_flags(struct bcm_softc *sc)
+{
+	uint32_t retval = 0;
+	uint32_t val;
+
+	val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
+
+	if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
+		if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
+			retval |= MF_PROTO_SUPPORT_ETHERNET;
+		}
+		if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
+			retval |= MF_PROTO_SUPPORT_ISCSI;
+		}
+		if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
+			retval |= MF_PROTO_SUPPORT_FCOE;
+		}
+	}
+
+	return retval;
+}
+
+static int bcm_get_shmem_mf_cfg_info_si(struct bcm_softc *sc)
+{
+	struct bcm_mf_info *mf_info = &sc->devinfo.mf_info;
+	uint32_t val;
+
+	/*
+	 * There is no outer vlan if we're in switch-independent mode.
+	 * If the mac is valid then assume multi-function.
+	 */
+
+	val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
+
+	mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
+
+	mf_info->mf_protos_supported =
+	    bcm_get_shmem_ext_proto_support_flags(sc);
+
+	mf_info->vnics_per_port =
+	    (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
+
+	return 0;
+}
+
+static int bcm_get_shmem_mf_cfg_info_niv(struct bcm_softc *sc)
+{
+	struct bcm_mf_info *mf_info = &sc->devinfo.mf_info;
+	uint32_t e1hov_tag;
+	uint32_t func_config;
+	uint32_t niv_config;
+
+	mf_info->multi_vnics_mode = 1;
+
+	e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
+	func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
+	niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
+
+	mf_info->ext_id =
+	    (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
+			FUNC_MF_CFG_E1HOV_TAG_SHIFT);
+
+	mf_info->default_vlan =
+	    (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
+			FUNC_MF_CFG_AFEX_VLAN_SHIFT);
+
+	mf_info->niv_allowed_priorities =
+	    (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
+		       FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
+
+	mf_info->niv_default_cos =
+	    (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
+		       FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
+
+	mf_info->afex_vlan_mode =
+	    ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
+	     FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
+
+	mf_info->niv_mba_enabled =
+	    ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
+	     FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
+
+	mf_info->mf_protos_supported =
+	    bcm_get_shmem_ext_proto_support_flags(sc);
+
+	mf_info->vnics_per_port =
+	    (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
+
+	return 0;
+}
+
+static int bcm_check_valid_mf_cfg(struct bcm_softc *sc)
+{
+	struct bcm_mf_info *mf_info = &sc->devinfo.mf_info;
+	uint32_t mf_cfg1;
+	uint32_t mf_cfg2;
+	uint32_t ovlan1;
+	uint32_t ovlan2;
+	uint8_t i, j;
+
+	/* various MF mode sanity checks... */
+
+	if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
+		PMD_DRV_LOG(NOTICE,
+			    "Enumerated function %d is marked as hidden",
+			    SC_PORT(sc));
+		return 1;
+	}
+
+	if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
+		PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
+			    mf_info->vnics_per_port, mf_info->multi_vnics_mode);
+		return 1;
+	}
+
+	if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
+/* vnic id > 0 must have valid ovlan in switch-dependent mode */
+		if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
+			PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
+				    SC_VN(sc), OVLAN(sc));
+			return 1;
+		}
+
+		if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
+			PMD_DRV_LOG(NOTICE,
+				    "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
+				    mf_info->multi_vnics_mode, OVLAN(sc));
+			return 1;
+		}
+
+/*
+ * Verify all functions are either MF or SF mode. If MF, make sure
+ * sure that all non-hidden functions have a valid ovlan. If SF,
+ * make sure that all non-hidden functions have an invalid ovlan.
+ */
+		FOREACH_ABS_FUNC_IN_PORT(sc, i) {
+			mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
+			ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
+			if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
+			    (((mf_info->multi_vnics_mode)
+			      && !VALID_OVLAN(ovlan1))
+			     || ((!mf_info->multi_vnics_mode)
+				 && VALID_OVLAN(ovlan1)))) {
+				PMD_DRV_LOG(NOTICE,
+					    "mf_mode=SD function %d MF config "
+					    "mismatch, multi_vnics_mode=%d ovlan=%d",
+					    i, mf_info->multi_vnics_mode,
+					    ovlan1);
+				return 1;
+			}
+		}
+
+/* Verify all funcs on the same port each have a different ovlan. */
+		FOREACH_ABS_FUNC_IN_PORT(sc, i) {
+			mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
+			ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
+			/* iterate from the next function on the port to the max func */
+			for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
+				mf_cfg2 =
+				    MFCFG_RD(sc, func_mf_config[j].config);
+				ovlan2 =
+				    MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
+				if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
+				    && VALID_OVLAN(ovlan1)
+				    && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
+				    && VALID_OVLAN(ovlan2)
+				    && (ovlan1 == ovlan2)) {
+					PMD_DRV_LOG(NOTICE,
+						    "mf_mode=SD functions %d and %d "
+						    "have the same ovlan (%d)",
+						    i, j, ovlan1);
+					return 1;
+				}
+			}
+		}
+	}
+	/* MULTI_FUNCTION_SD */
+	return 0;
+}
+
+static int bcm_get_mf_cfg_info(struct bcm_softc *sc)
+{
+	struct bcm_mf_info *mf_info = &sc->devinfo.mf_info;
+	uint32_t val, mac_upper;
+	uint8_t i, vnic;
+
+	/* initialize mf_info defaults */
+	mf_info->vnics_per_port = 1;
+	mf_info->multi_vnics_mode = FALSE;
+	mf_info->path_has_ovlan = FALSE;
+	mf_info->mf_mode = SINGLE_FUNCTION;
+
+	if (!CHIP_IS_MF_CAP(sc)) {
+		return 0;
+	}
+
+	if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
+		PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
+		return 1;
+	}
+
+	/* get the MF mode (switch dependent / independent / single-function) */
+
+	val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
+
+	switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
+	case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
+
+		mac_upper =
+		    MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
+
+		/* check for legal upper mac bytes */
+		if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
+			mf_info->mf_mode = MULTI_FUNCTION_SI;
+		} else {
+			PMD_DRV_LOG(NOTICE,
+				    "Invalid config for Switch Independent mode");
+		}
+
+		break;
+
+	case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
+	case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
+
+		/* get outer vlan configuration */
+		val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
+
+		if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
+		    FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
+			mf_info->mf_mode = MULTI_FUNCTION_SD;
+		} else {
+			PMD_DRV_LOG(NOTICE,
+				    "Invalid config for Switch Dependent mode");
+		}
+
+		break;
+
+	case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
+
+		/* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
+		return 0;
+
+	case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
+
+		/*
+		 * Mark MF mode as NIV if MCP version includes NPAR-SD support
+		 * and the MAC address is valid.
+		 */
+		mac_upper =
+		    MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
+
+		if ((SHMEM2_HAS(sc, afex_driver_support)) &&
+		    (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
+			mf_info->mf_mode = MULTI_FUNCTION_AFEX;
+		} else {
+			PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
+		}
+
+		break;
+
+	default:
+
+		PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
+			    (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
+
+		return 1;
+	}
+
+	/* set path mf_mode (which could be different than function mf_mode) */
+	if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
+		mf_info->path_has_ovlan = TRUE;
+	} else if (mf_info->mf_mode == SINGLE_FUNCTION) {
+/*
+ * Decide on path multi vnics mode. If we're not in MF mode and in
+ * 4-port mode, this is good enough to check vnic-0 of the other port
+ * on the same path
+ */
+		if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
+			uint8_t other_port = !(PORT_ID(sc) & 1);
+			uint8_t abs_func_other_port =
+			    (SC_PATH(sc) + (2 * other_port));
+
+			val =
+			    MFCFG_RD(sc,
+				     func_mf_config
+				     [abs_func_other_port].e1hov_tag);
+
+			mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
+		}
+	}
+
+	if (mf_info->mf_mode == SINGLE_FUNCTION) {
+/* invalid MF config */
+		if (SC_VN(sc) >= 1) {
+			PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
+			return 1;
+		}
+
+		return 0;
+	}
+
+	/* get the MF configuration */
+	mf_info->mf_config[SC_VN(sc)] =
+	    MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
+
+	switch (mf_info->mf_mode) {
+	case MULTI_FUNCTION_SD:
+
+		bcm_get_shmem_mf_cfg_info_sd(sc);
+		break;
+
+	case MULTI_FUNCTION_SI:
+
+		bcm_get_shmem_mf_cfg_info_si(sc);
+		break;
+
+	case MULTI_FUNCTION_AFEX:
+
+		bcm_get_shmem_mf_cfg_info_niv(sc);
+		break;
+
+	default:
+
+		PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
+			    mf_info->mf_mode);
+		return 1;
+	}
+
+	/* get the congestion management parameters */
+
+	vnic = 0;
+	FOREACH_ABS_FUNC_IN_PORT(sc, i) {
+/* get min/max bw */
+		val = MFCFG_RD(sc, func_mf_config[i].config);
+		mf_info->min_bw[vnic] =
+		    ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
+		     FUNC_MF_CFG_MIN_BW_SHIFT);
+		mf_info->max_bw[vnic] =
+		    ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
+		     FUNC_MF_CFG_MAX_BW_SHIFT);
+		vnic++;
+	}
+
+	return bcm_check_valid_mf_cfg(sc);
+}
+
+static int bcm_get_shmem_info(struct bcm_softc *sc)
+{
+	int port;
+	uint32_t mac_hi, mac_lo, val;
+
+	PMD_INIT_FUNC_TRACE();
+
+	port = SC_PORT(sc);
+	mac_hi = mac_lo = 0;
+
+	sc->link_params.sc = sc;
+	sc->link_params.port = port;
+
+	/* get the hardware config info */
+	sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
+	sc->devinfo.hw_config2 =
+	    SHMEM_RD(sc, dev_info.shared_hw_config.config2);
+
+	sc->link_params.hw_led_mode =
+	    ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
+	     SHARED_HW_CFG_LED_MODE_SHIFT);
+
+	/* get the port feature config */
+	sc->port.config =
+	    SHMEM_RD(sc, dev_info.port_feature_config[port].config);
+
+	/* get the link params */
+	sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
+	    & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
+	sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
+	    & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
+
+	/* get the lane config */
+	sc->link_params.lane_config =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
+
+	/* get the link config */
+	val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
+	sc->port.link_config[ELINK_INT_PHY] = val;
+	sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
+	sc->port.link_config[ELINK_EXT_PHY1] =
+	    SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
+
+	/* get the override preemphasis flag and enable it or turn it off */
+	val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
+	if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
+		sc->link_params.feature_config_flags |=
+		    ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
+	} else {
+		sc->link_params.feature_config_flags &=
+		    ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
+	}
+
+	/* get the initial value of the link params */
+	sc->link_params.multi_phy_config =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
+
+	/* get external phy info */
+	sc->port.ext_phy_config =
+	    SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
+
+	/* get the multifunction configuration */
+	bcm_get_mf_cfg_info(sc);
+
+	/* get the mac address */
+	if (IS_MF(sc)) {
+		mac_hi =
+		    MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
+		mac_lo =
+		    MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
+	} else {
+		mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
+		mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
+	}
+
+	if ((mac_lo == 0) && (mac_hi == 0)) {
+		*sc->mac_addr_str = 0;
+		PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
+	} else {
+		sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
+		sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
+		sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
+		sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
+		sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
+		sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
+		snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
+			 "%02x:%02x:%02x:%02x:%02x:%02x",
+			 sc->link_params.mac_addr[0],
+			 sc->link_params.mac_addr[1],
+			 sc->link_params.mac_addr[2],
+			 sc->link_params.mac_addr[3],
+			 sc->link_params.mac_addr[4],
+			 sc->link_params.mac_addr[5]);
+		PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
+	}
+
+	return 0;
+}
+
+static void bcm_media_detect(struct bcm_softc *sc)
+{
+	uint32_t phy_idx = bcm_get_cur_phy_idx(sc);
+	switch (sc->link_params.phy[phy_idx].media_type) {
+	case ELINK_ETH_PHY_SFPP_10G_FIBER:
+	case ELINK_ETH_PHY_SFP_1G_FIBER:
+	case ELINK_ETH_PHY_XFP_FIBER:
+	case ELINK_ETH_PHY_KR:
+	case ELINK_ETH_PHY_CX4:
+		PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
+		sc->media = IFM_10G_CX4;
+		break;
+	case ELINK_ETH_PHY_DA_TWINAX:
+		PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
+		sc->media = IFM_10G_TWINAX;
+		break;
+	case ELINK_ETH_PHY_BASE_T:
+		PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
+		sc->media = IFM_10G_T;
+		break;
+	case ELINK_ETH_PHY_NOT_PRESENT:
+		PMD_DRV_LOG(INFO, "Media not present.");
+		sc->media = 0;
+		break;
+	case ELINK_ETH_PHY_UNSPECIFIED:
+	default:
+		PMD_DRV_LOG(INFO, "Unknown media!");
+		sc->media = 0;
+		break;
+	}
+}
+
+#define GET_FIELD(value, fname)                     \
+(((value) & (fname##_MASK)) >> (fname##_SHIFT))
+#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
+#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
+
+static int bcm_get_igu_cam_info(struct bcm_softc *sc)
+{
+	int pfid = SC_FUNC(sc);
+	int igu_sb_id;
+	uint32_t val;
+	uint8_t fid, igu_sb_cnt = 0;
+
+	sc->igu_base_sb = 0xff;
+
+	if (CHIP_INT_MODE_IS_BC(sc)) {
+		int vn = SC_VN(sc);
+		igu_sb_cnt = sc->igu_sb_cnt;
+		sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
+				   FP_SB_MAX_E1x);
+		sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
+				  (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
+		return 0;
+	}
+
+	/* IGU in normal mode - read CAM */
+	for (igu_sb_id = 0;
+	     igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
+		val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
+		if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
+			continue;
+		}
+		fid = IGU_FID(val);
+		if ((fid & IGU_FID_ENCODE_IS_PF)) {
+			if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
+				continue;
+			}
+			if (IGU_VEC(val) == 0) {
+				/* default status block */
+				sc->igu_dsb_id = igu_sb_id;
+			} else {
+				if (sc->igu_base_sb == 0xff) {
+					sc->igu_base_sb = igu_sb_id;
+				}
+				igu_sb_cnt++;
+			}
+		}
+	}
+
+	/*
+	 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
+	 * that number of CAM entries will not be equal to the value advertised in
+	 * PCI. Driver should use the minimal value of both as the actual status
+	 * block count
+	 */
+	sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
+
+	if (igu_sb_cnt == 0) {
+		PMD_DRV_LOG(ERR, "CAM configuration error");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+* Gather various information from the device config space, the device itself,
+* shmem, and the user input.
+*/
+static int bcm_get_device_info(struct bcm_softc *sc)
+{
+	uint32_t val;
+	int rc;
+
+	/* get the chip revision (chip metal comes from pci config space) */
+	sc->devinfo.chip_id = sc->link_params.chip_id =
+	    (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
+	     ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
+	     (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
+	     ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
+
+	/* force 57811 according to MISC register */
+	if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
+		if (CHIP_IS_57810(sc)) {
+			sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
+					       (sc->
+						devinfo.chip_id & 0x0000ffff));
+		} else if (CHIP_IS_57810_MF(sc)) {
+			sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
+					       (sc->
+						devinfo.chip_id & 0x0000ffff));
+		}
+		sc->devinfo.chip_id |= 0x1;
+	}
+
+	PMD_DRV_LOG(DEBUG,
+		    "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
+		    sc->devinfo.chip_id,
+		    ((sc->devinfo.chip_id >> 16) & 0xffff),
+		    ((sc->devinfo.chip_id >> 12) & 0xf),
+		    ((sc->devinfo.chip_id >> 4) & 0xff),
+		    ((sc->devinfo.chip_id >> 0) & 0xf));
+
+	val = (REG_RD(sc, 0x2874) & 0x55);
+	if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
+		sc->flags |= BCM_ONE_PORT_FLAG;
+		PMD_DRV_LOG(DEBUG, "single port device");
+	}
+
+	/* set the doorbell size */
+	sc->doorbell_size = (1 << BCM_DB_SHIFT);
+
+	/* determine whether the device is in 2 port or 4 port mode */
+	sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;	/* E1h */
+	if (CHIP_IS_E2E3(sc)) {
+/*
+ * Read port4mode_en_ovwr[0]:
+ *   If 1, four port mode is in port4mode_en_ovwr[1].
+ *   If 0, four port mode is in port4mode_en[0].
+ */
+		val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
+		if (val & 1) {
+			val = ((val >> 1) & 1);
+		} else {
+			val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
+		}
+
+		sc->devinfo.chip_port_mode =
+		    (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
+
+		PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
+	}
+
+	/* get the function and path info for the device */
+	bcm_get_function_num(sc);
+
+	/* get the shared memory base address */
+	sc->devinfo.shmem_base =
+	    sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
+	sc->devinfo.shmem2_base =
+	    REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
+			MISC_REG_GENERIC_CR_0));
+
+	if (!sc->devinfo.shmem_base) {
+/* this should ONLY prevent upcoming shmem reads */
+		PMD_DRV_LOG(INFO, "MCP not active");
+		sc->flags |= BCM_NO_MCP_FLAG;
+		return 0;
+	}
+
+	/* make sure the shared memory contents are valid */
+	val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
+	if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
+	    (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
+		PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
+			    val);
+		return 0;
+	}
+
+	/* get the bootcode version */
+	sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
+	snprintf(sc->devinfo.bc_ver_str,
+		 sizeof(sc->devinfo.bc_ver_str),
+		 "%d.%d.%d",
+		 ((sc->devinfo.bc_ver >> 24) & 0xff),
+		 ((sc->devinfo.bc_ver >> 16) & 0xff),
+		 ((sc->devinfo.bc_ver >> 8) & 0xff));
+	PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
+
+	/* get the bootcode shmem address */
+	sc->devinfo.mf_cfg_base = bcm_get_shmem_mf_cfg_base(sc);
+
+	/* clean indirect addresses as they're not used */
+	pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
+	if (IS_PF(sc)) {
+		REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
+		REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
+		REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
+		REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
+		if (CHIP_IS_E1x(sc)) {
+			REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
+			REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
+			REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
+			REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
+		}
+
+/*
+ * Enable internal target-read (in case we are probed after PF
+ * FLR). Must be done prior to any BAR read access. Only for
+ * 57712 and up
+ */
+		if (!CHIP_IS_E1x(sc)) {
+			REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
+			       1);
+		}
+	}
+
+	/* get the nvram size */
+	val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
+	sc->devinfo.flash_size =
+	    (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
+
+	bcm_set_power_state(sc, PCI_PM_D0);
+	/* get various configuration parameters from shmem */
+	bcm_get_shmem_info(sc);
+
+	/* initialize IGU parameters */
+	if (CHIP_IS_E1x(sc)) {
+		sc->devinfo.int_block = INT_BLOCK_HC;
+		sc->igu_dsb_id = DEF_SB_IGU_ID;
+		sc->igu_base_sb = 0;
+	} else {
+		sc->devinfo.int_block = INT_BLOCK_IGU;
+
+/* do not allow device reset during IGU info preocessing */
+		bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
+
+		val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
+
+		if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
+			int tout = 5000;
+
+			val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
+			REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
+			REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
+
+			while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
+				tout--;
+				DELAY(1000);
+			}
+
+			if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
+				PMD_DRV_LOG(NOTICE,
+					    "FORCING IGU Normal Mode failed!!!");
+				bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
+				return -1;
+			}
+		}
+
+		if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
+			PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
+			sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
+		} else {
+			PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
+		}
+
+		rc = bcm_get_igu_cam_info(sc);
+
+		bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
+
+		if (rc) {
+			return rc;
+		}
+	}
+
+	/*
+	 * Get base FW non-default (fast path) status block ID. This value is
+	 * used to initialize the fw_sb_id saved on the fp/queue structure to
+	 * determine the id used by the FW.
+	 */
+	if (CHIP_IS_E1x(sc)) {
+		sc->base_fw_ndsb =
+		    ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
+	} else {
+/*
+ * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
+ * the same queue are indicated on the same IGU SB). So we prefer
+ * FW and IGU SBs to be the same value.
+ */
+		sc->base_fw_ndsb = sc->igu_base_sb;
+	}
+
+	elink_phy_probe(&sc->link_params);
+
+	return 0;
+}
+
+static void
+bcm_link_settings_supported(struct bcm_softc *sc, uint32_t switch_cfg)
+{
+	uint32_t cfg_size = 0;
+	uint32_t idx;
+	uint8_t port = SC_PORT(sc);
+
+	/* aggregation of supported attributes of all external phys */
+	sc->port.supported[0] = 0;
+	sc->port.supported[1] = 0;
+
+	switch (sc->link_params.num_phys) {
+	case 1:
+		sc->port.supported[0] =
+		    sc->link_params.phy[ELINK_INT_PHY].supported;
+		cfg_size = 1;
+		break;
+	case 2:
+		sc->port.supported[0] =
+		    sc->link_params.phy[ELINK_EXT_PHY1].supported;
+		cfg_size = 1;
+		break;
+	case 3:
+		if (sc->link_params.multi_phy_config &
+		    PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
+			sc->port.supported[1] =
+			    sc->link_params.phy[ELINK_EXT_PHY1].supported;
+			sc->port.supported[0] =
+			    sc->link_params.phy[ELINK_EXT_PHY2].supported;
+		} else {
+			sc->port.supported[0] =
+			    sc->link_params.phy[ELINK_EXT_PHY1].supported;
+			sc->port.supported[1] =
+			    sc->link_params.phy[ELINK_EXT_PHY2].supported;
+		}
+		cfg_size = 2;
+		break;
+	}
+
+	if (!(sc->port.supported[0] || sc->port.supported[1])) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
+			    SHMEM_RD(sc,
+				     dev_info.port_hw_config
+				     [port].external_phy_config),
+			    SHMEM_RD(sc,
+				     dev_info.port_hw_config
+				     [port].external_phy_config2));
+		return;
+	}
+
+	if (CHIP_IS_E3(sc))
+		sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
+	else {
+		switch (switch_cfg) {
+		case ELINK_SWITCH_CFG_1G:
+			sc->port.phy_addr =
+			    REG_RD(sc,
+				   NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
+			break;
+		case ELINK_SWITCH_CFG_10G:
+			sc->port.phy_addr =
+			    REG_RD(sc,
+				   NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
+			break;
+		default:
+			PMD_DRV_LOG(ERR,
+				    "Invalid switch config in"
+				    "link_config=0x%08x",
+				    sc->port.link_config[0]);
+			return;
+		}
+	}
+
+	PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
+
+	/* mask what we support according to speed_cap_mask per configuration */
+	for (idx = 0; idx < cfg_size; idx++) {
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_10baseT_Half;
+		}
+
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_10baseT_Full;
+		}
+
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_100baseT_Half;
+		}
+
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_100baseT_Full;
+		}
+
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_1000baseT_Full;
+		}
+
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_2500baseX_Full;
+		}
+
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_10000baseT_Full;
+		}
+
+		if (!(sc->link_params.speed_cap_mask[idx] &
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
+			sc->port.supported[idx] &=
+			    ~ELINK_SUPPORTED_20000baseKR2_Full;
+		}
+	}
+
+	PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
+		    sc->port.supported[0], sc->port.supported[1]);
+}
+
+static void bcm_link_settings_requested(struct bcm_softc *sc)
+{
+	uint32_t link_config;
+	uint32_t idx;
+	uint32_t cfg_size = 0;
+
+	sc->port.advertising[0] = 0;
+	sc->port.advertising[1] = 0;
+
+	switch (sc->link_params.num_phys) {
+	case 1:
+	case 2:
+		cfg_size = 1;
+		break;
+	case 3:
+		cfg_size = 2;
+		break;
+	}
+
+	for (idx = 0; idx < cfg_size; idx++) {
+		sc->link_params.req_duplex[idx] = DUPLEX_FULL;
+		link_config = sc->port.link_config[idx];
+
+		switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
+		case PORT_FEATURE_LINK_SPEED_AUTO:
+			if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_AUTO_NEG;
+				sc->port.advertising[idx] |=
+				    sc->port.supported[idx];
+				if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
+				    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
+					sc->port.advertising[idx] |=
+					    (ELINK_SUPPORTED_100baseT_Half |
+					     ELINK_SUPPORTED_100baseT_Full);
+			} else {
+				/* force 10G, no AN */
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_10000;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_10000baseT_Full |
+				     ADVERTISED_FIBRE);
+				continue;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_10M_FULL:
+			if (sc->
+			    port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
+			{
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_10;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_10baseT_Full | ADVERTISED_TP);
+			} else {
+				PMD_DRV_LOG(ERR,
+					    "Invalid NVRAM config link_config=0x%08x "
+					    "speed_cap_mask=0x%08x",
+					    link_config,
+					    sc->
+					    link_params.speed_cap_mask[idx]);
+				return;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_10M_HALF:
+			if (sc->
+			    port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
+			{
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_10;
+				sc->link_params.req_duplex[idx] = DUPLEX_HALF;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_10baseT_Half | ADVERTISED_TP);
+			} else {
+				PMD_DRV_LOG(ERR,
+					    "Invalid NVRAM config link_config=0x%08x "
+					    "speed_cap_mask=0x%08x",
+					    link_config,
+					    sc->
+					    link_params.speed_cap_mask[idx]);
+				return;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_100M_FULL:
+			if (sc->
+			    port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
+			{
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_100;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_100baseT_Full | ADVERTISED_TP);
+			} else {
+				PMD_DRV_LOG(ERR,
+					    "Invalid NVRAM config link_config=0x%08x "
+					    "speed_cap_mask=0x%08x",
+					    link_config,
+					    sc->
+					    link_params.speed_cap_mask[idx]);
+				return;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_100M_HALF:
+			if (sc->
+			    port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
+			{
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_100;
+				sc->link_params.req_duplex[idx] = DUPLEX_HALF;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_100baseT_Half | ADVERTISED_TP);
+			} else {
+				PMD_DRV_LOG(ERR,
+					    "Invalid NVRAM config link_config=0x%08x "
+					    "speed_cap_mask=0x%08x",
+					    link_config,
+					    sc->
+					    link_params.speed_cap_mask[idx]);
+				return;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_1G:
+			if (sc->port.supported[idx] &
+			    ELINK_SUPPORTED_1000baseT_Full) {
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_1000;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
+			} else {
+				PMD_DRV_LOG(ERR,
+					    "Invalid NVRAM config link_config=0x%08x "
+					    "speed_cap_mask=0x%08x",
+					    link_config,
+					    sc->
+					    link_params.speed_cap_mask[idx]);
+				return;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_2_5G:
+			if (sc->port.supported[idx] &
+			    ELINK_SUPPORTED_2500baseX_Full) {
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_2500;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
+			} else {
+				PMD_DRV_LOG(ERR,
+					    "Invalid NVRAM config link_config=0x%08x "
+					    "speed_cap_mask=0x%08x",
+					    link_config,
+					    sc->
+					    link_params.speed_cap_mask[idx]);
+				return;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_10G_CX4:
+			if (sc->port.supported[idx] &
+			    ELINK_SUPPORTED_10000baseT_Full) {
+				sc->link_params.req_line_speed[idx] =
+				    ELINK_SPEED_10000;
+				sc->port.advertising[idx] |=
+				    (ADVERTISED_10000baseT_Full |
+				     ADVERTISED_FIBRE);
+			} else {
+				PMD_DRV_LOG(ERR,
+					    "Invalid NVRAM config link_config=0x%08x "
+					    "speed_cap_mask=0x%08x",
+					    link_config,
+					    sc->
+					    link_params.speed_cap_mask[idx]);
+				return;
+			}
+			break;
+
+		case PORT_FEATURE_LINK_SPEED_20G:
+			sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
+			break;
+
+		default:
+			PMD_DRV_LOG(ERR,
+				    "Invalid NVRAM config link_config=0x%08x "
+				    "speed_cap_mask=0x%08x", link_config,
+				    sc->link_params.speed_cap_mask[idx]);
+			sc->link_params.req_line_speed[idx] =
+			    ELINK_SPEED_AUTO_NEG;
+			sc->port.advertising[idx] = sc->port.supported[idx];
+			break;
+		}
+
+		sc->link_params.req_flow_ctrl[idx] =
+		    (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
+
+		if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
+			if (!
+			    (sc->
+			     port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
+				sc->link_params.req_flow_ctrl[idx] =
+				    ELINK_FLOW_CTRL_NONE;
+			} else {
+				bcm_set_requested_fc(sc);
+			}
+		}
+	}
+}
+
+static void bcm_get_phy_info(struct bcm_softc *sc)
+{
+	uint8_t port = SC_PORT(sc);
+	uint32_t eee_mode;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/* shmem data already read in bcm_get_shmem_info() */
+
+	bcm_link_settings_supported(sc, sc->link_params.switch_cfg);
+	bcm_link_settings_requested(sc);
+
+	/* configure link feature according to nvram value */
+	eee_mode =
+	    (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
+	      & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
+	     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
+	if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
+		sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
+					    ELINK_EEE_MODE_ENABLE_LPI |
+					    ELINK_EEE_MODE_OUTPUT_TIME);
+	} else {
+		sc->link_params.eee_mode = 0;
+	}
+
+	/* get the media type */
+	bcm_media_detect(sc);
+}
+
+static void bcm_set_modes_bitmap(struct bcm_softc *sc)
+{
+	uint32_t flags = MODE_ASIC | MODE_PORT2;
+
+	if (CHIP_IS_E2(sc)) {
+		flags |= MODE_E2;
+	} else if (CHIP_IS_E3(sc)) {
+		flags |= MODE_E3;
+		if (CHIP_REV(sc) == CHIP_REV_Ax) {
+			flags |= MODE_E3_A0;
+		} else {	/*if (CHIP_REV(sc) == CHIP_REV_Bx) */
+
+			flags |= MODE_E3_B0 | MODE_COS3;
+		}
+	}
+
+	if (IS_MF(sc)) {
+		flags |= MODE_MF;
+		switch (sc->devinfo.mf_info.mf_mode) {
+		case MULTI_FUNCTION_SD:
+			flags |= MODE_MF_SD;
+			break;
+		case MULTI_FUNCTION_SI:
+			flags |= MODE_MF_SI;
+			break;
+		case MULTI_FUNCTION_AFEX:
+			flags |= MODE_MF_AFEX;
+			break;
+		}
+	} else {
+		flags |= MODE_SF;
+	}
+
+#if defined(__LITTLE_ENDIAN)
+	flags |= MODE_LITTLE_ENDIAN;
+#else /* __BIG_ENDIAN */
+	flags |= MODE_BIG_ENDIAN;
+#endif
+
+	INIT_MODE_FLAGS(sc) = flags;
+}
+
+int bcm_alloc_hsi_mem(struct bcm_softc *sc)
+{
+	struct bcm_fastpath *fp;
+	char buf[32];
+	uint32_t i;
+
+	if (IS_PF(sc)) {
+/************************/
+/* DEFAULT STATUS BLOCK */
+/************************/
+
+		if (bcm_dma_alloc(sc, sizeof(struct host_sp_status_block),
+				  &sc->def_sb_dma, "def_sb",
+				  RTE_CACHE_LINE_SIZE) != 0) {
+			return -1;
+		}
+
+		sc->def_sb =
+		    (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
+/***************/
+/* EVENT QUEUE */
+/***************/
+
+		if (bcm_dma_alloc(sc, BCM_PAGE_SIZE,
+				  &sc->eq_dma, "ev_queue",
+				  RTE_CACHE_LINE_SIZE) != 0) {
+			sc->def_sb = NULL;
+			return -1;
+		}
+
+		sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
+
+/*************/
+/* SLOW PATH */
+/*************/
+
+		if (bcm_dma_alloc(sc, sizeof(struct bcm_slowpath),
+				  &sc->sp_dma, "sp",
+				  RTE_CACHE_LINE_SIZE) != 0) {
+			sc->eq = NULL;
+			sc->def_sb = NULL;
+			return -1;
+		}
+
+		sc->sp = (struct bcm_slowpath *)sc->sp_dma.vaddr;
+
+/*******************/
+/* SLOW PATH QUEUE */
+/*******************/
+
+		if (bcm_dma_alloc(sc, BCM_PAGE_SIZE,
+				  &sc->spq_dma, "sp_queue",
+				  RTE_CACHE_LINE_SIZE) != 0) {
+			sc->sp = NULL;
+			sc->eq = NULL;
+			sc->def_sb = NULL;
+			return -1;
+		}
+
+		sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
+
+/***************************/
+/* FW DECOMPRESSION BUFFER */
+/***************************/
+
+		if (bcm_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
+				  "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
+			sc->spq = NULL;
+			sc->sp = NULL;
+			sc->eq = NULL;
+			sc->def_sb = NULL;
+			return -1;
+		}
+
+		sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
+	}
+
+	/*************/
+	/* FASTPATHS */
+	/*************/
+
+	/* allocate DMA memory for each fastpath structure */
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+		fp->sc = sc;
+		fp->index = i;
+
+/*******************/
+/* FP STATUS BLOCK */
+/*******************/
+
+		snprintf(buf, sizeof(buf), "fp_%d_sb", i);
+		if (bcm_dma_alloc(sc, sizeof(union bcm_host_hc_status_block),
+				  &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
+			PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
+			return -1;
+		} else {
+			if (CHIP_IS_E2E3(sc)) {
+				fp->status_block.e2_sb =
+				    (struct host_hc_status_block_e2 *)
+				    fp->sb_dma.vaddr;
+			} else {
+				fp->status_block.e1x_sb =
+				    (struct host_hc_status_block_e1x *)
+				    fp->sb_dma.vaddr;
+			}
+		}
+	}
+
+	return 0;
+}
+
+void bcm_free_hsi_mem(struct bcm_softc *sc)
+{
+	struct bcm_fastpath *fp;
+	int i;
+
+	for (i = 0; i < sc->num_queues; i++) {
+		fp = &sc->fp[i];
+
+/*******************/
+/* FP STATUS BLOCK */
+/*******************/
+
+		memset(&fp->status_block, 0, sizeof(fp->status_block));
+	}
+
+	/***************************/
+	/* FW DECOMPRESSION BUFFER */
+	/***************************/
+
+	sc->gz_buf = NULL;
+
+	/*******************/
+	/* SLOW PATH QUEUE */
+	/*******************/
+
+	sc->spq = NULL;
+
+	/*************/
+	/* SLOW PATH */
+	/*************/
+
+	sc->sp = NULL;
+
+	/***************/
+	/* EVENT QUEUE */
+	/***************/
+
+	sc->eq = NULL;
+
+	/************************/
+	/* DEFAULT STATUS BLOCK */
+	/************************/
+
+	sc->def_sb = NULL;
+
+}
+
+/*
+* Previous driver DMAE transaction may have occurred when pre-boot stage
+* ended and boot began. This would invalidate the addresses of the
+* transaction, resulting in was-error bit set in the PCI causing all
+* hw-to-host PCIe transactions to timeout. If this happened we want to clear
+* the interrupt which detected this from the pglueb and the was-done bit
+*/
+static void bcm_prev_interrupted_dmae(struct bcm_softc *sc)
+{
+	uint32_t val;
+
+	if (!CHIP_IS_E1x(sc)) {
+		val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
+		if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
+			REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
+			       1 << SC_FUNC(sc));
+		}
+	}
+}
+
+static int bcm_prev_mcp_done(struct bcm_softc *sc)
+{
+	uint32_t rc = bcm_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
+				     DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
+	if (!rc) {
+		PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+		return -1;
+	}
+
+	return 0;
+}
+
+static struct bcm_prev_list_node *bcm_prev_path_get_entry(struct bcm_softc *sc)
+{
+	struct bcm_prev_list_node *tmp;
+
+	LIST_FOREACH(tmp, &bcm_prev_list, node) {
+		if ((sc->pcie_bus == tmp->bus) &&
+		    (sc->pcie_device == tmp->slot) &&
+		    (SC_PATH(sc) == tmp->path)) {
+			return tmp;
+		}
+	}
+
+	return NULL;
+}
+
+static uint8_t bcm_prev_is_path_marked(struct bcm_softc *sc)
+{
+	struct bcm_prev_list_node *tmp;
+	int rc = FALSE;
+
+	rte_spinlock_lock(&bcm_prev_mtx);
+
+	tmp = bcm_prev_path_get_entry(sc);
+	if (tmp) {
+		if (tmp->aer) {
+			PMD_DRV_LOG(DEBUG,
+				    "Path %d/%d/%d was marked by AER",
+				    sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
+		} else {
+			rc = TRUE;
+			PMD_DRV_LOG(DEBUG,
+				    "Path %d/%d/%d was already cleaned from previous drivers",
+				    sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
+		}
+	}
+
+	rte_spinlock_unlock(&bcm_prev_mtx);
+
+	return rc;
+}
+
+static int bcm_prev_mark_path(struct bcm_softc *sc, uint8_t after_undi)
+{
+	struct bcm_prev_list_node *tmp;
+
+	rte_spinlock_lock(&bcm_prev_mtx);
+
+	/* Check whether the entry for this path already exists */
+	tmp = bcm_prev_path_get_entry(sc);
+	if (tmp) {
+		if (!tmp->aer) {
+			PMD_DRV_LOG(DEBUG,
+				    "Re-marking AER in path %d/%d/%d",
+				    sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
+		} else {
+			PMD_DRV_LOG(DEBUG,
+				    "Removing AER indication from path %d/%d/%d",
+				    sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
+			tmp->aer = 0;
+		}
+
+		rte_spinlock_unlock(&bcm_prev_mtx);
+		return 0;
+	}
+
+	rte_spinlock_unlock(&bcm_prev_mtx);
+
+	/* Create an entry for this path and add it */
+	tmp = rte_malloc("", sizeof(struct bcm_prev_list_node),
+			 RTE_CACHE_LINE_SIZE);
+	if (!tmp) {
+		PMD_DRV_LOG(NOTICE, "Failed to allocate 'bcm_prev_list_node'");
+		return -1;
+	}
+
+	tmp->bus = sc->pcie_bus;
+	tmp->slot = sc->pcie_device;
+	tmp->path = SC_PATH(sc);
+	tmp->aer = 0;
+	tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
+
+	rte_spinlock_lock(&bcm_prev_mtx);
+
+	LIST_INSERT_HEAD(&bcm_prev_list, tmp, node);
+
+	rte_spinlock_unlock(&bcm_prev_mtx);
+
+	return 0;
+}
+
+static int bcm_do_flr(struct bcm_softc *sc)
+{
+	int i;
+
+	/* only E2 and onwards support FLR */
+	if (CHIP_IS_E1x(sc)) {
+		PMD_DRV_LOG(WARN, "FLR not supported in E1H");
+		return -1;
+	}
+
+	/* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
+	if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
+		PMD_DRV_LOG(WARN,
+			    "FLR not supported by BC_VER: 0x%08x",
+			    sc->devinfo.bc_ver);
+		return -1;
+	}
+
+	/* Wait for Transaction Pending bit clean */
+	for (i = 0; i < 4; i++) {
+		if (i) {
+			DELAY(((1 << (i - 1)) * 100) * 1000);
+		}
+
+		if (!bcm_is_pcie_pending(sc)) {
+			goto clear;
+		}
+	}
+
+	PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
+		    "proceeding with reset anyway");
+
+clear:
+	bcm_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
+
+	return 0;
+}
+
+struct bcm_mac_vals {
+	uint32_t xmac_addr;
+	uint32_t xmac_val;
+	uint32_t emac_addr;
+	uint32_t emac_val;
+	uint32_t umac_addr;
+	uint32_t umac_val;
+	uint32_t bmac_addr;
+	uint32_t bmac_val[2];
+};
+
+static void
+bcm_prev_unload_close_mac(struct bcm_softc *sc, struct bcm_mac_vals *vals)
+{
+	uint32_t val, base_addr, offset, mask, reset_reg;
+	uint8_t mac_stopped = FALSE;
+	uint8_t port = SC_PORT(sc);
+	uint32_t wb_data[2];
+
+	/* reset addresses as they also mark which values were changed */
+	vals->bmac_addr = 0;
+	vals->umac_addr = 0;
+	vals->xmac_addr = 0;
+	vals->emac_addr = 0;
+
+	reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
+
+	if (!CHIP_IS_E3(sc)) {
+		val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
+		mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
+		if ((mask & reset_reg) && val) {
+			base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
+			    : NIG_REG_INGRESS_BMAC0_MEM;
+			offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
+			    : BIGMAC_REGISTER_BMAC_CONTROL;
+
+			/*
+			 * use rd/wr since we cannot use dmae. This is safe
+			 * since MCP won't access the bus due to the request
+			 * to unload, and no function on the path can be
+			 * loaded at this time.
+			 */
+			wb_data[0] = REG_RD(sc, base_addr + offset);
+			wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
+			vals->bmac_addr = base_addr + offset;
+			vals->bmac_val[0] = wb_data[0];
+			vals->bmac_val[1] = wb_data[1];
+			wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
+			REG_WR(sc, vals->bmac_addr, wb_data[0]);
+			REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
+		}
+
+		vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
+		vals->emac_val = REG_RD(sc, vals->emac_addr);
+		REG_WR(sc, vals->emac_addr, 0);
+		mac_stopped = TRUE;
+	} else {
+		if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
+			base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
+			val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
+			REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
+			       val & ~(1 << 1));
+			REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
+			       val | (1 << 1));
+			vals->xmac_addr = base_addr + XMAC_REG_CTRL;
+			vals->xmac_val = REG_RD(sc, vals->xmac_addr);
+			REG_WR(sc, vals->xmac_addr, 0);
+			mac_stopped = TRUE;
+		}
+
+		mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
+		if (mask & reset_reg) {
+			base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
+			vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
+			vals->umac_val = REG_RD(sc, vals->umac_addr);
+			REG_WR(sc, vals->umac_addr, 0);
+			mac_stopped = TRUE;
+		}
+	}
+
+	if (mac_stopped) {
+		DELAY(20000);
+	}
+}
+
+#define BCM_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
+#define BCM_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
+#define BCM_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
+#define BCM_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
+
+static void
+bcm_prev_unload_undi_inc(struct bcm_softc *sc, uint8_t port, uint8_t inc)
+{
+	uint16_t rcq, bd;
+	uint32_t tmp_reg = REG_RD(sc, BCM_PREV_UNDI_PROD_ADDR(port));
+
+	rcq = BCM_PREV_UNDI_RCQ(tmp_reg) + inc;
+	bd = BCM_PREV_UNDI_BD(tmp_reg) + inc;
+
+	tmp_reg = BCM_PREV_UNDI_PROD(rcq, bd);
+	REG_WR(sc, BCM_PREV_UNDI_PROD_ADDR(port), tmp_reg);
+}
+
+static int bcm_prev_unload_common(struct bcm_softc *sc)
+{
+	uint32_t reset_reg, tmp_reg = 0, rc;
+	uint8_t prev_undi = FALSE;
+	struct bcm_mac_vals mac_vals;
+	uint32_t timer_count = 1000;
+	uint32_t prev_brb;
+
+	/*
+	 * It is possible a previous function received 'common' answer,
+	 * but hasn't loaded yet, therefore creating a scenario of
+	 * multiple functions receiving 'common' on the same path.
+	 */
+	memset(&mac_vals, 0, sizeof(mac_vals));
+
+	if (bcm_prev_is_path_marked(sc)) {
+		return bcm_prev_mcp_done(sc);
+	}
+
+	reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
+
+	/* Reset should be performed after BRB is emptied */
+	if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
+		/* Close the MAC Rx to prevent BRB from filling up */
+		bcm_prev_unload_close_mac(sc, &mac_vals);
+
+		/* close LLH filters towards the BRB */
+		elink_set_rx_filter(&sc->link_params, 0);
+
+		/*
+		 * Check if the UNDI driver was previously loaded.
+		 * UNDI driver initializes CID offset for normal bell to 0x7
+		 */
+		if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
+			tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
+			if (tmp_reg == 0x7) {
+				PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
+				prev_undi = TRUE;
+				/* clear the UNDI indication */
+				REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
+				/* clear possible idle check errors */
+				REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
+			}
+		}
+
+		/* wait until BRB is empty */
+		tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
+		while (timer_count) {
+			prev_brb = tmp_reg;
+
+			tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
+			if (!tmp_reg) {
+				break;
+			}
+
+			PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
+
+			/* reset timer as long as BRB actually gets emptied */
+			if (prev_brb > tmp_reg) {
+				timer_count = 1000;
+			} else {
+				timer_count--;
+			}
+
+			/* If UNDI resides in memory, manually increment it */
+			if (prev_undi) {
+				bcm_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
+			}
+
+			DELAY(10);
+		}
+
+		if (!timer_count) {
+			PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
+		}
+	}
+
+	/* No packets are in the pipeline, path is ready for reset */
+	bcm_reset_common(sc);
+
+	if (mac_vals.xmac_addr) {
+		REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
+	}
+	if (mac_vals.umac_addr) {
+		REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
+	}
+	if (mac_vals.emac_addr) {
+		REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
+	}
+	if (mac_vals.bmac_addr) {
+		REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
+		REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
+	}
+
+	rc = bcm_prev_mark_path(sc, prev_undi);
+	if (rc) {
+		bcm_prev_mcp_done(sc);
+		return rc;
+	}
+
+	return bcm_prev_mcp_done(sc);
+}
+
+static int bcm_prev_unload_uncommon(struct bcm_softc *sc)
+{
+	int rc;
+
+	/* Test if previous unload process was already finished for this path */
+	if (bcm_prev_is_path_marked(sc)) {
+		return bcm_prev_mcp_done(sc);
+	}
+
+	/*
+	 * If function has FLR capabilities, and existing FW version matches
+	 * the one required, then FLR will be sufficient to clean any residue
+	 * left by previous driver
+	 */
+	rc = bcm_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
+	if (!rc) {
+		/* fw version is good */
+		rc = bcm_do_flr(sc);
+	}
+
+	if (!rc) {
+		/* FLR was performed */
+		return 0;
+	}
+
+	PMD_DRV_LOG(INFO, "Could not FLR");
+
+	/* Close the MCP request, return failure */
+	rc = bcm_prev_mcp_done(sc);
+	if (!rc) {
+		rc = BCM_PREV_WAIT_NEEDED;
+	}
+
+	return rc;
+}
+
+static int bcm_prev_unload(struct bcm_softc *sc)
+{
+	int time_counter = 10;
+	uint32_t fw, hw_lock_reg, hw_lock_val;
+	uint32_t rc = 0;
+
+	/*
+	 * Clear HW from errors which may have resulted from an interrupted
+	 * DMAE transaction.
+	 */
+	bcm_prev_interrupted_dmae(sc);
+
+	/* Release previously held locks */
+	if (SC_FUNC(sc) <= 5)
+		hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
+	else
+		hw_lock_reg =
+		    (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
+
+	hw_lock_val = (REG_RD(sc, hw_lock_reg));
+	if (hw_lock_val) {
+		if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
+			REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
+			       (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
+		}
+		REG_WR(sc, hw_lock_reg, 0xffffffff);
+	}
+
+	if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
+		REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
+	}
+
+	do {
+		/* Lock MCP using an unload request */
+		fw = bcm_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
+		if (!fw) {
+			PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
+			rc = -1;
+			break;
+		}
+
+		if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
+			rc = bcm_prev_unload_common(sc);
+			break;
+		}
+
+		/* non-common reply from MCP might require looping */
+		rc = bcm_prev_unload_uncommon(sc);
+		if (rc != BCM_PREV_WAIT_NEEDED) {
+			break;
+		}
+
+		DELAY(20000);
+	} while (--time_counter);
+
+	if (!time_counter || rc) {
+		PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
+		rc = -1;
+	}
+
+	return rc;
+}
+
+static void
+bcm_dcbx_set_state(struct bcm_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
+{
+	if (!CHIP_IS_E1x(sc)) {
+		sc->dcb_state = dcb_on;
+		sc->dcbx_enabled = dcbx_enabled;
+	} else {
+		sc->dcb_state = FALSE;
+		sc->dcbx_enabled = BCM_DCBX_ENABLED_INVALID;
+	}
+	PMD_DRV_LOG(DEBUG,
+		    "DCB state [%s:%s]",
+		    dcb_on ? "ON" : "OFF",
+		    (dcbx_enabled == BCM_DCBX_ENABLED_OFF) ? "user-mode" :
+		    (dcbx_enabled ==
+		     BCM_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
+		    : (dcbx_enabled ==
+		       BCM_DCBX_ENABLED_ON_NEG_ON) ?
+		    "on-chip with negotiation" : "invalid");
+}
+
+static int bcm_set_qm_cid_count(struct bcm_softc *sc)
+{
+	int cid_count = BCM_L2_MAX_CID(sc);
+
+	if (CNIC_SUPPORT(sc)) {
+		cid_count += CNIC_CID_MAX;
+	}
+
+	return roundup(cid_count, QM_CID_ROUND);
+}
+
+static void bcm_init_multi_cos(struct bcm_softc *sc)
+{
+	int pri, cos;
+
+	uint32_t pri_map = 0;
+
+	for (pri = 0; pri < BCM_MAX_PRIORITY; pri++) {
+		cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
+		if (cos < sc->max_cos) {
+			sc->prio_to_cos[pri] = cos;
+		} else {
+			PMD_DRV_LOG(WARN,
+				    "Invalid COS %d for priority %d "
+				    "(max COS is %d), setting to 0", cos, pri,
+				    (sc->max_cos - 1));
+			sc->prio_to_cos[pri] = 0;
+		}
+	}
+}
+
+static int bcm_pci_get_caps(struct bcm_softc *sc)
+{
+	struct {
+		uint8_t id;
+		uint8_t next;
+	} pci_cap;
+	uint16_t status;
+	struct bcm_pci_cap *cap;
+
+	cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bcm_pci_cap),
+					 RTE_CACHE_LINE_SIZE);
+	if (!cap) {
+		PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
+		return -ENOMEM;
+	}
+
+	pci_read(sc, PCI_STATUS, &status, 2);
+	if (!(status & PCI_STATUS_CAP_LIST)) {
+		PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
+		return -1;
+	}
+
+	pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
+	while (pci_cap.next) {
+		cap->addr = pci_cap.next & ~3;
+		pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
+		if (pci_cap.id == 0xff)
+			break;
+		cap->id = pci_cap.id;
+		cap->type = BCM_PCI_CAP;
+		cap->next = rte_zmalloc("pci_cap",
+					sizeof(struct bcm_pci_cap),
+					RTE_CACHE_LINE_SIZE);
+		if (!cap->next) {
+			PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
+			return -ENOMEM;
+		}
+		cap = cap->next;
+	}
+
+	return 0;
+}
+
+static void bcm_init_rte(struct bcm_softc *sc)
+{
+	sc->max_tx_queues = 128;
+	sc->max_rx_queues = 128;
+}
+
+#define FW_HEADER_LEN 104
+#define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
+#define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
+
+void bcm_load_firmware(struct bcm_softc *sc)
+{
+	const char *fwname;
+	int f;
+	struct stat st;
+
+	fwname =
+	    sc->devinfo.device_id ==
+	    BROADCOM_DEV_ID_57711 ? FW_NAME_57711 : FW_NAME_57810;
+	f = open(fwname, O_RDONLY);
+	if (f < 0) {
+		PMD_DRV_LOG(NOTICE, "Can't open firmware file");
+		return;
+	}
+
+	if (fstat(f, &st) < 0) {
+		PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
+		close(f);
+		return;
+	}
+
+	sc->firmware = rte_zmalloc("bcm_fw", st.st_size, RTE_CACHE_LINE_SIZE);
+	if (!sc->firmware) {
+		PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
+		close(f);
+		return;
+	}
+
+	if (read(f, sc->firmware, st.st_size) != st.st_size) {
+		PMD_DRV_LOG(NOTICE, "Can't read firmware data");
+		close(f);
+		return;
+	}
+	close(f);
+
+	sc->fw_len = st.st_size;
+	if (sc->fw_len < FW_HEADER_LEN) {
+		PMD_DRV_LOG(NOTICE, "Invalid fw size: %lu", sc->fw_len);
+		return;
+	}
+	PMD_DRV_LOG(DEBUG, "fw_len = %lu", sc->fw_len);
+}
+
+static void
+bcm_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
+{
+	uint32_t *src = (uint32_t *) data;
+	uint32_t i, j, tmp;
+
+	for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
+		tmp = rte_be_to_cpu_32(src[j]);
+		dst[i].op = (tmp >> 24) & 0xFF;
+		dst[i].offset = tmp & 0xFFFFFF;
+		dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
+	}
+}
+
+static void
+bcm_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
+{
+	uint16_t *src = (uint16_t *) data;
+	uint32_t i;
+
+	for (i = 0; i < len / 2; ++i)
+		dst[i] = rte_be_to_cpu_16(src[i]);
+}
+
+static void bcm_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
+{
+	uint32_t *src = (uint32_t *) data;
+	uint32_t i;
+
+	for (i = 0; i < len / 4; ++i)
+		dst[i] = rte_be_to_cpu_32(src[i]);
+}
+
+static void bcm_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
+{
+	uint32_t *src = (uint32_t *) data;
+	uint32_t i, j, tmp;
+
+	for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
+		dst[i].base = rte_be_to_cpu_32(src[j++]);
+		tmp = rte_be_to_cpu_32(src[j]);
+		dst[i].m1 = (tmp >> 16) & 0xFFFF;
+		dst[i].m2 = tmp & 0xFFFF;
+		++j;
+		tmp = rte_be_to_cpu_32(src[j]);
+		dst[i].m3 = (tmp >> 16) & 0xFFFF;
+		dst[i].size = tmp & 0xFFFF;
+	}
+}
+
+/*
+* Device attach function.
+*
+* Allocates device resources, performs secondary chip identification, and
+* initializes driver instance variables. This function is called from driver
+* load after a successful probe.
+*
+* Returns:
+*   0 = Success, >0 = Failure
+*/
+int bcm_attach(struct bcm_softc *sc)
+{
+	int rc;
+
+	PMD_DRV_LOG(DEBUG, "Starting attach...");
+
+	rc = bcm_pci_get_caps(sc);
+	if (rc) {
+		PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
+		return rc;
+	}
+
+	sc->state = BCM_STATE_CLOSED;
+
+	/* Init RTE stuff */
+	bcm_init_rte(sc);
+
+	pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
+
+	sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
+
+	/* get PCI capabilites */
+	bcm_probe_pci_caps(sc);
+
+	if (sc->devinfo.pcie_msix_cap_reg != 0) {
+		uint32_t val;
+		pci_read(sc,
+			 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
+			 2);
+		sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
+	} else {
+		sc->igu_sb_cnt = 1;
+	}
+
+	if (IS_PF(sc)) {
+/* get device info and set params */
+		if (bcm_get_device_info(sc) != 0) {
+			PMD_DRV_LOG(NOTICE, "getting device info");
+			return -ENXIO;
+		}
+
+/* get phy settings from shmem and 'and' against admin settings */
+		bcm_get_phy_info(sc);
+	} else {
+/* Left mac of VF unfilled, PF should set it for VF */
+		memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
+	}
+
+	sc->wol = 0;
+
+	/* set the default MTU (changed via ifconfig) */
+	sc->mtu = ETHER_MTU;
+
+	bcm_set_modes_bitmap(sc);
+
+	/* need to reset chip if UNDI was active */
+	if (IS_PF(sc) && !BCM_NOMCP(sc)) {
+/* init fw_seq */
+		sc->fw_seq =
+		    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
+		     DRV_MSG_SEQ_NUMBER_MASK);
+		bcm_prev_unload(sc);
+	}
+
+	bcm_dcbx_set_state(sc, FALSE, BCM_DCBX_ENABLED_OFF);
+
+	/* calculate qm_cid_count */
+	sc->qm_cid_count = bcm_set_qm_cid_count(sc);
+
+	sc->max_cos = 1;
+	bcm_init_multi_cos(sc);
+
+	return 0;
+}
+
+static void
+bcm_igu_ack_sb(struct bcm_softc *sc, uint8_t igu_sb_id, uint8_t segment,
+	       uint16_t index, uint8_t op, uint8_t update)
+{
+	uint32_t igu_addr = sc->igu_base_addr;
+	igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
+	bcm_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
+}
+
+static void
+bcm_ack_sb(struct bcm_softc *sc, uint8_t igu_sb_id, uint8_t storm,
+	   uint16_t index, uint8_t op, uint8_t update)
+{
+	if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
+		bcm_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
+	else {
+		uint8_t segment;
+		if (CHIP_INT_MODE_IS_BC(sc)) {
+			segment = storm;
+		} else if (igu_sb_id != sc->igu_dsb_id) {
+			segment = IGU_SEG_ACCESS_DEF;
+		} else if (storm == ATTENTION_ID) {
+			segment = IGU_SEG_ACCESS_ATTN;
+		} else {
+			segment = IGU_SEG_ACCESS_DEF;
+		}
+		bcm_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
+	}
+}
+
+static void
+bcm_igu_clear_sb_gen(struct bcm_softc *sc, uint8_t func, uint8_t idu_sb_id,
+		     uint8_t is_pf)
+{
+	uint32_t data, ctl, cnt = 100;
+	uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
+	uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
+	uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
+	    (idu_sb_id / 32) * 4;
+	uint32_t sb_bit = 1 << (idu_sb_id % 32);
+	uint32_t func_encode = func |
+	    (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
+	uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
+
+	/* Not supported in BC mode */
+	if (CHIP_INT_MODE_IS_BC(sc)) {
+		return;
+	}
+
+	data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
+		 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
+		IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
+
+	ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
+	       (func_encode << IGU_CTRL_REG_FID_SHIFT) |
+	       (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
+
+	REG_WR(sc, igu_addr_data, data);
+
+	mb();
+
+	PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
+		    ctl, igu_addr_ctl);
+	REG_WR(sc, igu_addr_ctl, ctl);
+
+	mb();
+
+	/* wait for clean up to finish */
+	while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
+		DELAY(20000);
+	}
+
+	if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
+		PMD_DRV_LOG(DEBUG,
+			    "Unable to finish IGU cleanup: "
+			    "idu_sb_id %d offset %d bit %d (cnt %d)",
+			    idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
+	}
+}
+
+static void bcm_igu_clear_sb(struct bcm_softc *sc, uint8_t idu_sb_id)
+{
+	bcm_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
+}
+
+/*******************/
+/* ECORE CALLBACKS */
+/*******************/
+
+static void bcm_reset_common(struct bcm_softc *sc)
+{
+	uint32_t val = 0x1400;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/* reset_common */
+	REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
+	       0xd3ffff7f);
+
+	if (CHIP_IS_E3(sc)) {
+		val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
+		val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
+	}
+
+	REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
+}
+
+static void bcm_common_init_phy(struct bcm_softc *sc)
+{
+	uint32_t shmem_base[2];
+	uint32_t shmem2_base[2];
+
+	/* Avoid common init in case MFW supports LFA */
+	if (SHMEM2_RD(sc, size) >
+	    (uint32_t) offsetof(struct shmem2_region,
+				lfa_host_addr[SC_PORT(sc)])) {
+		return;
+	}
+
+	shmem_base[0] = sc->devinfo.shmem_base;
+	shmem2_base[0] = sc->devinfo.shmem2_base;
+
+	if (!CHIP_IS_E1x(sc)) {
+		shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
+		shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
+	}
+
+	elink_common_init_phy(sc, shmem_base, shmem2_base,
+			      sc->devinfo.chip_id, 0);
+}
+
+static void bcm_pf_disable(struct bcm_softc *sc)
+{
+	uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
+
+	val &= ~IGU_PF_CONF_FUNC_EN;
+
+	REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
+	REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
+	REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
+}
+
+static void bcm_init_pxp(struct bcm_softc *sc)
+{
+	uint16_t devctl;
+	int r_order, w_order;
+
+	devctl = bcm_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
+
+	w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
+	r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
+
+	ecore_init_pxp_arb(sc, r_order, w_order);
+}
+
+static uint32_t bcm_get_pretend_reg(struct bcm_softc *sc)
+{
+	uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
+	uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
+	return (base + (SC_ABS_FUNC(sc)) * stride);
+}
+
+/*
+ * Called only on E1H or E2.
+ * When pretending to be PF, the pretend value is the function number 0..7.
+ * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
+ * combination.
+ */
+static int bcm_pretend_func(struct bcm_softc *sc, uint16_t pretend_func_val)
+{
+	uint32_t pretend_reg;
+
+	if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
+		return -1;
+
+	/* get my own pretend register */
+	pretend_reg = bcm_get_pretend_reg(sc);
+	REG_WR(sc, pretend_reg, pretend_func_val);
+	REG_RD(sc, pretend_reg);
+	return 0;
+}
+
+static void bcm_setup_fan_failure_detection(struct bcm_softc *sc)
+{
+	int is_required;
+	uint32_t val;
+	int port;
+
+	is_required = 0;
+	val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
+	       SHARED_HW_CFG_FAN_FAILURE_MASK);
+
+	if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
+		is_required = 1;
+	}
+	/*
+	 * The fan failure mechanism is usually related to the PHY type since
+	 * the power consumption of the board is affected by the PHY. Currently,
+	 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
+	 */
+	else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
+		for (port = PORT_0; port < PORT_MAX; port++) {
+			is_required |= elink_fan_failure_det_req(sc,
+								 sc->
+								 devinfo.shmem_base,
+								 sc->
+								 devinfo.shmem2_base,
+								 port);
+		}
+	}
+
+	if (is_required == 0) {
+		return;
+	}
+
+	/* Fan failure is indicated by SPIO 5 */
+	bcm_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
+
+	/* set to active low mode */
+	val = REG_RD(sc, MISC_REG_SPIO_INT);
+	val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
+	REG_WR(sc, MISC_REG_SPIO_INT, val);
+
+	/* enable interrupt to signal the IGU */
+	val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
+	val |= MISC_SPIO_SPIO5;
+	REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
+}
+
+static void bcm_enable_blocks_attention(struct bcm_softc *sc)
+{
+	uint32_t val;
+
+	REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
+	if (!CHIP_IS_E1x(sc)) {
+		REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
+	} else {
+		REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
+	}
+	REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
+	REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
+	/*
+	 * mask read length error interrupts in brb for parser
+	 * (parsing unit and 'checksum and crc' unit)
+	 * these errors are legal (PU reads fixed length and CAC can cause
+	 * read length error on truncated packets)
+	 */
+	REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
+	REG_WR(sc, QM_REG_QM_INT_MASK, 0);
+	REG_WR(sc, TM_REG_TM_INT_MASK, 0);
+	REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
+	REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
+	REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
+	/*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
+	/*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
+	REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
+	REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
+	REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
+	/*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
+	/*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
+	REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
+	REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
+	REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
+	REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
+	/*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
+	/*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
+
+	val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
+	       PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
+	       PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
+	if (!CHIP_IS_E1x(sc)) {
+		val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
+			PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
+	}
+	REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
+
+	REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
+	REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
+	REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
+	/*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
+
+	if (!CHIP_IS_E1x(sc)) {
+/* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
+		REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
+	}
+
+	REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
+	REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
+	/*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
+	REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18);	/* bit 3,4 masked */
+}
+
+/**
+ * bcm_init_hw_common - initialize the HW at the COMMON phase.
+ *
+ * @sc:     driver handle
+ */
+static int bcm_init_hw_common(struct bcm_softc *sc)
+{
+	uint8_t abs_func_id;
+	uint32_t val;
+
+	PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
+
+	/*
+	 * take the RESET lock to protect undi_unload flow from accessing
+	 * registers while we are resetting the chip
+	 */
+	bcm_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
+
+	bcm_reset_common(sc);
+
+	REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
+
+	val = 0xfffc;
+	if (CHIP_IS_E3(sc)) {
+		val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
+		val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
+	}
+
+	REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
+
+	bcm_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
+
+	ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
+
+	if (!CHIP_IS_E1x(sc)) {
+/*
+ * 4-port mode or 2-port mode we need to turn off master-enable for
+ * everyone. After that we turn it back on for self. So, we disregard
+ * multi-function, and always disable all functions on the given path,
+ * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
+ */
+		for (abs_func_id = SC_PATH(sc);
+		     abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
+			if (abs_func_id == SC_ABS_FUNC(sc)) {
+				REG_WR(sc,
+				       PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
+				       1);
+				continue;
+			}
+
+			bcm_pretend_func(sc, abs_func_id);
+
+			/* clear pf enable */
+			bcm_pf_disable(sc);
+
+			bcm_pretend_func(sc, SC_ABS_FUNC(sc));
+		}
+	}
+
+	ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
+
+	ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
+	bcm_init_pxp(sc);
+
+#ifdef __BIG_ENDIAN
+	REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
+	REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
+	/* make sure this value is 0 */
+	REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
+
+	//REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
+	REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
+	REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
+	REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
+	REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
+#endif
+
+	ecore_ilt_init_page_size(sc, INITOP_SET);
+
+	if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
+		REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
+	}
+
+	/* let the HW do it's magic... */
+	DELAY(100000);
+
+	/* finish PXP init */
+
+	val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
+	if (val != 1) {
+		PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
+		return -1;
+	}
+	val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
+	if (val != 1) {
+		PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
+		return -1;
+	}
+
+	/*
+	 * Timer bug workaround for E2 only. We need to set the entire ILT to have
+	 * entries with value "0" and valid bit on. This needs to be done by the
+	 * first PF that is loaded in a path (i.e. common phase)
+	 */
+	if (!CHIP_IS_E1x(sc)) {
+/*
+ * In E2 there is a bug in the timers block that can cause function 6 / 7
+ * (i.e. vnic3) to start even if it is marked as "scan-off".
+ * This occurs when a different function (func2,3) is being marked
+ * as "scan-off". Real-life scenario for example: if a driver is being
+ * load-unloaded while func6,7 are down. This will cause the timer to access
+ * the ilt, translate to a logical address and send a request to read/write.
+ * Since the ilt for the function that is down is not valid, this will cause
+ * a translation error which is unrecoverable.
+ * The Workaround is intended to make sure that when this happens nothing
+ * fatal will occur. The workaround:
+ *  1.  First PF driver which loads on a path will:
+ *      a.  After taking the chip out of reset, by using pretend,
+ *          it will write "0" to the following registers of
+ *          the other vnics.
+ *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
+ *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
+ *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
+ *          And for itself it will write '1' to
+ *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
+ *          dmae-operations (writing to pram for example.)
+ *          note: can be done for only function 6,7 but cleaner this
+ *            way.
+ *      b.  Write zero+valid to the entire ILT.
+ *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
+ *          VNIC3 (of that port). The range allocated will be the
+ *          entire ILT. This is needed to prevent  ILT range error.
+ *  2.  Any PF driver load flow:
+ *      a.  ILT update with the physical addresses of the allocated
+ *          logical pages.
+ *      b.  Wait 20msec. - note that this timeout is needed to make
+ *          sure there are no requests in one of the PXP internal
+ *          queues with "old" ILT addresses.
+ *      c.  PF enable in the PGLC.
+ *      d.  Clear the was_error of the PF in the PGLC. (could have
+ *          occurred while driver was down)
+ *      e.  PF enable in the CFC (WEAK + STRONG)
+ *      f.  Timers scan enable
+ *  3.  PF driver unload flow:
+ *      a.  Clear the Timers scan_en.
+ *      b.  Polling for scan_on=0 for that PF.
+ *      c.  Clear the PF enable bit in the PXP.
+ *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
+ *      e.  Write zero+valid to all ILT entries (The valid bit must
+ *          stay set)
+ *      f.  If this is VNIC 3 of a port then also init
+ *          first_timers_ilt_entry to zero and last_timers_ilt_entry
+ *          to the last enrty in the ILT.
+ *
+ *      Notes:
+ *      Currently the PF error in the PGLC is non recoverable.
+ *      In the future the there will be a recovery routine for this error.
+ *      Currently attention is masked.
+ *      Having an MCP lock on the load/unload process does not guarantee that
+ *      there is no Timer disable during Func6/7 enable. This is because the
+ *      Timers scan is currently being cleared by the MCP on FLR.
+ *      Step 2.d can be done only for PF6/7 and the driver can also check if
+ *      there is error before clearing it. But the flow above is simpler and
+ *      more general.
+ *      All ILT entries are written by zero+valid and not just PF6/7
+ *      ILT entries since in the future the ILT entries allocation for
+ *      PF-s might be dynamic.
+ */
+		struct ilt_client_info ilt_cli;
+		struct ecore_ilt ilt;
+
+		memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
+		memset(&ilt, 0, sizeof(struct ecore_ilt));
+
+/* initialize dummy TM client */
+		ilt_cli.start = 0;
+		ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
+		ilt_cli.client_num = ILT_CLIENT_TM;
+
+/*
+ * Step 1: set zeroes to all ilt page entries with valid bit on
+ * Step 2: set the timers first/last ilt entry to point
+ * to the entire range to prevent ILT range error for 3rd/4th
+ * vnic (this code assumes existence of the vnic)
+ *
+ * both steps performed by call to ecore_ilt_client_init_op()
+ * with dummy TM client
+ *
+ * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
+ * and his brother are split registers
+ */
+
+		bcm_pretend_func(sc, (SC_PATH(sc) + 6));
+		ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
+		bcm_pretend_func(sc, SC_ABS_FUNC(sc));
+
+		REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BCM_PXP_DRAM_ALIGN);
+		REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BCM_PXP_DRAM_ALIGN);
+		REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
+	}
+
+	REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
+	REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
+
+	if (!CHIP_IS_E1x(sc)) {
+		int factor = 0;
+
+		ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
+		ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
+
+/* let the HW do it's magic... */
+		do {
+			DELAY(200000);
+			val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
+		} while (factor-- && (val != 1));
+
+		if (val != 1) {
+			PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
+			return -1;
+		}
+	}
+
+	ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
+
+	/* clean the DMAE memory */
+	sc->dmae_ready = 1;
+	ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
+
+	ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
+
+	ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
+
+	ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
+
+	ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
+
+	bcm_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
+	bcm_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
+	bcm_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
+	bcm_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
+
+	ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
+
+	/* QM queues pointers table */
+	ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
+
+	/* soft reset pulse */
+	REG_WR(sc, QM_REG_SOFT_RESET, 1);
+	REG_WR(sc, QM_REG_SOFT_RESET, 0);
+
+	if (CNIC_SUPPORT(sc))
+		ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
+
+	ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
+	REG_WR(sc, DORQ_REG_DPM_CID_OFST, BCM_DB_SHIFT);
+
+	if (!CHIP_REV_IS_SLOW(sc)) {
+/* enable hw interrupt from doorbell Q */
+		REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
+	}
+
+	ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
+
+	ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
+	REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
+	REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
+
+	if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
+		if (IS_MF_AFEX(sc)) {
+			/*
+			 * configure that AFEX and VLAN headers must be
+			 * received in AFEX mode
+			 */
+			REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
+			REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
+			REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
+			REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
+			REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
+		} else {
+			/*
+			 * Bit-map indicating which L2 hdrs may appear
+			 * after the basic Ethernet header
+			 */
+			REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
+			       sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
+		}
+	}
+
+	ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
+
+	if (!CHIP_IS_E1x(sc)) {
+/* reset VFC memories */
+		REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
+		       VFC_MEMORIES_RST_REG_CAM_RST |
+		       VFC_MEMORIES_RST_REG_RAM_RST);
+		REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
+		       VFC_MEMORIES_RST_REG_CAM_RST |
+		       VFC_MEMORIES_RST_REG_RAM_RST);
+
+		DELAY(20000);
+	}
+
+	ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
+
+	/* sync semi rtc */
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
+	REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
+
+	ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
+
+	if (!CHIP_IS_E1x(sc)) {
+		if (IS_MF_AFEX(sc)) {
+			/*
+			 * configure that AFEX and VLAN headers must be
+			 * sent in AFEX mode
+			 */
+			REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
+			REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
+			REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
+			REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
+			REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
+		} else {
+			REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
+			       sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
+		}
+	}
+
+	REG_WR(sc, SRC_REG_SOFT_RST, 1);
+
+	ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
+
+	if (CNIC_SUPPORT(sc)) {
+		REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
+		REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
+		REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
+		REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
+		REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
+		REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
+		REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
+		REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
+		REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
+		REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
+	}
+	REG_WR(sc, SRC_REG_SOFT_RST, 0);
+
+	if (sizeof(union cdu_context) != 1024) {
+/* we currently assume that a context is 1024 bytes */
+		PMD_DRV_LOG(NOTICE,
+			    "please adjust the size of cdu_context(%ld)",
+			    (long)sizeof(union cdu_context));
+	}
+
+	ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
+	val = (4 << 24) + (0 << 12) + 1024;
+	REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
+
+	ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
+
+	REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
+	/* enable context validation interrupt from CFC */
+	REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
+
+	/* set the thresholds to prevent CFC/CDU race */
+	REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
+	ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
+
+	if (!CHIP_IS_E1x(sc) && BCM_NOMCP(sc)) {
+		REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
+	}
+
+	ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
+	ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
+
+	/* Reset PCIE errors for debug */
+	REG_WR(sc, 0x2814, 0xffffffff);
+	REG_WR(sc, 0x3820, 0xffffffff);
+
+	if (!CHIP_IS_E1x(sc)) {
+		REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
+		       (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
+			PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
+		REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
+		       (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
+			PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
+			PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
+		REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
+		       (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
+			PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
+			PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
+	}
+
+	ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
+
+	/* in E3 this done in per-port section */
+	if (!CHIP_IS_E3(sc))
+		REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
+
+	if (CHIP_IS_E1H(sc)) {
+/* not applicable for E2 (and above ...) */
+		REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
+	}
+
+	if (CHIP_REV_IS_SLOW(sc)) {
+		DELAY(200000);
+	}
+
+	/* finish CFC init */
+	val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
+	if (val != 1) {
+		PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
+		return -1;
+	}
+	val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
+	if (val != 1) {
+		PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
+		return -1;
+	}
+	val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
+	if (val != 1) {
+		PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
+		return -1;
+	}
+	REG_WR(sc, CFC_REG_DEBUG0, 0);
+
+	bcm_setup_fan_failure_detection(sc);
+
+	/* clear PXP2 attentions */
+	REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
+
+	bcm_enable_blocks_attention(sc);
+
+	if (!CHIP_REV_IS_SLOW(sc)) {
+		ecore_enable_blocks_parity(sc);
+	}
+
+	if (!BCM_NOMCP(sc)) {
+		if (CHIP_IS_E1x(sc)) {
+			bcm_common_init_phy(sc);
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * bcm_init_hw_common_chip - init HW at the COMMON_CHIP phase.
+ *
+ * @sc:     driver handle
+ */
+static int bcm_init_hw_common_chip(struct bcm_softc *sc)
+{
+	int rc = bcm_init_hw_common(sc);
+
+	if (rc) {
+		return rc;
+	}
+
+	/* In E2 2-PORT mode, same ext phy is used for the two paths */
+	if (!BCM_NOMCP(sc)) {
+		bcm_common_init_phy(sc);
+	}
+
+	return 0;
+}
+
+static int bcm_init_hw_port(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
+	uint32_t low, high;
+	uint32_t val;
+
+	PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
+
+	REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
+
+	ecore_init_block(sc, BLOCK_MISC, init_phase);
+	ecore_init_block(sc, BLOCK_PXP, init_phase);
+	ecore_init_block(sc, BLOCK_PXP2, init_phase);
+
+	/*
+	 * Timers bug workaround: disables the pf_master bit in pglue at
+	 * common phase, we need to enable it here before any dmae access are
+	 * attempted. Therefore we manually added the enable-master to the
+	 * port phase (it also happens in the function phase)
+	 */
+	if (!CHIP_IS_E1x(sc)) {
+		REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
+	}
+
+	ecore_init_block(sc, BLOCK_ATC, init_phase);
+	ecore_init_block(sc, BLOCK_DMAE, init_phase);
+	ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
+	ecore_init_block(sc, BLOCK_QM, init_phase);
+
+	ecore_init_block(sc, BLOCK_TCM, init_phase);
+	ecore_init_block(sc, BLOCK_UCM, init_phase);
+	ecore_init_block(sc, BLOCK_CCM, init_phase);
+	ecore_init_block(sc, BLOCK_XCM, init_phase);
+
+	/* QM cid (connection) count */
+	ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
+
+	if (CNIC_SUPPORT(sc)) {
+		ecore_init_block(sc, BLOCK_TM, init_phase);
+		REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
+		REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
+	}
+
+	ecore_init_block(sc, BLOCK_DORQ, init_phase);
+
+	ecore_init_block(sc, BLOCK_BRB1, init_phase);
+
+	if (CHIP_IS_E1H(sc)) {
+		if (IS_MF(sc)) {
+			low = (BCM_ONE_PORT(sc) ? 160 : 246);
+		} else if (sc->mtu > 4096) {
+			if (BCM_ONE_PORT(sc)) {
+				low = 160;
+			} else {
+				val = sc->mtu;
+				/* (24*1024 + val*4)/256 */
+				low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
+			}
+		} else {
+			low = (BCM_ONE_PORT(sc) ? 80 : 160);
+		}
+		high = (low + 56);	/* 14*1024/256 */
+		REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
+		REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
+	}
+
+	if (CHIP_IS_MODE_4_PORT(sc)) {
+		REG_WR(sc, SC_PORT(sc) ?
+		       BRB1_REG_MAC_GUARANTIED_1 :
+		       BRB1_REG_MAC_GUARANTIED_0, 40);
+	}
+
+	ecore_init_block(sc, BLOCK_PRS, init_phase);
+	if (CHIP_IS_E3B0(sc)) {
+		if (IS_MF_AFEX(sc)) {
+			/* configure headers for AFEX mode */
+			if (SC_PORT(sc)) {
+				REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
+				       0xE);
+				REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
+				       0x6);
+				REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
+			} else {
+				REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
+				       0xE);
+				REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
+				       0x6);
+				REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
+			}
+		} else {
+			/* Ovlan exists only if we are in multi-function +
+			 * switch-dependent mode, in switch-independent there
+			 * is no ovlan headers
+			 */
+			REG_WR(sc, SC_PORT(sc) ?
+			       PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
+			       PRS_REG_HDRS_AFTER_BASIC_PORT_0,
+			       (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
+		}
+	}
+
+	ecore_init_block(sc, BLOCK_TSDM, init_phase);
+	ecore_init_block(sc, BLOCK_CSDM, init_phase);
+	ecore_init_block(sc, BLOCK_USDM, init_phase);
+	ecore_init_block(sc, BLOCK_XSDM, init_phase);
+
+	ecore_init_block(sc, BLOCK_TSEM, init_phase);
+	ecore_init_block(sc, BLOCK_USEM, init_phase);
+	ecore_init_block(sc, BLOCK_CSEM, init_phase);
+	ecore_init_block(sc, BLOCK_XSEM, init_phase);
+
+	ecore_init_block(sc, BLOCK_UPB, init_phase);
+	ecore_init_block(sc, BLOCK_XPB, init_phase);
+
+	ecore_init_block(sc, BLOCK_PBF, init_phase);
+
+	if (CHIP_IS_E1x(sc)) {
+/* configure PBF to work without PAUSE mtu 9000 */
+		REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
+
+/* update threshold */
+		REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
+/* update init credit */
+		REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
+		       (9040 / 16) + 553 - 22);
+
+/* probe changes */
+		REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
+		DELAY(50);
+		REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
+	}
+
+	if (CNIC_SUPPORT(sc)) {
+		ecore_init_block(sc, BLOCK_SRC, init_phase);
+	}
+
+	ecore_init_block(sc, BLOCK_CDU, init_phase);
+	ecore_init_block(sc, BLOCK_CFC, init_phase);
+	ecore_init_block(sc, BLOCK_HC, init_phase);
+	ecore_init_block(sc, BLOCK_IGU, init_phase);
+	ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
+	/* init aeu_mask_attn_func_0/1:
+	 *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
+	 *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
+	 *             bits 4-7 are used for "per vn group attention" */
+	val = IS_MF(sc) ? 0xF7 : 0x7;
+	val |= 0x10;
+	REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
+
+	ecore_init_block(sc, BLOCK_NIG, init_phase);
+
+	if (!CHIP_IS_E1x(sc)) {
+/* Bit-map indicating which L2 hdrs may appear after the
+ * basic Ethernet header
+ */
+		if (IS_MF_AFEX(sc)) {
+			REG_WR(sc, SC_PORT(sc) ?
+			       NIG_REG_P1_HDRS_AFTER_BASIC :
+			       NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
+		} else {
+			REG_WR(sc, SC_PORT(sc) ?
+			       NIG_REG_P1_HDRS_AFTER_BASIC :
+			       NIG_REG_P0_HDRS_AFTER_BASIC,
+			       IS_MF_SD(sc) ? 7 : 6);
+		}
+
+		if (CHIP_IS_E3(sc)) {
+			REG_WR(sc, SC_PORT(sc) ?
+			       NIG_REG_LLH1_MF_MODE :
+			       NIG_REG_LLH_MF_MODE, IS_MF(sc));
+		}
+	}
+	if (!CHIP_IS_E3(sc)) {
+		REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
+	}
+
+	/* 0x2 disable mf_ov, 0x1 enable */
+	REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
+	       (IS_MF_SD(sc) ? 0x1 : 0x2));
+
+	if (!CHIP_IS_E1x(sc)) {
+		val = 0;
+		switch (sc->devinfo.mf_info.mf_mode) {
+		case MULTI_FUNCTION_SD:
+			val = 1;
+			break;
+		case MULTI_FUNCTION_SI:
+		case MULTI_FUNCTION_AFEX:
+			val = 2;
+			break;
+		}
+
+		REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
+			    NIG_REG_LLH0_CLS_TYPE), val);
+	}
+	REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
+	REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
+	REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
+
+	/* If SPIO5 is set to generate interrupts, enable it for this port */
+	val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
+	if (val & MISC_SPIO_SPIO5) {
+		uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
+				     MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
+		val = REG_RD(sc, reg_addr);
+		val |= AEU_INPUTS_ATTN_BITS_SPIO5;
+		REG_WR(sc, reg_addr, val);
+	}
+
+	return 0;
+}
+
+static uint32_t
+bcm_flr_clnup_reg_poll(struct bcm_softc *sc, uint32_t reg,
+		       uint32_t expected, uint32_t poll_count)
+{
+	uint32_t cur_cnt = poll_count;
+	uint32_t val;
+
+	while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
+		DELAY(FLR_WAIT_INTERVAL);
+	}
+
+	return val;
+}
+
+static int
+bcm_flr_clnup_poll_hw_counter(struct bcm_softc *sc, uint32_t reg,
+			      __rte_unused const char *msg, uint32_t poll_cnt)
+{
+	uint32_t val = bcm_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
+
+	if (val != 0) {
+		PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Common routines with VF FLR cleanup */
+static uint32_t bcm_flr_clnup_poll_count(struct bcm_softc *sc)
+{
+	/* adjust polling timeout */
+	if (CHIP_REV_IS_EMUL(sc)) {
+		return (FLR_POLL_CNT * 2000);
+	}
+
+	if (CHIP_REV_IS_FPGA(sc)) {
+		return (FLR_POLL_CNT * 120);
+	}
+
+	return FLR_POLL_CNT;
+}
+
+static int bcm_poll_hw_usage_counters(struct bcm_softc *sc, uint32_t poll_cnt)
+{
+	/* wait for CFC PF usage-counter to zero (includes all the VFs) */
+	if (bcm_flr_clnup_poll_hw_counter(sc,
+					  CFC_REG_NUM_LCIDS_INSIDE_PF,
+					  "CFC PF usage counter timed out",
+					  poll_cnt)) {
+		return -1;
+	}
+
+	/* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
+	if (bcm_flr_clnup_poll_hw_counter(sc,
+					  DORQ_REG_PF_USAGE_CNT,
+					  "DQ PF usage counter timed out",
+					  poll_cnt)) {
+		return -1;
+	}
+
+	/* Wait for QM PF usage-counter to zero (until DQ cleanup) */
+	if (bcm_flr_clnup_poll_hw_counter(sc,
+					  QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
+					  "QM PF usage counter timed out",
+					  poll_cnt)) {
+		return -1;
+	}
+
+	/* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
+	if (bcm_flr_clnup_poll_hw_counter(sc,
+					  TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
+					  "Timers VNIC usage counter timed out",
+					  poll_cnt)) {
+		return -1;
+	}
+
+	if (bcm_flr_clnup_poll_hw_counter(sc,
+					  TM_REG_LIN0_NUM_SCANS +
+					  4 * SC_PORT(sc),
+					  "Timers NUM_SCANS usage counter timed out",
+					  poll_cnt)) {
+		return -1;
+	}
+
+	/* Wait DMAE PF usage counter to zero */
+	if (bcm_flr_clnup_poll_hw_counter(sc,
+					  dmae_reg_go_c[INIT_DMAE_C(sc)],
+					  "DMAE dommand register timed out",
+					  poll_cnt)) {
+		return -1;
+	}
+
+	return 0;
+}
+
+#define OP_GEN_PARAM(param)                                            \
+	(((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
+#define OP_GEN_TYPE(type)                                           \
+	(((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
+#define OP_GEN_AGG_VECT(index)                                             \
+	(((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
+
+static int
+bcm_send_final_clnup(struct bcm_softc *sc, uint8_t clnup_func,
+		     uint32_t poll_cnt)
+{
+	uint32_t op_gen_command = 0;
+	uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
+			      CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
+	int ret = 0;
+
+	if (REG_RD(sc, comp_addr)) {
+		PMD_DRV_LOG(NOTICE,
+			    "Cleanup complete was not 0 before sending");
+		return -1;
+	}
+
+	op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
+	op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
+	op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
+	op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
+
+	REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
+
+	if (bcm_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
+		PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
+		PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
+			    (REG_RD(sc, comp_addr)));
+		rte_panic("FLR cleanup failed");
+		return -1;
+	}
+
+	/* Zero completion for nxt FLR */
+	REG_WR(sc, comp_addr, 0);
+
+	return ret;
+}
+
+static void
+bcm_pbf_pN_buf_flushed(struct bcm_softc *sc, struct pbf_pN_buf_regs *regs,
+		       uint32_t poll_count)
+{
+	uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
+	uint32_t cur_cnt = poll_count;
+
+	crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
+	crd = crd_start = REG_RD(sc, regs->crd);
+	init_crd = REG_RD(sc, regs->init_crd);
+
+	while ((crd != init_crd) &&
+	       ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
+		(init_crd - crd_start))) {
+		if (cur_cnt--) {
+			DELAY(FLR_WAIT_INTERVAL);
+			crd = REG_RD(sc, regs->crd);
+			crd_freed = REG_RD(sc, regs->crd_freed);
+		} else {
+			break;
+		}
+	}
+}
+
+static void
+bcm_pbf_pN_cmd_flushed(struct bcm_softc *sc, struct pbf_pN_cmd_regs *regs,
+		       uint32_t poll_count)
+{
+	uint32_t occup, to_free, freed, freed_start;
+	uint32_t cur_cnt = poll_count;
+
+	occup = to_free = REG_RD(sc, regs->lines_occup);
+	freed = freed_start = REG_RD(sc, regs->lines_freed);
+
+	while (occup &&
+	       ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
+		to_free)) {
+		if (cur_cnt--) {
+			DELAY(FLR_WAIT_INTERVAL);
+			occup = REG_RD(sc, regs->lines_occup);
+			freed = REG_RD(sc, regs->lines_freed);
+		} else {
+			break;
+		}
+	}
+}
+
+static void bcm_tx_hw_flushed(struct bcm_softc *sc, uint32_t poll_count)
+{
+	struct pbf_pN_cmd_regs cmd_regs[] = {
+		{0, (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
+		 (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
+		{1, (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
+		 (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
+		{4, (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
+		 (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
+		 PBF_REG_P4_TQ_LINES_FREED_CNT}
+	};
+
+	struct pbf_pN_buf_regs buf_regs[] = {
+		{0, (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
+		 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
+		 (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
+		 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
+		{1, (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
+		 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
+		 (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
+		 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
+		{4, (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
+		 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
+		 (CHIP_IS_E3B0(sc)) ?
+		 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
+		 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
+	};
+
+	uint32_t i;
+
+	/* Verify the command queues are flushed P0, P1, P4 */
+	for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
+		bcm_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
+	}
+
+	/* Verify the transmission buffers are flushed P0, P1, P4 */
+	for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
+		bcm_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
+	}
+}
+
+static void bcm_hw_enable_status(struct bcm_softc *sc)
+{
+	__rte_unused uint32_t val;
+
+	val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
+	PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
+
+	val = REG_RD(sc, PBF_REG_DISABLE_PF);
+	PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
+
+	val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
+	PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
+
+	val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
+	PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
+
+	val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
+	PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
+
+	val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
+	PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
+
+	val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
+	PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
+
+	val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
+	PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
+		    val);
+}
+
+/**
+ *	bcm_pf_flr_clnup
+ *	a. re-enable target read on the PF
+ *	b. poll cfc per function usgae counter
+ *	c. poll the qm perfunction usage counter
+ *	d. poll the tm per function usage counter
+ *	e. poll the tm per function scan-done indication
+ *	f. clear the dmae channel associated wit hthe PF
+ *	g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
+ *	h. call the common flr cleanup code with -1 (pf indication)
+ */
+static int bcm_pf_flr_clnup(struct bcm_softc *sc)
+{
+	uint32_t poll_cnt = bcm_flr_clnup_poll_count(sc);
+
+	/* Re-enable PF target read access */
+	REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
+
+	/* Poll HW usage counters */
+	if (bcm_poll_hw_usage_counters(sc, poll_cnt)) {
+		return -1;
+	}
+
+	/* Zero the igu 'trailing edge' and 'leading edge' */
+
+	/* Send the FW cleanup command */
+	if (bcm_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
+		return -1;
+	}
+
+	/* ATC cleanup */
+
+	/* Verify TX hw is flushed */
+	bcm_tx_hw_flushed(sc, poll_cnt);
+
+	/* Wait 100ms (not adjusted according to platform) */
+	DELAY(100000);
+
+	/* Verify no pending pci transactions */
+	if (bcm_is_pcie_pending(sc)) {
+		PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
+	}
+
+	/* Debug */
+	bcm_hw_enable_status(sc);
+
+	/*
+	 * Master enable - Due to WB DMAE writes performed before this
+	 * register is re-initialized as part of the regular function init
+	 */
+	REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
+
+	return 0;
+}
+
+static int bcm_init_hw_func(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	int func = SC_FUNC(sc);
+	int init_phase = PHASE_PF0 + func;
+	struct ecore_ilt *ilt = sc->ilt;
+	uint16_t cdu_ilt_start;
+	uint32_t addr, val;
+	uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
+	int main_mem_width, rc;
+	uint32_t i;
+
+	PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
+
+	/* FLR cleanup */
+	if (!CHIP_IS_E1x(sc)) {
+		rc = bcm_pf_flr_clnup(sc);
+		if (rc) {
+			PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
+			return rc;
+		}
+	}
+
+	/* set MSI reconfigure capability */
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
+		val = REG_RD(sc, addr);
+		val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
+		REG_WR(sc, addr, val);
+	}
+
+	ecore_init_block(sc, BLOCK_PXP, init_phase);
+	ecore_init_block(sc, BLOCK_PXP2, init_phase);
+
+	ilt = sc->ilt;
+	cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
+
+	for (i = 0; i < L2_ILT_LINES(sc); i++) {
+		ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
+		ilt->lines[cdu_ilt_start + i].page_mapping =
+		    (phys_addr_t) ((void *)sc->context[i].vcxt_dma.paddr);
+		ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
+	}
+	ecore_ilt_init_op(sc, INITOP_SET);
+
+	REG_WR(sc, PRS_REG_NIC_MODE, 1);
+
+	if (!CHIP_IS_E1x(sc)) {
+		uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
+
+/* Turn on a single ISR mode in IGU if driver is going to use
+ * INT#x or MSI
+ */
+		if ((sc->interrupt_mode != INTR_MODE_MSIX)
+		    || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
+			pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
+		}
+
+/*
+ * Timers workaround bug: function init part.
+ * Need to wait 20msec after initializing ILT,
+ * needed to make sure there are no requests in
+ * one of the PXP internal queues with "old" ILT addresses
+ */
+		DELAY(20000);
+
+/*
+ * Master enable - Due to WB DMAE writes performed before this
+ * register is re-initialized as part of the regular function
+ * init
+ */
+		REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
+/* Enable the function in IGU */
+		REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
+	}
+
+	sc->dmae_ready = 1;
+
+	ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
+
+	if (!CHIP_IS_E1x(sc))
+		REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
+
+	ecore_init_block(sc, BLOCK_ATC, init_phase);
+	ecore_init_block(sc, BLOCK_DMAE, init_phase);
+	ecore_init_block(sc, BLOCK_NIG, init_phase);
+	ecore_init_block(sc, BLOCK_SRC, init_phase);
+	ecore_init_block(sc, BLOCK_MISC, init_phase);
+	ecore_init_block(sc, BLOCK_TCM, init_phase);
+	ecore_init_block(sc, BLOCK_UCM, init_phase);
+	ecore_init_block(sc, BLOCK_CCM, init_phase);
+	ecore_init_block(sc, BLOCK_XCM, init_phase);
+	ecore_init_block(sc, BLOCK_TSEM, init_phase);
+	ecore_init_block(sc, BLOCK_USEM, init_phase);
+	ecore_init_block(sc, BLOCK_CSEM, init_phase);
+	ecore_init_block(sc, BLOCK_XSEM, init_phase);
+
+	if (!CHIP_IS_E1x(sc))
+		REG_WR(sc, QM_REG_PF_EN, 1);
+
+	if (!CHIP_IS_E1x(sc)) {
+		REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BCM_MAX_NUM_OF_VFS + func);
+		REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BCM_MAX_NUM_OF_VFS + func);
+		REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BCM_MAX_NUM_OF_VFS + func);
+		REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BCM_MAX_NUM_OF_VFS + func);
+	}
+	ecore_init_block(sc, BLOCK_QM, init_phase);
+
+	ecore_init_block(sc, BLOCK_TM, init_phase);
+	ecore_init_block(sc, BLOCK_DORQ, init_phase);
+
+	ecore_init_block(sc, BLOCK_BRB1, init_phase);
+	ecore_init_block(sc, BLOCK_PRS, init_phase);
+	ecore_init_block(sc, BLOCK_TSDM, init_phase);
+	ecore_init_block(sc, BLOCK_CSDM, init_phase);
+	ecore_init_block(sc, BLOCK_USDM, init_phase);
+	ecore_init_block(sc, BLOCK_XSDM, init_phase);
+	ecore_init_block(sc, BLOCK_UPB, init_phase);
+	ecore_init_block(sc, BLOCK_XPB, init_phase);
+	ecore_init_block(sc, BLOCK_PBF, init_phase);
+	if (!CHIP_IS_E1x(sc))
+		REG_WR(sc, PBF_REG_DISABLE_PF, 0);
+
+	ecore_init_block(sc, BLOCK_CDU, init_phase);
+
+	ecore_init_block(sc, BLOCK_CFC, init_phase);
+
+	if (!CHIP_IS_E1x(sc))
+		REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
+
+	if (IS_MF(sc)) {
+		REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
+		REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
+	}
+
+	ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
+
+	/* HC init per function */
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		if (CHIP_IS_E1H(sc)) {
+			REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
+
+			REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
+			REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
+		}
+		ecore_init_block(sc, BLOCK_HC, init_phase);
+
+	} else {
+		uint32_t num_segs, sb_idx, prod_offset;
+
+		REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
+
+		if (!CHIP_IS_E1x(sc)) {
+			REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
+			REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
+		}
+
+		ecore_init_block(sc, BLOCK_IGU, init_phase);
+
+		if (!CHIP_IS_E1x(sc)) {
+			int dsb_idx = 0;
+	/**
+	 * Producer memory:
+	 * E2 mode: address 0-135 match to the mapping memory;
+	 * 136 - PF0 default prod; 137 - PF1 default prod;
+	 * 138 - PF2 default prod; 139 - PF3 default prod;
+	 * 140 - PF0 attn prod;    141 - PF1 attn prod;
+	 * 142 - PF2 attn prod;    143 - PF3 attn prod;
+	 * 144-147 reserved.
+	 *
+	 * E1.5 mode - In backward compatible mode;
+	 * for non default SB; each even line in the memory
+	 * holds the U producer and each odd line hold
+	 * the C producer. The first 128 producers are for
+	 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
+	 * producers are for the DSB for each PF.
+	 * Each PF has five segments: (the order inside each
+	 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
+	 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
+	 * 144-147 attn prods;
+	 */
+			/* non-default-status-blocks */
+			num_segs = CHIP_INT_MODE_IS_BC(sc) ?
+			    IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
+			for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
+				prod_offset = (sc->igu_base_sb + sb_idx) *
+				    num_segs;
+
+				for (i = 0; i < num_segs; i++) {
+					addr = IGU_REG_PROD_CONS_MEMORY +
+					    (prod_offset + i) * 4;
+					REG_WR(sc, addr, 0);
+				}
+				/* send consumer update with value 0 */
+				bcm_ack_sb(sc, sc->igu_base_sb + sb_idx,
+					   USTORM_ID, 0, IGU_INT_NOP, 1);
+				bcm_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
+			}
+
+			/* default-status-blocks */
+			num_segs = CHIP_INT_MODE_IS_BC(sc) ?
+			    IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
+
+			if (CHIP_IS_MODE_4_PORT(sc))
+				dsb_idx = SC_FUNC(sc);
+			else
+				dsb_idx = SC_VN(sc);
+
+			prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
+				       IGU_BC_BASE_DSB_PROD + dsb_idx :
+				       IGU_NORM_BASE_DSB_PROD + dsb_idx);
+
+			/*
+			 * igu prods come in chunks of E1HVN_MAX (4) -
+			 * does not matters what is the current chip mode
+			 */
+			for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
+				addr = IGU_REG_PROD_CONS_MEMORY +
+				    (prod_offset + i) * 4;
+				REG_WR(sc, addr, 0);
+			}
+			/* send consumer update with 0 */
+			if (CHIP_INT_MODE_IS_BC(sc)) {
+				bcm_ack_sb(sc, sc->igu_dsb_id,
+					   USTORM_ID, 0, IGU_INT_NOP, 1);
+				bcm_ack_sb(sc, sc->igu_dsb_id,
+					   CSTORM_ID, 0, IGU_INT_NOP, 1);
+				bcm_ack_sb(sc, sc->igu_dsb_id,
+					   XSTORM_ID, 0, IGU_INT_NOP, 1);
+				bcm_ack_sb(sc, sc->igu_dsb_id,
+					   TSTORM_ID, 0, IGU_INT_NOP, 1);
+				bcm_ack_sb(sc, sc->igu_dsb_id,
+					   ATTENTION_ID, 0, IGU_INT_NOP, 1);
+			} else {
+				bcm_ack_sb(sc, sc->igu_dsb_id,
+					   USTORM_ID, 0, IGU_INT_NOP, 1);
+				bcm_ack_sb(sc, sc->igu_dsb_id,
+					   ATTENTION_ID, 0, IGU_INT_NOP, 1);
+			}
+			bcm_igu_clear_sb(sc, sc->igu_dsb_id);
+
+			/* !!! these should become driver const once
+			   rf-tool supports split-68 const */
+			REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
+			REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
+			REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
+			REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
+			REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
+			REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
+		}
+	}
+
+	/* Reset PCIE errors for debug */
+	REG_WR(sc, 0x2114, 0xffffffff);
+	REG_WR(sc, 0x2120, 0xffffffff);
+
+	if (CHIP_IS_E1x(sc)) {
+		main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;	/*dwords */
+		main_mem_base = HC_REG_MAIN_MEMORY +
+		    SC_PORT(sc) * (main_mem_size * 4);
+		main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
+		main_mem_width = 8;
+
+		val = REG_RD(sc, main_mem_prty_clr);
+		if (val) {
+			PMD_DRV_LOG(DEBUG,
+				    "Parity errors in HC block during function init (0x%x)!",
+				    val);
+		}
+
+/* Clear "false" parity errors in MSI-X table */
+		for (i = main_mem_base;
+		     i < main_mem_base + main_mem_size * 4;
+		     i += main_mem_width) {
+			bcm_read_dmae(sc, i, main_mem_width / 4);
+			bcm_write_dmae(sc, BCM_SP_MAPPING(sc, wb_data),
+				       i, main_mem_width / 4);
+		}
+/* Clear HC parity attention */
+		REG_RD(sc, main_mem_prty_clr);
+	}
+
+	/* Enable STORMs SP logging */
+	REG_WR8(sc, BAR_USTRORM_INTMEM +
+		USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
+	REG_WR8(sc, BAR_TSTRORM_INTMEM +
+		TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
+	REG_WR8(sc, BAR_CSTRORM_INTMEM +
+		CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
+	REG_WR8(sc, BAR_XSTRORM_INTMEM +
+		XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
+
+	elink_phy_probe(&sc->link_params);
+
+	return 0;
+}
+
+static void bcm_link_reset(struct bcm_softc *sc)
+{
+	if (!BCM_NOMCP(sc)) {
+		elink_lfa_reset(&sc->link_params, &sc->link_vars);
+	} else {
+		if (!CHIP_REV_IS_SLOW(sc)) {
+			PMD_DRV_LOG(WARN,
+				    "Bootcode is missing - cannot reset link");
+		}
+	}
+}
+
+static void bcm_reset_port(struct bcm_softc *sc)
+{
+	int port = SC_PORT(sc);
+	uint32_t val;
+
+	/* reset physical Link */
+	bcm_link_reset(sc);
+
+	REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
+
+	/* Do not rcv packets to BRB */
+	REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
+	/* Do not direct rcv packets that are not for MCP to the BRB */
+	REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
+		    NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
+
+	/* Configure AEU */
+	REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
+
+	DELAY(100000);
+
+	/* Check for BRB port occupancy */
+	val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
+	if (val) {
+		PMD_DRV_LOG(DEBUG,
+			    "BRB1 is not empty, %d blocks are occupied", val);
+	}
+}
+
+static void bcm_ilt_wr(struct bcm_softc *sc, uint32_t index, phys_addr_t addr)
+{
+	int reg;
+	uint32_t wb_write[2];
+
+	reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
+
+	wb_write[0] = ONCHIP_ADDR1(addr);
+	wb_write[1] = ONCHIP_ADDR2(addr);
+	REG_WR_DMAE(sc, reg, wb_write, 2);
+}
+
+static void bcm_clear_func_ilt(struct bcm_softc *sc, uint32_t func)
+{
+	uint32_t i, base = FUNC_ILT_BASE(func);
+	for (i = base; i < base + ILT_PER_FUNC; i++) {
+		bcm_ilt_wr(sc, i, 0);
+	}
+}
+
+static void bcm_reset_func(struct bcm_softc *sc)
+{
+	struct bcm_fastpath *fp;
+	int port = SC_PORT(sc);
+	int func = SC_FUNC(sc);
+	int i;
+
+	/* Disable the function in the FW */
+	REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
+	REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
+	REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
+	REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
+
+	/* FP SBs */
+	FOR_EACH_ETH_QUEUE(sc, i) {
+		fp = &sc->fp[i];
+		REG_WR8(sc, BAR_CSTRORM_INTMEM +
+			CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
+			SB_DISABLED);
+	}
+
+	/* SP SB */
+	REG_WR8(sc, BAR_CSTRORM_INTMEM +
+		CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
+
+	for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
+		REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
+		       0);
+	}
+
+	/* Configure IGU */
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
+		REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
+	} else {
+		REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
+		REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
+	}
+
+	if (CNIC_LOADED(sc)) {
+/* Disable Timer scan */
+		REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
+/*
+ * Wait for at least 10ms and up to 2 second for the timers
+ * scan to complete
+ */
+		for (i = 0; i < 200; i++) {
+			DELAY(10000);
+			if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
+				break;
+		}
+	}
+
+	/* Clear ILT */
+	bcm_clear_func_ilt(sc, func);
+
+	/*
+	 * Timers workaround bug for E2: if this is vnic-3,
+	 * we need to set the entire ilt range for this timers.
+	 */
+	if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
+		struct ilt_client_info ilt_cli;
+/* use dummy TM client */
+		memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
+		ilt_cli.start = 0;
+		ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
+		ilt_cli.client_num = ILT_CLIENT_TM;
+
+		ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
+	}
+
+	/* this assumes that reset_port() called before reset_func() */
+	if (!CHIP_IS_E1x(sc)) {
+		bcm_pf_disable(sc);
+	}
+
+	sc->dmae_ready = 0;
+}
+
+static void bcm_release_firmware(struct bcm_softc *sc)
+{
+	rte_free(sc->init_ops);
+	rte_free(sc->init_ops_offsets);
+	rte_free(sc->init_data);
+	rte_free(sc->iro_array);
+}
+
+static int bcm_init_firmware(struct bcm_softc *sc)
+{
+	uint32_t len, i;
+	uint8_t *p = sc->firmware;
+	uint32_t off[24];
+
+	for (i = 0; i < 24; ++i)
+		off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
+
+	len = off[0];
+	sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
+	if (!sc->init_ops)
+		goto alloc_failed;
+	bcm_data_to_init_ops(p + off[1], sc->init_ops, len);
+
+	len = off[2];
+	sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
+	if (!sc->init_ops_offsets)
+		goto alloc_failed;
+	bcm_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
+
+	len = off[4];
+	sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
+	if (!sc->init_data)
+		goto alloc_failed;
+	bcm_data_to_init_data(p + off[5], sc->init_data, len);
+
+	sc->tsem_int_table_data = p + off[7];
+	sc->tsem_pram_data = p + off[9];
+	sc->usem_int_table_data = p + off[11];
+	sc->usem_pram_data = p + off[13];
+	sc->csem_int_table_data = p + off[15];
+	sc->csem_pram_data = p + off[17];
+	sc->xsem_int_table_data = p + off[19];
+	sc->xsem_pram_data = p + off[21];
+
+	len = off[22];
+	sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
+	if (!sc->iro_array)
+		goto alloc_failed;
+	bcm_data_to_iro_array(p + off[23], sc->iro_array, len);
+
+	return 0;
+
+alloc_failed:
+	bcm_release_firmware(sc);
+	return -1;
+}
+
+static int cut_gzip_prefix(const uint8_t * zbuf, int len)
+{
+#define MIN_PREFIX_SIZE (10)
+
+	int n = MIN_PREFIX_SIZE;
+	uint16_t xlen;
+
+	if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
+	    len <= MIN_PREFIX_SIZE) {
+		return -1;
+	}
+
+	/* optional extra fields are present */
+	if (zbuf[3] & 0x4) {
+		xlen = zbuf[13];
+		xlen <<= 8;
+		xlen += zbuf[12];
+
+		n += xlen;
+	}
+	/* file name is present */
+	if (zbuf[3] & 0x8) {
+		while ((zbuf[n++] != 0) && (n < len)) ;
+	}
+
+	return n;
+}
+
+static int ecore_gunzip(struct bcm_softc *sc, const uint8_t * zbuf, int len)
+{
+	int ret;
+	int data_begin = cut_gzip_prefix(zbuf, len);
+
+	PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
+
+	if (data_begin <= 0) {
+		PMD_DRV_LOG(NOTICE, "bad gzip prefix");
+		return -1;
+	}
+
+	memset(&zlib_stream, 0, sizeof(zlib_stream));
+	zlib_stream.next_in = zbuf + data_begin;
+	zlib_stream.avail_in = len - data_begin;
+	zlib_stream.next_out = sc->gz_buf;
+	zlib_stream.avail_out = FW_BUF_SIZE;
+
+	ret = inflateInit2(&zlib_stream, -MAX_WBITS);
+	if (ret != Z_OK) {
+		PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
+		return ret;
+	}
+
+	ret = inflate(&zlib_stream, Z_FINISH);
+	if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
+		PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
+			    zlib_stream.msg);
+	}
+
+	sc->gz_outlen = zlib_stream.total_out;
+	if (sc->gz_outlen & 0x3) {
+		PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
+			    sc->gz_outlen);
+	}
+	sc->gz_outlen >>= 2;
+
+	inflateEnd(&zlib_stream);
+
+	if (ret == Z_STREAM_END)
+		return 0;
+
+	return ret;
+}
+
+static void
+ecore_write_dmae_phys_len(struct bcm_softc *sc, phys_addr_t phys_addr,
+			  uint32_t addr, uint32_t len)
+{
+	bcm_write_dmae_phys_len(sc, phys_addr, addr, len);
+}
+
+void
+ecore_storm_memset_struct(struct bcm_softc *sc, uint32_t addr, size_t size,
+			  uint32_t * data)
+{
+	uint8_t i;
+	for (i = 0; i < size / 4; i++) {
+		REG_WR(sc, addr + (i * 4), data[i]);
+	}
+}
+
+static const char *get_ext_phy_type(uint32_t ext_phy_type)
+{
+	uint32_t phy_type_idx = ext_phy_type >> 8;
+	static const char *types[] =
+	    { "DIRECT", "BCM-8071", "BCM-8072", "BCM-8073",
+		"BCM-8705", "BCM-8706", "BCM-8726", "BCM-8481", "SFX-7101",
+		"BCM-8727",
+		"BCM-8727-NOC", "BCM-84823", "NOT_CONN", "FAILURE"
+	};
+
+	if (phy_type_idx < 12)
+		return types[phy_type_idx];
+	else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
+		return types[12];
+	else
+		return types[13];
+}
+
+static const char *get_state(uint32_t state)
+{
+	uint32_t state_idx = state >> 12;
+	static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
+		"OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
+		"CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
+		"UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
+		"UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
+	};
+
+	if (state_idx <= 0xF)
+		return states[state_idx];
+	else
+		return states[0x10];
+}
+
+static const char *get_recovery_state(uint32_t state)
+{
+	static const char *states[] = { "NONE", "DONE", "INIT",
+		"WAIT", "FAILED", "NIC_LOADING"
+	};
+	return states[state];
+}
+
+static const char *get_rx_mode(uint32_t mode)
+{
+	static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
+		"PROMISC", "MAX_MULTICAST", "ERROR"
+	};
+
+	if (mode < 0x4)
+		return modes[mode];
+	else if (BCM_MAX_MULTICAST == mode)
+		return modes[4];
+	else
+		return modes[5];
+}
+
+#define BCM_INFO_STR_MAX 256
+static const char *get_bcm_flags(uint32_t flags)
+{
+	int i;
+	static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
+		"NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
+		"USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
+		"SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
+	};
+	static char flag_str[BCM_INFO_STR_MAX];
+	memset(flag_str, 0, BCM_INFO_STR_MAX);
+
+	for (i = 0; i < 5; i++)
+		if (flags & (1 << i)) {
+			strcat(flag_str, flag[i]);
+			flags ^= (1 << i);
+		}
+	if (flags) {
+		static char unknown[BCM_INFO_STR_MAX];
+		snprintf(unknown, 32, "Unknown flag mask %x", flags);
+		strcat(flag_str, unknown);
+	}
+	return flag_str;
+}
+
+/*
+ * Prints useful adapter info.
+ */
+void bcm_print_adapter_info(struct bcm_softc *sc)
+{
+	int i = 0;
+	__rte_unused uint32_t ext_phy_type;
+
+	PMD_INIT_FUNC_TRACE();
+	if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
+		ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
+							      sc->
+							      devinfo.shmem_base
+							      + offsetof(struct
+									 shmem_region,
+									 dev_info.port_hw_config
+									 [0].external_phy_config)));
+	else
+		ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
+								sc->
+								devinfo.shmem_base
+								+
+								offsetof(struct
+									 shmem_region,
+									 dev_info.port_hw_config
+									 [0].external_phy_config)));
+
+	PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
+	/* Hardware chip info. */
+	PMD_INIT_LOG(DEBUG, "%10s : %#08x\n", "ASIC", sc->devinfo.chip_id);
+	PMD_INIT_LOG(DEBUG, "%10s : %c%d\n", "Rev", (CHIP_REV(sc) >> 12) + 'A',
+		     (CHIP_METAL(sc) >> 4));
+
+	/* Bus info. */
+	PMD_INIT_LOG(DEBUG, "%10s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
+	switch (sc->devinfo.pcie_link_speed) {
+	case 1:
+		PMD_INIT_LOG(DEBUG, "2.5 Gbps\n");
+		break;
+	case 2:
+		PMD_INIT_LOG(DEBUG, "5 Gbps\n");
+		break;
+	case 4:
+		PMD_INIT_LOG(DEBUG, "8 Gbps\n");
+		break;
+	default:
+		PMD_INIT_LOG(DEBUG, "Unknown link speed\n");
+	}
+
+	/* Device features. */
+	PMD_INIT_LOG(DEBUG, "%10s : ", "Flags");
+
+	/* Miscellaneous flags. */
+	if (sc->devinfo.pcie_cap_flags & BCM_MSI_CAPABLE_FLAG) {
+		PMD_INIT_LOG(DEBUG, "MSI");
+		i++;
+	}
+
+	if (sc->devinfo.pcie_cap_flags & BCM_MSIX_CAPABLE_FLAG) {
+		if (i > 0)
+			PMD_INIT_LOG(DEBUG, "|");
+		PMD_INIT_LOG(DEBUG, "MSI-X");
+		i++;
+	}
+
+	PMD_INIT_LOG(DEBUG, "\n");
+
+	if (IS_PF(sc)) {
+		PMD_INIT_LOG(DEBUG, "\n%10s : ", "Queues");
+		switch (sc->sp->rss_rdata.rss_mode) {
+		case ETH_RSS_MODE_DISABLED:
+			PMD_INIT_LOG(DEBUG, "None\n");
+			break;
+		case ETH_RSS_MODE_REGULAR:
+			PMD_INIT_LOG(DEBUG, "RSS : %d\n", sc->num_queues);
+			break;
+		default:
+			PMD_INIT_LOG(DEBUG, "Unknown\n");
+			break;
+		}
+	}
+
+	/* Firmware versions and device features. */
+	PMD_INIT_LOG(DEBUG, "%10s : %d.%d.%d\n%10s : %s\n",
+		     "Firmware",
+		     BCM_5710_FW_MAJOR_VERSION,
+		     BCM_5710_FW_MINOR_VERSION,
+		     BCM_5710_FW_REVISION_VERSION,
+		     "Bootcode", sc->devinfo.bc_ver_str);
+
+	PMD_INIT_LOG(DEBUG, "===================================\n");
+	PMD_INIT_LOG(DEBUG, "%10s : %u\n", "Bcm Func", sc->pcie_func);
+	PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Bcm Flags", get_bcm_flags(sc->flags));
+	PMD_INIT_LOG(DEBUG, "%10s : %s\n", "DMAE Is",
+		     (sc->dmae_ready ? "Ready" : "Not Ready"));
+	PMD_INIT_LOG(DEBUG, "%10s : %s\n", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
+	PMD_INIT_LOG(DEBUG, "%10s : %s\n", "MF", (IS_MF(sc) ? "YES" : "NO"));
+	PMD_INIT_LOG(DEBUG, "%10s : %u\n", "MTU", sc->mtu);
+	PMD_INIT_LOG(DEBUG, "%10s : %s\n", "PHY Type", get_ext_phy_type(ext_phy_type));
+	PMD_INIT_LOG(DEBUG, "%10s : ", "MAC Addr");
+	for (i = 0; i < 6; i++)
+		PMD_INIT_LOG(DEBUG, "%x%s", sc->link_params.mac_addr[i],
+			     i < 5 ? ":" : "\n");
+	PMD_INIT_LOG(DEBUG, "%10s : %s\n", "RX Mode", get_rx_mode(sc->rx_mode));
+	PMD_INIT_LOG(DEBUG, "%10s : %s\n", "State", get_state(sc->state));
+	if (sc->recovery_state)
+		PMD_INIT_LOG(DEBUG, "%10s : %s\n", "Recovery",
+			     get_recovery_state(sc->recovery_state));
+	PMD_INIT_LOG(DEBUG, "%10s : CQ = %lx,  EQ = %lx\n", "SPQ Left",
+		     sc->cq_spq_left, sc->eq_spq_left);
+	PMD_INIT_LOG(DEBUG, "%10s : %x\n", "Switch", sc->link_params.switch_cfg);
+	PMD_INIT_LOG(DEBUG, "===================================\n\n");
+}
diff --git a/lib/librte_pmd_bcm/bcm.h b/lib/librte_pmd_bcm/bcm.h
new file mode 100644
index 0000000..4e07dc9
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm.h
@@ -0,0 +1,1998 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BCM_H__
+#define __BCM_H__
+
+#include "bcm_ethdev.h"
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN
+#endif
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN
+#endif
+#undef BIG_ENDIAN
+#undef __BIG_ENDIAN
+#else /* _BIG_ENDIAN */
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN
+#endif
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN
+#endif
+#undef LITTLE_ENDIAN
+#undef __LITTLE_ENDIAN
+#endif
+
+#include "ecore_mfw_req.h"
+#include "ecore_fw_defs.h"
+#include "ecore_hsi.h"
+#include "ecore_reg.h"
+#include "bcm_stats.h"
+#include "bcm_vfpf.h"
+
+#include "elink.h"
+
+#include <linux/pci_regs.h>
+
+#define PCIY_PMG                       PCI_CAP_ID_PM
+#define PCIY_MSI                       PCI_CAP_ID_MSI
+#define PCIY_EXPRESS                   PCI_CAP_ID_EXP
+#define PCIY_MSIX                      PCI_CAP_ID_MSIX
+#define PCIR_EXPRESS_DEVICE_STA        PCI_EXP_TYPE_RC_EC
+#define PCIM_EXP_STA_TRANSACTION_PND   PCI_EXP_DEVSTA_TRPND
+#define PCIR_EXPRESS_LINK_STA          PCI_EXP_LNKSTA
+#define PCIM_LINK_STA_WIDTH            PCI_EXP_LNKSTA_NLW
+#define PCIM_LINK_STA_SPEED            PCI_EXP_LNKSTA_CLS
+#define PCIR_EXPRESS_DEVICE_CTL        PCI_EXP_DEVCTL
+#define PCIM_EXP_CTL_MAX_PAYLOAD       PCI_EXP_DEVCTL_PAYLOAD
+#define PCIM_EXP_CTL_MAX_READ_REQUEST  PCI_EXP_DEVCTL_READRQ
+#define PCIR_POWER_STATUS              PCI_PM_CTRL
+#define PCIM_PSTAT_DMASK               PCI_PM_CTRL_STATE_MASK
+#define PCIM_PSTAT_PME                 PCI_PM_CTRL_PME_STATUS
+#define PCIM_PSTAT_D3                  0x3
+#define PCIM_PSTAT_PMEENABLE           PCI_PM_CTRL_PME_ENABLE
+#define PCIR_MSIX_CTRL                 PCI_MSIX_FLAGS
+#define PCIM_MSIXCTRL_TABLE_SIZE       PCI_MSIX_FLAGS_QSIZE
+
+#define IFM_10G_CX4                    20 /* 10GBase CX4 copper */
+#define IFM_10G_TWINAX                 22 /* 10GBase Twinax copper */
+#define IFM_10G_T                      26 /* 10GBase-T - RJ45 */
+
+#define PCIR_EXPRESS_DEVICE_STA        PCI_EXP_TYPE_RC_EC
+#define PCIM_EXP_STA_TRANSACTION_PND   PCI_EXP_DEVSTA_TRPND
+#define PCIR_EXPRESS_LINK_STA          PCI_EXP_LNKSTA
+#define PCIM_LINK_STA_WIDTH            PCI_EXP_LNKSTA_NLW
+#define PCIM_LINK_STA_SPEED            PCI_EXP_LNKSTA_CLS
+#define PCIR_EXPRESS_DEVICE_CTL        PCI_EXP_DEVCTL
+#define PCIM_EXP_CTL_MAX_PAYLOAD       PCI_EXP_DEVCTL_PAYLOAD
+#define PCIM_EXP_CTL_MAX_READ_REQUEST  PCI_EXP_DEVCTL_READRQ
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#endif
+#ifndef ARRSIZE
+#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#endif
+#ifndef DIV_ROUND_UP
+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+#endif
+#ifndef roundup
+#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+#endif
+#ifndef ilog2
+static inline
+int bcm_ilog2(int x)
+{
+	int log = 0;
+	x >>= 1;
+
+	while(x) {
+		log++;
+		x >>= 1;
+	}
+	return log;
+}
+#define ilog2(x) bcm_ilog2(x)
+#endif
+
+#include "ecore_sp.h"
+
+struct bcm_device_type
+{
+    uint16_t bcm_vid;
+    uint16_t bcm_did;
+    uint16_t bcm_svid;
+    uint16_t bcm_sdid;
+    char     *bcm_name;
+};
+
+#define RTE_MBUF_DATA_DMA_ADDR(mb) \
+	(uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
+
+#define BCM_PAGE_SHIFT       12
+#define BCM_PAGE_SIZE        (1 << BCM_PAGE_SHIFT)
+#define BCM_PAGE_MASK        (~(BCM_PAGE_SIZE - 1))
+#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
+
+#if BCM_PAGE_SIZE != 4096
+#error Page sizes other than 4KB are unsupported!
+#endif
+
+#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
+#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
+#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
+
+/* dropless fc FW/HW related params */
+#define BRB_SIZE(sc)         (CHIP_IS_E3(sc) ? 1024 : 512)
+#define MAX_AGG_QS(sc)       ETH_MAX_AGGREGATION_QUEUES_E1H_E2
+#define FW_DROP_LEVEL(sc)    (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
+#define FW_PREFETCH_CNT      16U
+#define DROPLESS_FC_HEADROOM 100
+
+#ifndef MCLSHIFT
+#define MCLSHIFT                              11
+#endif
+#define MCLBYTES                              (1 << MCLSHIFT)
+
+#if BCM_PAGE_SIZE < 2048
+#define MJUMPAGESIZE    MCLBYTES
+#elif BCM_PAGE_SIZE <= 8192
+#define MJUMPAGESIZE    BCM_PAGE_SIZE
+#else
+#define MJUMPAGESIZE    (8 * 1024)
+#endif
+#define MJUM9BYTES      (9 * 1024)
+#define MJUM16BYTES     (16 * 1024)
+
+/*
+ * Transmit Buffer Descriptor (tx_bd) definitions*
+ */
+/* NUM_TX_PAGES must be a power of 2. */
+#define TOTAL_TX_BD_PER_PAGE     (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /*  256 */
+#define USABLE_TX_BD_PER_PAGE    (TOTAL_TX_BD_PER_PAGE - 1)                      /*  255 */
+
+#define TOTAL_TX_BD(q)           (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages)         /*  512 */
+#define USABLE_TX_BD(q)          (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages)        /*  510 */
+#define MAX_TX_BD(q)             (TOTAL_TX_BD(q) - 1)                            /*  511 */
+
+#define NEXT_TX_BD(x)                                                   \
+	((((x) & USABLE_TX_BD_PER_PAGE) ==                              \
+	  (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
+
+#define TX_BD(x, q)             ((x) & MAX_TX_BD(q))
+#define TX_PAGE(x)              (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
+#define TX_IDX(x)               ((x) & USABLE_TX_BD_PER_PAGE)
+
+/*
+ * Trigger pending transmits when the number of available BDs is greater
+ * than 1/8 of the total number of usable BDs.
+ */
+#define BCM_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
+#define BCM_TX_TIMEOUT 5
+
+/*
+ * Receive Buffer Descriptor (rx_bd) definitions*
+ */
+//#define NUM_RX_PAGES            1
+#define TOTAL_RX_BD_PER_PAGE    (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))      /*  512 */
+#define USABLE_RX_BD_PER_PAGE   (TOTAL_RX_BD_PER_PAGE - 2)                      /*  510 */
+#define RX_BD_PER_PAGE_MASK     (TOTAL_RX_BD_PER_PAGE - 1)                      /*  511 */
+#define TOTAL_RX_BD(q)          (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages)         /*  512 */
+#define USABLE_RX_BD(q)         (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages)        /*  510 */
+#define MAX_RX_BD(q)            (TOTAL_RX_BD(q) - 1)                            /*  511 */
+#define RX_BD_NEXT_PAGE_DESC_CNT 2
+
+#define NEXT_RX_BD(x)                                                   \
+        ((((x) & RX_BD_PER_PAGE_MASK) ==                                \
+        (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
+
+/* x & 0x3ff */
+#define RX_BD(x, q)             ((x) & MAX_RX_BD(q))
+#define RX_PAGE(x)              (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
+#define RX_IDX(x)               ((x) & RX_BD_PER_PAGE_MASK)
+
+/*
+ * Receive Completion Queue definitions*
+ */
+//#define NUM_RCQ_PAGES           (NUM_RX_PAGES * 4)
+#define TOTAL_RCQ_ENTRIES_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))   /*  128 */
+#define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1)            /*  127 */
+#define TOTAL_RCQ_ENTRIES(q)    (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages)   /*  512 */
+#define USABLE_RCQ_ENTRIES(q)   (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages)  /*  508 */
+#define MAX_RCQ_ENTRIES(q)      (TOTAL_RCQ_ENTRIES(q) - 1)                      /*  511 */
+#define RCQ_NEXT_PAGE_DESC_CNT 1
+
+#define NEXT_RCQ_IDX(x)                                                 \
+        ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) ==                        \
+        (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
+
+#define CQE_BD_REL                                                      \
+	(sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
+
+#define RCQ_BD_PAGES(q)                                                 \
+	(q->nb_rx_pages * CQE_BD_REL)
+
+#define RCQ_ENTRY(x, q)         ((x) & MAX_RCQ_ENTRIES(q))
+#define RCQ_PAGE(x)             (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
+#define RCQ_IDX(x)              ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
+
+/*
+ * dropless fc calculations for BDs
+ * Number of BDs should be as number of buffers in BRB:
+ * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
+ * "next" elements on each page
+ */
+#define NUM_BD_REQ(sc) \
+    BRB_SIZE(sc)
+#define NUM_BD_PG_REQ(sc)                                                  \
+    ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
+#define BD_TH_LO(sc)                                \
+    (NUM_BD_REQ(sc) +                               \
+     NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
+     FW_DROP_LEVEL(sc))
+#define BD_TH_HI(sc)                      \
+    (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
+#define MIN_RX_AVAIL(sc)                           \
+    ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
+
+/*
+ * dropless fc calculations for RCQs
+ * Number of RCQs should be as number of buffers in BRB:
+ * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
+ * "next" elements on each page
+ */
+#define NUM_RCQ_REQ(sc) \
+    BRB_SIZE(sc)
+#define NUM_RCQ_PG_REQ(sc)                                              \
+    ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
+#define RCQ_TH_LO(sc)                              \
+    (NUM_RCQ_REQ(sc) +                             \
+     NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
+     FW_DROP_LEVEL(sc))
+#define RCQ_TH_HI(sc)                      \
+    (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
+
+/* Load / Unload modes */
+#define LOAD_NORMAL       0
+#define LOAD_OPEN         1
+#define LOAD_DIAG         2
+#define LOAD_LOOPBACK_EXT 3
+#define UNLOAD_NORMAL     0
+#define UNLOAD_CLOSE      1
+#define UNLOAD_RECOVERY   2
+
+/* Some constants... */
+//#define MAX_PATH_NUM       2
+//#define E2_MAX_NUM_OF_VFS  64
+//#define E1H_FUNC_MAX       8
+//#define E2_FUNC_MAX        4   /* per path */
+#define MAX_VNIC_NUM       4
+#define MAX_FUNC_NUM       8   /* common to all chips */
+//#define MAX_NDSB           HC_SB_MAX_SB_E2 /* max non-default status block */
+#define MAX_RSS_CHAINS     16 /* a constant for HW limit */
+#define MAX_MSI_VECTOR     8  /* a constant for HW limit */
+
+#define ILT_NUM_PAGE_ENTRIES 3072
+/*
+ * 57711 we use whole table since we have 8 functions.
+ * 57712 we have only 4 functions, but use same size per func, so only half
+ * of the table is used.
+ */
+#define ILT_PER_FUNC        (ILT_NUM_PAGE_ENTRIES / 8)
+#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
+/*
+ * the phys address is shifted right 12 bits and has an added
+ * 1=valid bit added to the 53rd bit
+ * then since this is a wide register(TM)
+ * we split it into two 32 bit writes
+ */
+#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
+#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
+
+/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
+#define ETH_HLEN                  14
+#define ETH_OVERHEAD              (ETH_HLEN + 8 + 8)
+#define ETH_MIN_PACKET_SIZE       60
+#define ETH_MAX_PACKET_SIZE       ETHERMTU /* 1500 */
+#define ETH_MAX_JUMBO_PACKET_SIZE 9600
+/* TCP with Timestamp Option (32) + IPv6 (40) */
+
+/* max supported alignment is 256 (8 shift) */
+#define BCM_RX_ALIGN_SHIFT 8
+/* FW uses 2 cache lines alignment for start packet and size  */
+#define BCM_FW_RX_ALIGN_START (1 << BCM_RX_ALIGN_SHIFT)
+#define BCM_FW_RX_ALIGN_END   (1 << BCM_RX_ALIGN_SHIFT)
+
+#define BCM_PXP_DRAM_ALIGN (BCM_RX_ALIGN_SHIFT - 5)
+
+struct bcm_bar {
+	void* base_addr;
+};
+
+/* Used to manage DMA allocations. */
+struct bcm_dma {
+	struct bcm_softc        *sc;
+	phys_addr_t             paddr;
+	void                    *vaddr;
+	int                     nseg;
+	char                    msg[RTE_MEMZONE_NAMESIZE - 6];
+};
+
+/* attn group wiring */
+#define MAX_DYNAMIC_ATTN_GRPS 8
+
+struct attn_route {
+    uint32_t sig[5];
+};
+
+struct iro {
+    uint32_t base;
+    uint16_t m1;
+    uint16_t m2;
+    uint16_t m3;
+    uint16_t size;
+};
+
+union bcm_host_hc_status_block {
+    /* pointer to fp status block e2 */
+    struct host_hc_status_block_e2  *e2_sb;
+    /* pointer to fp status block e1x */
+    struct host_hc_status_block_e1x *e1x_sb;
+};
+
+union bcm_db_prod {
+    struct doorbell_set_prod data;
+    uint32_t                 raw;
+};
+
+struct bcm_sw_tx_bd {
+    struct mbuf  *m;
+    uint16_t     first_bd;
+    uint8_t      flags;
+/* set on the first BD descriptor when there is a split BD */
+#define BCM_TSO_SPLIT_BD (1 << 0)
+};
+
+/*
+ * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
+ * instances of the fastpath structure when using multiple queues.
+ */
+struct bcm_fastpath {
+	/* pointer back to parent structure */
+	struct bcm_softc *sc;
+
+	/* status block */
+	struct bcm_dma                 sb_dma;
+	union bcm_host_hc_status_block status_block;
+
+	phys_addr_t tx_desc_mapping;
+
+	phys_addr_t rx_desc_mapping;
+	phys_addr_t rx_comp_mapping;
+
+	uint16_t *sb_index_values;
+	uint16_t *sb_running_index;
+	uint32_t ustorm_rx_prods_offset;
+
+	uint8_t igu_sb_id; /* status block number in HW */
+	uint8_t fw_sb_id;  /* status block number in FW */
+
+	uint32_t rx_buf_size;
+	int mbuf_alloc_size;
+
+	int state;
+#define BCM_FP_STATE_CLOSED  0x01
+#define BCM_FP_STATE_IRQ     0x02
+#define BCM_FP_STATE_OPENING 0x04
+#define BCM_FP_STATE_OPEN    0x08
+#define BCM_FP_STATE_HALTING 0x10
+#define BCM_FP_STATE_HALTED  0x20
+
+	/* reference back to this fastpath queue number */
+	uint8_t index; /* this is also the 'cid' */
+#define FP_IDX(fp) (fp->index)
+
+	/* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
+	uint8_t cl_id;
+#define FP_CL_ID(fp) (fp->cl_id)
+	uint8_t cl_qzone_id;
+
+	uint16_t fp_hc_idx;
+
+	union bcm_db_prod tx_db;
+
+	struct tstorm_per_queue_stats old_tclient;
+	struct ustorm_per_queue_stats old_uclient;
+	struct xstorm_per_queue_stats old_xclient;
+	struct bcm_eth_q_stats        eth_q_stats;
+	struct bcm_eth_q_stats_old    eth_q_stats_old;
+
+	/* Pointer to the receive consumer in the status block */
+	uint16_t *rx_cq_cons_sb;
+
+	/* Pointer to the transmit consumer in the status block */
+	uint16_t *tx_cons_sb;
+
+	/* transmit timeout until chip reset */
+	int watchdog_timer;
+
+}; /* struct bcm_fastpath */
+
+#define BCM_MAX_NUM_OF_VFS 64
+#define BCM_VF_ID_INVALID  0xFF
+
+/* maximum number of fast-path interrupt contexts */
+#define FP_SB_MAX_E1x 16
+#define FP_SB_MAX_E2  HC_SB_MAX_SB_E2
+
+union cdu_context {
+    struct eth_context eth;
+    char pad[1024];
+};
+
+/* CDU host DB constants */
+#define CDU_ILT_PAGE_SZ_HW 2
+#define CDU_ILT_PAGE_SZ    (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
+#define ILT_PAGE_CIDS      (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
+
+#define CNIC_ISCSI_CID_MAX 256
+#define CNIC_FCOE_CID_MAX  2048
+#define CNIC_CID_MAX       (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
+#define CNIC_ILT_LINES     DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
+
+#define QM_ILT_PAGE_SZ_HW  0
+#define QM_ILT_PAGE_SZ     (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
+#define QM_CID_ROUND       1024
+
+/* TM (timers) host DB constants */
+#define TM_ILT_PAGE_SZ_HW  0
+#define TM_ILT_PAGE_SZ     (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
+/*#define TM_CONN_NUM        (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
+#define TM_CONN_NUM        1024
+#define TM_ILT_SZ          (8 * TM_CONN_NUM)
+#define TM_ILT_LINES       DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
+
+/* SRC (Searcher) host DB constants */
+#define SRC_ILT_PAGE_SZ_HW 0
+#define SRC_ILT_PAGE_SZ    (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
+#define SRC_HASH_BITS      10
+#define SRC_CONN_NUM       (1 << SRC_HASH_BITS) /* 1024 */
+#define SRC_ILT_SZ         (sizeof(struct src_ent) * SRC_CONN_NUM)
+#define SRC_T2_SZ          SRC_ILT_SZ
+#define SRC_ILT_LINES      DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
+
+struct hw_context {
+    struct bcm_dma    vcxt_dma;
+    union cdu_context *vcxt;
+    //phys_addr_t        cxt_mapping;
+    size_t            size;
+};
+
+#define SM_RX_ID 0
+#define SM_TX_ID 1
+
+/* defines for multiple tx priority indices */
+#define FIRST_TX_ONLY_COS_INDEX 1
+#define FIRST_TX_COS_INDEX      0
+
+#define CID_TO_FP(cid, sc) ((cid) % BCM_NUM_NON_CNIC_QUEUES(sc))
+
+#define HC_INDEX_ETH_RX_CQ_CONS       1
+#define HC_INDEX_OOO_TX_CQ_CONS       4
+#define HC_INDEX_ETH_TX_CQ_CONS_COS0  5
+#define HC_INDEX_ETH_TX_CQ_CONS_COS1  6
+#define HC_INDEX_ETH_TX_CQ_CONS_COS2  7
+#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
+
+/* congestion management fairness mode */
+#define CMNG_FNS_NONE   0
+#define CMNG_FNS_MINMAX 1
+
+/* CMNG constants, as derived from system spec calculations */
+/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
+#define DEF_MIN_RATE 100
+/* resolution of the rate shaping timer - 400 usec */
+#define RS_PERIODIC_TIMEOUT_USEC 400
+/* number of bytes in single QM arbitration cycle -
+ * coefficient for calculating the fairness timer */
+#define QM_ARB_BYTES 160000
+/* resolution of Min algorithm 1:100 */
+#define MIN_RES 100
+/* how many bytes above threshold for the minimal credit of Min algorithm*/
+#define MIN_ABOVE_THRESH 32768
+/* fairness algorithm integration time coefficient -
+ * for calculating the actual Tfair */
+#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
+/* memory of fairness algorithm - 2 cycles */
+#define FAIR_MEM 2
+
+#define HC_SEG_ACCESS_DEF   0 /* Driver decision 0-3 */
+#define HC_SEG_ACCESS_ATTN  4
+#define HC_SEG_ACCESS_NORM  0 /* Driver decision 0-1 */
+
+/*
+ * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
+ * control by the number of fast-path status blocks supported by the
+ * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
+ * status block represents an independent interrupts context that can
+ * serve a regular L2 networking queue. However special L2 queues such
+ * as the FCoE queue do not require a FP-SB and other components like
+ * the CNIC may consume FP-SB reducing the number of possible L2 queues
+ *
+ * If the maximum number of FP-SB available is X then:
+ * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
+ *    regular L2 queues is Y=X-1
+ * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
+ * c. If the FCoE L2 queue is supported the actual number of L2 queues
+ *    is Y+1
+ * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
+ *    slow-path interrupts) or Y+2 if CNIC is supported (one additional
+ *    FP interrupt context for the CNIC).
+ * e. The number of HW context (CID count) is always X or X+1 if FCoE
+ *    L2 queue is supported. the cid for the FCoE L2 queue is always X.
+ *
+ * So this is quite simple for now as no ULPs are supported yet. :-)
+ */
+#define BCM_NUM_QUEUES(sc)          ((sc)->num_queues)
+#define BCM_NUM_ETH_QUEUES(sc)      BCM_NUM_QUEUES(sc)
+#define BCM_NUM_NON_CNIC_QUEUES(sc) BCM_NUM_QUEUES(sc)
+#define BCM_NUM_RX_QUEUES(sc)       BCM_NUM_QUEUES(sc)
+
+#define FOR_EACH_QUEUE(sc, var)                          \
+    for ((var) = 0; (var) < BCM_NUM_QUEUES(sc); (var)++)
+
+#define FOR_EACH_NONDEFAULT_QUEUE(sc, var)               \
+    for ((var) = 1; (var) < BCM_NUM_QUEUES(sc); (var)++)
+
+#define FOR_EACH_ETH_QUEUE(sc, var)                          \
+    for ((var) = 0; (var) < BCM_NUM_ETH_QUEUES(sc); (var)++)
+
+#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var)               \
+    for ((var) = 1; (var) < BCM_NUM_ETH_QUEUES(sc); (var)++)
+
+#define FOR_EACH_COS_IN_TX_QUEUE(sc, var)           \
+    for ((var) = 0; (var) < (sc)->max_cos; (var)++)
+
+#define FOR_EACH_CNIC_QUEUE(sc, var)     \
+    for ((var) = BCM_NUM_ETH_QUEUES(sc); \
+         (var) < BCM_NUM_QUEUES(sc);     \
+         (var)++)
+
+enum {
+    OOO_IDX_OFFSET,
+    FCOE_IDX_OFFSET,
+    FWD_IDX_OFFSET,
+};
+
+#define FCOE_IDX(sc)              (BCM_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
+#define bcm_fcoe_fp(sc)           (&sc->fp[FCOE_IDX(sc)])
+#define bcm_fcoe(sc, var)         (bcm_fcoe_fp(sc)->var)
+#define bcm_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
+#define bcm_fcoe_sp_obj(sc, var)  (bcm_fcoe_inner_sp_obj(sc)->var)
+#define bcm_fcoe_tx(sc, var)      (bcm_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
+
+#define OOO_IDX(sc)               (BCM_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
+#define bcm_ooo_fp(sc)            (&sc->fp[OOO_IDX(sc)])
+#define bcm_ooo(sc, var)          (bcm_ooo_fp(sc)->var)
+#define bcm_ooo_inner_sp_obj(sc)  (&sc->sp_objs[OOO_IDX(sc)])
+#define bcm_ooo_sp_obj(sc, var)   (bcm_ooo_inner_sp_obj(sc)->var)
+
+#define FWD_IDX(sc)               (BCM_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
+#define bcm_fwd_fp(sc)            (&sc->fp[FWD_IDX(sc)])
+#define bcm_fwd(sc, var)          (bcm_fwd_fp(sc)->var)
+#define bcm_fwd_inner_sp_obj(sc)  (&sc->sp_objs[FWD_IDX(sc)])
+#define bcm_fwd_sp_obj(sc, var)   (bcm_fwd_inner_sp_obj(sc)->var)
+#define bcm_fwd_txdata(fp)        (fp->txdata_ptr[FIRST_TX_COS_INDEX])
+
+#define IS_ETH_FP(fp)    ((fp)->index < BCM_NUM_ETH_QUEUES((fp)->sc))
+#define IS_FCOE_FP(fp)   ((fp)->index == FCOE_IDX((fp)->sc))
+#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
+#define IS_FWD_FP(fp)    ((fp)->index == FWD_IDX((fp)->sc))
+#define IS_FWD_IDX(idx)  ((idx) == FWD_IDX(sc))
+#define IS_OOO_FP(fp)    ((fp)->index == OOO_IDX((fp)->sc))
+#define IS_OOO_IDX(idx)  ((idx) == OOO_IDX(sc))
+
+enum {
+    BCM_PORT_QUERY_IDX,
+    BCM_PF_QUERY_IDX,
+    BCM_FCOE_QUERY_IDX,
+    BCM_FIRST_QUEUE_QUERY_IDX,
+};
+
+struct bcm_fw_stats_req {
+    struct stats_query_header hdr;
+    struct stats_query_entry  query[FP_SB_MAX_E1x +
+                                    BCM_FIRST_QUEUE_QUERY_IDX];
+};
+
+struct bcm_fw_stats_data {
+    struct stats_counter          storm_counters;
+    struct per_port_stats         port;
+    struct per_pf_stats           pf;
+    struct per_queue_stats        queue_stats[1];
+};
+
+/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
+#define BCM_IGU_STAS_MSG_VF_CNT 64
+#define BCM_IGU_STAS_MSG_PF_CNT 4
+
+#define MAX_DMAE_C 8
+
+/*
+ * This is the slowpath data structure. It is mapped into non-paged memory
+ * so that the hardware can access it's contents directly and must be page
+ * aligned.
+ */
+struct bcm_slowpath {
+
+    /* used by the DMAE command executer */
+    struct dmae_command dmae[MAX_DMAE_C];
+
+    /* statistics completion */
+    uint32_t stats_comp;
+
+    /* firmware defined statistics blocks */
+    union mac_stats        mac_stats;
+    struct nig_stats       nig_stats;
+    struct host_port_stats port_stats;
+    struct host_func_stats func_stats;
+
+    /* DMAE completion value and data source/sink */
+    uint32_t wb_comp;
+    uint32_t wb_data[4];
+
+    union {
+        struct mac_configuration_cmd          e1x;
+        struct eth_classify_rules_ramrod_data e2;
+    } mac_rdata;
+
+    union {
+        struct tstorm_eth_mac_filter_config e1x;
+        struct eth_filter_rules_ramrod_data e2;
+    } rx_mode_rdata;
+
+    struct eth_rss_update_ramrod_data rss_rdata;
+
+    union {
+        struct mac_configuration_cmd           e1;
+        struct eth_multicast_rules_ramrod_data e2;
+    } mcast_rdata;
+
+    union {
+        struct function_start_data        func_start;
+        struct flow_control_configuration pfc_config; /* for DCBX ramrod */
+    } func_rdata;
+
+    /* Queue State related ramrods */
+    union {
+        struct client_init_ramrod_data   init_data;
+        struct client_update_ramrod_data update_data;
+    } q_rdata;
+
+    /*
+     * AFEX ramrod can not be a part of func_rdata union because these
+     * events might arrive in parallel to other events from func_rdata.
+     * If they were defined in the same union the data can get corrupted.
+     */
+    struct afex_vif_list_ramrod_data func_afex_rdata;
+
+    union drv_info_to_mcp drv_info_to_mcp;
+}; /* struct bcm_slowpath */
+
+/*
+ * Port specifc data structure.
+ */
+struct bcm_port {
+    /*
+     * Port Management Function (for 57711E only).
+     * When this field is set the driver instance is
+     * responsible for managing port specifc
+     * configurations such as handling link attentions.
+     */
+    uint32_t pmf;
+
+    /* Ethernet maximum transmission unit. */
+    uint16_t ether_mtu;
+
+    uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
+
+    uint32_t ext_phy_config;
+
+    /* Port feature config.*/
+    uint32_t config;
+
+    /* Defines the features supported by the PHY. */
+    uint32_t supported[ELINK_LINK_CONFIG_SIZE];
+
+    /* Defines the features advertised by the PHY. */
+    uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
+#define ADVERTISED_10baseT_Half    (1 << 1)
+#define ADVERTISED_10baseT_Full    (1 << 2)
+#define ADVERTISED_100baseT_Half   (1 << 3)
+#define ADVERTISED_100baseT_Full   (1 << 4)
+#define ADVERTISED_1000baseT_Half  (1 << 5)
+#define ADVERTISED_1000baseT_Full  (1 << 6)
+#define ADVERTISED_TP              (1 << 7)
+#define ADVERTISED_FIBRE           (1 << 8)
+#define ADVERTISED_Autoneg         (1 << 9)
+#define ADVERTISED_Asym_Pause      (1 << 10)
+#define ADVERTISED_Pause           (1 << 11)
+#define ADVERTISED_2500baseX_Full  (1 << 15)
+#define ADVERTISED_10000baseT_Full (1 << 16)
+
+    uint32_t    phy_addr;
+
+    /*
+     * MCP scratchpad address for port specific statistics.
+     * The device is responsible for writing statistcss
+     * back to the MCP for use with management firmware such
+     * as UMP/NC-SI.
+     */
+    uint32_t port_stx;
+
+    struct nig_stats old_nig_stats;
+}; /* struct bcm_port */
+
+struct bcm_mf_info {
+    uint32_t mf_config[E1HVN_MAX];
+
+    uint32_t vnics_per_port;   /* 1, 2 or 4 */
+    uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
+    uint32_t path_has_ovlan;   /* MF mode in the path (can be different than the MF mode of the function */
+
+#define IS_MULTI_VNIC(sc)  ((sc)->devinfo.mf_info.multi_vnics_mode)
+#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
+#define VNICS_PER_PATH(sc)                                  \
+    ((sc)->devinfo.mf_info.vnics_per_port *                 \
+     ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
+
+    uint8_t min_bw[MAX_VNIC_NUM];
+    uint8_t max_bw[MAX_VNIC_NUM];
+
+    uint16_t ext_id; /* vnic outer vlan or VIF ID */
+#define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
+#define INVALID_VIF_ID 0xFFFF
+#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
+#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
+
+    uint16_t default_vlan;
+#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
+
+    uint8_t niv_allowed_priorities;
+#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
+
+    uint8_t niv_default_cos;
+#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
+
+    uint8_t niv_mba_enabled;
+
+    enum mf_cfg_afex_vlan_mode afex_vlan_mode;
+#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
+    int                        afex_def_vlan_tag;
+    uint32_t                   pending_max;
+
+    uint16_t flags;
+#define MF_INFO_VALID_MAC       0x0001
+
+    uint16_t mf_ov;
+    uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
+#define IS_MF(sc)                        \
+    (IS_MULTI_VNIC(sc) &&                \
+     ((sc)->devinfo.mf_info.mf_mode != 0))
+#define IS_MF_SD(sc)                                     \
+    (IS_MULTI_VNIC(sc) &&                                \
+     ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
+#define IS_MF_SI(sc)                                     \
+    (IS_MULTI_VNIC(sc) &&                                \
+     ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
+#define IS_MF_AFEX(sc)                              \
+    (IS_MULTI_VNIC(sc) &&                           \
+     ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
+#define IS_MF_SD_MODE(sc)   IS_MF_SD(sc)
+#define IS_MF_SI_MODE(sc)   IS_MF_SI(sc)
+#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
+
+    uint32_t mf_protos_supported;
+    #define MF_PROTO_SUPPORT_ETHERNET 0x1
+    #define MF_PROTO_SUPPORT_ISCSI    0x2
+    #define MF_PROTO_SUPPORT_FCOE     0x4
+}; /* struct bcm_mf_info */
+
+/* Device information data structure. */
+struct bcm_devinfo {
+    /* PCIe info */
+    uint16_t vendor_id;
+    uint16_t device_id;
+    uint16_t subvendor_id;
+    uint16_t subdevice_id;
+
+    /*
+     * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
+     *   C = Chip Number   (bits 16-31)
+     *   R = Chip Revision (bits 12-15)
+     *   M = Chip Metal    (bits 4-11)
+     *   B = Chip Bond ID  (bits 0-3)
+     */
+    uint32_t chip_id;
+#define CHIP_ID(sc)           ((sc)->devinfo.chip_id & 0xffff0000)
+#define CHIP_NUM(sc)          ((sc)->devinfo.chip_id >> 16)
+/* device ids */
+#define CHIP_NUM_57711        0x164f
+#define CHIP_NUM_57711E       0x1650
+#define CHIP_NUM_57712        0x1662
+#define CHIP_NUM_57712_MF     0x1663
+#define CHIP_NUM_57712_VF     0x166f
+#define CHIP_NUM_57800        0x168a
+#define CHIP_NUM_57800_MF     0x16a5
+#define CHIP_NUM_57800_VF     0x16a9
+#define CHIP_NUM_57810        0x168e
+#define CHIP_NUM_57810_MF     0x16ae
+#define CHIP_NUM_57810_VF     0x16af
+#define CHIP_NUM_57811        0x163d
+#define CHIP_NUM_57811_MF     0x163e
+#define CHIP_NUM_57811_VF     0x163f
+#define CHIP_NUM_57840_OBS    0x168d
+#define CHIP_NUM_57840_OBS_MF 0x16ab
+#define CHIP_NUM_57840_4_10   0x16a1
+#define CHIP_NUM_57840_2_20   0x16a2
+#define CHIP_NUM_57840_MF     0x16a4
+#define CHIP_NUM_57840_VF     0x16ad
+
+#define CHIP_REV_SHIFT      12
+#define CHIP_REV_MASK       (0xF << CHIP_REV_SHIFT)
+#define CHIP_REV(sc)        ((sc)->devinfo.chip_id & CHIP_REV_MASK)
+
+#define CHIP_REV_Ax         (0x0 << CHIP_REV_SHIFT)
+#define CHIP_REV_Bx         (0x1 << CHIP_REV_SHIFT)
+#define CHIP_REV_Cx         (0x2 << CHIP_REV_SHIFT)
+
+#define CHIP_REV_IS_SLOW(sc)    \
+    (CHIP_REV(sc) > 0x00005000)
+#define CHIP_REV_IS_FPGA(sc)                              \
+    (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
+#define CHIP_REV_IS_EMUL(sc)                               \
+    (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
+#define CHIP_REV_IS_ASIC(sc) \
+    (!CHIP_REV_IS_SLOW(sc))
+
+#define CHIP_METAL(sc)      ((sc->devinfo.chip_id) & 0x00000ff0)
+#define CHIP_BOND_ID(sc)    ((sc->devinfo.chip_id) & 0x0000000f)
+
+#define CHIP_IS_57711(sc)   (CHIP_NUM(sc) == CHIP_NUM_57711)
+#define CHIP_IS_57711E(sc)  (CHIP_NUM(sc) == CHIP_NUM_57711E)
+#define CHIP_IS_E1H(sc)     ((CHIP_IS_57711(sc)) || \
+                             (CHIP_IS_57711E(sc)))
+#define CHIP_IS_E1x(sc)     CHIP_IS_E1H(sc)
+
+#define CHIP_IS_57712(sc)    (CHIP_NUM(sc) == CHIP_NUM_57712)
+#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
+#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
+#define CHIP_IS_E2(sc)       (CHIP_IS_57712(sc) ||  \
+                              CHIP_IS_57712_MF(sc))
+
+#define CHIP_IS_57800(sc)    (CHIP_NUM(sc) == CHIP_NUM_57800)
+#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
+#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
+#define CHIP_IS_57810(sc)    (CHIP_NUM(sc) == CHIP_NUM_57810)
+#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
+#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
+#define CHIP_IS_57811(sc)    (CHIP_NUM(sc) == CHIP_NUM_57811)
+#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
+#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
+#define CHIP_IS_57840(sc)    ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS)  || \
+                              (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
+                              (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
+#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
+                              (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
+#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
+
+#define CHIP_IS_E3(sc)      (CHIP_IS_57800(sc)    || \
+                             CHIP_IS_57800_MF(sc) || \
+                             CHIP_IS_57800_VF(sc) || \
+                             CHIP_IS_57810(sc)    || \
+                             CHIP_IS_57810_MF(sc) || \
+                             CHIP_IS_57810_VF(sc) || \
+                             CHIP_IS_57811(sc)    || \
+                             CHIP_IS_57811_MF(sc) || \
+                             CHIP_IS_57811_VF(sc) || \
+                             CHIP_IS_57840(sc)    || \
+                             CHIP_IS_57840_MF(sc) || \
+                             CHIP_IS_57840_VF(sc))
+#define CHIP_IS_E3A0(sc)    (CHIP_IS_E3(sc) &&              \
+                             (CHIP_REV(sc) == CHIP_REV_Ax))
+#define CHIP_IS_E3B0(sc)    (CHIP_IS_E3(sc) &&              \
+                             (CHIP_REV(sc) == CHIP_REV_Bx))
+
+#define USES_WARPCORE(sc)   (CHIP_IS_E3(sc))
+#define CHIP_IS_E2E3(sc)    (CHIP_IS_E2(sc) || \
+                             CHIP_IS_E3(sc))
+
+#define CHIP_IS_MF_CAP(sc)  (CHIP_IS_57711E(sc)  ||  \
+                             CHIP_IS_57712_MF(sc) || \
+                             CHIP_IS_E3(sc))
+
+#define IS_VF(sc)           ((sc)->flags & BCM_IS_VF_FLAG)
+#define IS_PF(sc)           (!IS_VF(sc))
+
+/*
+ * This define is used in two main places:
+ * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
+ * to nic-only mode or to offload mode. Offload mode is configured if either
+ * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
+ * already registered for this port (which means that the user wants storage
+ * services).
+ * 2. During cnic-related load, to know if offload mode is already configured
+ * in the HW or needs to be configrued. Since the transition from nic-mode to
+ * offload-mode in HW causes traffic coruption, nic-mode is configured only
+ * in ports on which storage services where never requested.
+ */
+#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
+
+    uint8_t  chip_port_mode;
+#define CHIP_4_PORT_MODE        0x0
+#define CHIP_2_PORT_MODE        0x1
+#define CHIP_PORT_MODE_NONE     0x2
+#define CHIP_PORT_MODE(sc)      ((sc)->devinfo.chip_port_mode)
+#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
+
+    uint8_t int_block;
+#define INT_BLOCK_HC            0
+#define INT_BLOCK_IGU           1
+#define INT_BLOCK_MODE_NORMAL   0
+#define INT_BLOCK_MODE_BW_COMP  2
+#define CHIP_INT_MODE_IS_NBC(sc)                          \
+    (!CHIP_IS_E1x(sc) &&                                  \
+     !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
+#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
+
+    uint32_t shmem_base;
+    uint32_t shmem2_base;
+    uint32_t bc_ver;
+    char bc_ver_str[32];
+    uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
+    struct bcm_mf_info mf_info;
+
+    uint32_t flash_size;
+#define NVRAM_1MB_SIZE      0x20000
+#define NVRAM_TIMEOUT_COUNT 30000
+#define NVRAM_PAGE_SIZE     256
+
+    /* PCIe capability information */
+    uint32_t pcie_cap_flags;
+#define BCM_PM_CAPABLE_FLAG     0x00000001
+#define BCM_PCIE_CAPABLE_FLAG   0x00000002
+#define BCM_MSI_CAPABLE_FLAG    0x00000004
+#define BCM_MSIX_CAPABLE_FLAG   0x00000008
+    uint16_t pcie_pm_cap_reg;
+    uint16_t pcie_link_width;
+    uint16_t pcie_link_speed;
+    uint16_t pcie_msi_cap_reg;
+    uint16_t pcie_msix_cap_reg;
+
+    /* device configuration read from bootcode shared memory */
+    uint32_t hw_config;
+    uint32_t hw_config2;
+}; /* struct bcm_devinfo */
+
+struct bcm_sp_objs {
+    struct ecore_vlan_mac_obj mac_obj; /* MACs object */
+    struct ecore_queue_sp_obj q_obj; /* Queue State object */
+}; /* struct bcm_sp_objs */
+
+/*
+ * Data that will be used to create a link report message. We will keep the
+ * data used for the last link report in order to prevent reporting the same
+ * link parameters twice.
+ */
+struct bcm_link_report_data {
+    uint16_t      line_speed;        /* Effective line speed */
+    unsigned long link_report_flags; /* BCM_LINK_REPORT_XXX flags */
+};
+enum {
+    BCM_LINK_REPORT_FULL_DUPLEX,
+    BCM_LINK_REPORT_LINK_DOWN,
+    BCM_LINK_REPORT_RX_FC_ON,
+    BCM_LINK_REPORT_TX_FC_ON
+};
+
+#define BCM_RX_CHAIN_PAGE_SZ    BCM_PAGE_SIZE
+
+struct bcm_pci_cap {
+	struct bcm_pci_cap *next;
+	uint16_t id;
+	uint16_t type;
+	uint16_t addr;
+};
+
+struct bcm_vfdb;
+
+/* Top level device private data structure. */
+struct bcm_softc {
+
+	void            **rx_queues;
+	void            **tx_queues;
+	uint32_t        max_tx_queues;
+	uint32_t        max_rx_queues;
+	const struct rte_pci_device *pci_dev;
+	uint32_t        pci_val;
+	struct bcm_pci_cap *pci_caps;
+#define BCM_INTRS_POLL_PERIOD   1
+
+	void            *firmware;
+	uint64_t        fw_len;
+
+	/* MAC address operations */
+	struct bcm_mac_ops mac_ops;
+
+	/* structures for VF mbox/response/bulletin */
+	struct bcm_vf_mbx_msg	*vf2pf_mbox;
+	struct bcm_dma		vf2pf_mbox_mapping;
+	struct vf_acquire_resp_tlv acquire_resp;
+	struct bcm_vf_bulletin	*pf2vf_bulletin;
+	struct bcm_dma		pf2vf_bulletin_mapping;
+	struct bcm_vf_bulletin	old_bulletin;
+
+	int             media;
+
+	int             state; /* device state */
+#define BCM_STATE_CLOSED                 0x0000
+#define BCM_STATE_OPENING_WAITING_LOAD   0x1000
+#define BCM_STATE_OPENING_WAITING_PORT   0x2000
+#define BCM_STATE_OPEN                   0x3000
+#define BCM_STATE_CLOSING_WAITING_HALT   0x4000
+#define BCM_STATE_CLOSING_WAITING_DELETE 0x5000
+#define BCM_STATE_CLOSING_WAITING_UNLOAD 0x6000
+#define BCM_STATE_DISABLED               0xD000
+#define BCM_STATE_DIAG                   0xE000
+#define BCM_STATE_ERROR                  0xF000
+
+	int flags;
+#define BCM_ONE_PORT_FLAG     0x1
+#define BCM_NO_FCOE_FLAG      0x2
+#define BCM_NO_WOL_FLAG       0x4
+#define BCM_NO_MCP_FLAG       0x8
+#define BCM_NO_ISCSI_OOO_FLAG 0x10
+#define BCM_NO_ISCSI_FLAG     0x20
+#define BCM_MF_FUNC_DIS       0x40
+#define BCM_TX_SWITCHING      0x80
+#define BCM_IS_VF_FLAG        0x100
+
+#define BCM_ONE_PORT(sc)      (sc->flags & BCM_ONE_PORT_FLAG)
+#define BCM_NOFCOE(sc)        (sc->flags & BCM_NO_FCOE_FLAG)
+#define BCM_NOMCP(sc)         (sc->flags & BCM_NO_MCP_FLAG)
+
+#define MAX_BARS 5
+	struct bcm_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
+
+	uint16_t doorbell_size;
+
+	/* periodic timer callout */
+#define PERIODIC_STOP 0
+#define PERIODIC_GO   1
+	volatile unsigned long periodic_flags;
+
+	struct bcm_fastpath fp[MAX_RSS_CHAINS];
+	struct bcm_sp_objs  sp_objs[MAX_RSS_CHAINS];
+
+	uint8_t  unit; /* driver instance number */
+
+	int pcie_bus;    /* PCIe bus number */
+	int pcie_device; /* PCIe device/slot number */
+	int pcie_func;   /* PCIe function number */
+
+	uint8_t pfunc_rel; /* function relative */
+	uint8_t pfunc_abs; /* function absolute */
+	uint8_t path_id;   /* function absolute */
+#define SC_PATH(sc)     (sc->path_id)
+#define SC_PORT(sc)     (sc->pfunc_rel & 1)
+#define SC_FUNC(sc)     (sc->pfunc_rel)
+#define SC_ABS_FUNC(sc) (sc->pfunc_abs)
+#define SC_VN(sc)       (sc->pfunc_rel >> 1)
+#define SC_L_ID(sc)     (SC_VN(sc) << 2)
+#define PORT_ID(sc)     SC_PORT(sc)
+#define PATH_ID(sc)     SC_PATH(sc)
+#define VNIC_ID(sc)     SC_VN(sc)
+#define FUNC_ID(sc)     SC_FUNC(sc)
+#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
+#define SC_FW_MB_IDX_VN(sc, vn)                                \
+	(SC_PORT(sc) + (vn) *                                      \
+	 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
+#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
+
+	int if_capen; /* enabled interface capabilities */
+
+	struct bcm_devinfo devinfo;
+	char fw_ver_str[32];
+	char mf_mode_str[32];
+	char pci_link_str[32];
+
+	struct iro *iro_array;
+
+	int dmae_ready;
+#define DMAE_READY(sc) (sc->dmae_ready)
+
+	struct ecore_credit_pool_obj vlans_pool;
+	struct ecore_credit_pool_obj macs_pool;
+	struct ecore_rx_mode_obj     rx_mode_obj;
+	struct ecore_mcast_obj       mcast_obj;
+	struct ecore_rss_config_obj  rss_conf_obj;
+	struct ecore_func_sp_obj     func_obj;
+
+	uint16_t fw_seq;
+	uint16_t fw_drv_pulse_wr_seq;
+	uint32_t func_stx;
+
+	struct elink_params         link_params;
+	struct elink_vars           link_vars;
+	uint32_t                    link_cnt;
+	struct bcm_link_report_data last_reported_link;
+	char mac_addr_str[32];
+
+	uint32_t tx_ring_size;
+	uint32_t rx_ring_size;
+	int wol;
+
+	int is_leader;
+	int recovery_state;
+#define BCM_RECOVERY_DONE        1
+#define BCM_RECOVERY_INIT        2
+#define BCM_RECOVERY_WAIT        3
+#define BCM_RECOVERY_FAILED      4
+#define BCM_RECOVERY_NIC_LOADING 5
+
+	uint32_t rx_mode;
+#define BCM_RX_MODE_NONE     0
+#define BCM_RX_MODE_NORMAL   1
+#define BCM_RX_MODE_ALLMULTI 2
+#define BCM_RX_MODE_PROMISC  3
+#define BCM_MAX_MULTICAST    64
+
+	struct bcm_port port;
+
+	struct cmng_init cmng;
+
+	/* user configs */
+	uint8_t  num_queues;
+	int      hc_rx_ticks;
+	int      hc_tx_ticks;
+	uint32_t rx_budget;
+	int      interrupt_mode;
+#define INTR_MODE_INTX 0
+#define INTR_MODE_MSI  1
+#define INTR_MODE_MSIX 2
+#define INTR_MODE_SINGLE_MSIX 3
+	int      udp_rss;
+
+	uint8_t         igu_dsb_id;
+	uint8_t         igu_base_sb;
+	uint8_t         igu_sb_cnt;
+	uint32_t        igu_base_addr;
+	uint8_t         base_fw_ndsb;
+#define DEF_SB_IGU_ID 16
+#define DEF_SB_ID     HC_SP_SB_ID
+
+	/* default status block */
+	struct bcm_dma              def_sb_dma;
+	struct host_sp_status_block *def_sb;
+	uint16_t                    def_idx;
+	uint16_t                    def_att_idx;
+	uint32_t                    attn_state;
+	struct attn_route           attn_group[MAX_DYNAMIC_ATTN_GRPS];
+
+	/* general SP events - stats query, cfc delete, etc */
+#define HC_SP_INDEX_ETH_DEF_CONS         3
+	/* EQ completions */
+#define HC_SP_INDEX_EQ_CONS              7
+	/* FCoE L2 connection completions */
+#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS  6
+#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS  4
+	/* iSCSI L2 */
+#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS    5
+#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
+
+	/* event queue */
+	struct bcm_dma        eq_dma;
+	union event_ring_elem *eq;
+	uint16_t              eq_prod;
+	uint16_t              eq_cons;
+	uint16_t              *eq_cons_sb;
+#define NUM_EQ_PAGES     1 /* must be a power of 2 */
+#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
+#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
+#define NUM_EQ_DESC      (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
+#define EQ_DESC_MASK     (NUM_EQ_DESC - 1)
+#define MAX_EQ_AVAIL     (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
+	/* depends on EQ_DESC_CNT_PAGE being a power of 2 */
+#define NEXT_EQ_IDX(x)                                      \
+	((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
+	 ((x) + 2) : ((x) + 1))
+	/* depends on the above and on NUM_EQ_PAGES being a power of 2 */
+#define EQ_DESC(x) ((x) & EQ_DESC_MASK)
+
+	/* slow path */
+	struct bcm_dma      sp_dma;
+	struct bcm_slowpath *sp;
+	unsigned long       sp_state;
+
+	/* slow path queue */
+	struct bcm_dma spq_dma;
+	struct eth_spe *spq;
+#define SP_DESC_CNT     (BCM_PAGE_SIZE / sizeof(struct eth_spe))
+#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
+#define MAX_SPQ_PENDING 8
+
+	uint16_t       spq_prod_idx;
+	struct eth_spe *spq_prod_bd;
+	struct eth_spe *spq_last_bd;
+	uint16_t       *dsb_sp_prod;
+
+	volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
+	volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
+
+	/* fw decompression buffer */
+	struct bcm_dma gz_buf_dma;
+	void           *gz_buf;
+	uint32_t       gz_outlen;
+#define GUNZIP_BUF(sc)    (sc->gz_buf)
+#define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
+#define GUNZIP_PHYS(sc)   (phys_addr_t)((void *)(sc->gz_buf_dma.paddr))
+#define FW_BUF_SIZE       0x40000
+
+	struct raw_op *init_ops;
+	uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
+	uint32_t *init_data;        /* data blob, 32 bit granularity */
+	uint32_t       init_mode_flags;
+#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
+	/* PRAM blobs - raw data */
+	const uint8_t *tsem_int_table_data;
+	const uint8_t *tsem_pram_data;
+	const uint8_t *usem_int_table_data;
+	const uint8_t *usem_pram_data;
+	const uint8_t *xsem_int_table_data;
+	const uint8_t *xsem_pram_data;
+	const uint8_t *csem_int_table_data;
+	const uint8_t *csem_pram_data;
+#define INIT_OPS(sc)                 (sc->init_ops)
+#define INIT_OPS_OFFSETS(sc)         (sc->init_ops_offsets)
+#define INIT_DATA(sc)                (sc->init_data)
+#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
+#define INIT_TSEM_PRAM_DATA(sc)      (sc->tsem_pram_data)
+#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
+#define INIT_USEM_PRAM_DATA(sc)      (sc->usem_pram_data)
+#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
+#define INIT_XSEM_PRAM_DATA(sc)      (sc->xsem_pram_data)
+#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
+#define INIT_CSEM_PRAM_DATA(sc)      (sc->csem_pram_data)
+
+#define PHY_FW_VER_LEN			20
+	char			fw_ver[32];
+
+	/* ILT
+	 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
+	 * context size we need 8 ILT entries.
+	 */
+#define ILT_MAX_L2_LINES 8
+	struct hw_context context[ILT_MAX_L2_LINES];
+	struct ecore_ilt *ilt;
+#define ILT_MAX_LINES 256
+
+	/* max supported number of RSS queues: IGU SBs minus one for CNIC */
+#define BCM_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
+	/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
+#define BCM_L2_MAX_CID(sc)                                              \
+	(BCM_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
+#define BCM_L2_CID_COUNT(sc)                                             \
+	(BCM_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
+#define L2_ILT_LINES(sc)                                \
+	(DIV_ROUND_UP(BCM_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
+
+	int qm_cid_count;
+
+	uint8_t dropless_fc;
+
+	/* total number of FW statistics requests */
+	uint8_t fw_stats_num;
+	/*
+	 * This is a memory buffer that will contain both statistics ramrod
+	 * request and data.
+	 */
+	struct bcm_dma fw_stats_dma;
+	/*
+	 * FW statistics request shortcut (points at the beginning of fw_stats
+	 * buffer).
+	 */
+	int                     fw_stats_req_size;
+	struct bcm_fw_stats_req *fw_stats_req;
+	phys_addr_t              fw_stats_req_mapping;
+	/*
+	 * FW statistics data shortcut (points at the beginning of fw_stats
+	 * buffer + fw_stats_req_size).
+	 */
+	int                      fw_stats_data_size;
+	struct bcm_fw_stats_data *fw_stats_data;
+	phys_addr_t               fw_stats_data_mapping;
+
+	/* tracking a pending STAT_QUERY ramrod */
+	uint16_t stats_pending;
+	/* number of completed statistics ramrods */
+	uint16_t stats_comp;
+	uint16_t stats_counter;
+	uint8_t  stats_init;
+	int      stats_state;
+
+	struct bcm_eth_stats         eth_stats;
+	struct host_func_stats       func_stats;
+	struct bcm_eth_stats_old     eth_stats_old;
+	struct bcm_net_stats_old     net_stats_old;
+	struct bcm_fw_port_stats_old fw_stats_old;
+
+	struct dmae_command stats_dmae; /* used by dmae command loader */
+	int                 executer_idx;
+
+	int mtu;
+
+	/* DCB support on/off */
+	int dcb_state;
+#define BCM_DCB_STATE_OFF 0
+#define BCM_DCB_STATE_ON  1
+	/* DCBX engine mode */
+	int dcbx_enabled;
+#define BCM_DCBX_ENABLED_OFF        0
+#define BCM_DCBX_ENABLED_ON_NEG_OFF 1
+#define BCM_DCBX_ENABLED_ON_NEG_ON  2
+#define BCM_DCBX_ENABLED_INVALID    -1
+
+	uint8_t cnic_support;
+	uint8_t cnic_enabled;
+	uint8_t cnic_loaded;
+#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
+#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
+#define CNIC_LOADED(sc)  0 /* ((sc)->cnic_loaded) */
+
+	/* multiple tx classes of service */
+	uint8_t max_cos;
+#define BCM_MAX_PRIORITY 8
+	/* priority to cos mapping */
+	uint8_t prio_to_cos[BCM_MAX_PRIORITY];
+
+	int panic;
+}; /* struct bcm_softc */
+
+/* IOCTL sub-commands for edebug and firmware upgrade */
+#define BCM_IOC_RD_NVRAM        1
+#define BCM_IOC_WR_NVRAM        2
+#define BCM_IOC_STATS_SHOW_NUM  3
+#define BCM_IOC_STATS_SHOW_STR  4
+#define BCM_IOC_STATS_SHOW_CNT  5
+
+struct bcm_nvram_data {
+    uint32_t op; /* ioctl sub-command */
+    uint32_t offset;
+    uint32_t len;
+    uint32_t value[1]; /* variable */
+};
+
+union bcm_stats_show_data {
+    uint32_t op; /* ioctl sub-command */
+
+    struct {
+        uint32_t num; /* return number of stats */
+        uint32_t len; /* length of each string item */
+    } desc;
+
+    /* variable length... */
+    char str[1]; /* holds names of desc.num stats, each desc.len in length */
+
+    /* variable length... */
+    uint64_t stats[1]; /* holds all stats */
+};
+
+/* function init flags */
+#define FUNC_FLG_RSS     0x0001
+#define FUNC_FLG_STATS   0x0002
+/* FUNC_FLG_UNMATCHED       0x0004 */
+#define FUNC_FLG_SPQ     0x0010
+#define FUNC_FLG_LEADING 0x0020 /* PF only */
+
+struct bcm_func_init_params {
+    phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
+    phys_addr_t spq_map;     /* (dma) valid if FUNC_FLG_SPQ */
+    uint16_t   func_flgs;
+    uint16_t   func_id;     /* abs function id */
+    uint16_t   pf_id;
+    uint16_t   spq_prod;    /* valid if FUNC_FLG_SPQ */
+};
+
+/* memory resources reside at BARs 0, 2, 4 */
+/* Run `pciconf -lb` to see mappings */
+#define BAR0 0
+#define BAR1 2
+#define BAR2 4
+
+#ifdef RTE_LIBRTE_BCM_DEBUG
+uint8_t bcm_reg_read8(struct bcm_softc *sc, size_t offset);
+uint16_t bcm_reg_read16(struct bcm_softc *sc, size_t offset);
+uint32_t bcm_reg_read32(struct bcm_softc *sc, size_t offset);
+
+void bcm_reg_write8(struct bcm_softc *sc, size_t offset, uint8_t val);
+void bcm_reg_write16(struct bcm_softc *sc, size_t offset, uint16_t val);
+void bcm_reg_write32(struct bcm_softc *sc, size_t offset, uint32_t val);
+#else
+#define bcm_reg_write8(sc, offset, val)\
+	*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val
+
+#define bcm_reg_write16(sc, offset, val)\
+	*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val
+
+#define bcm_reg_write32(sc, offset, val)\
+	*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val
+
+#define bcm_reg_read8(sc, offset)\
+	(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))
+
+#define bcm_reg_read16(sc, offset)\
+	(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))
+
+#define bcm_reg_read32(sc, offset)\
+	(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))
+#endif
+
+#define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
+
+#define REG_RD8(sc, offset)  bcm_reg_read8(sc, (offset))
+#define REG_RD16(sc, offset) bcm_reg_read16(sc, (offset))
+#define REG_RD32(sc, offset) bcm_reg_read32(sc, (offset))
+
+#define REG_WR8(sc, offset, val)  bcm_reg_write8(sc, (offset), val)
+#define REG_WR16(sc, offset, val) bcm_reg_write16(sc, (offset), val)
+#define REG_WR32(sc, offset, val) bcm_reg_write32(sc, (offset), val)
+
+#define REG_RD(sc, offset)      REG_RD32(sc, offset)
+#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
+
+#define BCM_SP(sc, var) (&(sc)->sp->var)
+#define BCM_SP_MAPPING(sc, var) \
+    (sc->sp_dma.paddr + offsetof(struct bcm_slowpath, var))
+
+#define BCM_FP(sc, nr, var) ((sc)->fp[(nr)].var)
+#define BCM_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
+
+#define bcm_fp(sc, nr, var)   ((sc)->fp[nr].var)
+
+#define REG_RD_DMAE(sc, offset, valp, len32)               \
+    do {                                                   \
+        (void)bcm_read_dmae(sc, offset, len32);                  \
+        (void)rte_memcpy(valp, BCM_SP(sc, wb_data[0]), (len32) * 4); \
+    } while (0)
+
+#define REG_WR_DMAE(sc, offset, valp, len32)                            \
+    do {                                                                \
+        (void)rte_memcpy(BCM_SP(sc, wb_data[0]), valp, (len32) * 4);              \
+        (void)bcm_write_dmae(sc, BCM_SP_MAPPING(sc, wb_data), offset, len32); \
+    } while (0)
+
+#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
+    REG_WR_DMAE(sc, offset, valp, len32)
+
+#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
+    REG_RD_DMAE(sc, offset, valp, len32)
+
+#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap)         \
+    do {                                                           \
+        /* if (le32_swap) {                                     */ \
+        /*    PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
+        /* }                                                    */ \
+        rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4);                   \
+        ecore_write_big_buf_wb(sc, addr, len32);                   \
+    } while (0)
+
+#define BCM_DB_MIN_SHIFT 3   /* 8 bytes */
+#define BCM_DB_SHIFT     7   /* 128 bytes */
+#if (BCM_DB_SHIFT < BCM_DB_MIN_SHIFT)
+#error "Minimum DB doorbell stride is 8"
+#endif
+#define DPM_TRIGGER_TYPE 0x40
+
+/* Doorbell macro */
+#define BCM_DB_WRITE(db_bar, val) \
+	*((volatile uint32_t *)(db_bar)) = (val)
+
+#define BCM_DB_READ(db_bar) \
+	*((volatile uint32_t *)(db_bar))
+
+#define DOORBELL_ADDR(sc, offset) \
+	(volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
+
+#define DOORBELL(sc, cid, val) \
+	if (IS_PF(sc)) \
+	BCM_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
+	else \
+	BCM_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
+
+#define SHMEM_ADDR(sc, field)                                       \
+    (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
+#define SHMEM_RD(sc, field)      REG_RD(sc, SHMEM_ADDR(sc, field))
+#define SHMEM_RD16(sc, field)    REG_RD16(sc, SHMEM_ADDR(sc, field))
+#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
+
+#define SHMEM2_ADDR(sc, field)                                        \
+    (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
+#define SHMEM2_HAS(sc, field)                                            \
+    (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) >     \
+                                 offsetof(struct shmem2_region, field)))
+#define SHMEM2_RD(sc, field)      REG_RD(sc, SHMEM2_ADDR(sc, field))
+#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
+
+#define MFCFG_ADDR(sc, field)                                  \
+    (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
+#define MFCFG_RD(sc, field)      REG_RD(sc, MFCFG_ADDR(sc, field))
+#define MFCFG_RD16(sc, field)    REG_RD16(sc, MFCFG_ADDR(sc, field))
+#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
+
+/* DMAE command defines */
+
+#define DMAE_TIMEOUT      -1
+#define DMAE_PCI_ERROR    -2 /* E2 and onward */
+#define DMAE_NOT_RDY      -3
+#define DMAE_PCI_ERR_FLAG 0x80000000
+
+#define DMAE_SRC_PCI      0
+#define DMAE_SRC_GRC      1
+
+#define DMAE_DST_NONE     0
+#define DMAE_DST_PCI      1
+#define DMAE_DST_GRC      2
+
+#define DMAE_COMP_PCI     0
+#define DMAE_COMP_GRC     1
+
+#define DMAE_COMP_REGULAR 0
+#define DMAE_COM_SET_ERR  1
+
+#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
+#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
+#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
+#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
+
+#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
+#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
+
+#define DMAE_CMD_ENDIANITY_NO_SWAP   (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_B_SWAP    (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_DW_SWAP   (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
+
+#define DMAE_CMD_PORT_0 0
+#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
+
+#define DMAE_SRC_PF 0
+#define DMAE_SRC_VF 1
+
+#define DMAE_DST_PF 0
+#define DMAE_DST_VF 1
+
+#define DMAE_C_SRC 0
+#define DMAE_C_DST 1
+
+#define DMAE_LEN32_RD_MAX     0x80
+#define DMAE_LEN32_WR_MAX(sc) 0x2000
+
+#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
+
+#define MAX_DMAE_C_PER_PORT 8
+#define INIT_DMAE_C(sc)     ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
+#define PMF_DMAE_C(sc)      ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
+
+static const uint32_t dmae_reg_go_c[] = {
+    DMAE_REG_GO_C0,  DMAE_REG_GO_C1,  DMAE_REG_GO_C2,  DMAE_REG_GO_C3,
+    DMAE_REG_GO_C4,  DMAE_REG_GO_C5,  DMAE_REG_GO_C6,  DMAE_REG_GO_C7,
+    DMAE_REG_GO_C8,  DMAE_REG_GO_C9,  DMAE_REG_GO_C10, DMAE_REG_GO_C11,
+    DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
+};
+
+#define ATTN_NIG_FOR_FUNC     (1L << 8)
+#define ATTN_SW_TIMER_4_FUNC  (1L << 9)
+#define GPIO_2_FUNC           (1L << 10)
+#define GPIO_3_FUNC           (1L << 11)
+#define GPIO_4_FUNC           (1L << 12)
+#define ATTN_GENERAL_ATTN_1   (1L << 13)
+#define ATTN_GENERAL_ATTN_2   (1L << 14)
+#define ATTN_GENERAL_ATTN_3   (1L << 15)
+#define ATTN_GENERAL_ATTN_4   (1L << 13)
+#define ATTN_GENERAL_ATTN_5   (1L << 14)
+#define ATTN_GENERAL_ATTN_6   (1L << 15)
+#define ATTN_HARD_WIRED_MASK  0xff00
+#define ATTENTION_ID          4
+
+#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
+    AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
+
+#define MAX_IGU_ATTN_ACK_TO 100
+
+#define STORM_ASSERT_ARRAY_SIZE 50
+
+#define BCM_PMF_LINK_ASSERT(sc) \
+    GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
+
+#define BCM_MC_ASSERT_BITS \
+    (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+     GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+     GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+     GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
+
+#define BCM_MCP_ASSERT \
+    GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
+
+#define BCM_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
+#define BCM_GRC_RSV     (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
+                         GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
+                         GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
+                         GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
+                         GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
+                         GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
+
+#define MULTI_MASK 0x7f
+
+#define PFS_PER_PORT(sc)                               \
+    ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
+#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
+
+#define FIRST_ABS_FUNC_IN_PORT(sc)                    \
+    ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ?    \
+     PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
+
+#define FOREACH_ABS_FUNC_IN_PORT(sc, i)            \
+    for ((i) = FIRST_ABS_FUNC_IN_PORT(sc);         \
+         (i) < MAX_FUNC_NUM;                       \
+         (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
+
+#define BCM_SWCID_SHIFT 17
+#define BCM_SWCID_MASK  ((0x1 << BCM_SWCID_SHIFT) - 1)
+
+#define SW_CID(x)  (le32toh(x) & BCM_SWCID_MASK)
+#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
+
+#define CQE_TYPE(cqe_fp_flags)   ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
+#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
+#define CQE_TYPE_STOP(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
+#define CQE_TYPE_SLOW(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
+#define CQE_TYPE_FAST(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
+
+/* must be used on a CID before placing it on a HW ring */
+#define HW_CID(sc, x) \
+    ((SC_PORT(sc) << 23) | (SC_VN(sc) << BCM_SWCID_SHIFT) | (x))
+
+#define SPEED_10    10
+#define SPEED_100   100
+#define SPEED_1000  1000
+#define SPEED_2500  2500
+#define SPEED_10000 10000
+
+#define PCI_PM_D0    1
+#define PCI_PM_D3hot 2
+
+int  bcm_test_bit(int nr, volatile unsigned long * addr);
+void bcm_set_bit(unsigned int nr, volatile unsigned long * addr);
+void bcm_clear_bit(int nr, volatile unsigned long * addr);
+int  bcm_test_and_clear_bit(int nr, volatile unsigned long * addr);
+int  bcm_cmpxchg(volatile int *addr, int old, int new);
+
+int bcm_dma_alloc(struct bcm_softc *sc, size_t size,
+		struct bcm_dma *dma, const char *msg, uint32_t align);
+
+uint32_t bcm_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
+uint32_t bcm_dmae_opcode_clr_src_reset(uint32_t opcode);
+uint32_t bcm_dmae_opcode(struct bcm_softc *sc, uint8_t src_type,
+                         uint8_t dst_type, uint8_t with_comp,
+                         uint8_t comp_type);
+void bcm_post_dmae(struct bcm_softc *sc, struct dmae_command *dmae, int idx);
+void bcm_read_dmae(struct bcm_softc *sc, uint32_t src_addr, uint32_t len32);
+void bcm_write_dmae(struct bcm_softc *sc, phys_addr_t dma_addr,
+                    uint32_t dst_addr, uint32_t len32);
+void bcm_set_ctx_validation(struct bcm_softc *sc, struct eth_context *cxt,
+                            uint32_t cid);
+void bcm_update_coalesce_sb_index(struct bcm_softc *sc, uint8_t fw_sb_id,
+                                  uint8_t sb_index, uint8_t disable,
+                                  uint16_t usec);
+
+int bcm_sp_post(struct bcm_softc *sc, int command, int cid,
+                uint32_t data_hi, uint32_t data_lo, int cmd_type);
+
+void ecore_init_e1h_firmware(struct bcm_softc *sc);
+void ecore_init_e2_firmware(struct bcm_softc *sc);
+
+void ecore_storm_memset_struct(struct bcm_softc *sc, uint32_t addr,
+                               size_t size, uint32_t *data);
+
+#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
+#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
+
+#define BCM_MAC_FMT		"%pM"
+#define BCM_MAC_PRN_LIST(mac)	(mac)
+
+/***********/
+/* INLINES */
+/***********/
+
+static inline uint32_t
+reg_poll(struct bcm_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
+{
+    uint32_t val;
+    do {
+        val = REG_RD(sc, reg);
+        if (val == expected) {
+            break;
+        }
+        ms -= wait;
+        DELAY(wait * 1000);
+    } while (ms > 0);
+
+    return val;
+}
+
+static inline void
+bcm_update_fp_sb_idx(struct bcm_fastpath *fp)
+{
+	mb(); /* status block is written to by the chip */
+	fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
+}
+
+static inline void
+bcm_igu_ack_sb_gen(struct bcm_softc *sc, uint8_t segment,
+	uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
+{
+	struct igu_regular cmd_data = {0};
+
+	cmd_data.sb_id_and_flags =
+		((index << IGU_REGULAR_SB_INDEX_SHIFT) |
+		 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
+		 (update << IGU_REGULAR_BUPDATE_SHIFT) |
+		 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
+
+	REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
+
+	/* Make sure that ACK is written */
+	mb();
+}
+
+static inline void
+bcm_hc_ack_sb(struct bcm_softc *sc, uint8_t sb_id, uint8_t storm,
+		uint16_t index, uint8_t op, uint8_t update)
+{
+	uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
+			COMMAND_REG_INT_ACK);
+	union igu_ack_register igu_ack;
+
+	igu_ack.sb.status_block_index = index;
+	igu_ack.sb.sb_id_and_flags =
+		((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
+		 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
+		 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
+		 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
+
+	REG_WR(sc, hc_addr, igu_ack.raw_data);
+
+	/* Make sure that ACK is written */
+	mb();
+}
+
+static inline uint32_t
+bcm_hc_ack_int(struct bcm_softc *sc)
+{
+	uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
+			COMMAND_REG_SIMD_MASK);
+	uint32_t result = REG_RD(sc, hc_addr);
+
+	mb();
+	return result;
+}
+
+static inline uint32_t
+bcm_igu_ack_int(struct bcm_softc *sc)
+{
+	uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
+	uint32_t result = REG_RD(sc, igu_addr);
+
+	/* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
+			result, igu_addr); */
+
+	mb();
+	return result;
+}
+
+static inline uint32_t
+bcm_ack_int(struct bcm_softc *sc)
+{
+	mb();
+	if (sc->devinfo.int_block == INT_BLOCK_HC) {
+		return bcm_hc_ack_int(sc);
+	} else {
+		return bcm_igu_ack_int(sc);
+	}
+}
+
+static inline int
+func_by_vn(struct bcm_softc *sc, int vn)
+{
+    return (2 * vn + SC_PORT(sc));
+}
+
+/*
+ * send notification to other functions.
+ */
+static inline void
+bcm_link_sync_notify(struct bcm_softc *sc)
+{
+	int func, vn;
+
+	/* Set the attention towards other drivers on the same port */
+	for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
+		if (vn == SC_VN(sc))
+			continue;
+
+		func = func_by_vn(sc, vn);
+		REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
+				(LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
+	}
+}
+
+/*
+ * Statistics ID are global per chip/path, while Client IDs for E1x
+ * are per port.
+ */
+static inline uint8_t
+bcm_stats_id(struct bcm_fastpath *fp)
+{
+    struct bcm_softc *sc = fp->sc;
+
+    if (!CHIP_IS_E1x(sc)) {
+        return fp->cl_id;
+    }
+
+    return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
+}
+
+int bcm_init(struct bcm_softc *sc);
+void bcm_load_firmware(struct bcm_softc *sc);
+int bcm_attach(struct bcm_softc *sc);
+int bcm_nic_unload(struct bcm_softc *sc, uint32_t unload_mode, uint8_t keep_link);
+int bcm_alloc_hsi_mem(struct bcm_softc *sc);
+int bcm_alloc_ilt_mem(struct bcm_softc *sc);
+void bcm_free_ilt_mem(struct bcm_softc *sc);
+void bcm_dump_tx_chain(struct bcm_fastpath * fp, int bd_prod, int count);
+int bcm_tx_encap(struct bcm_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts);
+uint8_t bcm_txeof(struct bcm_softc *sc, struct bcm_fastpath *fp);
+void bcm_print_adapter_info(struct bcm_softc *sc);
+int bcm_intr_legacy(struct bcm_softc *sc, int scan_fp);
+void bcm_link_status_update(struct bcm_softc *sc);
+int bcm_complete_sp(struct bcm_softc *sc);
+int bcm_set_storm_rx_mode(struct bcm_softc *sc);
+void bcm_periodic_callout(struct bcm_softc *sc);
+
+int bcm_vf_get_resources(struct bcm_softc *sc, uint8_t tx_count, uint8_t rx_count);
+void bcm_vf_close(struct bcm_softc *sc);
+int bcm_vf_init(struct bcm_softc *sc);
+void bcm_vf_unload(struct bcm_softc *sc);
+int bcm_vf_setup_queue(struct bcm_softc *sc, struct bcm_fastpath *fp,
+	int leading);
+void bcm_free_hsi_mem(struct bcm_softc *sc);
+int bcm_vf_set_rx_mode(struct bcm_softc *sc);
+int bcm_fill_accept_flags(struct bcm_softc *sc, uint32_t rx_mode,
+	unsigned long *rx_accept_flags, unsigned long *tx_accept_flags);
+int bcm_check_bull(struct bcm_softc *sc);
+
+//#define BCM_PULSE
+
+#define BCM_PCI_CAP  1
+#define BCM_PCI_ECAP 2
+
+static inline struct bcm_pci_cap*
+pci_find_cap(struct bcm_softc *sc, uint8_t id, uint8_t type)
+{
+	struct bcm_pci_cap *cap = sc->pci_caps;
+
+	while (cap) {
+		if (cap->id == id && cap->type == type)
+			return cap;
+		cap = cap->next;
+	}
+
+	return NULL;
+}
+
+static inline int is_valid_ether_addr(uint8_t *addr)
+{
+	if (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
+		return 0;
+	else
+		return 1;
+}
+
+static inline void
+bcm_set_rx_mode(struct bcm_softc *sc)
+{
+	if (sc->state == BCM_STATE_OPEN) {
+		if (IS_PF(sc)) {
+			bcm_set_storm_rx_mode(sc);
+		} else {
+			sc->rx_mode = BCM_RX_MODE_PROMISC;
+			bcm_vf_set_rx_mode(sc);
+		}
+	} else {
+		PMD_DRV_LOG(NOTICE, "Card is not ready to change mode");
+	}
+}
+
+static inline int pci_read(struct bcm_softc *sc, size_t addr,
+			   void *val, uint8_t size)
+{
+	if (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
+		PMD_DRV_LOG(ERR, "Can't read from PCI config space");
+		return ENXIO;
+	}
+
+	return 0;
+}
+
+static inline int pci_write_word(struct bcm_softc *sc, size_t addr, off_t val)
+{
+	uint16_t val16 = val;
+
+	if (rte_eal_pci_write_config(sc->pci_dev, &val16,
+				     sizeof(val16), addr) <= 0) {
+		PMD_DRV_LOG(ERR, "Can't write to PCI config space");
+		return ENXIO;
+	}
+
+	return 0;
+}
+
+static inline int pci_write_long(struct bcm_softc *sc, size_t addr, off_t val)
+{
+	uint32_t val32 = val;
+	if (rte_eal_pci_write_config(sc->pci_dev, &val32,
+				     sizeof(val32), addr) <= 0) {
+		PMD_DRV_LOG(ERR, "Can't write to PCI config space");
+		return ENXIO;
+	}
+
+	return 0;
+}
+
+#endif /* __BCM_H__ */
diff --git a/lib/librte_pmd_bcm/bcm_ethdev.c b/lib/librte_pmd_bcm/bcm_ethdev.c
new file mode 100644
index 0000000..c56d93b
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_ethdev.c
@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ *
+ * All rights reserved.
+ */
+
+#include "bcm.h"
+#include "bcm_rxtx.h"
+
+#include <rte_dev.h>
+
+/*
+ * The set of PCI devices this driver supports
+ */
+static struct rte_pci_id pci_id_bcm_map[] = {
+#define RTE_PCI_DEV_ID_DECL_BCM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
+#include "rte_pci_dev_ids.h"
+	{ .vendor_id = 0, }
+};
+
+static struct rte_pci_id pci_id_bcmvf_map[] = {
+#define RTE_PCI_DEV_ID_DECL_BCMVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
+#include "rte_pci_dev_ids.h"
+	{ .vendor_id = 0, }
+};
+
+static void
+bcm_link_update(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+	bcm_link_status_update(sc);
+	mb();
+	dev->data->dev_link.link_speed = sc->link_vars.line_speed;
+	switch (sc->link_vars.duplex) {
+		case DUPLEX_FULL:
+			dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
+			break;
+		case DUPLEX_HALF:
+			dev->data->dev_link.link_duplex = ETH_LINK_HALF_DUPLEX;
+			break;
+		default:
+			dev->data->dev_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX;
+	}
+	dev->data->dev_link.link_status = sc->link_vars.link_up;
+}
+
+static void
+bcm_interrupt_action(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+	uint32_t link_status;
+
+	PMD_DRV_LOG(INFO, "Interrupt handled");
+
+	if (bcm_intr_legacy(sc, 0))
+		DELAY_MS(250);
+	if (sc->periodic_flags & PERIODIC_GO)
+		bcm_periodic_callout(sc);
+	link_status = REG_RD(sc, sc->link_params.shmem_base +
+			offsetof(struct shmem_region,
+				port_mb[sc->link_params.port].link_status));
+	if ((link_status & LINK_STATUS_LINK_UP) != dev->data->dev_link.link_status)
+		bcm_link_update(dev);
+}
+
+static __rte_unused void
+bcm_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param)
+{
+	struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
+
+	bcm_interrupt_action(dev);
+	rte_intr_enable(&(dev->pci_dev->intr_handle));
+}
+
+/*
+ * Devops - helper functions can be called from user application
+ */
+
+static int
+bcm_dev_configure(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+	int mp_ncpus = sysconf(_SC_NPROCESSORS_CONF);
+	int ret;
+
+	PMD_INIT_FUNC_TRACE();
+
+	if (dev->data->dev_conf.rxmode.jumbo_frame)
+		sc->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len;
+
+	if (dev->data->nb_tx_queues > dev->data->nb_rx_queues) {
+		PMD_DRV_LOG(ERR, "The number of TX queues is greater than number of RX queues");
+		return -EINVAL;
+	}
+
+	sc->num_queues = MAX(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
+	if (sc->num_queues > mp_ncpus) {
+		PMD_DRV_LOG(ERR, "The number of queues is more than number of CPUs");
+		return -EINVAL;
+	}
+
+	PMD_DRV_LOG(DEBUG, "num_queues=%d, mtu=%d",
+		       sc->num_queues, sc->mtu);
+
+	/* allocate ilt */
+	if (bcm_alloc_ilt_mem(sc) != 0) {
+		PMD_DRV_LOG(ERR, "bcm_alloc_ilt_mem was failed");
+		return -ENXIO;
+	}
+
+	/* allocate the host hardware/software hsi structures */
+	if (bcm_alloc_hsi_mem(sc) != 0) {
+		PMD_DRV_LOG(ERR, "bcm_alloc_hsi_mem was failed");
+		bcm_free_ilt_mem(sc);
+		return -ENXIO;
+	}
+
+	if (IS_VF(sc)) {
+		if (bcm_dma_alloc(sc, sizeof(struct bcm_vf_mbx_msg),
+				  &sc->vf2pf_mbox_mapping, "vf2pf_mbox",
+				  RTE_CACHE_LINE_SIZE) != 0)
+			return -ENOMEM;
+
+		sc->vf2pf_mbox = (struct bcm_vf_mbx_msg *)sc->vf2pf_mbox_mapping.vaddr;
+		if (bcm_dma_alloc(sc, sizeof(struct bcm_vf_bulletin),
+				  &sc->pf2vf_bulletin_mapping, "vf2pf_bull",
+				  RTE_CACHE_LINE_SIZE) != 0)
+			return -ENOMEM;
+
+		sc->pf2vf_bulletin = (struct bcm_vf_bulletin *)sc->pf2vf_bulletin_mapping.vaddr;
+
+		ret = bcm_vf_get_resources(sc, sc->num_queues, sc->num_queues);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int
+bcm_dev_start(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+	int ret = 0;
+
+	PMD_INIT_FUNC_TRACE();
+
+	ret = bcm_init(sc);
+	if (ret) {
+		PMD_DRV_LOG(DEBUG, "bcm_init failed (%d)", ret);
+		return -1;
+	}
+
+	if (IS_PF(sc)) {
+		rte_intr_callback_register(&(dev->pci_dev->intr_handle),
+				bcm_interrupt_handler, (void *)dev);
+
+		if(rte_intr_enable(&(dev->pci_dev->intr_handle)))
+			PMD_DRV_LOG(ERR, "rte_intr_enable failed");
+	}
+
+	ret = bcm_dev_rx_init(dev);
+	if (ret != 0) {
+		PMD_DRV_LOG(DEBUG, "bcm_dev_rx_init returned error code");
+		return -3;
+	}
+
+	/* Print important adapter info for the user. */
+	bcm_print_adapter_info(sc);
+
+	DELAY_MS(2500);
+
+	return ret;
+}
+
+static void
+bcm_dev_stop(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+	int ret = 0;
+
+	PMD_INIT_FUNC_TRACE();
+
+	if (IS_PF(sc)) {
+		rte_intr_disable(&(dev->pci_dev->intr_handle));
+		rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
+				bcm_interrupt_handler, (void *)dev);
+	}
+
+	ret = bcm_nic_unload(sc, UNLOAD_NORMAL, FALSE);
+	if (ret) {
+		PMD_DRV_LOG(DEBUG, "bcm_nic_unload failed (%d)", ret);
+		return;
+	}
+
+	return;
+}
+
+static void
+bcm_dev_close(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+
+	if (IS_VF(sc))
+		bcm_vf_close(sc);
+
+	bcm_dev_clear_queues(dev);
+	memset(&(dev->data->dev_link), 0 , sizeof(struct rte_eth_link));
+
+	/* free the host hardware/software hsi structures */
+	bcm_free_hsi_mem(sc);
+
+	/* free ilt */
+	bcm_free_ilt_mem(sc);
+}
+
+static void
+bcm_promisc_enable(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+	sc->rx_mode = BCM_RX_MODE_PROMISC;
+	bcm_set_rx_mode(sc);
+}
+
+static void
+bcm_promisc_disable(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+	sc->rx_mode = BCM_RX_MODE_NORMAL;
+	bcm_set_rx_mode(sc);
+}
+
+static void
+bcm_dev_allmulticast_enable(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+	sc->rx_mode = BCM_RX_MODE_ALLMULTI;
+	bcm_set_rx_mode(sc);
+}
+
+static void
+bcm_dev_allmulticast_disable(struct rte_eth_dev *dev)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+	sc->rx_mode = BCM_RX_MODE_NORMAL;
+	bcm_set_rx_mode(sc);
+}
+
+static int
+bcm_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
+{
+	PMD_INIT_FUNC_TRACE();
+
+	int old_link_status = dev->data->dev_link.link_status;
+
+	bcm_link_update(dev);
+
+	return old_link_status == dev->data->dev_link.link_status ? -1 : 0;
+}
+
+static int
+bcmvf_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
+{
+	int old_link_status = dev->data->dev_link.link_status;
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	bcm_link_update(dev);
+
+	bcm_check_bull(sc);
+	if (sc->old_bulletin.valid_bitmap & (1 << CHANNEL_DOWN)) {
+		PMD_DRV_LOG(ERR, "PF indicated channel is down."
+				"VF device is no longer operational");
+		dev->data->dev_link.link_status = 0;
+	}
+
+	return old_link_status == dev->data->dev_link.link_status ? -1 : 0;
+}
+
+static void
+bcm_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+
+	bcm_stats_handle(sc, STATS_EVENT_UPDATE);
+
+	memset(stats, 0, sizeof (struct rte_eth_stats));
+
+	stats->ipackets =
+		HILO_U64(sc->eth_stats.total_unicast_packets_received_hi,
+				sc->eth_stats.total_unicast_packets_received_lo) +
+		HILO_U64(sc->eth_stats.total_multicast_packets_received_hi,
+				sc->eth_stats.total_multicast_packets_received_lo) +
+		HILO_U64(sc->eth_stats.total_broadcast_packets_received_hi,
+				sc->eth_stats.total_broadcast_packets_received_lo);
+
+	stats->opackets =
+		HILO_U64(sc->eth_stats.total_unicast_packets_transmitted_hi,
+				sc->eth_stats.total_unicast_packets_transmitted_lo) +
+		HILO_U64(sc->eth_stats.total_multicast_packets_transmitted_hi,
+				sc->eth_stats.total_multicast_packets_transmitted_lo) +
+		HILO_U64(sc->eth_stats.total_broadcast_packets_transmitted_hi,
+				sc->eth_stats.total_broadcast_packets_transmitted_lo);
+
+	stats->ibytes =
+		HILO_U64(sc->eth_stats.total_bytes_received_hi,
+				sc->eth_stats.total_bytes_received_lo);
+
+	stats->obytes =
+		HILO_U64(sc->eth_stats.total_bytes_transmitted_hi,
+				sc->eth_stats.total_bytes_transmitted_lo);
+
+	stats->ierrors =
+		HILO_U64(sc->eth_stats.error_bytes_received_hi,
+				sc->eth_stats.error_bytes_received_lo);
+
+	stats->oerrors = 0;
+
+	stats->rx_nombuf =
+		HILO_U64(sc->eth_stats.no_buff_discard_hi,
+				sc->eth_stats.no_buff_discard_lo);
+}
+
+static void
+bcm_dev_infos_get(struct rte_eth_dev *dev, __rte_unused struct rte_eth_dev_info *dev_info)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+	dev_info->max_rx_queues  = sc->max_rx_queues;
+	dev_info->max_tx_queues  = sc->max_tx_queues;
+	dev_info->min_rx_bufsize = BCM_MIN_RX_BUF_SIZE;
+	dev_info->max_rx_pktlen  = BCM_MAX_RX_PKT_LEN;
+	dev_info->max_mac_addrs  = BCM_MAX_MAC_ADDRS;
+}
+
+static void
+bcm_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
+		uint32_t index, uint32_t pool)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	if (sc->mac_ops.mac_addr_add)
+		sc->mac_ops.mac_addr_add(dev, mac_addr, index, pool);
+}
+
+static void
+bcm_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
+{
+	struct bcm_softc *sc = dev->data->dev_private;
+
+	if (sc->mac_ops.mac_addr_remove)
+		sc->mac_ops.mac_addr_remove(dev, index);
+}
+
+static struct eth_dev_ops bcm_eth_dev_ops = {
+	.dev_configure                = bcm_dev_configure,
+	.dev_start                    = bcm_dev_start,
+	.dev_stop                     = bcm_dev_stop,
+	.dev_close                    = bcm_dev_close,
+	.promiscuous_enable           = bcm_promisc_enable,
+	.promiscuous_disable          = bcm_promisc_disable,
+	.allmulticast_enable          = bcm_dev_allmulticast_enable,
+	.allmulticast_disable         = bcm_dev_allmulticast_disable,
+	.link_update                  = bcm_dev_link_update,
+	.stats_get                    = bcm_dev_stats_get,
+	.dev_infos_get                = bcm_dev_infos_get,
+	.rx_queue_setup               = bcm_dev_rx_queue_setup,
+	.rx_queue_release             = bcm_dev_rx_queue_release,
+	.tx_queue_setup               = bcm_dev_tx_queue_setup,
+	.tx_queue_release             = bcm_dev_tx_queue_release,
+	.mac_addr_add                 = bcm_mac_addr_add,
+	.mac_addr_remove              = bcm_mac_addr_remove,
+};
+
+/*
+ * dev_ops for virtual function
+ */
+static struct eth_dev_ops bcmvf_eth_dev_ops = {
+	.dev_configure                = bcm_dev_configure,
+	.dev_start                    = bcm_dev_start,
+	.dev_stop                     = bcm_dev_stop,
+	.dev_close                    = bcm_dev_close,
+	.promiscuous_enable           = bcm_promisc_enable,
+	.promiscuous_disable          = bcm_promisc_disable,
+	.allmulticast_enable          = bcm_dev_allmulticast_enable,
+	.allmulticast_disable         = bcm_dev_allmulticast_disable,
+	.link_update                  = bcmvf_dev_link_update,
+	.stats_get                    = bcm_dev_stats_get,
+	.dev_infos_get                = bcm_dev_infos_get,
+	.rx_queue_setup               = bcm_dev_rx_queue_setup,
+	.rx_queue_release             = bcm_dev_rx_queue_release,
+	.tx_queue_setup               = bcm_dev_tx_queue_setup,
+	.tx_queue_release             = bcm_dev_tx_queue_release,
+	.mac_addr_add                 = bcm_mac_addr_add,
+	.mac_addr_remove              = bcm_mac_addr_remove,
+};
+
+
+static int
+bcm_common_dev_init(struct rte_eth_dev *eth_dev, int is_vf)
+{
+	int ret = 0;
+	struct rte_pci_device *pci_dev;
+	struct bcm_softc *sc;
+
+	PMD_INIT_FUNC_TRACE();
+
+	eth_dev->dev_ops = is_vf ? &bcmvf_eth_dev_ops : &bcm_eth_dev_ops;
+	pci_dev = eth_dev->pci_dev;
+	sc = eth_dev->data->dev_private;
+	sc->pcie_bus    = pci_dev->addr.bus;
+	sc->pcie_device = pci_dev->addr.devid;
+
+	if (is_vf)
+		sc->flags = BCM_IS_VF_FLAG;
+
+	sc->devinfo.vendor_id    = pci_dev->id.vendor_id;
+        sc->devinfo.device_id    = pci_dev->id.device_id;
+        sc->devinfo.subvendor_id = pci_dev->id.subsystem_vendor_id;
+        sc->devinfo.subdevice_id = pci_dev->id.subsystem_device_id;
+
+	sc->pcie_func = pci_dev->addr.function;
+	sc->bar[BAR0].base_addr = (void *)pci_dev->mem_resource[0].addr;
+	if (is_vf)
+		sc->bar[BAR1].base_addr = (void *)
+			((uint64_t)pci_dev->mem_resource[0].addr + PXP_VF_ADDR_DB_START);
+	else
+		sc->bar[BAR1].base_addr = pci_dev->mem_resource[2].addr;
+
+	assert(sc->bar[BAR0].base_addr);
+	assert(sc->bar[BAR1].base_addr);
+
+	bcm_load_firmware(sc);
+	assert(sc->firmware);
+
+	if (eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf & ETH_RSS_IPV4_UDP)
+		sc->udp_rss = 1;
+
+	sc->rx_budget = BCM_RX_BUDGET;
+	sc->hc_rx_ticks = BCM_RX_TICKS;
+	sc->hc_tx_ticks = BCM_TX_TICKS;
+
+	sc->interrupt_mode = INTR_MODE_SINGLE_MSIX;
+	sc->rx_mode = BCM_RX_MODE_NORMAL;
+
+	sc->pci_dev = pci_dev;
+	ret = bcm_attach(sc);
+	if (ret) {
+		PMD_DRV_LOG(ERR, "bcm_attach failed (%d)", ret);
+	}
+
+	eth_dev->data->mac_addrs = (struct ether_addr *)sc->link_params.mac_addr;
+
+	PMD_DRV_LOG(INFO, "pcie_bus=%d, pcie_device=%d",
+			sc->pcie_bus, sc->pcie_device);
+	PMD_DRV_LOG(INFO, "bar0.addr=%p, bar1.addr=%p",
+			sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
+	PMD_DRV_LOG(INFO, "port=%d, path=%d, vnic=%d, func=%d",
+			PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
+	PMD_DRV_LOG(INFO, "portID=%d vendorID=0x%x deviceID=0x%x",
+			eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id);
+
+	return ret;
+}
+
+static int
+eth_bcm_dev_init(__rte_unused struct eth_driver *eth_drv,
+                     struct rte_eth_dev *eth_dev)
+{
+	PMD_INIT_FUNC_TRACE();
+	return bcm_common_dev_init(eth_dev, 0);
+}
+
+static int
+eth_bcmvf_dev_init(__rte_unused struct eth_driver *eth_drv,
+                     struct rte_eth_dev *eth_dev)
+{
+	PMD_INIT_FUNC_TRACE();
+	return bcm_common_dev_init(eth_dev, 1);
+}
+
+static struct eth_driver rte_bcm_pmd = {
+	.pci_drv = {
+		.name = "rte_bcm_pmd",
+		.id_table = pci_id_bcm_map,
+		.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
+	},
+	.eth_dev_init = eth_bcm_dev_init,
+	.dev_private_size = sizeof(struct bcm_softc),
+};
+
+/*
+ * virtual function driver struct
+ */
+static struct eth_driver rte_bcmvf_pmd = {
+	.pci_drv = {
+		.name = "rte_bcmvf_pmd",
+		.id_table = pci_id_bcmvf_map,
+		.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	},
+	.eth_dev_init = eth_bcmvf_dev_init,
+	.dev_private_size = sizeof(struct bcm_softc),
+};
+
+static int rte_bcm_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
+{
+	PMD_INIT_FUNC_TRACE();
+	rte_eth_driver_register(&rte_bcm_pmd);
+
+	return 0;
+}
+
+static int rte_bcmvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
+{
+	PMD_INIT_FUNC_TRACE();
+	rte_eth_driver_register(&rte_bcmvf_pmd);
+
+	return 0;
+}
+
+static struct rte_driver rte_bcm_driver = {
+	.type = PMD_PDEV,
+	.init = rte_bcm_pmd_init,
+};
+
+static struct rte_driver rte_bcmvf_driver = {
+	.type = PMD_PDEV,
+	.init = rte_bcmvf_pmd_init,
+};
+
+PMD_REGISTER_DRIVER(rte_bcm_driver);
+PMD_REGISTER_DRIVER(rte_bcmvf_driver);
diff --git a/lib/librte_pmd_bcm/bcm_ethdev.h b/lib/librte_pmd_bcm/bcm_ethdev.h
new file mode 100644
index 0000000..da3abe3
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_ethdev.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ *
+ * All rights reserved.
+ */
+
+#ifndef PMD_BCM_ETHDEV_H
+#define PMD_BCM_ETHDEV_H
+
+#include <sys/queue.h>
+#include <sys/param.h>
+#include <sys/user.h>
+#include <sys/stat.h>
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdarg.h>
+#include <inttypes.h>
+#include <assert.h>
+
+#include <rte_byteorder.h>
+#include <rte_common.h>
+#include <rte_cycles.h>
+#include <rte_log.h>
+#include <rte_debug.h>
+#include <rte_pci.h>
+#include <rte_malloc.h>
+#include <rte_ethdev.h>
+#include <rte_spinlock.h>
+#include <rte_memzone.h>
+#include <rte_eal.h>
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+
+#include "bcm_rxtx.h"
+#include "bcm_logs.h"
+
+#define DELAY(x) rte_delay_us(x)
+#define DELAY_MS(x) rte_delay_ms(x)
+#define usec_delay(x) DELAY(x)
+#define msec_delay(x) DELAY(1000*(x))
+
+#define FALSE               0
+#define TRUE                1
+
+#define false               0
+#define true                1
+#define min(a,b)        RTE_MIN(a,b)
+
+#define mb()    rte_mb()
+#define wmb()   rte_wmb()
+#define rmb()   rte_rmb()
+
+
+#define MAX_QUEUES sysconf(_SC_NPROCESSORS_CONF)
+
+#define BCM_MIN_RX_BUF_SIZE 1024
+#define BCM_MAX_RX_PKT_LEN  15872
+#define BCM_MAX_MAC_ADDRS   1
+
+/* Hardware RX tick timer (usecs) */
+#define BCM_RX_TICKS 25
+/* Hardware TX tick timer (usecs) */
+#define BCM_TX_TICKS 50
+/* Maximum number of Rx packets to process at a time */
+#define BCM_RX_BUDGET 0xffffffff
+
+#endif
+
+/* MAC address operations */
+struct bcm_mac_ops {
+	void (*mac_addr_add)(struct rte_eth_dev *dev, struct ether_addr *addr,
+			uint16_t index, uint32_t pool);                           /* not implemented yet */
+	void (*mac_addr_remove)(struct rte_eth_dev *dev, uint16_t index); /* not implemented yet */
+};
diff --git a/lib/librte_pmd_bcm/bcm_logs.h b/lib/librte_pmd_bcm/bcm_logs.h
new file mode 100644
index 0000000..d562415
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_logs.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ *
+ * All rights reserved.
+ */
+
+#ifndef _PMD_LOGS_H_
+#define _PMD_LOGS_H_
+
+#define PMD_INIT_LOG(level, fmt, args...) \
+	rte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \
+		"PMD: %s(): " fmt "\n", __func__, ##args)
+
+#ifdef RTE_LIBRTE_BCM_DEBUG_INIT
+#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>")
+#else
+#define PMD_INIT_FUNC_TRACE() do { } while(0)
+#endif
+
+#ifdef RTE_LIBRTE_BCM_DEBUG_RX
+#define PMD_RX_LOG(level, fmt, args...) \
+	RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
+#else
+#define PMD_RX_LOG(level, fmt, args...) do { } while(0)
+#endif
+
+#ifdef RTE_LIBRTE_BCM_DEBUG_TX
+#define PMD_TX_LOG(level, fmt, args...) \
+	RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
+#else
+#define PMD_TX_LOG(level, fmt, args...) do { } while(0)
+#endif
+
+#ifdef RTE_LIBRTE_BCM_DEBUG_TX_FREE
+#define PMD_TX_FREE_LOG(level, fmt, args...) \
+	RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args)
+#else
+#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)
+#endif
+
+#ifdef RTE_LIBRTE_BCM_DEBUG_DRIVER
+#define PMD_DRV_LOG_RAW(level, fmt, args...) \
+	RTE_LOG(level, PMD, "%s(): " fmt, __func__, ## args)
+#else
+#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)
+#endif
+
+#define PMD_DRV_LOG(level, fmt, args...) \
+	PMD_DRV_LOG_RAW(level, fmt "\n", ## args)
+
+#endif /* _PMD_LOGS_H_ */
diff --git a/lib/librte_pmd_bcm/bcm_rxtx.c b/lib/librte_pmd_bcm/bcm_rxtx.c
new file mode 100644
index 0000000..f263e95
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_rxtx.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ *
+ * All rights reserved.
+ */
+
+#include "bcm.h"
+#include "bcm_rxtx.h"
+
+static inline struct rte_mbuf *
+bcm_rxmbuf_alloc(struct rte_mempool *mp)
+{
+	struct rte_mbuf *m;
+
+	m = __rte_mbuf_raw_alloc(mp);
+	__rte_mbuf_sanity_check(m, 0);
+
+	return m;
+}
+
+static const struct rte_memzone *
+ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
+                      uint16_t queue_id, uint32_t ring_size, int socket_id)
+{
+	char z_name[RTE_MEMZONE_NAMESIZE];
+	const struct rte_memzone *mz;
+
+	snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
+			dev->driver->pci_drv.name, ring_name, dev->data->port_id, queue_id);
+
+	mz = rte_memzone_lookup(z_name);
+	if (mz)
+		return mz;
+
+	return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0, BCM_PAGE_SIZE);
+}
+
+static void
+bcm_rx_queue_release(struct bcm_rx_queue *rx_queue)
+{
+	uint16_t i;
+	struct rte_mbuf **sw_ring;
+
+	if (NULL != rx_queue) {
+
+		sw_ring = rx_queue->sw_ring;
+		if (NULL != sw_ring) {
+			for (i = 0; i < rx_queue->nb_rx_desc; i++) {
+				if (NULL != sw_ring[i])
+					rte_pktmbuf_free(sw_ring[i]);
+			}
+			rte_free(sw_ring);
+		}
+		rte_free(rx_queue);
+	}
+}
+
+void
+bcm_dev_rx_queue_release(void *rxq)
+{
+        bcm_rx_queue_release(rxq);
+}
+
+int
+bcm_dev_rx_queue_setup(struct rte_eth_dev *dev,
+                       uint16_t queue_idx,
+                       uint16_t nb_desc,
+                       unsigned int socket_id,
+                       const struct rte_eth_rxconf *rx_conf,
+                       struct rte_mempool *mp)
+{
+	uint16_t j, idx;
+	const struct rte_memzone *dma;
+	struct bcm_rx_queue *rxq;
+	uint32_t dma_size;
+	struct rte_mbuf *mbuf;
+	struct bcm_softc *sc = dev->data->dev_private;
+	struct bcm_fastpath *fp = &sc->fp[queue_idx];
+	struct eth_rx_cqe_next_page *nextpg;
+	phys_addr_t *rx_bd;
+	phys_addr_t busaddr;
+
+	/* First allocate the rx queue data structure */
+	rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct bcm_rx_queue),
+				 RTE_CACHE_LINE_SIZE, socket_id);
+	if (NULL == rxq) {
+		PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!");
+		return (-ENOMEM);
+	}
+	rxq->sc = sc;
+	rxq->mb_pool = mp;
+	rxq->queue_id = queue_idx;
+	rxq->port_id = dev->data->port_id;
+	rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 : ETHER_CRC_LEN);
+
+	rxq->nb_rx_pages = 1;
+	while (USABLE_RX_BD(rxq) < nb_desc)
+		rxq->nb_rx_pages <<= 1;
+
+	rxq->nb_rx_desc  = TOTAL_RX_BD(rxq);
+	sc->rx_ring_size = USABLE_RX_BD(rxq);
+	rxq->nb_cq_pages = RCQ_BD_PAGES(rxq);
+
+	rxq->rx_free_thresh = rx_conf->rx_free_thresh ?
+		rx_conf->rx_free_thresh : DEFAULT_RX_FREE_THRESH;
+
+	PMD_INIT_LOG(DEBUG, "fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, "
+		       "total_bd=%lu, rx_pages=%u, cq_pages=%u",
+		       queue_idx, nb_desc, rxq->rx_free_thresh, USABLE_RX_BD(rxq),
+		       TOTAL_RX_BD(rxq), rxq->nb_rx_pages, rxq->nb_cq_pages);
+
+	/* Allocate RX ring hardware descriptors */
+	dma_size = rxq->nb_rx_desc * sizeof(struct eth_rx_bd);
+	dma = ring_dma_zone_reserve(dev, "hw_ring", queue_idx, dma_size, socket_id);
+	if (NULL == dma) {
+		PMD_RX_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed!");
+		bcm_rx_queue_release(rxq);
+		return (-ENOMEM);
+	}
+	fp->rx_desc_mapping = rxq->rx_ring_phys_addr = (uint64_t)dma->phys_addr;
+	rxq->rx_ring = (uint64_t*)dma->addr;
+	memset((void *)rxq->rx_ring, 0, dma_size);
+
+	/* Link the RX chain pages. */
+	for (j = 1; j <= rxq->nb_rx_pages; j++) {
+		rx_bd = &rxq->rx_ring[TOTAL_RX_BD_PER_PAGE * j - 2];
+		busaddr = rxq->rx_ring_phys_addr + BCM_PAGE_SIZE * (j % rxq->nb_rx_pages);
+		*rx_bd = busaddr;
+	}
+
+	/* Allocate software ring */
+	dma_size = rxq->nb_rx_desc * sizeof(struct bcm_rx_entry);
+	rxq->sw_ring = rte_zmalloc_socket("sw_ring", dma_size,
+					  RTE_CACHE_LINE_SIZE,
+					  socket_id);
+	if (NULL == rxq->sw_ring) {
+		PMD_RX_LOG(ERR, "rte_zmalloc for sw_ring failed!");
+		bcm_rx_queue_release(rxq);
+		return (-ENOMEM);
+	}
+
+	/* Initialize software ring entries */
+	rxq->rx_mbuf_alloc = 0;
+	for (idx = 0; idx < rxq->nb_rx_desc; idx = NEXT_RX_BD(idx)) {
+		mbuf = bcm_rxmbuf_alloc(mp);
+		if (NULL == mbuf) {
+			PMD_RX_LOG(ERR, "RX mbuf alloc failed queue_id=%u, idx=%d",
+				   (unsigned)rxq->queue_id, idx);
+			bcm_rx_queue_release(rxq);
+			return (-ENOMEM);
+		}
+		rxq->sw_ring[idx] = mbuf;
+		rxq->rx_ring[idx] = mbuf->buf_physaddr;
+		rxq->rx_mbuf_alloc++;
+	}
+	rxq->pkt_first_seg = NULL;
+	rxq->pkt_last_seg = NULL;
+	rxq->rx_bd_head = 0;
+	rxq->rx_bd_tail = idx;
+
+	/* Allocate CQ chain. */
+	dma_size = BCM_RX_CHAIN_PAGE_SZ * rxq->nb_cq_pages;
+	dma = ring_dma_zone_reserve(dev, "bcm_rcq", queue_idx, dma_size, socket_id);
+	if (NULL == dma) {
+		PMD_RX_LOG(ERR, "RCQ  alloc failed");
+		return (-ENOMEM);
+	}
+	fp->rx_comp_mapping = rxq->cq_ring_phys_addr = (uint64_t)dma->phys_addr;
+	rxq->cq_ring = (union eth_rx_cqe*)dma->addr;
+
+	/* Link the CQ chain pages. */
+	for (j = 1; j <= rxq->nb_cq_pages; j++) {
+		nextpg = &rxq->cq_ring[TOTAL_RCQ_ENTRIES_PER_PAGE * j - 1].next_page_cqe;
+		busaddr = rxq->cq_ring_phys_addr + BCM_PAGE_SIZE * (j % rxq->nb_cq_pages);
+		nextpg->addr_hi = rte_cpu_to_le_32(U64_HI(busaddr));
+		nextpg->addr_lo = rte_cpu_to_le_32(U64_LO(busaddr));
+	}
+	rxq->rx_cq_head = 0;
+	rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
+
+	dev->data->rx_queues[queue_idx] = rxq;
+	if (!sc->rx_queues) sc->rx_queues = dev->data->rx_queues;
+
+	return 0;
+}
+
+static void
+bcm_tx_queue_release(struct bcm_tx_queue *tx_queue)
+{
+	uint16_t i;
+	struct rte_mbuf **sw_ring;
+
+	if (NULL != tx_queue) {
+
+		sw_ring = tx_queue->sw_ring;
+		if (NULL != sw_ring) {
+			for (i = 0; i < tx_queue->nb_tx_desc; i++) {
+				if (NULL != sw_ring[i])
+					rte_pktmbuf_free(sw_ring[i]);
+			}
+			rte_free(sw_ring);
+		}
+		rte_free(tx_queue);
+	}
+}
+
+void
+bcm_dev_tx_queue_release(void *txq)
+{
+	bcm_tx_queue_release(txq);
+}
+
+static uint16_t
+bcm_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
+{
+	struct bcm_tx_queue *txq;
+	struct bcm_softc *sc;
+	struct bcm_fastpath *fp;
+	uint32_t burst, nb_tx;
+	struct rte_mbuf **m = tx_pkts;
+	int ret;
+
+	txq = p_txq;
+	sc = txq->sc;
+	fp = &sc->fp[txq->queue_id];
+
+	nb_tx = nb_pkts;
+
+	do {
+		burst = RTE_MIN(nb_pkts, RTE_PMD_BCM_TX_MAX_BURST);
+
+		ret = bcm_tx_encap(txq, m, burst);
+		if (unlikely(ret)) {
+			PMD_TX_LOG(ERR, "tx_encap failed!");
+		}
+
+		bcm_update_fp_sb_idx(fp);
+
+		if ((txq->nb_tx_desc - txq->nb_tx_avail) > txq->tx_free_thresh) {
+			bcm_txeof(sc, fp);
+		}
+
+		if (unlikely(ret == ENOMEM)) {
+			break;
+		}
+
+		m += burst;
+		nb_pkts -= burst;
+
+	} while (nb_pkts);
+
+	return nb_tx - nb_pkts;
+}
+
+int
+bcm_dev_tx_queue_setup(struct rte_eth_dev *dev,
+		       uint16_t queue_idx,
+		       uint16_t nb_desc,
+		       unsigned int socket_id,
+		       const struct rte_eth_txconf *tx_conf)
+{
+	uint16_t i;
+	unsigned int tsize;
+	const struct rte_memzone *tz;
+	struct bcm_tx_queue *txq;
+	struct eth_tx_next_bd *tx_n_bd;
+	uint64_t busaddr;
+	struct bcm_softc *sc = dev->data->dev_private;
+	struct bcm_fastpath *fp = &sc->fp[queue_idx];
+
+	/* First allocate the tx queue data structure */
+	txq = rte_zmalloc("ethdev TX queue", sizeof(struct bcm_tx_queue),
+			  RTE_CACHE_LINE_SIZE);
+	if (txq == NULL)
+		return (-ENOMEM);
+	txq->sc = sc;
+
+	txq->nb_tx_pages = 1;
+	while (USABLE_TX_BD(txq) < nb_desc)
+		txq->nb_tx_pages <<= 1;
+
+	txq->nb_tx_desc  = TOTAL_TX_BD(txq);
+	sc->tx_ring_size = TOTAL_TX_BD(txq);
+
+	txq->tx_free_thresh = tx_conf->tx_free_thresh ?
+		tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH;
+
+	PMD_INIT_LOG(DEBUG, "fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, "
+		     "total_bd=%lu, tx_pages=%u",
+		     queue_idx, nb_desc, txq->tx_free_thresh, USABLE_TX_BD(txq),
+		     TOTAL_TX_BD(txq), txq->nb_tx_pages);
+
+	/* Allocate TX ring hardware descriptors */
+	tsize = txq->nb_tx_desc * sizeof(union eth_tx_bd_types);
+	tz = ring_dma_zone_reserve(dev, "tx_hw_ring", queue_idx, tsize, socket_id);
+	if (tz == NULL) {
+		bcm_tx_queue_release(txq);
+		return (-ENOMEM);
+	}
+	fp->tx_desc_mapping = txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
+	txq->tx_ring = (union eth_tx_bd_types *) tz->addr;
+	memset(txq->tx_ring, 0, tsize);
+
+	/* Allocate software ring */
+	tsize = txq->nb_tx_desc * sizeof(struct rte_mbuf *);
+	txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize,
+				   RTE_CACHE_LINE_SIZE);
+	if (txq->sw_ring == NULL) {
+		bcm_tx_queue_release(txq);
+		return (-ENOMEM);
+	}
+
+	/* PMD_DRV_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
+	   txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr); */
+
+	/* Link TX pages */
+	for (i = 1; i <= txq->nb_tx_pages; i++) {
+		tx_n_bd = &txq->tx_ring[TOTAL_TX_BD_PER_PAGE * i - 1].next_bd;
+		busaddr = txq->tx_ring_phys_addr + BCM_PAGE_SIZE * (i % txq->nb_tx_pages);
+		tx_n_bd->addr_hi = rte_cpu_to_le_32(U64_HI(busaddr));
+		tx_n_bd->addr_lo = rte_cpu_to_le_32(U64_LO(busaddr));
+		/* PMD_DRV_LOG(DEBUG, "link tx page %lu", (TOTAL_TX_BD_PER_PAGE * i - 1)); */
+	}
+
+	txq->queue_id = queue_idx;
+	txq->port_id = dev->data->port_id;
+	txq->tx_pkt_tail = 0;
+	txq->tx_pkt_head = 0;
+	txq->tx_bd_tail = 0;
+	txq->tx_bd_head = 0;
+	txq->nb_tx_avail = txq->nb_tx_desc;
+	dev->tx_pkt_burst = bcm_xmit_pkts;
+	dev->data->tx_queues[queue_idx] = txq;
+	if (!sc->tx_queues) sc->tx_queues = dev->data->tx_queues;
+
+	return 0;
+}
+
+static inline void
+bcm_upd_rx_prod_fast(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		uint16_t rx_bd_prod, uint16_t rx_cq_prod)
+{
+	union ustorm_eth_rx_producers rx_prods;
+
+	rx_prods.prod.bd_prod  = rx_bd_prod;
+	rx_prods.prod.cqe_prod = rx_cq_prod;
+
+	REG_WR(sc, fp->ustorm_rx_prods_offset, rx_prods.raw_data[0]);
+}
+
+static uint16_t
+bcm_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
+{
+	struct bcm_rx_queue *rxq = p_rxq;
+	struct bcm_softc *sc = rxq->sc;
+	struct bcm_fastpath *fp = &sc->fp[rxq->queue_id];
+	uint32_t nb_rx = 0;
+	uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
+	uint16_t bd_cons, bd_prod;
+	struct rte_mbuf *new_mb;
+	uint16_t rx_pref;
+	struct eth_fast_path_rx_cqe *cqe_fp;
+	uint16_t len, pad;
+	struct rte_mbuf *rx_mb = NULL;
+
+	hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
+	if ((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
+			USABLE_RCQ_ENTRIES_PER_PAGE) {
+		++hw_cq_cons;
+	}
+
+	bd_cons = rxq->rx_bd_head;
+	bd_prod = rxq->rx_bd_tail;
+	sw_cq_cons = rxq->rx_cq_head;
+	sw_cq_prod = rxq->rx_cq_tail;
+
+	while (nb_rx < nb_pkts && sw_cq_cons != hw_cq_cons) {
+
+		bd_prod &= MAX_RX_BD(rxq);
+		bd_cons &= MAX_RX_BD(rxq);
+
+		cqe_fp = &rxq->cq_ring[sw_cq_cons & MAX_RX_BD(rxq)].fast_path_cqe;
+
+		if (unlikely(CQE_TYPE_SLOW(cqe_fp->type_error_flags & ETH_FAST_PATH_RX_CQE_TYPE))) {
+			PMD_RX_LOG(ERR, "slowpath event during traffic processing");
+			break;
+		}
+
+		if (unlikely(cqe_fp->type_error_flags & ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
+			PMD_RX_LOG(ERR, "flags 0x%x rx packet %u",
+					cqe_fp->type_error_flags, sw_cq_cons);
+			goto next_rx;
+		}
+
+		len = cqe_fp->pkt_len_or_gro_seg_len;
+		pad = cqe_fp->placement_offset;
+
+		new_mb = bcm_rxmbuf_alloc(rxq->mb_pool);
+		if (unlikely(!new_mb)) {
+			PMD_RX_LOG(ERR, "mbuf alloc fail fp[%02d]", fp->index);
+			goto next_rx;
+		}
+
+		rx_mb = rxq->sw_ring[bd_cons];
+		rxq->sw_ring[bd_cons] = new_mb;
+		rxq->rx_ring[bd_prod] = new_mb->buf_physaddr;
+
+		rx_pref = NEXT_RX_BD(bd_cons) & MAX_RX_BD(rxq);
+		rte_prefetch0(rxq->sw_ring[rx_pref]);
+		if ((rx_pref & 0x3) == 0) {
+			rte_prefetch0(&rxq->rx_ring[rx_pref]);
+			rte_prefetch0(&rxq->sw_ring[rx_pref]);
+		}
+
+		rx_mb->data_off = pad;
+		rx_mb->nb_segs = 1;
+		rx_mb->next = NULL;
+		rx_mb->pkt_len = rx_mb->data_len = len;
+		rx_mb->port = rxq->port_id;
+		rx_mb->buf_len = len + pad;
+		rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
+
+		/*
+		 * If we received a packet with a vlan tag,
+		 * attach that information to the packet.
+		 */
+		if (cqe_fp->pars_flags.flags & PARSING_FLAGS_VLAN) {
+			rx_mb->vlan_tci = cqe_fp->vlan_tag;
+			rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
+		}
+
+		rx_pkts[nb_rx] = rx_mb;
+		nb_rx++;
+
+		/* limit spinning on the queue */
+		if (unlikely(nb_rx == sc->rx_budget)) {
+			PMD_RX_LOG(ERR, "Limit spinning on the queue");
+			break;
+		}
+
+next_rx:
+		bd_cons    = NEXT_RX_BD(bd_cons);
+		bd_prod    = NEXT_RX_BD(bd_prod);
+		sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
+		sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
+	}
+	rxq->rx_bd_head = bd_cons;
+	rxq->rx_bd_tail = bd_prod;
+	rxq->rx_cq_head = sw_cq_cons;
+	rxq->rx_cq_tail = sw_cq_prod;
+
+	bcm_upd_rx_prod_fast(sc, fp, bd_prod, sw_cq_prod);
+
+	return nb_rx;
+}
+
+int
+bcm_dev_rx_init(struct rte_eth_dev *dev)
+{
+	dev->rx_pkt_burst = bcm_recv_pkts;
+
+	return 0;
+}
+
+void
+bcm_dev_clear_queues(struct rte_eth_dev *dev)
+{
+	uint8_t i;
+
+	PMD_INIT_FUNC_TRACE();
+
+	for (i = 0; i < dev->data->nb_tx_queues; i++) {
+		struct bcm_tx_queue *txq = dev->data->tx_queues[i];
+		if (txq != NULL) {
+			bcm_tx_queue_release(txq);
+			dev->data->tx_queues[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < dev->data->nb_rx_queues; i++) {
+		struct bcm_rx_queue *rxq = dev->data->rx_queues[i];
+		if (rxq != NULL) {
+			bcm_rx_queue_release(rxq);
+			dev->data->rx_queues[i] = NULL;
+		}
+	}
+}
diff --git a/lib/librte_pmd_bcm/bcm_rxtx.h b/lib/librte_pmd_bcm/bcm_rxtx.h
new file mode 100644
index 0000000..978b801
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_rxtx.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ *
+ * All rights reserved.
+ */
+
+#ifndef _BCM_RXTX_H_
+#define _BCM_RXTX_H_
+
+
+#define DEFAULT_RX_FREE_THRESH   0
+#define DEFAULT_TX_FREE_THRESH   512
+#define RTE_PMD_BCM_TX_MAX_BURST 1
+
+/**
+ * Structure associated with each descriptor of the RX ring of a RX queue.
+ */
+struct bcm_rx_entry {
+        struct rte_mbuf     *mbuf;                /**< mbuf associated with RX descriptor. */
+};
+
+/**
+ * Structure associated with each RX queue.
+ */
+struct bcm_rx_queue {
+        struct rte_mempool         *mb_pool;             /**< mbuf pool to populate RX ring. */
+        union eth_rx_cqe           *cq_ring;             /**< RCQ ring virtual address. */
+        uint64_t                   cq_ring_phys_addr;    /**< RCQ ring DMA address. */
+        uint64_t                   *rx_ring;             /**< RX ring virtual address. */
+        uint64_t                   rx_ring_phys_addr;    /**< RX ring DMA address. */
+        struct rte_mbuf            **sw_ring;            /**< address of RX software ring. */
+        struct rte_mbuf            *pkt_first_seg;       /**< First segment of current packet. */
+        struct rte_mbuf            *pkt_last_seg;        /**< Last segment of current packet. */
+        uint16_t                   nb_cq_pages;          /**< number of RCQ pages. */
+        uint16_t                   nb_rx_desc;           /**< number of RX descriptors. */
+        uint16_t                   nb_rx_pages;          /**< number of RX pages. */
+        uint16_t                   rx_bd_head;           /**< Index of current rx bd. */
+        uint16_t                   rx_bd_tail;           /**< Index of last rx bd. */
+        uint16_t                   rx_cq_head;           /**< Index of current rcq bd. */
+        uint16_t                   rx_cq_tail;           /**< Index of last rcq bd. */
+        uint16_t                   nb_rx_hold;           /**< number of held free RX desc. */
+        uint16_t                   rx_free_thresh;       /**< max free RX desc to hold. */
+        uint16_t                   queue_id;             /**< RX queue index. */
+        uint8_t                    port_id;              /**< Device port identifier. */
+        uint8_t                    crc_len;              /**< 0 if CRC stripped, 4 otherwise. */
+        struct bcm_softc           *sc;                  /**< Ptr to dev_private data. */
+        uint64_t                   rx_mbuf_alloc;        /**< Number of allocated mbufs. */
+};
+
+/**
+ * Structure associated with each TX queue.
+ */
+struct bcm_tx_queue {
+	/** TX ring virtual address. */
+	union eth_tx_bd_types      *tx_ring;             /**< TX ring virtual address. */
+	uint64_t                   tx_ring_phys_addr;    /**< TX ring DMA address. */
+	struct rte_mbuf            **sw_ring;            /**< virtual address of SW ring. */
+	uint16_t                   tx_pkt_tail;          /**< Index of current tx pkt. */
+	uint16_t                   tx_pkt_head;          /**< Index of last pkt counted by txeof. */
+	uint16_t                   tx_bd_tail;           /**< Index of current tx bd. */
+	uint16_t                   tx_bd_head;           /**< Index of last bd counted by txeof. */
+	uint16_t                   nb_tx_desc;           /**< number of TX descriptors. */
+	uint16_t                   tx_free_thresh;       /**< minimum TX before freeing. */
+	uint16_t                   nb_tx_avail;          /**< Number of TX descriptors available. */
+	uint16_t                   nb_tx_pages;          /**< number of TX pages */
+	uint16_t                   queue_id;             /**< TX queue index. */
+	uint8_t                    port_id;              /**< Device port identifier. */
+	struct bcm_softc           *sc;                  /**< Ptr to dev_private data */
+};
+
+int bcm_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
+                              uint16_t nb_rx_desc, unsigned int socket_id,
+                              const struct rte_eth_rxconf *rx_conf,
+                              struct rte_mempool *mb_pool);
+
+int bcm_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
+                              uint16_t nb_tx_desc, unsigned int socket_id,
+                              const struct rte_eth_txconf *tx_conf);
+
+void bcm_dev_rx_queue_release(void *rxq);
+void bcm_dev_tx_queue_release(void *txq);
+int bcm_dev_rx_init(struct rte_eth_dev *dev);
+void bcm_dev_clear_queues(struct rte_eth_dev *dev);
+
+#endif /* _BCM_RXTX_H_ */
diff --git a/lib/librte_pmd_bcm/bcm_stats.c b/lib/librte_pmd_bcm/bcm_stats.c
new file mode 100644
index 0000000..73d9c1c
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_stats.c
@@ -0,0 +1,1619 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bcm.h"
+#include "bcm_stats.h"
+
+#ifdef __i386__
+#define BITS_PER_LONG 32
+#else
+#define BITS_PER_LONG 64
+#endif
+
+static inline long
+bcm_hilo(uint32_t *hiref)
+{
+    uint32_t lo = *(hiref + 1);
+#if (BITS_PER_LONG == 64)
+    uint32_t hi = *hiref;
+    return HILO_U64(hi, lo);
+#else
+    return lo;
+#endif
+}
+
+static inline uint16_t
+bcm_get_port_stats_dma_len(struct bcm_softc *sc)
+{
+	uint16_t res = 0;
+	uint32_t size;
+
+	/* 'newest' convention - shmem2 contains the size of the port stats */
+	if (SHMEM2_HAS(sc, sizeof_port_stats)) {
+		size = SHMEM2_RD(sc, sizeof_port_stats);
+		if (size) {
+			res = size;
+		}
+
+		/* prevent newer BC from causing buffer overflow */
+		if (res > sizeof(struct host_port_stats)) {
+			res = sizeof(struct host_port_stats);
+		}
+	}
+
+	/*
+	 * Older convention - all BCs support the port stats fields up until
+	 * the 'not_used' field
+	 */
+	if (!res) {
+		res = (offsetof(struct host_port_stats, not_used) + 4);
+
+		/* if PFC stats are supported by the MFW, DMA them as well */
+		if (sc->devinfo.bc_ver >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) {
+			res += (offsetof(struct host_port_stats, pfc_frames_rx_lo) -
+				offsetof(struct host_port_stats, pfc_frames_tx_hi) + 4);
+		}
+	}
+
+	res >>= 2;
+
+	return res;
+}
+
+/*
+ * Init service functions
+ */
+
+/*
+ * Post the next statistics ramrod. Protect it with the lock in
+ * order to ensure the strict order between statistics ramrods
+ * (each ramrod has a sequence number passed in a
+ * sc->fw_stats_req->hdr.drv_stats_counter and ramrods must be
+ * sent in order).
+ */
+static void
+bcm_storm_stats_post(struct bcm_softc *sc)
+{
+	int rc;
+
+	if (!sc->stats_pending) {
+		if (sc->stats_pending) {
+			return;
+		}
+
+		sc->fw_stats_req->hdr.drv_stats_counter =
+			htole16(sc->stats_counter++);
+
+		PMD_DRV_LOG(DEBUG,
+				"sending statistics ramrod %d",
+				le16toh(sc->fw_stats_req->hdr.drv_stats_counter));
+
+		/* adjust the ramrod to include VF queues statistics */
+
+		/* send FW stats ramrod */
+		rc = bcm_sp_post(sc, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
+				U64_HI(sc->fw_stats_req_mapping),
+				U64_LO(sc->fw_stats_req_mapping),
+				NONE_CONNECTION_TYPE);
+		if (rc == 0) {
+			sc->stats_pending = 1;
+		}
+	}
+}
+
+static void
+bcm_hw_stats_post(struct bcm_softc *sc)
+{
+	struct dmae_command *dmae = &sc->stats_dmae;
+	uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+	int loader_idx;
+	uint32_t opcode;
+
+	*stats_comp = DMAE_COMP_VAL;
+	if (CHIP_REV_IS_SLOW(sc)) {
+		return;
+	}
+
+	/* Update MCP's statistics if possible */
+	if (sc->func_stx) {
+		rte_memcpy(BCM_SP(sc, func_stats), &sc->func_stats,
+				sizeof(sc->func_stats));
+	}
+
+	/* loader */
+	if (sc->executer_idx) {
+		loader_idx = PMF_DMAE_C(sc);
+		opcode =  bcm_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
+				TRUE, DMAE_COMP_GRC);
+		opcode = bcm_dmae_opcode_clr_src_reset(opcode);
+
+		memset(dmae, 0, sizeof(struct dmae_command));
+		dmae->opcode = opcode;
+		dmae->src_addr_lo = U64_LO(BCM_SP_MAPPING(sc, dmae[0]));
+		dmae->src_addr_hi = U64_HI(BCM_SP_MAPPING(sc, dmae[0]));
+		dmae->dst_addr_lo = ((DMAE_REG_CMD_MEM +
+					sizeof(struct dmae_command) *
+					(loader_idx + 1)) >> 2);
+		dmae->dst_addr_hi = 0;
+		dmae->len = sizeof(struct dmae_command) >> 2;
+		dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx + 1] >> 2);
+		dmae->comp_addr_hi = 0;
+		dmae->comp_val = 1;
+
+		*stats_comp = 0;
+		bcm_post_dmae(sc, dmae, loader_idx);
+	} else if (sc->func_stx) {
+		*stats_comp = 0;
+		bcm_post_dmae(sc, dmae, INIT_DMAE_C(sc));
+	}
+}
+
+static int
+bcm_stats_comp(struct bcm_softc *sc)
+{
+	uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+	int cnt = 10;
+
+	while (*stats_comp != DMAE_COMP_VAL) {
+		if (!cnt) {
+			PMD_DRV_LOG(ERR, "Timeout waiting for stats finished");
+			break;
+		}
+
+		cnt--;
+		DELAY(1000);
+	}
+
+	return 1;
+}
+
+/*
+ * Statistics service functions
+ */
+
+static void
+bcm_stats_pmf_update(struct bcm_softc *sc)
+{
+	struct dmae_command *dmae;
+	uint32_t opcode;
+	int loader_idx = PMF_DMAE_C(sc);
+	uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+
+	if (sc->devinfo.bc_ver <= 0x06001400) {
+		/*
+		 * Bootcode v6.0.21 fixed a GRC timeout that occurs when accessing
+		 * BRB registers while the BRB block is in reset. The DMA transfer
+		 * below triggers this issue resulting in the DMAE to stop
+		 * functioning. Skip this initial stats transfer for old bootcode
+		 * versions <= 6.0.20.
+		 */
+		return;
+	}
+	/* sanity */
+	if (!sc->port.pmf || !sc->port.port_stx) {
+		PMD_DRV_LOG(ERR, "BUG!");
+		return;
+	}
+
+	sc->executer_idx = 0;
+
+	opcode = bcm_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI, FALSE, 0);
+
+	dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = bcm_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
+	dmae->src_addr_lo = (sc->port.port_stx >> 2);
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, port_stats));
+	dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, port_stats));
+	dmae->len = DMAE_LEN32_RD_MAX;
+	dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+	dmae->comp_addr_hi = 0;
+	dmae->comp_val = 1;
+
+	dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+	dmae->opcode = bcm_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
+	dmae->src_addr_lo = ((sc->port.port_stx >> 2) + DMAE_LEN32_RD_MAX);
+	dmae->src_addr_hi = 0;
+	dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, port_stats) +
+			DMAE_LEN32_RD_MAX * 4);
+	dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, port_stats) +
+			DMAE_LEN32_RD_MAX * 4);
+	dmae->len = (bcm_get_port_stats_dma_len(sc) - DMAE_LEN32_RD_MAX);
+
+	dmae->comp_addr_lo = U64_LO(BCM_SP_MAPPING(sc, stats_comp));
+	dmae->comp_addr_hi = U64_HI(BCM_SP_MAPPING(sc, stats_comp));
+	dmae->comp_val = DMAE_COMP_VAL;
+
+	*stats_comp = 0;
+	bcm_hw_stats_post(sc);
+	bcm_stats_comp(sc);
+}
+
+static void
+bcm_port_stats_init(struct bcm_softc *sc)
+{
+    struct dmae_command *dmae;
+    int port = SC_PORT(sc);
+    uint32_t opcode;
+    int loader_idx = PMF_DMAE_C(sc);
+    uint32_t mac_addr;
+    uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+
+    /* sanity */
+    if (!sc->link_vars.link_up || !sc->port.pmf) {
+        PMD_DRV_LOG(ERR, "BUG!");
+        return;
+    }
+
+    sc->executer_idx = 0;
+
+    /* MCP */
+    opcode = bcm_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
+                             TRUE, DMAE_COMP_GRC);
+
+    if (sc->port.port_stx) {
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo = U64_LO(BCM_SP_MAPPING(sc, port_stats));
+        dmae->src_addr_hi = U64_HI(BCM_SP_MAPPING(sc, port_stats));
+        dmae->dst_addr_lo = sc->port.port_stx >> 2;
+        dmae->dst_addr_hi = 0;
+        dmae->len = bcm_get_port_stats_dma_len(sc);
+        dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+    }
+
+    if (sc->func_stx) {
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo = U64_LO(BCM_SP_MAPPING(sc, func_stats));
+        dmae->src_addr_hi = U64_HI(BCM_SP_MAPPING(sc, func_stats));
+        dmae->dst_addr_lo = (sc->func_stx >> 2);
+        dmae->dst_addr_hi = 0;
+        dmae->len = (sizeof(struct host_func_stats) >> 2);
+        dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+    }
+
+    /* MAC */
+    opcode = bcm_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI,
+                             TRUE, DMAE_COMP_GRC);
+
+    /* EMAC is special */
+    if (sc->link_vars.mac_type == ELINK_MAC_TYPE_EMAC) {
+        mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
+
+        /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_RX_STAT_AC) >> 2;
+        dmae->src_addr_hi = 0;
+        dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, mac_stats));
+        dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, mac_stats));
+        dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
+        dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+
+        /* EMAC_REG_EMAC_RX_STAT_AC_28 */
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo = ((mac_addr + EMAC_REG_EMAC_RX_STAT_AC_28) >> 2);
+        dmae->src_addr_hi = 0;
+        dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, mac_stats) +
+                                   offsetof(struct emac_stats,
+                                            rx_stat_falsecarriererrors));
+        dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, mac_stats) +
+                                   offsetof(struct emac_stats,
+                                            rx_stat_falsecarriererrors));
+        dmae->len = 1;
+        dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+
+        /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo = ((mac_addr + EMAC_REG_EMAC_TX_STAT_AC) >> 2);
+        dmae->src_addr_hi = 0;
+        dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, mac_stats) +
+                                   offsetof(struct emac_stats,
+                                            tx_stat_ifhcoutoctets));
+        dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, mac_stats) +
+                                   offsetof(struct emac_stats,
+                                            tx_stat_ifhcoutoctets));
+        dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
+        dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+    } else {
+        uint32_t tx_src_addr_lo, rx_src_addr_lo;
+        uint16_t rx_len, tx_len;
+
+        /* configure the params according to MAC type */
+        switch (sc->link_vars.mac_type) {
+        case ELINK_MAC_TYPE_BMAC:
+            mac_addr = (port) ? NIG_REG_INGRESS_BMAC1_MEM :
+                                NIG_REG_INGRESS_BMAC0_MEM;
+
+            /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
+               BIGMAC_REGISTER_TX_STAT_GTBYT */
+            if (CHIP_IS_E1x(sc)) {
+                tx_src_addr_lo =
+                    ((mac_addr + BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2);
+                tx_len = ((8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
+                           BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2);
+                rx_src_addr_lo =
+                    ((mac_addr + BIGMAC_REGISTER_RX_STAT_GR64) >> 2);
+                rx_len = ((8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
+                           BIGMAC_REGISTER_RX_STAT_GR64) >> 2);
+            } else {
+                tx_src_addr_lo =
+                    ((mac_addr + BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2);
+                tx_len = ((8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
+                           BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2);
+                rx_src_addr_lo =
+                    ((mac_addr + BIGMAC2_REGISTER_RX_STAT_GR64) >> 2);
+                rx_len = ((8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
+                           BIGMAC2_REGISTER_RX_STAT_GR64) >> 2);
+            }
+
+            break;
+
+        case ELINK_MAC_TYPE_UMAC: /* handled by MSTAT */
+        case ELINK_MAC_TYPE_XMAC: /* handled by MSTAT */
+        default:
+            mac_addr = (port) ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
+            tx_src_addr_lo = ((mac_addr + MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2);
+            rx_src_addr_lo = ((mac_addr + MSTAT_REG_RX_STAT_GR64_LO) >> 2);
+            tx_len =
+                (sizeof(sc->sp->mac_stats.mstat_stats.stats_tx) >> 2);
+            rx_len =
+                (sizeof(sc->sp->mac_stats.mstat_stats.stats_rx) >> 2);
+            break;
+        }
+
+        /* TX stats */
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo = tx_src_addr_lo;
+        dmae->src_addr_hi = 0;
+        dmae->len = tx_len;
+        dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, mac_stats));
+        dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, mac_stats));
+        dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+
+        /* RX stats */
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_hi = 0;
+        dmae->src_addr_lo = rx_src_addr_lo;
+        dmae->dst_addr_lo =
+            U64_LO(BCM_SP_MAPPING(sc, mac_stats) + (tx_len << 2));
+        dmae->dst_addr_hi =
+            U64_HI(BCM_SP_MAPPING(sc, mac_stats) + (tx_len << 2));
+        dmae->len = rx_len;
+        dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+    }
+
+    /* NIG */
+    if (!CHIP_IS_E3(sc)) {
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo =
+            (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
+                    NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
+        dmae->src_addr_hi = 0;
+        dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, nig_stats) +
+                                   offsetof(struct nig_stats,
+                                            egress_mac_pkt0_lo));
+        dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, nig_stats) +
+                                   offsetof(struct nig_stats,
+                                            egress_mac_pkt0_lo));
+        dmae->len = ((2 * sizeof(uint32_t)) >> 2);
+        dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = opcode;
+        dmae->src_addr_lo =
+            (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
+                    NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
+        dmae->src_addr_hi = 0;
+        dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, nig_stats) +
+                                   offsetof(struct nig_stats,
+                                            egress_mac_pkt1_lo));
+        dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, nig_stats) +
+                                   offsetof(struct nig_stats,
+                                            egress_mac_pkt1_lo));
+        dmae->len = ((2 * sizeof(uint32_t)) >> 2);
+        dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+        dmae->comp_addr_hi = 0;
+        dmae->comp_val = 1;
+    }
+
+    dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+    dmae->opcode = bcm_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI,
+                                   TRUE, DMAE_COMP_PCI);
+    dmae->src_addr_lo =
+        (port ? NIG_REG_STAT1_BRB_DISCARD :
+                NIG_REG_STAT0_BRB_DISCARD) >> 2;
+    dmae->src_addr_hi = 0;
+    dmae->dst_addr_lo = U64_LO(BCM_SP_MAPPING(sc, nig_stats));
+    dmae->dst_addr_hi = U64_HI(BCM_SP_MAPPING(sc, nig_stats));
+    dmae->len = (sizeof(struct nig_stats) - 4*sizeof(uint32_t)) >> 2;
+
+    dmae->comp_addr_lo = U64_LO(BCM_SP_MAPPING(sc, stats_comp));
+    dmae->comp_addr_hi = U64_HI(BCM_SP_MAPPING(sc, stats_comp));
+    dmae->comp_val = DMAE_COMP_VAL;
+
+    *stats_comp = 0;
+}
+
+static void
+bcm_func_stats_init(struct bcm_softc *sc)
+{
+    struct dmae_command *dmae = &sc->stats_dmae;
+    uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+
+    /* sanity */
+    if (!sc->func_stx) {
+        PMD_DRV_LOG(ERR, "BUG!");
+        return;
+    }
+
+    sc->executer_idx = 0;
+    memset(dmae, 0, sizeof(struct dmae_command));
+
+    dmae->opcode = bcm_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
+                                   TRUE, DMAE_COMP_PCI);
+    dmae->src_addr_lo = U64_LO(BCM_SP_MAPPING(sc, func_stats));
+    dmae->src_addr_hi = U64_HI(BCM_SP_MAPPING(sc, func_stats));
+    dmae->dst_addr_lo = (sc->func_stx >> 2);
+    dmae->dst_addr_hi = 0;
+    dmae->len = (sizeof(struct host_func_stats) >> 2);
+    dmae->comp_addr_lo = U64_LO(BCM_SP_MAPPING(sc, stats_comp));
+    dmae->comp_addr_hi = U64_HI(BCM_SP_MAPPING(sc, stats_comp));
+    dmae->comp_val = DMAE_COMP_VAL;
+
+    *stats_comp = 0;
+}
+
+static void
+bcm_stats_start(struct bcm_softc *sc)
+{
+    /*
+     * VFs travel through here as part of the statistics FSM, but no action
+     * is required
+     */
+    if (IS_VF(sc)) {
+        return;
+    }
+
+    if (sc->port.pmf) {
+        bcm_port_stats_init(sc);
+    }
+
+    else if (sc->func_stx) {
+        bcm_func_stats_init(sc);
+    }
+
+    bcm_hw_stats_post(sc);
+    bcm_storm_stats_post(sc);
+}
+
+static void
+bcm_stats_pmf_start(struct bcm_softc *sc)
+{
+    bcm_stats_comp(sc);
+    bcm_stats_pmf_update(sc);
+    bcm_stats_start(sc);
+}
+
+static void
+bcm_stats_restart(struct bcm_softc *sc)
+{
+    /*
+     * VFs travel through here as part of the statistics FSM, but no action
+     * is required
+     */
+    if (IS_VF(sc)) {
+        return;
+    }
+
+    bcm_stats_comp(sc);
+    bcm_stats_start(sc);
+}
+
+static void
+bcm_bmac_stats_update(struct bcm_softc *sc)
+{
+    struct host_port_stats *pstats = BCM_SP(sc, port_stats);
+    struct bcm_eth_stats *estats = &sc->eth_stats;
+    struct {
+        uint32_t lo;
+        uint32_t hi;
+    } diff;
+
+    if (CHIP_IS_E1x(sc)) {
+        struct bmac1_stats *new = BCM_SP(sc, mac_stats.bmac1_stats);
+
+        /* the macros below will use "bmac1_stats" type */
+        UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
+        UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
+        UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
+        UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
+        UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
+        UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
+        UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
+        UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
+        UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
+
+        UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
+        UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
+        UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
+        UPDATE_STAT64(tx_stat_gt127,
+                      tx_stat_etherstatspkts65octetsto127octets);
+        UPDATE_STAT64(tx_stat_gt255,
+                      tx_stat_etherstatspkts128octetsto255octets);
+        UPDATE_STAT64(tx_stat_gt511,
+                      tx_stat_etherstatspkts256octetsto511octets);
+        UPDATE_STAT64(tx_stat_gt1023,
+                      tx_stat_etherstatspkts512octetsto1023octets);
+        UPDATE_STAT64(tx_stat_gt1518,
+                      tx_stat_etherstatspkts1024octetsto1522octets);
+        UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
+        UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
+        UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
+        UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
+        UPDATE_STAT64(tx_stat_gterr,
+                      tx_stat_dot3statsinternalmactransmiterrors);
+        UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
+    } else {
+        struct bmac2_stats *new = BCM_SP(sc, mac_stats.bmac2_stats);
+        struct bcm_fw_port_stats_old *fwstats = &sc->fw_stats_old;
+
+        /* the macros below will use "bmac2_stats" type */
+        UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
+        UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
+        UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
+        UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
+        UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
+        UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
+        UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
+        UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
+        UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
+        UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
+        UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
+        UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
+        UPDATE_STAT64(tx_stat_gt127,
+                      tx_stat_etherstatspkts65octetsto127octets);
+        UPDATE_STAT64(tx_stat_gt255,
+                      tx_stat_etherstatspkts128octetsto255octets);
+        UPDATE_STAT64(tx_stat_gt511,
+                      tx_stat_etherstatspkts256octetsto511octets);
+        UPDATE_STAT64(tx_stat_gt1023,
+                      tx_stat_etherstatspkts512octetsto1023octets);
+        UPDATE_STAT64(tx_stat_gt1518,
+                      tx_stat_etherstatspkts1024octetsto1522octets);
+        UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
+        UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
+        UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
+        UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
+        UPDATE_STAT64(tx_stat_gterr,
+                      tx_stat_dot3statsinternalmactransmiterrors);
+        UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
+
+        /* collect PFC stats */
+        pstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;
+        pstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;
+        ADD_64(pstats->pfc_frames_tx_hi, fwstats->pfc_frames_tx_hi,
+               pstats->pfc_frames_tx_lo, fwstats->pfc_frames_tx_lo);
+
+        pstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;
+        pstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;
+        ADD_64(pstats->pfc_frames_rx_hi, fwstats->pfc_frames_rx_hi,
+               pstats->pfc_frames_rx_lo, fwstats->pfc_frames_rx_lo);
+    }
+
+    estats->pause_frames_received_hi = pstats->mac_stx[1].rx_stat_mac_xpf_hi;
+    estats->pause_frames_received_lo = pstats->mac_stx[1].rx_stat_mac_xpf_lo;
+
+    estats->pause_frames_sent_hi = pstats->mac_stx[1].tx_stat_outxoffsent_hi;
+    estats->pause_frames_sent_lo = pstats->mac_stx[1].tx_stat_outxoffsent_lo;
+
+    estats->pfc_frames_received_hi = pstats->pfc_frames_rx_hi;
+    estats->pfc_frames_received_lo = pstats->pfc_frames_rx_lo;
+    estats->pfc_frames_sent_hi = pstats->pfc_frames_tx_hi;
+    estats->pfc_frames_sent_lo = pstats->pfc_frames_tx_lo;
+}
+
+static void
+bcm_mstat_stats_update(struct bcm_softc *sc)
+{
+    struct host_port_stats *pstats = BCM_SP(sc, port_stats);
+    struct bcm_eth_stats *estats = &sc->eth_stats;
+    struct mstat_stats *new = BCM_SP(sc, mac_stats.mstat_stats);
+
+    ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
+    ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
+    ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
+    ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
+    ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
+    ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
+    ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
+    ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
+    ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
+    ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
+
+    /* collect pfc stats */
+    ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,
+           pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);
+    ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,
+           pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);
+
+    ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
+    ADD_STAT64(stats_tx.tx_gt127, tx_stat_etherstatspkts65octetsto127octets);
+    ADD_STAT64(stats_tx.tx_gt255, tx_stat_etherstatspkts128octetsto255octets);
+    ADD_STAT64(stats_tx.tx_gt511, tx_stat_etherstatspkts256octetsto511octets);
+    ADD_STAT64(stats_tx.tx_gt1023,
+               tx_stat_etherstatspkts512octetsto1023octets);
+    ADD_STAT64(stats_tx.tx_gt1518,
+               tx_stat_etherstatspkts1024octetsto1522octets);
+    ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
+
+    ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
+    ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
+    ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
+
+    ADD_STAT64(stats_tx.tx_gterr, tx_stat_dot3statsinternalmactransmiterrors);
+    ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
+
+    estats->etherstatspkts1024octetsto1522octets_hi =
+        pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_hi;
+    estats->etherstatspkts1024octetsto1522octets_lo =
+        pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_lo;
+
+    estats->etherstatspktsover1522octets_hi =
+        pstats->mac_stx[1].tx_stat_mac_2047_hi;
+    estats->etherstatspktsover1522octets_lo =
+        pstats->mac_stx[1].tx_stat_mac_2047_lo;
+
+    ADD_64(estats->etherstatspktsover1522octets_hi,
+           pstats->mac_stx[1].tx_stat_mac_4095_hi,
+           estats->etherstatspktsover1522octets_lo,
+           pstats->mac_stx[1].tx_stat_mac_4095_lo);
+
+    ADD_64(estats->etherstatspktsover1522octets_hi,
+           pstats->mac_stx[1].tx_stat_mac_9216_hi,
+           estats->etherstatspktsover1522octets_lo,
+           pstats->mac_stx[1].tx_stat_mac_9216_lo);
+
+    ADD_64(estats->etherstatspktsover1522octets_hi,
+           pstats->mac_stx[1].tx_stat_mac_16383_hi,
+           estats->etherstatspktsover1522octets_lo,
+           pstats->mac_stx[1].tx_stat_mac_16383_lo);
+
+    estats->pause_frames_received_hi = pstats->mac_stx[1].rx_stat_mac_xpf_hi;
+    estats->pause_frames_received_lo = pstats->mac_stx[1].rx_stat_mac_xpf_lo;
+
+    estats->pause_frames_sent_hi = pstats->mac_stx[1].tx_stat_outxoffsent_hi;
+    estats->pause_frames_sent_lo = pstats->mac_stx[1].tx_stat_outxoffsent_lo;
+
+    estats->pfc_frames_received_hi = pstats->pfc_frames_rx_hi;
+    estats->pfc_frames_received_lo = pstats->pfc_frames_rx_lo;
+    estats->pfc_frames_sent_hi = pstats->pfc_frames_tx_hi;
+    estats->pfc_frames_sent_lo = pstats->pfc_frames_tx_lo;
+}
+
+static void
+bcm_emac_stats_update(struct bcm_softc *sc)
+{
+    struct emac_stats *new = BCM_SP(sc, mac_stats.emac_stats);
+    struct host_port_stats *pstats = BCM_SP(sc, port_stats);
+    struct bcm_eth_stats *estats = &sc->eth_stats;
+
+    UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
+    UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
+    UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
+    UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
+    UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
+    UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
+    UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
+    UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
+    UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
+    UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
+    UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
+    UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
+    UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
+    UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
+    UPDATE_EXTEND_STAT(tx_stat_outxonsent);
+    UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
+    UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
+    UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
+    UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
+    UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
+    UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
+    UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
+    UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
+    UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
+
+    estats->pause_frames_received_hi =
+        pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
+    estats->pause_frames_received_lo =
+        pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
+    ADD_64(estats->pause_frames_received_hi,
+           pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
+           estats->pause_frames_received_lo,
+           pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
+
+    estats->pause_frames_sent_hi =
+        pstats->mac_stx[1].tx_stat_outxonsent_hi;
+    estats->pause_frames_sent_lo =
+        pstats->mac_stx[1].tx_stat_outxonsent_lo;
+    ADD_64(estats->pause_frames_sent_hi,
+           pstats->mac_stx[1].tx_stat_outxoffsent_hi,
+           estats->pause_frames_sent_lo,
+           pstats->mac_stx[1].tx_stat_outxoffsent_lo);
+}
+
+static int
+bcm_hw_stats_update(struct bcm_softc *sc)
+{
+    struct nig_stats *new = BCM_SP(sc, nig_stats);
+    struct nig_stats *old = &(sc->port.old_nig_stats);
+    struct host_port_stats *pstats = BCM_SP(sc, port_stats);
+    struct bcm_eth_stats *estats = &sc->eth_stats;
+    uint32_t lpi_reg, nig_timer_max;
+    struct {
+        uint32_t lo;
+        uint32_t hi;
+    } diff;
+
+    switch (sc->link_vars.mac_type) {
+    case ELINK_MAC_TYPE_BMAC:
+        bcm_bmac_stats_update(sc);
+        break;
+
+    case ELINK_MAC_TYPE_EMAC:
+        bcm_emac_stats_update(sc);
+        break;
+
+    case ELINK_MAC_TYPE_UMAC:
+    case ELINK_MAC_TYPE_XMAC:
+        bcm_mstat_stats_update(sc);
+        break;
+
+    case ELINK_MAC_TYPE_NONE: /* unreached */
+        PMD_DRV_LOG(DEBUG,
+              "stats updated by DMAE but no MAC active");
+        return -1;
+
+    default: /* unreached */
+        PMD_DRV_LOG(ERR, "stats update failed, unknown MAC type");
+    }
+
+    ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
+                  new->brb_discard - old->brb_discard);
+    ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
+                  new->brb_truncate - old->brb_truncate);
+
+    if (!CHIP_IS_E3(sc)) {
+        UPDATE_STAT64_NIG(egress_mac_pkt0,
+                          etherstatspkts1024octetsto1522octets);
+        UPDATE_STAT64_NIG(egress_mac_pkt1,
+                          etherstatspktsover1522octets);
+    }
+
+    rte_memcpy(old, new, sizeof(struct nig_stats));
+
+    rte_memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
+           sizeof(struct mac_stx));
+    estats->brb_drop_hi = pstats->brb_drop_hi;
+    estats->brb_drop_lo = pstats->brb_drop_lo;
+
+    pstats->host_port_stats_counter++;
+
+    if (CHIP_IS_E3(sc)) {
+        lpi_reg = (SC_PORT(sc)) ?
+                      MISC_REG_CPMU_LP_SM_ENT_CNT_P1 :
+                      MISC_REG_CPMU_LP_SM_ENT_CNT_P0;
+        estats->eee_tx_lpi += REG_RD(sc, lpi_reg);
+    }
+
+    if (!BCM_NOMCP(sc)) {
+        nig_timer_max = SHMEM_RD(sc, port_mb[SC_PORT(sc)].stat_nig_timer);
+        if (nig_timer_max != estats->nig_timer_max) {
+            estats->nig_timer_max = nig_timer_max;
+            PMD_DRV_LOG(ERR, "invalid NIG timer max (%u)",
+                  estats->nig_timer_max);
+        }
+    }
+
+    return 0;
+}
+
+static int
+bcm_storm_stats_validate_counters(struct bcm_softc *sc)
+{
+    struct stats_counter *counters = &sc->fw_stats_data->storm_counters;
+    uint16_t cur_stats_counter;
+
+    /*
+     * Make sure we use the value of the counter
+     * used for sending the last stats ramrod.
+     */
+    cur_stats_counter = (sc->stats_counter - 1);
+
+    /* are storm stats valid? */
+    if (le16toh(counters->xstats_counter) != cur_stats_counter) {
+        PMD_DRV_LOG(DEBUG,
+              "stats not updated by xstorm, "
+              "counter 0x%x != stats_counter 0x%x",
+              le16toh(counters->xstats_counter), sc->stats_counter);
+        return -EAGAIN;
+    }
+
+    if (le16toh(counters->ustats_counter) != cur_stats_counter) {
+        PMD_DRV_LOG(DEBUG,
+              "stats not updated by ustorm, "
+              "counter 0x%x != stats_counter 0x%x",
+              le16toh(counters->ustats_counter), sc->stats_counter);
+        return -EAGAIN;
+    }
+
+    if (le16toh(counters->cstats_counter) != cur_stats_counter) {
+        PMD_DRV_LOG(DEBUG,
+              "stats not updated by cstorm, "
+              "counter 0x%x != stats_counter 0x%x",
+              le16toh(counters->cstats_counter), sc->stats_counter);
+        return -EAGAIN;
+    }
+
+    if (le16toh(counters->tstats_counter) != cur_stats_counter) {
+        PMD_DRV_LOG(DEBUG,
+              "stats not updated by tstorm, "
+              "counter 0x%x != stats_counter 0x%x",
+              le16toh(counters->tstats_counter), sc->stats_counter);
+        return -EAGAIN;
+    }
+
+    return 0;
+}
+
+static int
+bcm_storm_stats_update(struct bcm_softc *sc)
+{
+	struct tstorm_per_port_stats *tport =
+		&sc->fw_stats_data->port.tstorm_port_statistics;
+	struct tstorm_per_pf_stats *tfunc =
+		&sc->fw_stats_data->pf.tstorm_pf_statistics;
+	struct host_func_stats *fstats = &sc->func_stats;
+	struct bcm_eth_stats *estats = &sc->eth_stats;
+	struct bcm_eth_stats_old *estats_old = &sc->eth_stats_old;
+	int i;
+
+	/* vfs stat counter is managed by pf */
+	if (IS_PF(sc) && bcm_storm_stats_validate_counters(sc)) {
+		return -EAGAIN;
+	}
+
+	estats->error_bytes_received_hi = 0;
+	estats->error_bytes_received_lo = 0;
+
+	for (i = 0; i < sc->num_queues; i++) {
+		struct bcm_fastpath *fp = &sc->fp[i];
+		struct tstorm_per_queue_stats *tclient =
+			&sc->fw_stats_data->queue_stats[i].tstorm_queue_statistics;
+		struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
+		struct ustorm_per_queue_stats *uclient =
+			&sc->fw_stats_data->queue_stats[i].ustorm_queue_statistics;
+		struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
+		struct xstorm_per_queue_stats *xclient =
+			&sc->fw_stats_data->queue_stats[i].xstorm_queue_statistics;
+		struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
+		struct bcm_eth_q_stats *qstats = &fp->eth_q_stats;
+		struct bcm_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
+
+		uint32_t diff;
+
+		/* PMD_DRV_LOG(DEBUG,
+				"queue[%d]: ucast_sent 0x%x bcast_sent 0x%x mcast_sent 0x%x",
+				i, xclient->ucast_pkts_sent, xclient->bcast_pkts_sent,
+				xclient->mcast_pkts_sent);
+
+		PMD_DRV_LOG(DEBUG, "---------------"); */
+
+		UPDATE_QSTAT(tclient->rcv_bcast_bytes,
+				total_broadcast_bytes_received);
+		UPDATE_QSTAT(tclient->rcv_mcast_bytes,
+				total_multicast_bytes_received);
+		UPDATE_QSTAT(tclient->rcv_ucast_bytes,
+				total_unicast_bytes_received);
+
+		/*
+		 * sum to total_bytes_received all
+		 * unicast/multicast/broadcast
+		 */
+		qstats->total_bytes_received_hi =
+			qstats->total_broadcast_bytes_received_hi;
+		qstats->total_bytes_received_lo =
+			qstats->total_broadcast_bytes_received_lo;
+
+		ADD_64(qstats->total_bytes_received_hi,
+				qstats->total_multicast_bytes_received_hi,
+				qstats->total_bytes_received_lo,
+				qstats->total_multicast_bytes_received_lo);
+
+		ADD_64(qstats->total_bytes_received_hi,
+				qstats->total_unicast_bytes_received_hi,
+				qstats->total_bytes_received_lo,
+				qstats->total_unicast_bytes_received_lo);
+
+		qstats->valid_bytes_received_hi = qstats->total_bytes_received_hi;
+		qstats->valid_bytes_received_lo = qstats->total_bytes_received_lo;
+
+		UPDATE_EXTEND_TSTAT(rcv_ucast_pkts, total_unicast_packets_received);
+		UPDATE_EXTEND_TSTAT(rcv_mcast_pkts, total_multicast_packets_received);
+		UPDATE_EXTEND_TSTAT(rcv_bcast_pkts, total_broadcast_packets_received);
+		UPDATE_EXTEND_E_TSTAT(pkts_too_big_discard,
+				etherstatsoverrsizepkts, 32);
+		UPDATE_EXTEND_E_TSTAT(no_buff_discard, no_buff_discard, 16);
+
+		SUB_EXTEND_USTAT(ucast_no_buff_pkts, total_unicast_packets_received);
+		SUB_EXTEND_USTAT(mcast_no_buff_pkts,
+				total_multicast_packets_received);
+		SUB_EXTEND_USTAT(bcast_no_buff_pkts,
+				total_broadcast_packets_received);
+		UPDATE_EXTEND_E_USTAT(ucast_no_buff_pkts, no_buff_discard);
+		UPDATE_EXTEND_E_USTAT(mcast_no_buff_pkts, no_buff_discard);
+		UPDATE_EXTEND_E_USTAT(bcast_no_buff_pkts, no_buff_discard);
+
+		UPDATE_QSTAT(xclient->bcast_bytes_sent,
+				total_broadcast_bytes_transmitted);
+		UPDATE_QSTAT(xclient->mcast_bytes_sent,
+				total_multicast_bytes_transmitted);
+		UPDATE_QSTAT(xclient->ucast_bytes_sent,
+				total_unicast_bytes_transmitted);
+
+		/*
+		 * sum to total_bytes_transmitted all
+		 * unicast/multicast/broadcast
+		 */
+		qstats->total_bytes_transmitted_hi =
+			qstats->total_unicast_bytes_transmitted_hi;
+		qstats->total_bytes_transmitted_lo =
+			qstats->total_unicast_bytes_transmitted_lo;
+
+		ADD_64(qstats->total_bytes_transmitted_hi,
+				qstats->total_broadcast_bytes_transmitted_hi,
+				qstats->total_bytes_transmitted_lo,
+				qstats->total_broadcast_bytes_transmitted_lo);
+
+		ADD_64(qstats->total_bytes_transmitted_hi,
+				qstats->total_multicast_bytes_transmitted_hi,
+				qstats->total_bytes_transmitted_lo,
+				qstats->total_multicast_bytes_transmitted_lo);
+
+		UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
+				total_unicast_packets_transmitted);
+		UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
+				total_multicast_packets_transmitted);
+		UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
+				total_broadcast_packets_transmitted);
+
+		UPDATE_EXTEND_TSTAT(checksum_discard,
+				total_packets_received_checksum_discarded);
+		UPDATE_EXTEND_TSTAT(ttl0_discard,
+				total_packets_received_ttl0_discarded);
+
+		UPDATE_EXTEND_XSTAT(error_drop_pkts,
+				total_transmitted_dropped_packets_error);
+
+		UPDATE_FSTAT_QSTAT(total_bytes_received);
+		UPDATE_FSTAT_QSTAT(total_bytes_transmitted);
+		UPDATE_FSTAT_QSTAT(total_unicast_packets_received);
+		UPDATE_FSTAT_QSTAT(total_multicast_packets_received);
+		UPDATE_FSTAT_QSTAT(total_broadcast_packets_received);
+		UPDATE_FSTAT_QSTAT(total_unicast_packets_transmitted);
+		UPDATE_FSTAT_QSTAT(total_multicast_packets_transmitted);
+		UPDATE_FSTAT_QSTAT(total_broadcast_packets_transmitted);
+		UPDATE_FSTAT_QSTAT(valid_bytes_received);
+	}
+
+	ADD_64(estats->total_bytes_received_hi,
+			estats->rx_stat_ifhcinbadoctets_hi,
+			estats->total_bytes_received_lo,
+			estats->rx_stat_ifhcinbadoctets_lo);
+
+	ADD_64_LE(estats->total_bytes_received_hi,
+			tfunc->rcv_error_bytes.hi,
+			estats->total_bytes_received_lo,
+			tfunc->rcv_error_bytes.lo);
+
+	ADD_64_LE(estats->error_bytes_received_hi,
+			tfunc->rcv_error_bytes.hi,
+			estats->error_bytes_received_lo,
+			tfunc->rcv_error_bytes.lo);
+
+	UPDATE_ESTAT(etherstatsoverrsizepkts, rx_stat_dot3statsframestoolong);
+
+	ADD_64(estats->error_bytes_received_hi,
+			estats->rx_stat_ifhcinbadoctets_hi,
+			estats->error_bytes_received_lo,
+			estats->rx_stat_ifhcinbadoctets_lo);
+
+	if (sc->port.pmf) {
+		struct bcm_fw_port_stats_old *fwstats = &sc->fw_stats_old;
+		UPDATE_FW_STAT(mac_filter_discard);
+		UPDATE_FW_STAT(mf_tag_discard);
+		UPDATE_FW_STAT(brb_truncate_discard);
+		UPDATE_FW_STAT(mac_discard);
+	}
+
+	fstats->host_func_stats_start = ++fstats->host_func_stats_end;
+
+	sc->stats_pending = 0;
+
+	return 0;
+}
+
+static void
+bcm_drv_stats_update(struct bcm_softc *sc)
+{
+    struct bcm_eth_stats *estats = &sc->eth_stats;
+    int i;
+
+    for (i = 0; i < sc->num_queues; i++) {
+        struct bcm_eth_q_stats *qstats = &sc->fp[i].eth_q_stats;
+        struct bcm_eth_q_stats_old *qstats_old = &sc->fp[i].eth_q_stats_old;
+
+        UPDATE_ESTAT_QSTAT(rx_calls);
+        UPDATE_ESTAT_QSTAT(rx_pkts);
+        UPDATE_ESTAT_QSTAT(rx_soft_errors);
+        UPDATE_ESTAT_QSTAT(rx_hw_csum_errors);
+        UPDATE_ESTAT_QSTAT(rx_ofld_frames_csum_ip);
+        UPDATE_ESTAT_QSTAT(rx_ofld_frames_csum_tcp_udp);
+        UPDATE_ESTAT_QSTAT(rx_budget_reached);
+        UPDATE_ESTAT_QSTAT(tx_pkts);
+        UPDATE_ESTAT_QSTAT(tx_soft_errors);
+        UPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_ip);
+        UPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_tcp);
+        UPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_udp);
+        UPDATE_ESTAT_QSTAT(tx_encap_failures);
+        UPDATE_ESTAT_QSTAT(tx_hw_queue_full);
+        UPDATE_ESTAT_QSTAT(tx_hw_max_queue_depth);
+        UPDATE_ESTAT_QSTAT(tx_dma_mapping_failure);
+        UPDATE_ESTAT_QSTAT(tx_max_drbr_queue_depth);
+        UPDATE_ESTAT_QSTAT(tx_window_violation_std);
+        UPDATE_ESTAT_QSTAT(tx_chain_lost_mbuf);
+        UPDATE_ESTAT_QSTAT(tx_frames_deferred);
+        UPDATE_ESTAT_QSTAT(tx_queue_xoff);
+
+        /* mbuf driver statistics */
+        UPDATE_ESTAT_QSTAT(mbuf_defrag_attempts);
+        UPDATE_ESTAT_QSTAT(mbuf_defrag_failures);
+        UPDATE_ESTAT_QSTAT(mbuf_rx_bd_alloc_failed);
+        UPDATE_ESTAT_QSTAT(mbuf_rx_bd_mapping_failed);
+
+        /* track the number of allocated mbufs */
+        UPDATE_ESTAT_QSTAT(mbuf_alloc_tx);
+        UPDATE_ESTAT_QSTAT(mbuf_alloc_rx);
+    }
+}
+
+static uint8_t
+bcm_edebug_stats_stopped(struct bcm_softc *sc)
+{
+    uint32_t val;
+
+    if (SHMEM2_HAS(sc, edebug_driver_if[1])) {
+        val = SHMEM2_RD(sc, edebug_driver_if[1]);
+
+        if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT) {
+            return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
+static void
+bcm_stats_update(struct bcm_softc *sc)
+{
+	uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+
+	if (bcm_edebug_stats_stopped(sc)) {
+		return;
+	}
+
+	if (IS_PF(sc)) {
+
+		bcm_storm_stats_update(sc);
+		bcm_hw_stats_post(sc);
+		bcm_storm_stats_post(sc);
+		DELAY_MS(5);
+
+		if (*stats_comp != DMAE_COMP_VAL) {
+			return;
+		}
+
+		if (sc->port.pmf) {
+			bcm_hw_stats_update(sc);
+		}
+
+		if (bcm_storm_stats_update(sc)) {
+			if (sc->stats_pending++ == 3) {
+				rte_panic("storm stats not updated for 3 times");
+			}
+			return;
+		}
+	} else {
+		/*
+		 * VF doesn't collect HW statistics, and doesn't get completions,
+		 * performs only update.
+		 */
+		bcm_storm_stats_update(sc);
+	}
+
+	bcm_drv_stats_update(sc);
+}
+
+static void
+bcm_port_stats_stop(struct bcm_softc *sc)
+{
+    struct dmae_command *dmae;
+    uint32_t opcode;
+    int loader_idx = PMF_DMAE_C(sc);
+    uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+
+    sc->executer_idx = 0;
+
+    opcode = bcm_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC, FALSE, 0);
+
+    if (sc->port.port_stx) {
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+
+        if (sc->func_stx) {
+            dmae->opcode = bcm_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
+        } else {
+            dmae->opcode = bcm_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
+        }
+
+        dmae->src_addr_lo = U64_LO(BCM_SP_MAPPING(sc, port_stats));
+        dmae->src_addr_hi = U64_HI(BCM_SP_MAPPING(sc, port_stats));
+        dmae->dst_addr_lo = sc->port.port_stx >> 2;
+        dmae->dst_addr_hi = 0;
+        dmae->len = bcm_get_port_stats_dma_len(sc);
+        if (sc->func_stx) {
+            dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);
+            dmae->comp_addr_hi = 0;
+            dmae->comp_val = 1;
+        } else {
+            dmae->comp_addr_lo = U64_LO(BCM_SP_MAPPING(sc, stats_comp));
+            dmae->comp_addr_hi = U64_HI(BCM_SP_MAPPING(sc, stats_comp));
+            dmae->comp_val = DMAE_COMP_VAL;
+
+            *stats_comp = 0;
+        }
+    }
+
+    if (sc->func_stx) {
+        dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+        dmae->opcode = bcm_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
+        dmae->src_addr_lo = U64_LO(BCM_SP_MAPPING(sc, func_stats));
+        dmae->src_addr_hi = U64_HI(BCM_SP_MAPPING(sc, func_stats));
+        dmae->dst_addr_lo = (sc->func_stx >> 2);
+        dmae->dst_addr_hi = 0;
+        dmae->len = (sizeof(struct host_func_stats) >> 2);
+        dmae->comp_addr_lo = U64_LO(BCM_SP_MAPPING(sc, stats_comp));
+        dmae->comp_addr_hi = U64_HI(BCM_SP_MAPPING(sc, stats_comp));
+        dmae->comp_val = DMAE_COMP_VAL;
+
+        *stats_comp = 0;
+    }
+}
+
+static void
+bcm_stats_stop(struct bcm_softc *sc)
+{
+    uint8_t update = FALSE;
+
+    bcm_stats_comp(sc);
+
+    if (sc->port.pmf) {
+        update = bcm_hw_stats_update(sc) == 0;
+    }
+
+    update |= bcm_storm_stats_update(sc) == 0;
+
+    if (update) {
+
+        if (sc->port.pmf) {
+            bcm_port_stats_stop(sc);
+        }
+
+        bcm_hw_stats_post(sc);
+        bcm_stats_comp(sc);
+    }
+}
+
+static void
+bcm_stats_do_nothing(__rte_unused struct bcm_softc *sc)
+{
+    return;
+}
+
+static const struct {
+    void (*action)(struct bcm_softc *sc);
+    enum bcm_stats_state next_state;
+} bcm_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
+    {
+    /* DISABLED PMF */ { bcm_stats_pmf_update, STATS_STATE_DISABLED },
+    /*      LINK_UP */ { bcm_stats_start,      STATS_STATE_ENABLED },
+    /*      UPDATE  */ { bcm_stats_do_nothing, STATS_STATE_DISABLED },
+    /*      STOP    */ { bcm_stats_do_nothing, STATS_STATE_DISABLED }
+    },
+    {
+    /* ENABLED  PMF */ { bcm_stats_pmf_start,  STATS_STATE_ENABLED },
+    /*      LINK_UP */ { bcm_stats_restart,    STATS_STATE_ENABLED },
+    /*      UPDATE  */ { bcm_stats_update,     STATS_STATE_ENABLED },
+    /*      STOP    */ { bcm_stats_stop,       STATS_STATE_DISABLED }
+    }
+};
+
+void bcm_stats_handle(struct bcm_softc *sc, enum bcm_stats_event event)
+{
+	enum bcm_stats_state state;
+
+	if (unlikely(sc->panic)) {
+		return;
+	}
+
+	state = sc->stats_state;
+	sc->stats_state = bcm_stats_stm[state][event].next_state;
+
+	bcm_stats_stm[state][event].action(sc);
+
+	if (event != STATS_EVENT_UPDATE) {
+		PMD_DRV_LOG(DEBUG,
+				"state %d -> event %d -> state %d",
+				state, event, sc->stats_state);
+	}
+}
+
+static void
+bcm_port_stats_base_init(struct bcm_softc *sc)
+{
+    struct dmae_command *dmae;
+    uint32_t *stats_comp = BCM_SP(sc, stats_comp);
+
+    /* sanity */
+    if (!sc->port.pmf || !sc->port.port_stx) {
+        PMD_DRV_LOG(ERR, "BUG!");
+        return;
+    }
+
+    sc->executer_idx = 0;
+
+    dmae = BCM_SP(sc, dmae[sc->executer_idx++]);
+    dmae->opcode = bcm_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,
+                                   TRUE, DMAE_COMP_PCI);
+    dmae->src_addr_lo = U64_LO(BCM_SP_MAPPING(sc, port_stats));
+    dmae->src_addr_hi = U64_HI(BCM_SP_MAPPING(sc, port_stats));
+    dmae->dst_addr_lo = (sc->port.port_stx >> 2);
+    dmae->dst_addr_hi = 0;
+    dmae->len = bcm_get_port_stats_dma_len(sc);
+    dmae->comp_addr_lo = U64_LO(BCM_SP_MAPPING(sc, stats_comp));
+    dmae->comp_addr_hi = U64_HI(BCM_SP_MAPPING(sc, stats_comp));
+    dmae->comp_val = DMAE_COMP_VAL;
+
+    *stats_comp = 0;
+    bcm_hw_stats_post(sc);
+    bcm_stats_comp(sc);
+}
+
+/*
+ * This function will prepare the statistics ramrod data the way
+ * we will only have to increment the statistics counter and
+ * send the ramrod each time we have to.
+ */
+static void
+bcm_prep_fw_stats_req(struct bcm_softc *sc)
+{
+    int i;
+    int first_queue_query_index;
+    struct stats_query_header *stats_hdr = &sc->fw_stats_req->hdr;
+    phys_addr_t cur_data_offset;
+    struct stats_query_entry *cur_query_entry;
+
+    stats_hdr->cmd_num = sc->fw_stats_num;
+    stats_hdr->drv_stats_counter = 0;
+
+    /*
+     * The storm_counters struct contains the counters of completed
+     * statistics requests per storm which are incremented by FW
+     * each time it completes hadning a statistics ramrod. We will
+     * check these counters in the timer handler and discard a
+     * (statistics) ramrod completion.
+     */
+    cur_data_offset = (sc->fw_stats_data_mapping +
+                       offsetof(struct bcm_fw_stats_data, storm_counters));
+
+    stats_hdr->stats_counters_addrs.hi = htole32(U64_HI(cur_data_offset));
+    stats_hdr->stats_counters_addrs.lo = htole32(U64_LO(cur_data_offset));
+
+    /*
+     * Prepare the first stats ramrod (will be completed with
+     * the counters equal to zero) - init counters to somethig different.
+     */
+    memset(&sc->fw_stats_data->storm_counters, 0xff,
+           sizeof(struct stats_counter));
+
+    /**** Port FW statistics data ****/
+    cur_data_offset = (sc->fw_stats_data_mapping +
+                       offsetof(struct bcm_fw_stats_data, port));
+
+    cur_query_entry = &sc->fw_stats_req->query[BCM_PORT_QUERY_IDX];
+
+    cur_query_entry->kind = STATS_TYPE_PORT;
+    /* For port query index is a DONT CARE */
+    cur_query_entry->index = SC_PORT(sc);
+    /* For port query funcID is a DONT CARE */
+    cur_query_entry->funcID = htole16(SC_FUNC(sc));
+    cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
+    cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
+
+    /**** PF FW statistics data ****/
+    cur_data_offset = (sc->fw_stats_data_mapping +
+                       offsetof(struct bcm_fw_stats_data, pf));
+
+    cur_query_entry = &sc->fw_stats_req->query[BCM_PF_QUERY_IDX];
+
+    cur_query_entry->kind = STATS_TYPE_PF;
+    /* For PF query index is a DONT CARE */
+    cur_query_entry->index = SC_PORT(sc);
+    cur_query_entry->funcID = htole16(SC_FUNC(sc));
+    cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
+    cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
+
+    /**** Clients' queries ****/
+    cur_data_offset = (sc->fw_stats_data_mapping +
+                       offsetof(struct bcm_fw_stats_data, queue_stats));
+
+    /*
+     * First queue query index depends whether FCoE offloaded request will
+     * be included in the ramrod
+     */
+        first_queue_query_index = (BCM_FIRST_QUEUE_QUERY_IDX - 1);
+
+    for (i = 0; i < sc->num_queues; i++) {
+        cur_query_entry =
+            &sc->fw_stats_req->query[first_queue_query_index + i];
+
+        cur_query_entry->kind = STATS_TYPE_QUEUE;
+        cur_query_entry->index = bcm_stats_id(&sc->fp[i]);
+        cur_query_entry->funcID = htole16(SC_FUNC(sc));
+        cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));
+        cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));
+
+        cur_data_offset += sizeof(struct per_queue_stats);
+    }
+}
+
+void bcm_memset_stats(struct bcm_softc *sc)
+{
+	int i;
+
+	/* function stats */
+	for (i = 0; i < sc->num_queues; i++) {
+		struct bcm_fastpath *fp = &sc->fp[i];
+
+		memset(&fp->old_tclient, 0,
+				sizeof(fp->old_tclient));
+		memset(&fp->old_uclient, 0,
+				sizeof(fp->old_uclient));
+		memset(&fp->old_xclient, 0,
+				sizeof(fp->old_xclient));
+		if (sc->stats_init) {
+			memset(&fp->eth_q_stats, 0,
+					sizeof(fp->eth_q_stats));
+			memset(&fp->eth_q_stats_old, 0,
+					sizeof(fp->eth_q_stats_old));
+		}
+	}
+
+	if (sc->stats_init) {
+		memset(&sc->net_stats_old, 0, sizeof(sc->net_stats_old));
+		memset(&sc->fw_stats_old, 0, sizeof(sc->fw_stats_old));
+		memset(&sc->eth_stats_old, 0, sizeof(sc->eth_stats_old));
+		memset(&sc->eth_stats, 0, sizeof(sc->eth_stats));
+		memset(&sc->func_stats, 0, sizeof(sc->func_stats));
+	}
+
+	sc->stats_state = STATS_STATE_DISABLED;
+
+	if (sc->port.pmf && sc->port.port_stx)
+		bcm_port_stats_base_init(sc);
+
+	/* mark the end of statistics initializiation */
+	sc->stats_init = false;
+}
+
+void
+bcm_stats_init(struct bcm_softc *sc)
+{
+	int /*abs*/port = SC_PORT(sc);
+	int mb_idx = SC_FW_MB_IDX(sc);
+	int i;
+
+	sc->stats_pending = 0;
+	sc->executer_idx = 0;
+	sc->stats_counter = 0;
+
+	sc->stats_init = TRUE;
+
+	/* port and func stats for management */
+	if (!BCM_NOMCP(sc)) {
+		sc->port.port_stx = SHMEM_RD(sc, port_mb[port].port_stx);
+		sc->func_stx = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_param);
+	} else {
+		sc->port.port_stx = 0;
+		sc->func_stx = 0;
+	}
+
+	PMD_DRV_LOG(DEBUG, "port_stx 0x%x func_stx 0x%x",
+			sc->port.port_stx, sc->func_stx);
+
+	/* pmf should retrieve port statistics from SP on a non-init*/
+	if (!sc->stats_init && sc->port.pmf && sc->port.port_stx) {
+		bcm_stats_handle(sc, STATS_EVENT_PMF);
+	}
+
+	port = SC_PORT(sc);
+	/* port stats */
+	memset(&(sc->port.old_nig_stats), 0, sizeof(struct nig_stats));
+	sc->port.old_nig_stats.brb_discard =
+		REG_RD(sc, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
+	sc->port.old_nig_stats.brb_truncate =
+		REG_RD(sc, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
+	if (!CHIP_IS_E3(sc)) {
+		REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
+				&(sc->port.old_nig_stats.egress_mac_pkt0_lo), 2);
+		REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
+				&(sc->port.old_nig_stats.egress_mac_pkt1_lo), 2);
+	}
+
+	/* function stats */
+	for (i = 0; i < sc->num_queues; i++) {
+		memset(&sc->fp[i].old_tclient, 0, sizeof(sc->fp[i].old_tclient));
+		memset(&sc->fp[i].old_uclient, 0, sizeof(sc->fp[i].old_uclient));
+		memset(&sc->fp[i].old_xclient, 0, sizeof(sc->fp[i].old_xclient));
+		if (sc->stats_init) {
+			memset(&sc->fp[i].eth_q_stats, 0,
+					sizeof(sc->fp[i].eth_q_stats));
+			memset(&sc->fp[i].eth_q_stats_old, 0,
+					sizeof(sc->fp[i].eth_q_stats_old));
+		}
+	}
+
+	/* prepare statistics ramrod data */
+	bcm_prep_fw_stats_req(sc);
+
+	if (sc->stats_init) {
+		memset(&sc->net_stats_old, 0, sizeof(sc->net_stats_old));
+		memset(&sc->fw_stats_old, 0, sizeof(sc->fw_stats_old));
+		memset(&sc->eth_stats_old, 0, sizeof(sc->eth_stats_old));
+		memset(&sc->eth_stats, 0, sizeof(sc->eth_stats));
+		memset(&sc->func_stats, 0, sizeof(sc->func_stats));
+
+		/* Clean SP from previous statistics */
+		if (sc->func_stx) {
+			memset(BCM_SP(sc, func_stats), 0, sizeof(struct host_func_stats));
+			bcm_func_stats_init(sc);
+			bcm_hw_stats_post(sc);
+			bcm_stats_comp(sc);
+		}
+	}
+
+	sc->stats_state = STATS_STATE_DISABLED;
+
+	if (sc->port.pmf && sc->port.port_stx) {
+		bcm_port_stats_base_init(sc);
+	}
+
+	/* mark the end of statistics initializiation */
+	sc->stats_init = FALSE;
+}
+
+void
+bcm_save_statistics(struct bcm_softc *sc)
+{
+	int i;
+
+	/* save queue statistics */
+	for (i = 0; i < sc->num_queues; i++) {
+		struct bcm_fastpath *fp = &sc->fp[i];
+		struct bcm_eth_q_stats *qstats = &fp->eth_q_stats;
+		struct bcm_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
+
+		UPDATE_QSTAT_OLD(total_unicast_bytes_received_hi);
+		UPDATE_QSTAT_OLD(total_unicast_bytes_received_lo);
+		UPDATE_QSTAT_OLD(total_broadcast_bytes_received_hi);
+		UPDATE_QSTAT_OLD(total_broadcast_bytes_received_lo);
+		UPDATE_QSTAT_OLD(total_multicast_bytes_received_hi);
+		UPDATE_QSTAT_OLD(total_multicast_bytes_received_lo);
+		UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_hi);
+		UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_lo);
+		UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_hi);
+		UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_lo);
+		UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_hi);
+		UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_lo);
+	}
+
+	/* store port firmware statistics */
+	if (sc->port.pmf) {
+		struct bcm_eth_stats *estats = &sc->eth_stats;
+		struct bcm_fw_port_stats_old *fwstats = &sc->fw_stats_old;
+		struct host_port_stats *pstats = BCM_SP(sc, port_stats);
+
+		fwstats->pfc_frames_rx_hi = pstats->pfc_frames_rx_hi;
+		fwstats->pfc_frames_rx_lo = pstats->pfc_frames_rx_lo;
+		fwstats->pfc_frames_tx_hi = pstats->pfc_frames_tx_hi;
+		fwstats->pfc_frames_tx_lo = pstats->pfc_frames_tx_lo;
+
+		if (IS_MF(sc)) {
+			UPDATE_FW_STAT_OLD(mac_filter_discard);
+			UPDATE_FW_STAT_OLD(mf_tag_discard);
+			UPDATE_FW_STAT_OLD(brb_truncate_discard);
+			UPDATE_FW_STAT_OLD(mac_discard);
+		}
+	}
+}
diff --git a/lib/librte_pmd_bcm/bcm_stats.h b/lib/librte_pmd_bcm/bcm_stats.h
new file mode 100644
index 0000000..da8240f
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_stats.h
@@ -0,0 +1,633 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef BCM_STATS_H
+#define BCM_STATS_H
+
+#include <sys/types.h>
+
+struct nig_stats {
+    uint32_t brb_discard;
+    uint32_t brb_packet;
+    uint32_t brb_truncate;
+    uint32_t flow_ctrl_discard;
+    uint32_t flow_ctrl_octets;
+    uint32_t flow_ctrl_packet;
+    uint32_t mng_discard;
+    uint32_t mng_octet_inp;
+    uint32_t mng_octet_out;
+    uint32_t mng_packet_inp;
+    uint32_t mng_packet_out;
+    uint32_t pbf_octets;
+    uint32_t pbf_packet;
+    uint32_t safc_inp;
+    uint32_t egress_mac_pkt0_lo;
+    uint32_t egress_mac_pkt0_hi;
+    uint32_t egress_mac_pkt1_lo;
+    uint32_t egress_mac_pkt1_hi;
+};
+
+
+enum bcm_stats_event {
+    STATS_EVENT_PMF = 0,
+    STATS_EVENT_LINK_UP,
+    STATS_EVENT_UPDATE,
+    STATS_EVENT_STOP,
+    STATS_EVENT_MAX
+};
+
+enum bcm_stats_state {
+    STATS_STATE_DISABLED = 0,
+    STATS_STATE_ENABLED,
+    STATS_STATE_MAX
+};
+
+struct bcm_eth_stats {
+    uint32_t total_bytes_received_hi;
+    uint32_t total_bytes_received_lo;
+    uint32_t total_bytes_transmitted_hi;
+    uint32_t total_bytes_transmitted_lo;
+    uint32_t total_unicast_packets_received_hi;
+    uint32_t total_unicast_packets_received_lo;
+    uint32_t total_multicast_packets_received_hi;
+    uint32_t total_multicast_packets_received_lo;
+    uint32_t total_broadcast_packets_received_hi;
+    uint32_t total_broadcast_packets_received_lo;
+    uint32_t total_unicast_packets_transmitted_hi;
+    uint32_t total_unicast_packets_transmitted_lo;
+    uint32_t total_multicast_packets_transmitted_hi;
+    uint32_t total_multicast_packets_transmitted_lo;
+    uint32_t total_broadcast_packets_transmitted_hi;
+    uint32_t total_broadcast_packets_transmitted_lo;
+    uint32_t valid_bytes_received_hi;
+    uint32_t valid_bytes_received_lo;
+
+    uint32_t error_bytes_received_hi;
+    uint32_t error_bytes_received_lo;
+    uint32_t etherstatsoverrsizepkts_hi;
+    uint32_t etherstatsoverrsizepkts_lo;
+    uint32_t no_buff_discard_hi;
+    uint32_t no_buff_discard_lo;
+
+    uint32_t rx_stat_ifhcinbadoctets_hi;
+    uint32_t rx_stat_ifhcinbadoctets_lo;
+    uint32_t tx_stat_ifhcoutbadoctets_hi;
+    uint32_t tx_stat_ifhcoutbadoctets_lo;
+    uint32_t rx_stat_dot3statsfcserrors_hi;
+    uint32_t rx_stat_dot3statsfcserrors_lo;
+    uint32_t rx_stat_dot3statsalignmenterrors_hi;
+    uint32_t rx_stat_dot3statsalignmenterrors_lo;
+    uint32_t rx_stat_dot3statscarriersenseerrors_hi;
+    uint32_t rx_stat_dot3statscarriersenseerrors_lo;
+    uint32_t rx_stat_falsecarriererrors_hi;
+    uint32_t rx_stat_falsecarriererrors_lo;
+    uint32_t rx_stat_etherstatsundersizepkts_hi;
+    uint32_t rx_stat_etherstatsundersizepkts_lo;
+    uint32_t rx_stat_dot3statsframestoolong_hi;
+    uint32_t rx_stat_dot3statsframestoolong_lo;
+    uint32_t rx_stat_etherstatsfragments_hi;
+    uint32_t rx_stat_etherstatsfragments_lo;
+    uint32_t rx_stat_etherstatsjabbers_hi;
+    uint32_t rx_stat_etherstatsjabbers_lo;
+    uint32_t rx_stat_maccontrolframesreceived_hi;
+    uint32_t rx_stat_maccontrolframesreceived_lo;
+    uint32_t rx_stat_bmac_xpf_hi;
+    uint32_t rx_stat_bmac_xpf_lo;
+    uint32_t rx_stat_bmac_xcf_hi;
+    uint32_t rx_stat_bmac_xcf_lo;
+    uint32_t rx_stat_xoffstateentered_hi;
+    uint32_t rx_stat_xoffstateentered_lo;
+    uint32_t rx_stat_xonpauseframesreceived_hi;
+    uint32_t rx_stat_xonpauseframesreceived_lo;
+    uint32_t rx_stat_xoffpauseframesreceived_hi;
+    uint32_t rx_stat_xoffpauseframesreceived_lo;
+    uint32_t tx_stat_outxonsent_hi;
+    uint32_t tx_stat_outxonsent_lo;
+    uint32_t tx_stat_outxoffsent_hi;
+    uint32_t tx_stat_outxoffsent_lo;
+    uint32_t tx_stat_flowcontroldone_hi;
+    uint32_t tx_stat_flowcontroldone_lo;
+    uint32_t tx_stat_etherstatscollisions_hi;
+    uint32_t tx_stat_etherstatscollisions_lo;
+    uint32_t tx_stat_dot3statssinglecollisionframes_hi;
+    uint32_t tx_stat_dot3statssinglecollisionframes_lo;
+    uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
+    uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
+    uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
+    uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
+    uint32_t tx_stat_dot3statsexcessivecollisions_hi;
+    uint32_t tx_stat_dot3statsexcessivecollisions_lo;
+    uint32_t tx_stat_dot3statslatecollisions_hi;
+    uint32_t tx_stat_dot3statslatecollisions_lo;
+    uint32_t tx_stat_etherstatspkts64octets_hi;
+    uint32_t tx_stat_etherstatspkts64octets_lo;
+    uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
+    uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
+    uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
+    uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
+    uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
+    uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
+    uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
+    uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
+    uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
+    uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
+    uint32_t tx_stat_etherstatspktsover1522octets_hi;
+    uint32_t tx_stat_etherstatspktsover1522octets_lo;
+    uint32_t tx_stat_bmac_2047_hi;
+    uint32_t tx_stat_bmac_2047_lo;
+    uint32_t tx_stat_bmac_4095_hi;
+    uint32_t tx_stat_bmac_4095_lo;
+    uint32_t tx_stat_bmac_9216_hi;
+    uint32_t tx_stat_bmac_9216_lo;
+    uint32_t tx_stat_bmac_16383_hi;
+    uint32_t tx_stat_bmac_16383_lo;
+    uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
+    uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
+    uint32_t tx_stat_bmac_ufl_hi;
+    uint32_t tx_stat_bmac_ufl_lo;
+
+    uint32_t pause_frames_received_hi;
+    uint32_t pause_frames_received_lo;
+    uint32_t pause_frames_sent_hi;
+    uint32_t pause_frames_sent_lo;
+
+    uint32_t etherstatspkts1024octetsto1522octets_hi;
+    uint32_t etherstatspkts1024octetsto1522octets_lo;
+    uint32_t etherstatspktsover1522octets_hi;
+    uint32_t etherstatspktsover1522octets_lo;
+
+    uint32_t brb_drop_hi;
+    uint32_t brb_drop_lo;
+    uint32_t brb_truncate_hi;
+    uint32_t brb_truncate_lo;
+
+    uint32_t mac_filter_discard;
+    uint32_t mf_tag_discard;
+    uint32_t brb_truncate_discard;
+    uint32_t mac_discard;
+
+    uint32_t nig_timer_max;
+
+    /* PFC */
+    uint32_t pfc_frames_received_hi;
+    uint32_t pfc_frames_received_lo;
+    uint32_t pfc_frames_sent_hi;
+    uint32_t pfc_frames_sent_lo;
+
+    /* Recovery */
+    uint32_t recoverable_error;
+    uint32_t unrecoverable_error;
+
+    /* src: Clear-on-Read register; Will not survive PMF Migration */
+    uint32_t eee_tx_lpi;
+
+    /* receive path driver statistics */
+    uint32_t rx_calls;
+    uint32_t rx_pkts;
+    uint32_t rx_soft_errors;
+    uint32_t rx_hw_csum_errors;
+    uint32_t rx_ofld_frames_csum_ip;
+    uint32_t rx_ofld_frames_csum_tcp_udp;
+    uint32_t rx_budget_reached;
+
+    /* tx path driver statistics */
+    uint32_t tx_pkts;
+    uint32_t tx_soft_errors;
+    uint32_t tx_ofld_frames_csum_ip;
+    uint32_t tx_ofld_frames_csum_tcp;
+    uint32_t tx_ofld_frames_csum_udp;
+    uint32_t tx_encap_failures;
+    uint32_t tx_hw_queue_full;
+    uint32_t tx_hw_max_queue_depth;
+    uint32_t tx_dma_mapping_failure;
+    uint32_t tx_max_drbr_queue_depth;
+    uint32_t tx_window_violation_std;
+    uint32_t tx_chain_lost_mbuf;
+    uint32_t tx_frames_deferred;
+    uint32_t tx_queue_xoff;
+
+    /* mbuf driver statistics */
+    uint32_t mbuf_defrag_attempts;
+    uint32_t mbuf_defrag_failures;
+    uint32_t mbuf_rx_bd_alloc_failed;
+    uint32_t mbuf_rx_bd_mapping_failed;
+
+    /* track the number of allocated mbufs */
+    uint32_t mbuf_alloc_tx;
+    uint32_t mbuf_alloc_rx;
+};
+
+
+struct bcm_eth_q_stats {
+    uint32_t total_unicast_bytes_received_hi;
+    uint32_t total_unicast_bytes_received_lo;
+    uint32_t total_broadcast_bytes_received_hi;
+    uint32_t total_broadcast_bytes_received_lo;
+    uint32_t total_multicast_bytes_received_hi;
+    uint32_t total_multicast_bytes_received_lo;
+    uint32_t total_bytes_received_hi;
+    uint32_t total_bytes_received_lo;
+    uint32_t total_unicast_bytes_transmitted_hi;
+    uint32_t total_unicast_bytes_transmitted_lo;
+    uint32_t total_broadcast_bytes_transmitted_hi;
+    uint32_t total_broadcast_bytes_transmitted_lo;
+    uint32_t total_multicast_bytes_transmitted_hi;
+    uint32_t total_multicast_bytes_transmitted_lo;
+    uint32_t total_bytes_transmitted_hi;
+    uint32_t total_bytes_transmitted_lo;
+    uint32_t total_unicast_packets_received_hi;
+    uint32_t total_unicast_packets_received_lo;
+    uint32_t total_multicast_packets_received_hi;
+    uint32_t total_multicast_packets_received_lo;
+    uint32_t total_broadcast_packets_received_hi;
+    uint32_t total_broadcast_packets_received_lo;
+    uint32_t total_unicast_packets_transmitted_hi;
+    uint32_t total_unicast_packets_transmitted_lo;
+    uint32_t total_multicast_packets_transmitted_hi;
+    uint32_t total_multicast_packets_transmitted_lo;
+    uint32_t total_broadcast_packets_transmitted_hi;
+    uint32_t total_broadcast_packets_transmitted_lo;
+    uint32_t valid_bytes_received_hi;
+    uint32_t valid_bytes_received_lo;
+
+    uint32_t etherstatsoverrsizepkts_hi;
+    uint32_t etherstatsoverrsizepkts_lo;
+    uint32_t no_buff_discard_hi;
+    uint32_t no_buff_discard_lo;
+
+    uint32_t total_packets_received_checksum_discarded_hi;
+    uint32_t total_packets_received_checksum_discarded_lo;
+    uint32_t total_packets_received_ttl0_discarded_hi;
+    uint32_t total_packets_received_ttl0_discarded_lo;
+    uint32_t total_transmitted_dropped_packets_error_hi;
+    uint32_t total_transmitted_dropped_packets_error_lo;
+
+    /* receive path driver statistics */
+    uint32_t rx_calls;
+    uint32_t rx_pkts;
+    uint32_t rx_soft_errors;
+    uint32_t rx_hw_csum_errors;
+    uint32_t rx_ofld_frames_csum_ip;
+    uint32_t rx_ofld_frames_csum_tcp_udp;
+    uint32_t rx_budget_reached;
+
+    /* tx path driver statistics */
+    uint32_t tx_pkts;
+    uint32_t tx_soft_errors;
+    uint32_t tx_ofld_frames_csum_ip;
+    uint32_t tx_ofld_frames_csum_tcp;
+    uint32_t tx_ofld_frames_csum_udp;
+    uint32_t tx_encap_failures;
+    uint32_t tx_hw_queue_full;
+    uint32_t tx_hw_max_queue_depth;
+    uint32_t tx_dma_mapping_failure;
+    uint32_t tx_max_drbr_queue_depth;
+    uint32_t tx_window_violation_std;
+    uint32_t tx_chain_lost_mbuf;
+    uint32_t tx_frames_deferred;
+    uint32_t tx_queue_xoff;
+
+    /* mbuf driver statistics */
+    uint32_t mbuf_defrag_attempts;
+    uint32_t mbuf_defrag_failures;
+    uint32_t mbuf_rx_bd_alloc_failed;
+    uint32_t mbuf_rx_bd_mapping_failed;
+
+    /* track the number of allocated mbufs */
+    uint32_t mbuf_alloc_tx;
+    uint32_t mbuf_alloc_rx;
+};
+
+struct bcm_eth_stats_old {
+    uint32_t rx_stat_dot3statsframestoolong_hi;
+    uint32_t rx_stat_dot3statsframestoolong_lo;
+};
+
+struct bcm_eth_q_stats_old {
+    /* Fields to perserve over fw reset*/
+    uint32_t total_unicast_bytes_received_hi;
+    uint32_t total_unicast_bytes_received_lo;
+    uint32_t total_broadcast_bytes_received_hi;
+    uint32_t total_broadcast_bytes_received_lo;
+    uint32_t total_multicast_bytes_received_hi;
+    uint32_t total_multicast_bytes_received_lo;
+    uint32_t total_unicast_bytes_transmitted_hi;
+    uint32_t total_unicast_bytes_transmitted_lo;
+    uint32_t total_broadcast_bytes_transmitted_hi;
+    uint32_t total_broadcast_bytes_transmitted_lo;
+    uint32_t total_multicast_bytes_transmitted_hi;
+    uint32_t total_multicast_bytes_transmitted_lo;
+
+    /* Fields to perserve last of */
+    uint32_t total_bytes_received_hi;
+    uint32_t total_bytes_received_lo;
+    uint32_t total_bytes_transmitted_hi;
+    uint32_t total_bytes_transmitted_lo;
+    uint32_t total_unicast_packets_received_hi;
+    uint32_t total_unicast_packets_received_lo;
+    uint32_t total_multicast_packets_received_hi;
+    uint32_t total_multicast_packets_received_lo;
+    uint32_t total_broadcast_packets_received_hi;
+    uint32_t total_broadcast_packets_received_lo;
+    uint32_t total_unicast_packets_transmitted_hi;
+    uint32_t total_unicast_packets_transmitted_lo;
+    uint32_t total_multicast_packets_transmitted_hi;
+    uint32_t total_multicast_packets_transmitted_lo;
+    uint32_t total_broadcast_packets_transmitted_hi;
+    uint32_t total_broadcast_packets_transmitted_lo;
+    uint32_t valid_bytes_received_hi;
+    uint32_t valid_bytes_received_lo;
+
+    /* receive path driver statistics */
+    uint32_t rx_calls_old;
+    uint32_t rx_pkts_old;
+    uint32_t rx_soft_errors_old;
+    uint32_t rx_hw_csum_errors_old;
+    uint32_t rx_ofld_frames_csum_ip_old;
+    uint32_t rx_ofld_frames_csum_tcp_udp_old;
+    uint32_t rx_budget_reached_old;
+
+    /* tx path driver statistics */
+    uint32_t tx_pkts_old;
+    uint32_t tx_soft_errors_old;
+    uint32_t tx_ofld_frames_csum_ip_old;
+    uint32_t tx_ofld_frames_csum_tcp_old;
+    uint32_t tx_ofld_frames_csum_udp_old;
+    uint32_t tx_encap_failures_old;
+    uint32_t tx_hw_queue_full_old;
+    uint32_t tx_hw_max_queue_depth_old;
+    uint32_t tx_dma_mapping_failure_old;
+    uint32_t tx_max_drbr_queue_depth_old;
+    uint32_t tx_window_violation_std_old;
+    uint32_t tx_chain_lost_mbuf_old;
+    uint32_t tx_frames_deferred_old;
+    uint32_t tx_queue_xoff_old;
+
+    /* mbuf driver statistics */
+    uint32_t mbuf_defrag_attempts_old;
+    uint32_t mbuf_defrag_failures_old;
+    uint32_t mbuf_rx_bd_alloc_failed_old;
+    uint32_t mbuf_rx_bd_mapping_failed_old;
+
+    /* track the number of allocated mbufs */
+    int mbuf_alloc_tx_old;
+    int mbuf_alloc_rx_old;
+};
+
+struct bcm_net_stats_old {
+    uint32_t rx_dropped;
+};
+
+struct bcm_fw_port_stats_old {
+    uint32_t pfc_frames_tx_hi;
+    uint32_t pfc_frames_tx_lo;
+    uint32_t pfc_frames_rx_hi;
+    uint32_t pfc_frames_rx_lo;
+
+    uint32_t mac_filter_discard;
+    uint32_t mf_tag_discard;
+    uint32_t brb_truncate_discard;
+    uint32_t mac_discard;
+};
+
+/* sum[hi:lo] += add[hi:lo] */
+#define ADD_64(s_hi, a_hi, s_lo, a_lo)          \
+    do {                                        \
+        s_lo += a_lo;                           \
+        s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
+    } while (0)
+
+#define LE32_0 ((uint32_t) 0)
+#define LE16_0 ((uint16_t) 0)
+
+/* The _force is for cases where high value is 0 */
+#define ADD_64_LE(s_hi, a_hi_le, s_lo, a_lo_le) \
+        ADD_64(s_hi, le32toh(a_hi_le),          \
+               s_lo, le32toh(a_lo_le))
+
+#define ADD_64_LE16(s_hi, a_hi_le, s_lo, a_lo_le) \
+        ADD_64(s_hi, le16toh(a_hi_le),            \
+               s_lo, le16toh(a_lo_le))
+
+/* difference = minuend - subtrahend */
+#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo)  \
+    do {                                             \
+        if (m_lo < s_lo) {                           \
+            /* underflow */                          \
+            d_hi = m_hi - s_hi;                      \
+            if (d_hi > 0) {                          \
+                /* we can 'loan' 1 */                \
+                d_hi--;                              \
+                d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
+            } else {                                 \
+                /* m_hi <= s_hi */                   \
+                d_hi = 0;                            \
+                d_lo = 0;                            \
+            }                                        \
+        } else {                                     \
+            /* m_lo >= s_lo */                       \
+            if (m_hi < s_hi) {                       \
+                d_hi = 0;                            \
+                d_lo = 0;                            \
+            } else {                                 \
+                /* m_hi >= s_hi */                   \
+                d_hi = m_hi - s_hi;                  \
+                d_lo = m_lo - s_lo;                  \
+            }                                        \
+        }                                            \
+    } while (0)
+
+#define UPDATE_STAT64(s, t)                                      \
+    do {                                                         \
+        DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
+            diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo);    \
+        pstats->mac_stx[0].t##_hi = new->s##_hi;                 \
+        pstats->mac_stx[0].t##_lo = new->s##_lo;                 \
+        ADD_64(pstats->mac_stx[1].t##_hi, diff.hi,               \
+               pstats->mac_stx[1].t##_lo, diff.lo);              \
+    } while (0)
+
+#define UPDATE_STAT64_NIG(s, t)                    \
+    do {                                           \
+        DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
+            diff.lo, new->s##_lo, old->s##_lo);    \
+        ADD_64(estats->t##_hi, diff.hi,            \
+               estats->t##_lo, diff.lo);           \
+    } while (0)
+
+/* sum[hi:lo] += add */
+#define ADD_EXTEND_64(s_hi, s_lo, a) \
+    do {                             \
+        s_lo += a;                   \
+        s_hi += (s_lo < a) ? 1 : 0;  \
+    } while (0)
+
+#define ADD_STAT64(diff, t)                                \
+    do {                                                   \
+        ADD_64(pstats->mac_stx[1].t##_hi, new->diff##_hi,  \
+               pstats->mac_stx[1].t##_lo, new->diff##_lo); \
+    } while (0)
+
+#define UPDATE_EXTEND_STAT(s)                    \
+    do {                                         \
+        ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
+                  pstats->mac_stx[1].s##_lo,     \
+                  new->s);                       \
+    } while (0)
+
+#define UPDATE_EXTEND_TSTAT_X(s, t, size)                    \
+    do {                                                     \
+        diff = le##size##toh(tclient->s) -                   \
+               le##size##toh(old_tclient->s);                \
+        old_tclient->s = tclient->s;                         \
+        ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
+    } while (0)
+
+#define UPDATE_EXTEND_TSTAT(s, t) UPDATE_EXTEND_TSTAT_X(s, t, 32)
+
+#define UPDATE_EXTEND_E_TSTAT(s, t, size)                    \
+    do {                                                     \
+        UPDATE_EXTEND_TSTAT_X(s, t, size);                   \
+        ADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \
+    } while (0)
+
+#define UPDATE_EXTEND_USTAT(s, t)                             \
+    do {                                                      \
+        diff = le32toh(uclient->s) - le32toh(old_uclient->s); \
+        old_uclient->s = uclient->s;                          \
+        ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff);  \
+    } while (0)
+
+#define UPDATE_EXTEND_E_USTAT(s, t)                          \
+    do {                                                     \
+        UPDATE_EXTEND_USTAT(s, t);                           \
+        ADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \
+    } while (0)
+
+#define UPDATE_EXTEND_XSTAT(s, t)                             \
+    do {                                                      \
+        diff = le32toh(xclient->s) - le32toh(old_xclient->s); \
+        old_xclient->s = xclient->s;                          \
+        ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff);  \
+    } while (0)
+
+#define UPDATE_QSTAT(s, t)                                   \
+    do {                                                     \
+        qstats->t##_hi = qstats_old->t##_hi + le32toh(s.hi); \
+        qstats->t##_lo = qstats_old->t##_lo + le32toh(s.lo); \
+    } while (0)
+
+#define UPDATE_QSTAT_OLD(f)        \
+    do {                           \
+        qstats_old->f = qstats->f; \
+    } while (0)
+
+#define UPDATE_ESTAT_QSTAT_64(s)                        \
+    do {                                                \
+        ADD_64(estats->s##_hi, qstats->s##_hi,          \
+               estats->s##_lo, qstats->s##_lo);         \
+        SUB_64(estats->s##_hi, qstats_old->s##_hi_old,  \
+               estats->s##_lo, qstats_old->s##_lo_old); \
+        qstats_old->s##_hi_old = qstats->s##_hi;        \
+        qstats_old->s##_lo_old = qstats->s##_lo;        \
+    } while (0)
+
+#define UPDATE_ESTAT_QSTAT(s)             \
+    do {                                  \
+        estats->s += qstats->s;           \
+        estats->s -= qstats_old->s##_old; \
+        qstats_old->s##_old = qstats->s;  \
+    } while (0)
+
+#define UPDATE_FSTAT_QSTAT(s)                       \
+    do {                                            \
+        ADD_64(fstats->s##_hi, qstats->s##_hi,      \
+               fstats->s##_lo, qstats->s##_lo);     \
+        SUB_64(fstats->s##_hi, qstats_old->s##_hi,  \
+               fstats->s##_lo, qstats_old->s##_lo); \
+        estats->s##_hi = fstats->s##_hi;            \
+        estats->s##_lo = fstats->s##_lo;            \
+        qstats_old->s##_hi = qstats->s##_hi;        \
+        qstats_old->s##_lo = qstats->s##_lo;        \
+    } while (0)
+
+#define UPDATE_FW_STAT(s)                           \
+    do {                                            \
+        estats->s = le32toh(tport->s) + fwstats->s; \
+    } while (0)
+
+#define UPDATE_FW_STAT_OLD(f)   \
+    do {                        \
+        fwstats->f = estats->f; \
+    } while (0)
+
+#define UPDATE_ESTAT(s, t)                          \
+    do {                                            \
+        SUB_64(estats->s##_hi, estats_old->t##_hi,  \
+               estats->s##_lo, estats_old->t##_lo); \
+        ADD_64(estats->s##_hi, estats->t##_hi,      \
+               estats->s##_lo, estats->t##_lo);     \
+        estats_old->t##_hi = estats->t##_hi;        \
+        estats_old->t##_lo = estats->t##_lo;        \
+    } while (0)
+
+/* minuend -= subtrahend */
+#define SUB_64(m_hi, s_hi, m_lo, s_lo)               \
+    do {                                             \
+        DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
+    } while (0)
+
+/* minuend[hi:lo] -= subtrahend */
+#define SUB_EXTEND_64(m_hi, m_lo, s)    \
+    do {                                \
+        uint32_t s_hi = 0;              \
+        SUB_64(m_hi, s_hi, m_lo, s);    \
+    } while (0)
+
+#define SUB_EXTEND_USTAT(s, t)                                \
+    do {                                                      \
+        diff = le32toh(uclient->s) - le32toh(old_uclient->s); \
+        SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff);  \
+    } while (0)
+
+struct bcm_softc;
+void bcm_stats_init(struct bcm_softc *sc);
+void bcm_stats_handle(struct bcm_softc *sc, enum bcm_stats_event event);
+void bcm_save_statistics(struct bcm_softc *sc);
+void bcm_memset_stats(struct bcm_softc *sc);
+
+#endif /* BCM_STATS_H */
+
diff --git a/lib/librte_pmd_bcm/bcm_vfpf.c b/lib/librte_pmd_bcm/bcm_vfpf.c
new file mode 100644
index 0000000..eef10de
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_vfpf.c
@@ -0,0 +1,597 @@
+/*
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ *
+ * All rights reserved.
+ */
+
+#include "bcm.h"
+
+/* calculate the crc in the bulletin board */
+static inline uint32_t
+bcm_vf_crc(struct bcm_vf_bulletin *bull)
+{
+	uint32_t crc_sz = sizeof(bull->crc), length = bull->length - crc_sz;
+
+	return ECORE_CRC32_LE(0, (uint8_t *)bull + crc_sz, length);
+}
+
+/* Checks are there mac/channel updates for VF
+ * returns TRUE if something was updated
+*/
+int
+bcm_check_bull(struct bcm_softc *sc)
+{
+	struct bcm_vf_bulletin *bull;
+	uint8_t tries = 0;
+	uint16_t old_version = sc->old_bulletin.version;
+	uint64_t valid_bitmap;
+
+	bull = sc->pf2vf_bulletin;
+	if (old_version == bull->version) {
+		return FALSE;
+	} else {
+		/* Check the crc until we get the correct data */
+		while (tries < BCM_VF_BULLETIN_TRIES) {
+			bull = sc->pf2vf_bulletin;
+			if (bull->crc == bcm_vf_crc(bull))
+				break;
+
+			PMD_DRV_LOG(ERR, "bad crc on bulletin board. contained %x computed %x",
+					bull->crc, bcm_vf_crc(bull));
+			++tries;
+		}
+		if (tries == BCM_VF_BULLETIN_TRIES) {
+			PMD_DRV_LOG(ERR, "pf to vf bulletin board crc was wrong %d consecutive times. Aborting",
+					tries);
+			return FALSE;
+		}
+	}
+
+	valid_bitmap = bull->valid_bitmap;
+
+	/* check the mac address and VLAN and allocate memory if valid */
+	if (valid_bitmap & (1 << MAC_ADDR_VALID) && memcmp(bull->mac, sc->old_bulletin.mac, ETH_ALEN))
+		rte_memcpy(&sc->link_params.mac_addr, bull->mac, ETH_ALEN);
+	if (valid_bitmap & (1 << VLAN_VALID))
+		rte_memcpy(&bull->vlan, &sc->old_bulletin.vlan, VLAN_HLEN);
+
+	sc->old_bulletin = *bull;
+
+	return TRUE;
+}
+
+/* add tlv to a buffer */
+#define BCM_TLV_APPEND(_tlvs, _offset, _type, _length) \
+	((struct vf_first_tlv *)((uint64_t)_tlvs + _offset))->type   = _type; \
+	((struct vf_first_tlv *)((uint64_t)_tlvs + _offset))->length = _length
+
+/* Initiliaze header of the first tlv and clear mailbox*/
+static void
+bcm_init_first_tlv(struct bcm_softc *sc, struct vf_first_tlv *tlv,
+	uint16_t type, uint16_t len)
+{
+	struct bcm_vf_mbx_msg *mbox = sc->vf2pf_mbox;
+	PMD_DRV_LOG(DEBUG, "Preparing %d tlv for sending", type);
+
+	memset(mbox, 0, sizeof(struct bcm_vf_mbx_msg));
+
+	BCM_TLV_APPEND(tlv, 0, type, len);
+
+	/* Initialize header of the first tlv */
+	tlv->reply_offset = sizeof(mbox->query);
+}
+
+#define BCM_VF_CMD_ADDR_LO PXP_VF_ADDR_CSDM_GLOBAL_START
+#define BCM_VF_CMD_ADDR_HI BCM_VF_CMD_ADDR_LO + 4
+#define BCM_VF_CMD_TRIGGER BCM_VF_CMD_ADDR_HI + 4
+#define BCM_VF_CHANNEL_DELAY 100
+#define BCM_VF_CHANNEL_TRIES 100
+
+static int
+bcm_do_req4pf(struct bcm_softc *sc, phys_addr_t phys_addr)
+{
+	uint8_t *status = &sc->vf2pf_mbox->resp.common_reply.status;
+	uint8_t i;
+
+	if (!*status) {
+		bcm_check_bull(sc);
+		if (sc->old_bulletin.valid_bitmap & (1 << CHANNEL_DOWN)) {
+			PMD_DRV_LOG(ERR, "channel is down. Aborting message sending");
+			*status = BCM_VF_STATUS_SUCCESS;
+			return 0;
+		}
+
+		REG_WR(sc, BCM_VF_CMD_ADDR_LO, U64_LO(phys_addr));
+		REG_WR(sc, BCM_VF_CMD_ADDR_HI, U64_HI(phys_addr));
+
+		/* memory barrier to ensure that FW can read phys_addr */
+		wmb();
+
+		REG_WR8(sc, BCM_VF_CMD_TRIGGER, 1);
+
+		/* Do several attempts until PF completes
+		 * "." is used to show progress
+		 */
+		for (i = 0; i < BCM_VF_CHANNEL_TRIES; i++) {
+			DELAY_MS(BCM_VF_CHANNEL_DELAY);
+			if (*status)
+				break;
+		}
+
+		if (i == BCM_VF_CHANNEL_TRIES) {
+			PMD_DRV_LOG(ERR, "Response from PF timed out");
+			return -EAGAIN;
+		}
+
+		if (BCM_VF_STATUS_SUCCESS != *status) {
+			PMD_DRV_LOG(ERR, "Bad reply from PF : %u",
+					*status);
+			return -EINVAL;
+		}
+	} else {
+		PMD_DRV_LOG(ERR, "status should be zero before message"
+				"to pf was sent");
+		return -EINVAL;
+	}
+
+	PMD_DRV_LOG(DEBUG, "Response from PF was received");
+	return 0;
+}
+
+static inline uint16_t bcm_check_me_flags(uint32_t val)
+{
+	if (((val) & ME_REG_VF_VALID) && (!((val) & ME_REG_VF_ERR)))
+		return ME_REG_VF_VALID;
+	else
+		return 0;
+}
+
+#define BCM_ME_ANSWER_DELAY 100
+#define BCM_ME_ANSWER_TRIES 10
+
+static inline int bcm_read_vf_id(struct bcm_softc *sc)
+{
+	uint32_t val;
+	uint8_t i = 0;
+
+	while (i <= BCM_ME_ANSWER_TRIES) {
+		val = BCM_DB_READ(DOORBELL_ADDR(sc, 0));
+		if (bcm_check_me_flags(val))
+			return VF_ID(val);
+
+		DELAY_MS(BCM_ME_ANSWER_DELAY);
+		i++;
+	}
+
+	return -EINVAL;
+}
+
+#define BCM_VF_OBTAIN_MAX_TRIES 3
+#define BCM_VF_OBTAIN_MAC_FILTERS 1
+#define BCM_VF_OBTAIN_MC_FILTERS 10
+
+struct bcm_obtain_status {
+	int success;
+	int err_code;
+};
+
+static
+struct bcm_obtain_status bcm_loop_obtain_resources(struct bcm_softc *sc)
+{
+	int tries = 0;
+	struct vf_acquire_resp_tlv *resp = &sc->vf2pf_mbox->resp.acquire_resp,
+								 *sc_resp = &sc->acquire_resp;
+	struct vf_resource_query    *res_query;
+	struct vf_resc            *resc;
+	struct bcm_obtain_status     status;
+	int res_obtained = false;
+
+	do {
+		PMD_DRV_LOG(DEBUG, "trying to get resources");
+
+		if ( bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr) ) {
+			/* timeout */
+			status.success = 0;
+			status.err_code = 0;
+			return status;
+		}
+
+		memcpy(sc_resp, resp, sizeof(sc->acquire_resp));
+
+		tries++;
+
+		/* check PF to request acceptance */
+		if (sc_resp->status == BCM_VF_STATUS_SUCCESS) {
+			PMD_DRV_LOG(DEBUG, "resources obtained successfully");
+			res_obtained = true;
+		} else if (sc_resp->status == BCM_VF_STATUS_NO_RESOURCES &&
+			tries < BCM_VF_OBTAIN_MAX_TRIES) {
+			PMD_DRV_LOG(DEBUG,
+			   "PF cannot allocate requested amount of resources");
+
+			res_query = &sc->vf2pf_mbox->query[0].acquire.res_query;
+			resc     = &sc_resp->resc;
+
+			/* PF refused our request. Try to decrease request params */
+			res_query->num_txqs         = min(res_query->num_txqs, resc->num_txqs);
+			res_query->num_rxqs         = min(res_query->num_rxqs, resc->num_rxqs);
+			res_query->num_sbs          = min(res_query->num_sbs, resc->num_sbs);
+			res_query->num_mac_filters  = min(res_query->num_mac_filters, resc->num_mac_filters);
+			res_query->num_vlan_filters = min(res_query->num_vlan_filters, resc->num_vlan_filters);
+			res_query->num_mc_filters   = min(res_query->num_mc_filters, resc->num_mc_filters);
+
+			memset(&sc->vf2pf_mbox->resp, 0, sizeof(union resp_tlvs));
+		} else {
+			PMD_DRV_LOG(ERR, "Resources cannot be obtained. Status of handling: %d. Aborting",
+					sc_resp->status);
+			status.success = 0;
+			status.err_code = -EAGAIN;
+			return status;
+		}
+	} while (!res_obtained);
+
+	status.success = 1;
+	return status;
+}
+
+int bcm_vf_get_resources(struct bcm_softc *sc, uint8_t tx_count, uint8_t rx_count)
+{
+	struct vf_acquire_tlv *acq = &sc->vf2pf_mbox->query[0].acquire;
+	int vf_id;
+	struct bcm_obtain_status obtain_status;
+
+	bcm_vf_close(sc);
+	bcm_init_first_tlv(sc, &acq->first_tlv, BCM_VF_TLV_ACQUIRE, sizeof(*acq));
+
+	vf_id = bcm_read_vf_id(sc);
+	if (vf_id < 0)
+		return -EAGAIN;
+
+	acq->vf_id = vf_id;
+
+	acq->res_query.num_rxqs = rx_count;
+	acq->res_query.num_txqs = tx_count;
+	acq->res_query.num_sbs = sc->igu_sb_cnt;
+	acq->res_query.num_mac_filters = BCM_VF_OBTAIN_MAC_FILTERS;
+	acq->res_query.num_mc_filters = BCM_VF_OBTAIN_MC_FILTERS;
+
+	acq->bulletin_addr = sc->pf2vf_bulletin_mapping.paddr;
+
+	BCM_TLV_APPEND(acq, acq->first_tlv.length, BCM_VF_TLV_LIST_END,
+			sizeof(struct channel_list_end_tlv));
+
+	/* requesting the resources in loop */
+	obtain_status = bcm_loop_obtain_resources(sc);
+	if (!obtain_status.success)
+		return obtain_status.err_code;
+
+	struct vf_acquire_resp_tlv sc_resp = sc->acquire_resp;
+
+	sc->devinfo.chip_id        |= (sc_resp.chip_num & 0xFFFF);
+	sc->devinfo.int_block       = INT_BLOCK_IGU;
+	sc->devinfo.chip_port_mode  = CHIP_2_PORT_MODE;
+	sc->devinfo.mf_info.mf_ov   = 0;
+	sc->devinfo.mf_info.mf_mode = 0;
+	sc->devinfo.flash_size      = 0;
+
+	sc->igu_sb_cnt  = sc_resp.resc.num_sbs;
+	sc->igu_base_sb = sc_resp.resc.hw_sbs[0] & 0xFF;
+	sc->igu_dsb_id  = -1;
+
+	sc->link_params.chip_id = sc->devinfo.chip_id;
+	sc->doorbell_size = sc_resp.db_size;
+	sc->flags |= BCM_NO_WOL_FLAG | BCM_NO_ISCSI_OOO_FLAG | BCM_NO_ISCSI_FLAG | BCM_NO_FCOE_FLAG;
+
+	PMD_DRV_LOG(DEBUG, "status block count = %d, base status block = %x",
+		sc->igu_sb_cnt, sc->igu_base_sb);
+	strncpy(sc->fw_ver, sc_resp.fw_ver, sizeof(sc->fw_ver));
+
+	if (is_valid_ether_addr(sc_resp.resc.current_mac_addr))
+		(void)rte_memcpy(sc->link_params.mac_addr,
+		       sc_resp.resc.current_mac_addr,
+		       ETH_ALEN);
+
+	return 0;
+}
+
+/* Ask PF to release VF's resources */
+void
+bcm_vf_close(struct bcm_softc *sc)
+{
+	struct vf_release_tlv *query;
+	int vf_id = bcm_read_vf_id(sc);
+	int ret;
+
+	if (vf_id >= 0) {
+		query = &sc->vf2pf_mbox->query[0].release;
+		bcm_init_first_tlv(sc, &query->first_tlv, BCM_VF_TLV_RELEASE,
+				sizeof(*query));
+
+		query->vf_id = vf_id;
+		BCM_TLV_APPEND(query, query->first_tlv.length, BCM_VF_TLV_LIST_END,
+				sizeof(struct channel_list_end_tlv));
+
+		ret = bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+
+		if (ret) {
+			PMD_DRV_LOG(ERR, "Failed to release VF");
+		}
+	}
+}
+
+/* Let PF know the VF status blocks phys_addrs */
+int
+bcm_vf_init(struct bcm_softc *sc)
+{
+	struct vf_init_tlv *query;
+	int i, ret;
+
+	query = &sc->vf2pf_mbox->query[0].init;
+	bcm_init_first_tlv(sc, &query->first_tlv, BCM_VF_TLV_INIT,
+			sizeof(*query));
+
+	FOR_EACH_QUEUE(sc, i) {
+		query->sb_addr[i] = (unsigned long)(sc->fp[i].sb_dma.paddr);
+	}
+
+	query->stats_step = sizeof(struct per_queue_stats);
+	query->stats_addr = sc->fw_stats_data_mapping +
+		offsetof(struct bcm_fw_stats_data, queue_stats);
+
+	BCM_TLV_APPEND(query, query->first_tlv.length, BCM_VF_TLV_LIST_END,
+			sizeof(struct channel_list_end_tlv));
+
+	ret = bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+
+	if (ret) {
+		PMD_DRV_LOG(ERR, "Failed to init VF");
+		return ret;
+	}
+
+	PMD_DRV_LOG(DEBUG, "VF was initialized");
+	return 0;
+}
+
+void
+bcm_vf_unload(struct bcm_softc *sc)
+{
+	struct vf_close_tlv *query;
+	struct vf_q_op_tlv *query_op;
+	int i, vf_id, ret;
+
+	vf_id = bcm_read_vf_id(sc);
+	if (vf_id > 0) {
+		FOR_EACH_QUEUE(sc, i) {
+			query_op = &sc->vf2pf_mbox->query[0].q_op;
+			bcm_init_first_tlv(sc, &query_op->first_tlv,
+					BCM_VF_TLV_TEARDOWN_Q,
+					sizeof(*query_op));
+
+			query_op->vf_qid = i;
+
+			BCM_TLV_APPEND(query_op, query_op->first_tlv.length,
+					BCM_VF_TLV_LIST_END,
+					sizeof(struct channel_list_end_tlv));
+
+			ret = bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+			if (ret)
+				PMD_DRV_LOG(ERR,
+						"Bad reply for vf_q %d teardown", i);
+		}
+
+		bcm_vf_set_mac(sc, false);
+
+		query = &sc->vf2pf_mbox->query[0].close;
+		bcm_init_first_tlv(sc, &query->first_tlv, BCM_VF_TLV_CLOSE,
+				sizeof(*query));
+
+		query->vf_id = vf_id;
+
+		BCM_TLV_APPEND(query, query->first_tlv.length,
+				BCM_VF_TLV_LIST_END,
+				sizeof(struct channel_list_end_tlv));
+
+		ret = bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+
+		if (ret)
+			PMD_DRV_LOG(ERR,
+				"Bad reply from PF for close message");
+	}
+}
+
+static inline uint16_t
+bcm_vf_q_flags(uint8_t leading)
+{
+	uint16_t flags = leading ? BCM_VF_Q_FLAG_LEADING_RSS : 0;
+
+	flags |= BCM_VF_Q_FLAG_CACHE_ALIGN;
+	flags |= BCM_VF_Q_FLAG_STATS;
+	flags |= BCM_VF_Q_FLAG_VLAN;
+
+	return flags;
+}
+
+static void
+bcm_vf_rx_q_prep(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		struct vf_rxq_params *rxq_init, uint16_t flags)
+{
+	struct bcm_rx_queue *rxq;
+
+	rxq = sc->rx_queues[fp->index];
+	if (!rxq) {
+		PMD_DRV_LOG(ERR, "RX queue %d is NULL", fp->index);
+		return;
+	}
+
+	rxq_init->rcq_addr = rxq->cq_ring_phys_addr;
+	rxq_init->rcq_np_addr = rxq->cq_ring_phys_addr + BCM_PAGE_SIZE;
+	rxq_init->rxq_addr = rxq->rx_ring_phys_addr;
+	rxq_init->vf_sb_id = fp->index;
+	rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
+	rxq_init->mtu = sc->mtu;
+	rxq_init->buf_sz = fp->rx_buf_size;
+	rxq_init->flags = flags;
+	rxq_init->stat_id = -1;
+	rxq_init->cache_line_log = BCM_RX_ALIGN_SHIFT;
+}
+
+static void
+bcm_vf_tx_q_prep(struct bcm_softc *sc, struct bcm_fastpath *fp,
+		struct vf_txq_params *txq_init, uint16_t flags)
+{
+	struct bcm_tx_queue *txq;
+
+	txq = sc->tx_queues[fp->index];
+	if (!txq) {
+		PMD_DRV_LOG(ERR, "TX queue %d is NULL", fp->index);
+		return;
+	}
+
+	txq_init->txq_addr = txq->tx_ring_phys_addr;
+	txq_init->sb_index = HC_INDEX_ETH_TX_CQ_CONS_COS0;
+	txq_init->flags = flags;
+	txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
+	txq_init->vf_sb_id = fp->index;
+}
+
+int
+bcm_vf_setup_queue(struct bcm_softc *sc, struct bcm_fastpath *fp, int leading)
+{
+	struct vf_setup_q_tlv *query;
+	uint16_t flags = bcm_vf_q_flags(leading);
+	int ret;
+
+	query = &sc->vf2pf_mbox->query[0].setup_q;
+	bcm_init_first_tlv(sc, &query->first_tlv, BCM_VF_TLV_SETUP_Q,
+			sizeof(*query));
+
+	query->vf_qid = fp->index;
+	query->param_valid = VF_RXQ_VALID | VF_TXQ_VALID;
+
+	bcm_vf_rx_q_prep(sc, fp, &query->rxq, flags);
+	bcm_vf_tx_q_prep(sc, fp, &query->txq, flags);
+
+	BCM_TLV_APPEND(query, query->first_tlv.length, BCM_VF_TLV_LIST_END,
+			sizeof(struct channel_list_end_tlv));
+
+	ret = bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+
+	if (ret) {
+		PMD_DRV_LOG(ERR, "Failed to setup VF queue[%d]",
+				fp->index);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int
+bcm_vf_set_mac(struct bcm_softc *sc, int set)
+{
+	struct vf_set_q_filters_tlv *query;
+	struct vf_common_reply_tlv *reply;
+
+	query = &sc->vf2pf_mbox->query[0].set_q_filters;
+	bcm_init_first_tlv(sc, &query->first_tlv, BCM_VF_TLV_SET_Q_FILTERS,
+			sizeof(*query));
+
+	query->vf_qid = sc->fp->index;
+	query->mac_filters_cnt = 1;
+	query->flags = BCM_VF_MAC_VLAN_CHANGED;
+
+	query->filters[0].flags = (set ? BCM_VF_Q_FILTER_SET_MAC : 0) |
+		BCM_VF_Q_FILTER_DEST_MAC_VALID;
+
+	bcm_check_bull(sc);
+
+	rte_memcpy(query->filters[0].mac, sc->link_params.mac_addr, ETH_ALEN);
+
+	BCM_TLV_APPEND(query, query->first_tlv.length, BCM_VF_TLV_LIST_END,
+			sizeof(struct channel_list_end_tlv));
+
+	bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+	reply = &sc->vf2pf_mbox->resp.common_reply;
+
+	while (BCM_VF_STATUS_FAILURE == reply->status &&
+			bcm_check_bull(sc)) {
+		/* A new mac was configured by PF for us */
+		rte_memcpy(sc->link_params.mac_addr, sc->pf2vf_bulletin->mac,
+				ETH_ALEN);
+		rte_memcpy(query->filters[0].mac, sc->pf2vf_bulletin->mac,
+				ETH_ALEN);
+
+		bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+	}
+
+	if (BCM_VF_STATUS_SUCCESS != reply->status) {
+		PMD_DRV_LOG(ERR, "Bad reply from PF for SET MAC message: %d",
+				reply->status);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int
+bcm_vf_config_rss(struct bcm_softc *sc,
+			  struct ecore_config_rss_params *params)
+{
+	struct vf_rss_tlv *query;
+	int ret;
+
+	query = &sc->vf2pf_mbox->query[0].update_rss;
+
+	bcm_init_first_tlv(sc, &query->first_tlv, BCM_VF_TLV_UPDATE_RSS,
+			sizeof(*query));
+
+	/* add list termination tlv */
+	BCM_TLV_APPEND(query, query->first_tlv.length, BCM_VF_TLV_LIST_END,
+			sizeof(struct channel_list_end_tlv));
+
+	rte_memcpy(query->rss_key, params->rss_key, sizeof(params->rss_key));
+	query->rss_key_size = T_ETH_RSS_KEY;
+
+	rte_memcpy(query->ind_table, params->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);
+	query->ind_table_size = T_ETH_INDIRECTION_TABLE_SIZE;
+
+	query->rss_result_mask = params->rss_result_mask;
+	query->rss_flags = params->rss_flags;
+
+	ret = bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+	if (ret) {
+		PMD_DRV_LOG(ERR, "Failed to send message to PF, rc %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int
+bcm_vf_set_rx_mode(struct bcm_softc *sc)
+{
+	struct vf_set_q_filters_tlv *query;
+	unsigned long tx_mask;
+	int ret;
+
+	query = &sc->vf2pf_mbox->query[0].set_q_filters;
+	bcm_init_first_tlv(sc, &query->first_tlv, BCM_VF_TLV_SET_Q_FILTERS,
+			sizeof(*query));
+
+	query->vf_qid = 0;
+	query->flags = BCM_VF_RX_MASK_CHANGED;
+
+	if (bcm_fill_accept_flags(sc, sc->rx_mode, &query->rx_mask, &tx_mask)) {
+		return -EINVAL;
+	}
+
+	BCM_TLV_APPEND(query, query->first_tlv.length, BCM_VF_TLV_LIST_END,
+			sizeof(struct channel_list_end_tlv));
+
+	ret = bcm_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);
+	if (ret) {
+		PMD_DRV_LOG(ERR, "Failed to send message to PF, rc %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/lib/librte_pmd_bcm/bcm_vfpf.h b/lib/librte_pmd_bcm/bcm_vfpf.h
new file mode 100644
index 0000000..7eecc62
--- /dev/null
+++ b/lib/librte_pmd_bcm/bcm_vfpf.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ *
+ * All rights reserved.
+ */
+
+#ifndef BCM_VFPF_H
+#define BCM_VFPF_H
+
+#include "ecore_sp.h"
+
+#define VLAN_HLEN 4
+
+struct vf_resource_query {
+	uint8_t num_rxqs;
+	uint8_t num_txqs;
+	uint8_t num_sbs;
+	uint8_t num_mac_filters;
+	uint8_t num_vlan_filters;
+	uint8_t num_mc_filters;
+};
+
+#define	BCM_VF_STATUS_SUCCESS         1
+#define	BCM_VF_STATUS_FAILURE         2
+#define	BCM_VF_STATUS_NO_RESOURCES    4
+#define	BCM_VF_BULLETIN_TRIES         5
+
+#define	BCM_VF_Q_FLAG_CACHE_ALIGN     0x0008
+#define	BCM_VF_Q_FLAG_STATS           0x0010
+#define	BCM_VF_Q_FLAG_OV              0x0020
+#define	BCM_VF_Q_FLAG_VLAN            0x0040
+#define	BCM_VF_Q_FLAG_COS             0x0080
+#define	BCM_VF_Q_FLAG_HC              0x0100
+#define	BCM_VF_Q_FLAG_DHC             0x0200
+#define	BCM_VF_Q_FLAG_LEADING_RSS     0x0400
+
+struct vf_first_tlv {
+	uint16_t type;
+	uint16_t length;
+	uint32_t reply_offset;
+};
+
+/* tlv struct for all PF replies except acquire */
+struct vf_common_reply_tlv {
+	uint16_t type;
+	uint16_t length;
+	uint8_t status;
+	uint8_t pad[3];
+};
+
+/* used to terminate and pad a tlv list */
+struct channel_list_end_tlv {
+	uint16_t type;
+	uint16_t length;
+	uint32_t pad;
+};
+
+/* Acquire */
+struct vf_acquire_tlv {
+	struct vf_first_tlv first_tlv;
+
+	uint8_t vf_id;
+	uint8_t pad[3];
+
+	struct vf_resource_query res_query;
+
+	uint64_t bulletin_addr;
+};
+
+/* simple operation request on queue */
+struct vf_q_op_tlv {
+	struct vf_first_tlv	first_tlv;
+	uint8_t vf_qid;
+	uint8_t pad[3];
+};
+
+/* receive side scaling tlv */
+struct vf_rss_tlv {
+	struct vf_first_tlv	first_tlv;
+	uint32_t		rss_flags;
+	uint8_t			rss_result_mask;
+	uint8_t			ind_table_size;
+	uint8_t			rss_key_size;
+	uint8_t			pad;
+	uint8_t			ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
+	uint32_t		rss_key[T_ETH_RSS_KEY];	/* hash values */
+};
+
+struct vf_resc {
+#define BCM_VF_MAX_QUEUES_PER_VF         16
+#define BCM_VF_MAX_SBS_PER_VF            16
+	uint16_t hw_sbs[BCM_VF_MAX_SBS_PER_VF];
+	uint8_t hw_qid[BCM_VF_MAX_QUEUES_PER_VF];
+	uint8_t num_rxqs;
+	uint8_t num_txqs;
+	uint8_t num_sbs;
+	uint8_t num_mac_filters;
+	uint8_t num_vlan_filters;
+	uint8_t num_mc_filters;
+	uint8_t permanent_mac_addr[ETH_ALEN];
+	uint8_t current_mac_addr[ETH_ALEN];
+	uint16_t pf_link_speed;
+	uint32_t pf_link_supported;
+};
+
+/* tlv struct holding reply for acquire */
+struct vf_acquire_resp_tlv {
+	uint16_t type;
+	uint16_t length;
+	uint8_t status;
+	uint8_t pad1[3];
+	uint32_t chip_num;
+	uint8_t pad2[4];
+	char fw_ver[32];
+	uint16_t db_size;
+	uint8_t pad3[2];
+	struct vf_resc resc;
+};
+
+/* Init VF */
+struct vf_init_tlv {
+	struct vf_first_tlv first_tlv;
+	uint64_t sb_addr[BCM_VF_MAX_SBS_PER_VF];
+	uint64_t spq_addr;
+	uint64_t stats_addr;
+	uint16_t stats_step;
+	uint32_t flags;
+	uint32_t pad[2];
+};
+
+struct vf_rxq_params {
+	/* physical addresses */
+	uint64_t rcq_addr;
+	uint64_t rcq_np_addr;
+	uint64_t rxq_addr;
+	uint64_t pad1;
+
+	/* sb + hc info */
+	uint8_t  vf_sb_id;
+	uint8_t  sb_cq_index;
+	uint16_t hc_rate;	/* desired interrupts per sec. */
+	/* rx buffer info */
+	uint16_t mtu;
+	uint16_t buf_sz;
+	uint16_t flags;         /* for BCM_VF_Q_FLAG_X flags */
+	uint16_t stat_id;	/* valid if BCM_VF_Q_FLAG_STATS */
+
+	uint8_t pad2[5];
+
+	uint8_t drop_flags;
+	uint8_t cache_line_log;	/* BCM_VF_Q_FLAG_CACHE_ALIGN */
+	uint8_t pad3;
+};
+
+struct vf_txq_params {
+	/* physical addresses */
+	uint64_t txq_addr;
+
+	/* sb + hc info */
+	uint8_t  vf_sb_id;	/* index in hw_sbs[] */
+	uint8_t  sb_index;	/* Index in the SB */
+	uint16_t hc_rate;	/* desired interrupts per sec. */
+	uint32_t flags;		/* for BCM_VF_Q_FLAG_X flags */
+	uint16_t stat_id;	/* valid if BCM_VF_Q_FLAG_STATS */
+	uint8_t  traffic_type;	/* see in setup_context() */
+	uint8_t  pad;
+};
+
+/* Setup Queue */
+struct vf_setup_q_tlv {
+	struct vf_first_tlv first_tlv;
+
+	struct vf_rxq_params rxq;
+	struct vf_txq_params txq;
+
+	uint8_t vf_qid;			/* index in hw_qid[] */
+	uint8_t param_valid;
+	#define VF_RXQ_VALID		0x01
+	#define VF_TXQ_VALID		0x02
+	uint8_t pad[2];
+};
+
+/* Set Queue Filters */
+struct vf_q_mac_vlan_filter {
+	uint32_t flags;
+	#define BCM_VF_Q_FILTER_DEST_MAC_VALID	0x01
+	#define BCM_VF_Q_FILTER_VLAN_TAG_VALID	0x02
+	#define BCM_VF_Q_FILTER_SET_MAC		0x100	/* set/clear */
+	uint8_t  mac[ETH_ALEN];
+	uint16_t vlan_tag;
+};
+
+
+#define _UP_ETH_ALEN	(6)
+
+/* configure queue filters */
+struct vf_set_q_filters_tlv {
+	struct vf_first_tlv first_tlv;
+
+	uint32_t flags;
+	#define BCM_VF_MAC_VLAN_CHANGED	0x01
+	#define BCM_VF_MULTICAST_CHANGED	0x02
+	#define BCM_VF_RX_MASK_CHANGED 	0x04
+
+	uint8_t vf_qid;			/* index in hw_qid[] */
+	uint8_t mac_filters_cnt;
+	uint8_t multicast_cnt;
+	uint8_t pad;
+
+	#define VF_MAX_MAC_FILTERS			16
+	#define VF_MAX_VLAN_FILTERS      		16
+	#define VF_MAX_FILTERS			(VF_MAX_MAC_FILTERS +\
+							VF_MAX_VLAN_FILTERS)
+	struct vf_q_mac_vlan_filter filters[VF_MAX_FILTERS];
+
+	#define VF_MAX_MULTICAST_PER_VF  		32
+	uint8_t  multicast[VF_MAX_MULTICAST_PER_VF][_UP_ETH_ALEN];
+	unsigned long rx_mask;
+};
+
+
+/* close VF (disable VF) */
+struct vf_close_tlv {
+	struct vf_first_tlv	first_tlv;
+	uint16_t		vf_id;  /* for debug */
+	uint8_t pad[2];
+};
+
+/* rlease the VF's acquired resources */
+struct vf_release_tlv {
+	struct vf_first_tlv   first_tlv;
+	uint16_t		vf_id;  /* for debug */
+	uint8_t pad[2];
+};
+
+union query_tlvs {
+	struct vf_first_tlv		first_tlv;
+	struct vf_acquire_tlv		acquire;
+	struct vf_init_tlv		init;
+	struct vf_close_tlv		close;
+	struct vf_q_op_tlv		q_op;
+	struct vf_setup_q_tlv		setup_q;
+	struct vf_set_q_filters_tlv	set_q_filters;
+	struct vf_release_tlv		release;
+	struct vf_rss_tlv		update_rss;
+	struct channel_list_end_tlv     list_end;
+};
+
+union resp_tlvs {
+	struct vf_common_reply_tlv	common_reply;
+	struct vf_acquire_resp_tlv	acquire_resp;
+	struct channel_list_end_tlv	list_end;
+};
+
+/* struct allocated by VF driver, PF sends updates to VF via bulletin */
+struct bcm_vf_bulletin {
+	uint32_t crc;			/* crc of structure to ensure is not in
+					 * mid-update
+					 */
+	uint16_t version;
+	uint16_t length;
+
+	uint64_t valid_bitmap;	/* bitmap indicating wich fields
+					 * hold valid values
+					 */
+
+#define MAC_ADDR_VALID		0	/* alert the vf that a new mac address
+					 * is available for it
+					 */
+#define VLAN_VALID		1	/* when set, the vf should no access the
+					 * vf channel
+					 */
+#define CHANNEL_DOWN		2	/* vf channel is disabled. VFs are not
+					 * to attempt to send messages on the
+					 * channel after this bit is set
+					 */
+	uint8_t mac[ETH_ALEN];
+	uint8_t mac_pad[2];
+
+	uint16_t vlan;
+	uint8_t vlan_pad[6];
+};
+
+#define MAX_TLVS_IN_LIST 50
+enum channel_tlvs {
+	BCM_VF_TLV_NONE, /* ends tlv sequence */
+	BCM_VF_TLV_ACQUIRE,
+	BCM_VF_TLV_INIT,
+	BCM_VF_TLV_SETUP_Q,
+	BCM_VF_TLV_SET_Q_FILTERS,
+	BCM_VF_TLV_ACTIVATE_Q,
+	BCM_VF_TLV_DEACTIVATE_Q,
+	BCM_VF_TLV_TEARDOWN_Q,
+	BCM_VF_TLV_CLOSE,
+	BCM_VF_TLV_RELEASE,
+	BCM_VF_TLV_UPDATE_RSS_OLD,
+	BCM_VF_TLV_PF_RELEASE_VF,
+	BCM_VF_TLV_LIST_END,
+	BCM_VF_TLV_FLR,
+	BCM_VF_TLV_PF_SET_MAC,
+	BCM_VF_TLV_PF_SET_VLAN,
+	BCM_VF_TLV_UPDATE_RSS,
+	BCM_VF_TLV_MAX
+};
+
+struct bcm_vf_mbx_msg {
+	union query_tlvs query[BCM_VF_MAX_QUEUES_PER_VF];
+	union resp_tlvs resp;
+};
+
+void bcm_add_tlv(void *tlvs_list, uint16_t offset, uint16_t type, uint16_t length);
+int bcm_vf_set_mac(struct bcm_softc *sc, int set);
+int bcm_vf_config_rss(struct bcm_softc *sc, struct ecore_config_rss_params *params);
+
+#endif /* BCM_VFPF_H */
diff --git a/lib/librte_pmd_bcm/debug.c b/lib/librte_pmd_bcm/debug.c
new file mode 100644
index 0000000..4bd2cf3
--- /dev/null
+++ b/lib/librte_pmd_bcm/debug.c
@@ -0,0 +1,113 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bcm.h"
+
+
+/*
+ * Debug versions of the 8/16/32 bit OS register read/write functions to
+ * capture/display values read/written from/to the controller.
+ */
+void
+bcm_reg_write8(struct bcm_softc *sc, size_t offset, uint8_t val)
+{
+	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
+	*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
+}
+
+void
+bcm_reg_write16(struct bcm_softc *sc, size_t offset, uint16_t val)
+{
+	if ((offset % 2) != 0) {
+		PMD_DRV_LOG(DEBUG, "Unaligned 16-bit write to 0x%08lx", offset);
+	}
+
+	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%04x", offset, val);
+	*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
+}
+
+void
+bcm_reg_write32(struct bcm_softc *sc, size_t offset, uint32_t val)
+{
+	if ((offset % 4) != 0) {
+		PMD_DRV_LOG(DEBUG, "Unaligned 32-bit write to 0x%08lx", offset);
+	}
+
+	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+	*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
+}
+
+uint8_t
+bcm_reg_read8(struct bcm_softc *sc, size_t offset)
+{
+	uint8_t val;
+
+	val = (uint8_t)(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
+	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
+
+	return (val);
+}
+
+uint16_t
+bcm_reg_read16(struct bcm_softc *sc, size_t offset)
+{
+	uint16_t val;
+
+	if ((offset % 2) != 0) {
+		PMD_DRV_LOG(DEBUG, "Unaligned 16-bit read from 0x%08lx", offset);
+	}
+
+	val = (uint16_t)(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
+	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+
+	return (val);
+}
+
+uint32_t
+bcm_reg_read32(struct bcm_softc *sc, size_t offset)
+{
+	uint32_t val;
+
+	if ((offset % 4) != 0) {
+		PMD_DRV_LOG(DEBUG, "Unaligned 32-bit read from 0x%08lx", offset);
+		return 0;
+	}
+
+	val = (uint32_t)(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
+	PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+
+	return (val);
+}
diff --git a/lib/librte_pmd_bcm/ecore_fw_defs.h b/lib/librte_pmd_bcm/ecore_fw_defs.h
new file mode 100644
index 0000000..197a82a
--- /dev/null
+++ b/lib/librte_pmd_bcm/ecore_fw_defs.h
@@ -0,0 +1,423 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ECORE_FW_DEFS_H
+#define ECORE_FW_DEFS_H
+
+
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET	(IRO[148].base)
+#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
+	(IRO[147].base + ((assertListEntry) * IRO[147].m1))
+#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
+	(IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
+	IRO[153].m2))
+#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
+	(IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
+	IRO[154].m2))
+#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
+	(IRO[155].base + ((vfId) * IRO[155].m1))
+#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
+	(IRO[156].base + ((vfId) * IRO[156].m1))
+#define CSTORM_VF_TO_PF_OFFSET(funcId) \
+	(IRO[150].base + ((funcId) * IRO[150].m1))
+#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
+	(IRO[159].base + ((funcId) * IRO[159].m1))
+#define CSTORM_FUNC_EN_OFFSET(funcId) \
+	(IRO[149].base + ((funcId) * IRO[149].m1))
+#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
+	(IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))
+#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
+	(IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \
+	* IRO[138].m2) + ((sbId) * IRO[138].m3))
+#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
+#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
+	(IRO[317].base + ((pfId) * IRO[317].m1))
+#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
+	(IRO[318].base + ((pfId) * IRO[318].m1))
+#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
+	(IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
+#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
+	(IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
+	(IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
+#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
+	(IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
+#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
+	(IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
+	(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
+#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
+	(IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))
+#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
+	(IRO[316].base + ((pfId) * IRO[316].m1))
+#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
+	(IRO[308].base + ((pfId) * IRO[308].m1))
+#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
+	(IRO[307].base + ((pfId) * IRO[307].m1))
+#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
+	(IRO[306].base + ((pfId) * IRO[306].m1))
+#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
+	(IRO[151].base + ((funcId) * IRO[151].m1))
+#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
+	(IRO[142].base + ((pfId) * IRO[142].m1))
+#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
+	(IRO[143].base + ((pfId) * IRO[143].m1))
+#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
+	(IRO[141].base + ((pfId) * IRO[141].m1))
+#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)
+#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
+	(IRO[144].base + ((pfId) * IRO[144].m1))
+#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)
+#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
+	(IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))
+#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
+	(IRO[133].base + ((sbId) * IRO[133].m1))
+#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
+	(IRO[134].base + ((sbId) * IRO[134].m1))
+#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
+	(IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))
+#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
+	(IRO[132].base + ((sbId) * IRO[132].m1))
+#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)
+#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
+	(IRO[137].base + ((sbId) * IRO[137].m1))
+#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)
+#define CSTORM_VF_TO_PF_OFFSET(funcId) \
+	(IRO[150].base + ((funcId) * IRO[150].m1))
+#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)
+#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
+	(IRO[203].base + ((pfId) * IRO[203].m1))
+#define TSTORM_ASSERT_LIST_INDEX_OFFSET	(IRO[102].base)
+#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
+	(IRO[101].base + ((assertListEntry) * IRO[101].m1))
+#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
+	(IRO[201].base + ((pfId) * IRO[201].m1))
+#define TSTORM_FUNC_EN_OFFSET(funcId) \
+	(IRO[103].base + ((funcId) * IRO[103].m1))
+#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
+	(IRO[272].base + ((pfId) * IRO[272].m1))
+#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
+	(IRO[271].base + ((pfId) * IRO[271].m1))
+#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
+	(IRO[270].base + ((pfId) * IRO[270].m1))
+#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
+	(IRO[269].base + ((pfId) * IRO[269].m1))
+#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
+	(IRO[268].base + ((pfId) * IRO[268].m1))
+#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
+	(IRO[278].base + ((pfId) * IRO[278].m1))
+#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
+	(IRO[264].base + ((pfId) * IRO[264].m1))
+#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
+	(IRO[265].base + ((pfId) * IRO[265].m1))
+#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
+	(IRO[266].base + ((pfId) * IRO[266].m1))
+#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
+	(IRO[267].base + ((pfId) * IRO[267].m1))
+#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
+	(IRO[202].base + ((pfId) * IRO[202].m1))
+#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
+	(IRO[105].base + ((funcId) * IRO[105].m1))
+#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
+	(IRO[217].base + ((pfId) * IRO[217].m1))
+#define TSTORM_VF_TO_PF_OFFSET(funcId) \
+	(IRO[104].base + ((funcId) * IRO[104].m1))
+#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
+#define USTORM_AGG_DATA_SIZE (IRO[206].size)
+#define USTORM_ASSERT_LIST_INDEX_OFFSET	(IRO[177].base)
+#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
+	(IRO[176].base + ((assertListEntry) * IRO[176].m1))
+#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \
+	(IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * IRO[205].m2))
+#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
+	(IRO[183].base + ((portId) * IRO[183].m1))
+#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
+	(IRO[319].base + ((pfId) * IRO[319].m1))
+#define USTORM_FUNC_EN_OFFSET(funcId) \
+	(IRO[178].base + ((funcId) * IRO[178].m1))
+#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
+	(IRO[283].base + ((pfId) * IRO[283].m1))
+#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
+	(IRO[284].base + ((pfId) * IRO[284].m1))
+#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
+	(IRO[288].base + ((pfId) * IRO[288].m1))
+#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
+	(IRO[285].base + ((pfId) * IRO[285].m1))
+#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
+	(IRO[281].base + ((pfId) * IRO[281].m1))
+#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
+	(IRO[280].base + ((pfId) * IRO[280].m1))
+#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
+	(IRO[279].base + ((pfId) * IRO[279].m1))
+#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
+	(IRO[282].base + ((pfId) * IRO[282].m1))
+#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
+	(IRO[286].base + ((pfId) * IRO[286].m1))
+#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
+	(IRO[287].base + ((pfId) * IRO[287].m1))
+#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
+	(IRO[182].base + ((pfId) * IRO[182].m1))
+#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
+	(IRO[180].base + ((funcId) * IRO[180].m1))
+#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
+	(IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \
+	IRO[209].m2))
+#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
+	(IRO[210].base + ((qzoneId) * IRO[210].m1))
+#define USTORM_TPA_BTR_OFFSET (IRO[207].base)
+#define USTORM_TPA_BTR_SIZE (IRO[207].size)
+#define USTORM_VF_TO_PF_OFFSET(funcId) \
+	(IRO[179].base + ((funcId) * IRO[179].m1))
+#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
+#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
+#define XSTORM_ASSERT_LIST_INDEX_OFFSET	(IRO[51].base)
+#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
+	(IRO[50].base + ((assertListEntry) * IRO[50].m1))
+#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \
+	(IRO[43].base + ((portId) * IRO[43].m1))
+#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \
+	(IRO[45].base + ((pfId) * IRO[45].m1))
+#define XSTORM_FUNC_EN_OFFSET(funcId) \
+	(IRO[47].base + ((funcId) * IRO[47].m1))
+#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
+	(IRO[296].base + ((pfId) * IRO[296].m1))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
+	(IRO[299].base + ((pfId) * IRO[299].m1))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
+	(IRO[300].base + ((pfId) * IRO[300].m1))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
+	(IRO[301].base + ((pfId) * IRO[301].m1))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
+	(IRO[302].base + ((pfId) * IRO[302].m1))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
+	(IRO[303].base + ((pfId) * IRO[303].m1))
+#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
+	(IRO[304].base + ((pfId) * IRO[304].m1))
+#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
+	(IRO[305].base + ((pfId) * IRO[305].m1))
+#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
+	(IRO[295].base + ((pfId) * IRO[295].m1))
+#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
+	(IRO[294].base + ((pfId) * IRO[294].m1))
+#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
+	(IRO[293].base + ((pfId) * IRO[293].m1))
+#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
+	(IRO[298].base + ((pfId) * IRO[298].m1))
+#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
+	(IRO[297].base + ((pfId) * IRO[297].m1))
+#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
+	(IRO[292].base + ((pfId) * IRO[292].m1))
+#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
+	(IRO[291].base + ((pfId) * IRO[291].m1))
+#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
+	(IRO[290].base + ((pfId) * IRO[290].m1))
+#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
+	(IRO[289].base + ((pfId) * IRO[289].m1))
+#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
+	(IRO[44].base + ((pfId) * IRO[44].m1))
+#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
+	(IRO[49].base + ((funcId) * IRO[49].m1))
+#define XSTORM_SPQ_DATA_OFFSET(funcId) \
+	(IRO[32].base + ((funcId) * IRO[32].m1))
+#define XSTORM_SPQ_DATA_SIZE (IRO[32].size)
+#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \
+	(IRO[30].base + ((funcId) * IRO[30].m1))
+#define XSTORM_SPQ_PROD_OFFSET(funcId) \
+	(IRO[31].base + ((funcId) * IRO[31].m1))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
+	(IRO[211].base + ((portId) * IRO[211].m1))
+#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
+	(IRO[212].base + ((portId) * IRO[212].m1))
+#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
+	(IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \
+	IRO[214].m2))
+#define XSTORM_VF_TO_PF_OFFSET(funcId) \
+	(IRO[48].base + ((funcId) * IRO[48].m1))
+#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)
+
+
+/* Ethernet Ring parameters */
+#define X_ETH_LOCAL_RING_SIZE 13
+#define FIRST_BD_IN_PKT	0
+#define PARSE_BD_INDEX 1
+#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
+
+/* Rx ring params */
+#define U_ETH_LOCAL_BD_RING_SIZE 8
+#define U_ETH_SGL_SIZE 8
+	/* The fw will padd the buffer with this value, so the IP header \
+	will be align to 4 Byte */
+#define IP_HEADER_ALIGNMENT_PADDING 2
+
+#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
+#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+
+#define U_ETH_BDS_PER_PAGE_MASK	(U_ETH_BDS_PER_PAGE-1)
+#define U_ETH_CQE_PER_PAGE_MASK	(TU_ETH_CQES_PER_PAGE-1)
+
+#define U_ETH_UNDEFINED_Q 0xFF
+
+#define T_ETH_INDIRECTION_TABLE_SIZE 128
+#define T_ETH_RSS_KEY 10
+#define ETH_NUM_OF_RSS_ENGINES_E2 72
+
+#define FILTER_RULES_COUNT 16
+#define MULTICAST_RULES_COUNT 16
+#define CLASSIFY_RULES_COUNT 16
+
+/*The CRC32 seed, that is used for the hash(reduction) multicast address */
+#define ETH_CRC32_HASH_SEED 0x00000000
+
+#define ETH_CRC32_HASH_BIT_SIZE	(8)
+#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
+
+/* Maximal L2 clients supported */
+#define ETH_MAX_RX_CLIENTS_E1H 28
+#define ETH_MAX_RX_CLIENTS_E2 152
+
+/* Maximal statistics client Ids */
+#define MAX_STAT_COUNTER_ID_E1H	56
+#define MAX_STAT_COUNTER_ID_E2 140
+
+#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
+#define MAX_MAC_CREDIT_E2 272 /* Per Path */
+#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
+#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
+
+
+/* Maximal aggregation queues supported */
+#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
+
+
+#define ETH_NUM_OF_MCAST_BINS 256
+#define ETH_NUM_OF_MCAST_ENGINES_E2 72
+
+#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
+#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
+	(ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
+
+#define DISABLE_STATISTIC_COUNTER_ID_VALUE 0
+
+
+/* This file defines HSI constants common to all microcode flows */
+
+/* offset in bits of protocol in the state context parameter */
+#define PROTOCOL_STATE_BIT_OFFSET 6
+
+#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+
+/* microcode fixed page page size 4K (chains and ring segments) */
+#define MC_PAGE_SIZE 4096
+
+/* Number of indices per slow-path SB */
+#define HC_SP_SB_MAX_INDICES 16 /* The Maximum of all */
+
+/* Number of indices per SB */
+#define HC_SB_MAX_INDICES_E1X 8 /* Multiple of 4 */
+#define HC_SB_MAX_INDICES_E2 8 /* Multiple of 4 */
+
+/* Number of SB */
+#define HC_SB_MAX_SB_E1X 32
+#define HC_SB_MAX_SB_E2	136 /* include PF */
+
+/* ID of slow path status block */
+#define HC_SP_SB_ID 0xde
+
+/* Num of State machines */
+#define HC_SB_MAX_SM 2 /* Fixed */
+
+/* Num of dynamic indices */
+#define HC_SB_MAX_DYNAMIC_INDICES 4 /* 0..3 fixed */
+
+/* max number of slow path commands per port */
+#define MAX_RAMRODS_PER_PORT 8
+
+
+/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
+
+/* chip timers frequency constants */
+#define TIMERS_TICK_SIZE_CHIP (1e-3)
+
+/* used in toe: TsRecentAge, MaxRt, and temporarily RTT */
+#define TSEMI_CLK1_RESUL_CHIP (1e-3)
+
+/* temporarily used for RTT */
+#define XSEMI_CLK1_RESUL_CHIP (1e-3)
+
+/* used for Host Coallescing */
+#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
+
+/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
+
+#define XSTORM_IP_ID_ROLL_HALF 0x8000
+#define XSTORM_IP_ID_ROLL_ALL 0
+
+/* assert list: number of entries */
+#define FW_LOG_LIST_SIZE 50
+
+#define NUM_OF_SAFC_BITS 16
+#define MAX_COS_NUMBER 4
+#define MAX_TRAFFIC_TYPES 8
+#define MAX_PFC_PRIORITIES 8
+
+	/* used by array traffic_type_to_priority[] to mark traffic type \
+	that is not mapped to priority*/
+#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
+
+/* Event Ring definitions */
+#define C_ERES_PER_PAGE \
+	(PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))
+#define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)
+
+/* number of statistic command */
+#define STATS_QUERY_CMD_COUNT 16
+
+/* niv list table size */
+#define AFEX_LIST_TABLE_SIZE 4096
+
+/* invalid VNIC Id. used in VNIC classification */
+#define INVALID_VNIC_ID	0xFF
+
+/* used for indicating an undefined RAM offset in the IRO arrays */
+#define UNDEF_IRO 0x80000000
+
+/* used for defining the amount of FCoE tasks supported for PF */
+#define MAX_FCOE_FUNCS_PER_ENGINE 2
+#define MAX_NUM_FCOE_TASKS_PER_ENGINE \
+	4096 /*Each port can have at max 1 function*/
+
+
+#endif /* ECORE_FW_DEFS_H */
+
diff --git a/lib/librte_pmd_bcm/ecore_hsi.h b/lib/librte_pmd_bcm/ecore_hsi.h
new file mode 100644
index 0000000..673d0c0
--- /dev/null
+++ b/lib/librte_pmd_bcm/ecore_hsi.h
@@ -0,0 +1,6349 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ECORE_HSI_H
+#define ECORE_HSI_H
+
+#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
+
+struct license_key {
+    uint32_t reserved[6];
+
+    uint32_t max_iscsi_conn;
+#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK  0xFFFF
+#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
+#define LICENSE_MAX_ISCSI_INIT_CONN_MASK  0xFFFF0000
+#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
+
+    uint32_t reserved_a;
+
+    uint32_t max_fcoe_conn;
+#define LICENSE_MAX_FCOE_TRGT_CONN_MASK  0xFFFF
+#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
+#define LICENSE_MAX_FCOE_INIT_CONN_MASK  0xFFFF0000
+#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
+
+    uint32_t reserved_b[4];
+};
+
+typedef struct license_key license_key_t;
+
+
+/****************************************************************************
+ * Shared HW configuration                                                  *
+ ****************************************************************************/
+#define PIN_CFG_NA                          0x00000000
+#define PIN_CFG_GPIO0_P0                    0x00000001
+#define PIN_CFG_GPIO1_P0                    0x00000002
+#define PIN_CFG_GPIO2_P0                    0x00000003
+#define PIN_CFG_GPIO3_P0                    0x00000004
+#define PIN_CFG_GPIO0_P1                    0x00000005
+#define PIN_CFG_GPIO1_P1                    0x00000006
+#define PIN_CFG_GPIO2_P1                    0x00000007
+#define PIN_CFG_GPIO3_P1                    0x00000008
+#define PIN_CFG_EPIO0                       0x00000009
+#define PIN_CFG_EPIO1                       0x0000000a
+#define PIN_CFG_EPIO2                       0x0000000b
+#define PIN_CFG_EPIO3                       0x0000000c
+#define PIN_CFG_EPIO4                       0x0000000d
+#define PIN_CFG_EPIO5                       0x0000000e
+#define PIN_CFG_EPIO6                       0x0000000f
+#define PIN_CFG_EPIO7                       0x00000010
+#define PIN_CFG_EPIO8                       0x00000011
+#define PIN_CFG_EPIO9                       0x00000012
+#define PIN_CFG_EPIO10                      0x00000013
+#define PIN_CFG_EPIO11                      0x00000014
+#define PIN_CFG_EPIO12                      0x00000015
+#define PIN_CFG_EPIO13                      0x00000016
+#define PIN_CFG_EPIO14                      0x00000017
+#define PIN_CFG_EPIO15                      0x00000018
+#define PIN_CFG_EPIO16                      0x00000019
+#define PIN_CFG_EPIO17                      0x0000001a
+#define PIN_CFG_EPIO18                      0x0000001b
+#define PIN_CFG_EPIO19                      0x0000001c
+#define PIN_CFG_EPIO20                      0x0000001d
+#define PIN_CFG_EPIO21                      0x0000001e
+#define PIN_CFG_EPIO22                      0x0000001f
+#define PIN_CFG_EPIO23                      0x00000020
+#define PIN_CFG_EPIO24                      0x00000021
+#define PIN_CFG_EPIO25                      0x00000022
+#define PIN_CFG_EPIO26                      0x00000023
+#define PIN_CFG_EPIO27                      0x00000024
+#define PIN_CFG_EPIO28                      0x00000025
+#define PIN_CFG_EPIO29                      0x00000026
+#define PIN_CFG_EPIO30                      0x00000027
+#define PIN_CFG_EPIO31                      0x00000028
+
+/* EPIO definition */
+#define EPIO_CFG_NA                         0x00000000
+#define EPIO_CFG_EPIO0                      0x00000001
+#define EPIO_CFG_EPIO1                      0x00000002
+#define EPIO_CFG_EPIO2                      0x00000003
+#define EPIO_CFG_EPIO3                      0x00000004
+#define EPIO_CFG_EPIO4                      0x00000005
+#define EPIO_CFG_EPIO5                      0x00000006
+#define EPIO_CFG_EPIO6                      0x00000007
+#define EPIO_CFG_EPIO7                      0x00000008
+#define EPIO_CFG_EPIO8                      0x00000009
+#define EPIO_CFG_EPIO9                      0x0000000a
+#define EPIO_CFG_EPIO10                     0x0000000b
+#define EPIO_CFG_EPIO11                     0x0000000c
+#define EPIO_CFG_EPIO12                     0x0000000d
+#define EPIO_CFG_EPIO13                     0x0000000e
+#define EPIO_CFG_EPIO14                     0x0000000f
+#define EPIO_CFG_EPIO15                     0x00000010
+#define EPIO_CFG_EPIO16                     0x00000011
+#define EPIO_CFG_EPIO17                     0x00000012
+#define EPIO_CFG_EPIO18                     0x00000013
+#define EPIO_CFG_EPIO19                     0x00000014
+#define EPIO_CFG_EPIO20                     0x00000015
+#define EPIO_CFG_EPIO21                     0x00000016
+#define EPIO_CFG_EPIO22                     0x00000017
+#define EPIO_CFG_EPIO23                     0x00000018
+#define EPIO_CFG_EPIO24                     0x00000019
+#define EPIO_CFG_EPIO25                     0x0000001a
+#define EPIO_CFG_EPIO26                     0x0000001b
+#define EPIO_CFG_EPIO27                     0x0000001c
+#define EPIO_CFG_EPIO28                     0x0000001d
+#define EPIO_CFG_EPIO29                     0x0000001e
+#define EPIO_CFG_EPIO30                     0x0000001f
+#define EPIO_CFG_EPIO31                     0x00000020
+
+struct mac_addr {
+	uint32_t upper;
+	uint32_t lower;
+};
+
+
+struct shared_hw_cfg {			 /* NVRAM Offset */
+	/* Up to 16 bytes of NULL-terminated string */
+	uint8_t  part_num[16];		    /* 0x104 */
+
+	uint32_t config;			/* 0x114 */
+	#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
+		#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
+		#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
+		#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
+
+	#define SHARED_HW_CFG_PORT_SWAP                     0x00000004
+
+	    #define SHARED_HW_CFG_BEACON_WOL_EN                  0x00000008
+
+	    #define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
+	    #define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
+
+	#define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
+		#define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
+	/* Whatever MFW found in NVM
+	   (if multiple found, priority order is: NC-SI, UMP, IPMI) */
+		#define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
+		#define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
+		#define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
+		#define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
+	/* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
+	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
+		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
+	/* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
+	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
+		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
+	/* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
+	  (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
+		#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
+
+	/* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For
+	   backwards compatibility, value of 0 is disabling this feature.
+	    That means that though 0 is a valid value, it cannot be
+	    configured. */
+	#define SHARED_HW_CFG_G2_TX_DRIVE_MASK                        0x0000F000
+	#define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT                       12
+
+	#define SHARED_HW_CFG_LED_MODE_MASK                 0x000F0000
+		#define SHARED_HW_CFG_LED_MODE_SHIFT                 16
+		#define SHARED_HW_CFG_LED_MAC1                       0x00000000
+		#define SHARED_HW_CFG_LED_PHY1                       0x00010000
+		#define SHARED_HW_CFG_LED_PHY2                       0x00020000
+		#define SHARED_HW_CFG_LED_PHY3                       0x00030000
+		#define SHARED_HW_CFG_LED_MAC2                       0x00040000
+		#define SHARED_HW_CFG_LED_PHY4                       0x00050000
+		#define SHARED_HW_CFG_LED_PHY5                       0x00060000
+		#define SHARED_HW_CFG_LED_PHY6                       0x00070000
+		#define SHARED_HW_CFG_LED_MAC3                       0x00080000
+		#define SHARED_HW_CFG_LED_PHY7                       0x00090000
+		#define SHARED_HW_CFG_LED_PHY9                       0x000a0000
+		#define SHARED_HW_CFG_LED_PHY11                      0x000b0000
+		#define SHARED_HW_CFG_LED_MAC4                       0x000c0000
+		#define SHARED_HW_CFG_LED_PHY8                       0x000d0000
+		#define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
+		#define SHARED_HW_CFG_LED_EXTPHY2                    0x000f0000
+
+    #define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
+		#define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
+		#define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
+
+	#define SHARED_HW_CFG_ATC_MASK                      0x80000000
+		#define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
+		#define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
+
+	uint32_t config2;			    /* 0x118 */
+
+	#define SHARED_HW_CFG_PCIE_GEN2_MASK                0x00000100
+	    #define SHARED_HW_CFG_PCIE_GEN2_SHIFT                8
+	    #define SHARED_HW_CFG_PCIE_GEN2_DISABLED             0x00000000
+	#define SHARED_HW_CFG_PCIE_GEN2_ENABLED              0x00000100
+
+	#define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
+		#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
+		#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
+
+	#define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
+
+
+		/* Output low when PERST is asserted */
+	#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
+		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
+		#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
+
+	#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
+		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
+		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
+		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
+		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
+		#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
+
+	/*  The fan failure mechanism is usually related to the PHY type
+	      since the power consumption of the board is determined by the PHY.
+	      Currently, fan is required for most designs with SFX7101, BCM8727
+	      and BCM8481. If a fan is not required for a board which uses one
+	      of those PHYs, this field should be set to "Disabled". If a fan is
+	      required for a different PHY type, this option should be set to
+	      "Enabled". The fan failure indication is expected on SPIO5 */
+	#define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
+		#define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
+		#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
+		#define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
+		#define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
+
+		/* ASPM Power Management support */
+	#define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
+		#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
+		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
+		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
+		#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
+		#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
+
+	/* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
+	   tl_control_0 (register 0x2800) */
+	#define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
+		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
+		#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
+
+
+	/*  Set the MDC/MDIO access for the first external phy */
+	#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
+
+	/*  Set the MDC/MDIO access for the second external phy */
+	#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
+		#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
+
+	/*  Max number of PF MSIX vectors */
+	uint32_t config_3;                                       /* 0x11C */
+	#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK                    0x0000007F
+	#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT                   0
+
+	uint32_t ump_nc_si_config;			/* 0x120 */
+	#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
+		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
+		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
+		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
+		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
+		#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
+
+	/* Reserved bits: 226-230 */
+
+	/*  The output pin template BSC_SEL which selects the I2C for this
+	port in the I2C Mux */
+	uint32_t board;			/* 0x124 */
+	#define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
+	    #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT              0
+
+	#define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
+	#define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
+	/* Use the PIN_CFG_XXX defines on top */
+	#define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
+	#define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
+
+	#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
+	#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
+
+	#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
+	#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
+
+	uint32_t wc_lane_config;				    /* 0x128 */
+	#define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
+		#define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
+		#define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
+		#define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
+		#define SHARED_HW_CFG_LANE_SWAP_CFG_31200213         0x000027d8
+		#define SHARED_HW_CFG_LANE_SWAP_CFG_02133120         0x0000d827
+		#define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
+		#define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
+	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
+	#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
+	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
+	#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
+
+	/* TX lane Polarity swap */
+	#define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
+	#define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
+	#define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
+	#define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
+	/* TX lane Polarity swap */
+	#define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
+	#define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
+	#define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
+	#define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
+
+	/*  Selects the port layout of the board */
+	#define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
+		#define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
+		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
+		#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
+		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
+		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
+		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
+		#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
+};
+
+
+/****************************************************************************
+ * Port HW configuration                                                    *
+ ****************************************************************************/
+struct port_hw_cfg {		    /* port 0: 0x12c  port 1: 0x2bc */
+
+	uint32_t pci_id;
+	#define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000FFFF
+	#define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT             0
+
+	#define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xFFFF0000
+	#define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT             16
+
+	uint32_t pci_sub_id;
+	#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000FFFF
+	#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT      0
+
+	#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xFFFF0000
+	#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT      16
+
+	uint32_t power_dissipated;
+	#define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000FF
+	#define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
+	#define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000FF00
+	#define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
+	#define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00FF0000
+	#define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
+	#define PORT_HW_CFG_POWER_DIS_D3_MASK               0xFF000000
+	#define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
+
+	uint32_t power_consumed;
+	#define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000FF
+	#define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
+	#define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000FF00
+	#define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
+	#define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00FF0000
+	#define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
+	#define PORT_HW_CFG_POWER_CONS_D3_MASK              0xFF000000
+	#define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
+
+	uint32_t mac_upper;
+	uint32_t mac_lower;                                      /* 0x140 */
+	#define PORT_HW_CFG_UPPERMAC_MASK                   0x0000FFFF
+	#define PORT_HW_CFG_UPPERMAC_SHIFT                           0
+
+
+	uint32_t iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
+	uint32_t iscsi_mac_lower;
+
+	uint32_t rdma_mac_upper;   /* Upper 16 bits are always zeroes */
+	uint32_t rdma_mac_lower;
+
+	uint32_t serdes_config;
+	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
+	#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
+
+	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xFFFF0000
+	#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
+
+
+	/*  Default values: 2P-64, 4P-32 */
+	uint32_t reserved;
+
+	uint32_t vf_config;					    /* 0x15C */
+	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
+	#define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
+
+	uint32_t mf_pci_id;					    /* 0x160 */
+	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
+	#define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
+
+	/*  Controls the TX laser of the SFP+ module */
+	uint32_t sfp_ctrl;					    /* 0x164 */
+	#define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
+		#define PORT_HW_CFG_TX_LASER_SHIFT                   0
+		#define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
+		#define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
+		#define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
+		#define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
+		#define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
+
+	/*  Controls the fault module LED of the SFP+ */
+	#define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
+		#define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
+		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
+		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
+		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
+		#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
+		#define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
+
+	/*  The output pin TX_DIS that controls the TX laser of the SFP+
+	  module. Use the PIN_CFG_XXX defines on top */
+	uint32_t e3_sfp_ctrl;				    /* 0x168 */
+	#define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
+	#define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
+
+	/*  The output pin for SFPP_TYPE which turns on the Fault module LED */
+	#define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
+	#define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
+
+	/*  The input pin MOD_ABS that indicates whether SFP+ module is
+	  present or not. Use the PIN_CFG_XXX defines on top */
+	#define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
+	#define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
+
+	/*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
+	  module. Use the PIN_CFG_XXX defines on top */
+	#define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
+	#define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
+
+	/*
+	 * The input pin which signals module transmit fault. Use the
+	 * PIN_CFG_XXX defines on top
+	 */
+	uint32_t e3_cmn_pin_cfg;				    /* 0x16C */
+	#define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
+	#define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
+
+	/*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
+	 top */
+	#define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
+	#define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
+
+	/*
+	 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
+	 * defines on top
+	 */
+	#define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
+	#define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
+
+	/*  The output pin values BSC_SEL which selects the I2C for this port
+	  in the I2C Mux */
+	#define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
+	#define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
+
+
+	/*
+	 * The input pin I_FAULT which indicate over-current has occurred.
+	 * Use the PIN_CFG_XXX defines on top
+	 */
+	uint32_t e3_cmn_pin_cfg1;				    /* 0x170 */
+	#define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
+	#define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
+
+	/*  pause on host ring */
+	uint32_t generic_features;                               /* 0x174 */
+	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001
+	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0
+	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000
+	#define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED                0x00000001
+
+	/* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
+	 * LOM recommended and tested value is 0xBEB2. Using a different
+	 * value means using a value not tested by BRCM
+	 */
+	uint32_t sfi_tap_values;                                 /* 0x178 */
+	#define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF
+	#define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0
+
+	/* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
+	 * value is 0x2. LOM recommended and tested value is 0x2. Using a
+	 * different value means using a value not tested by BRCM
+	 */
+	#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
+	#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
+
+	uint32_t reserved0[5];				    /* 0x17c */
+
+	uint32_t aeu_int_mask;				    /* 0x190 */
+
+	uint32_t media_type;					    /* 0x194 */
+	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
+	#define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
+
+	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
+	#define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
+
+	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
+	#define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
+
+	/*  4 times 16 bits for all 4 lanes. In case external PHY is present
+	      (not direct mode), those values will not take effect on the 4 XGXS
+	      lanes. For some external PHYs (such as 8706 and 8726) the values
+	      will be used to configure the external PHY  in those cases, not
+	      all 4 values are needed. */
+	uint16_t xgxs_config_rx[4];			/* 0x198 */
+	uint16_t xgxs_config_tx[4];			/* 0x1A0 */
+
+
+	/* For storing FCOE mac on shared memory */
+	uint32_t fcoe_fip_mac_upper;
+	#define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
+	#define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
+	uint32_t fcoe_fip_mac_lower;
+
+	uint32_t fcoe_wwn_port_name_upper;
+	uint32_t fcoe_wwn_port_name_lower;
+
+	uint32_t fcoe_wwn_node_name_upper;
+	uint32_t fcoe_wwn_node_name_lower;
+
+	/*  wwpn for npiv enabled */
+	uint32_t wwpn_for_npiv_config;                           /* 0x1C0 */
+	#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK                0x00000001
+	#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT               0
+	#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED            0x00000000
+	#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED             0x00000001
+
+	/*  wwpn for npiv valid addresses */
+	uint32_t wwpn_for_npiv_valid_addresses;                  /* 0x1C4 */
+	#define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK         0x0000FFFF
+	#define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT        0
+
+	struct mac_addr wwpn_for_niv_macs[16];
+
+	/* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */
+	uint32_t Reserved1[14];
+
+	uint32_t pf_allocation;                                  /* 0x280 */
+	/* number of vfs per PF, if 0 - sriov disabled */
+	#define PORT_HW_CFG_NUMBER_OF_VFS_MASK                        0x000000FF
+	#define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT                       0
+
+	/*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
+	      84833 only */
+	uint32_t xgbt_phy_cfg;				    /* 0x284 */
+	#define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
+	#define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
+
+		uint32_t default_cfg;			    /* 0x288 */
+	#define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
+		#define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
+		#define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
+		#define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
+		#define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
+		#define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
+
+	#define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
+		#define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
+		#define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
+		#define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
+		#define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
+		#define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
+
+	#define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
+		#define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
+		#define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
+		#define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
+		#define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
+		#define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
+
+	#define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
+		#define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
+		#define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
+		#define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
+		#define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
+		#define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
+
+	/*  When KR link is required to be set to force which is not
+	      KR-compliant, this parameter determine what is the trigger for it.
+	      When GPIO is selected, low input will force the speed. Currently
+	      default speed is 1G. In the future, it may be widen to select the
+	      forced speed in with another parameter. Note when force-1G is
+	      enabled, it override option 56: Link Speed option. */
+	#define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
+		#define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
+	/*  Enable to determine with which GPIO to reset the external phy */
+	#define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
+		#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
+
+	/*  Enable BAM on KR */
+	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
+	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
+	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
+	#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
+
+	/*  Enable Common Mode Sense */
+	#define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
+	#define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
+	#define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
+	#define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
+
+	/*  Determine the Serdes electrical interface   */
+	#define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
+	#define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
+	#define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
+	#define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
+	#define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
+	#define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
+	#define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
+	#define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
+
+	/*  SFP+ main TAP and post TAP volumes */
+	#define PORT_HW_CFG_TAP_LEVELS_MASK                           0x70000000
+	#define PORT_HW_CFG_TAP_LEVELS_SHIFT                          28
+	#define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43                0x00000000
+	#define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44                0x10000000
+	#define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45                0x20000000
+	#define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46                0x30000000
+	#define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47                0x40000000
+	#define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48                0x50000000
+
+	uint32_t speed_capability_mask2;			    /* 0x28C */
+	#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF    0x00000002
+	    #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF   0x00000004
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G        0x00000020
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
+
+	#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF    0x00020000
+	    #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF   0x00040000
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G        0x00200000
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
+		#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
+
+
+	/*  In the case where two media types (e.g. copper and fiber) are
+	      present and electrically active at the same time, PHY Selection
+	      will determine which of the two PHYs will be designated as the
+	      Active PHY and used for a connection to the network.  */
+	uint32_t multi_phy_config;				    /* 0x290 */
+	#define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
+		#define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
+		#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
+		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
+		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
+		#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
+		#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
+
+	/*  When enabled, all second phy nvram parameters will be swapped
+	      with the first phy parameters */
+	#define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
+		#define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
+		#define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
+		#define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
+
+
+	/*  Address of the second external phy */
+	uint32_t external_phy_config2;			    /* 0x294 */
+	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
+	#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
+
+	/*  The second XGXS external PHY type */
+	#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834      0x00001100
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
+		#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
+
+
+	/*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
+	      8706, 8726 and 8727) not all 4 values are needed. */
+	uint16_t xgxs_config2_rx[4];				    /* 0x296 */
+	uint16_t xgxs_config2_tx[4];				    /* 0x2A0 */
+
+	uint32_t lane_config;
+	#define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000FFFF
+		#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
+		/* AN and forced */
+		#define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
+		/* forced only */
+		#define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
+		/* forced only */
+		#define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
+		/* forced only */
+		#define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
+	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000FF
+	#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
+	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000FF00
+	#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
+	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000C000
+	#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
+
+	/*  Indicate whether to swap the external phy polarity */
+	#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
+		#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
+		#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
+
+
+	uint32_t external_phy_config;
+	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000FF
+	#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
+
+	#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000FF00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834       0x00001100
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
+		#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
+
+	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00FF0000
+	#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
+
+	#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xFF000000
+		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
+		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
+		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
+		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
+		#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
+
+	uint32_t speed_capability_mask;
+	#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000FFFF
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
+
+	#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xFFFF0000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
+		#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
+
+	/*  A place to hold the original MAC address as a backup */
+	uint32_t backup_mac_upper;			/* 0x2B4 */
+	uint32_t backup_mac_lower;			/* 0x2B8 */
+
+};
+
+
+/****************************************************************************
+ * Shared Feature configuration                                             *
+ ****************************************************************************/
+struct shared_feat_cfg {		 /* NVRAM Offset */
+
+	uint32_t config;			/* 0x450 */
+	#define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
+
+	/* Use NVRAM values instead of HW default values */
+	#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
+							    0x00000002
+		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
+								     0x00000000
+		#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
+								     0x00000002
+
+	#define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
+		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
+		#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
+
+	#define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
+	#define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
+
+	/*  Override the OTP back to single function mode. When using GPIO,
+	      high means only SF, 0 is according to CLP configuration */
+	#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
+		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
+		#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
+		#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
+		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
+		#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
+		#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400
+
+	/*  Act as if the FCoE license is invalid */
+	#define SHARED_FEAT_CFG_PREVENT_FCOE                0x00001000
+
+    /*  Force FLR capability to all ports */
+	#define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY        0x00002000
+
+	/*  Act as if the iSCSI license is invalid */
+	#define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK                    0x00004000
+	#define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT                   14
+	#define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED                0x00000000
+	#define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED                 0x00004000
+
+	/* The interval in seconds between sending LLDP packets. Set to zero
+	   to disable the feature */
+	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00FF0000
+	#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
+
+	/* The assigned device type ID for LLDP usage */
+	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xFF000000
+	#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
+
+};
+
+
+/****************************************************************************
+ * Port Feature configuration                                               *
+ ****************************************************************************/
+struct port_feat_cfg {		    /* port 0: 0x454  port 1: 0x4c8 */
+
+	uint32_t config;
+	#define PORT_FEAT_CFG_BAR1_SIZE_MASK                 0x0000000F
+		#define PORT_FEAT_CFG_BAR1_SIZE_SHIFT                 0
+		#define PORT_FEAT_CFG_BAR1_SIZE_DISABLED              0x00000000
+		#define PORT_FEAT_CFG_BAR1_SIZE_64K                   0x00000001
+		#define PORT_FEAT_CFG_BAR1_SIZE_128K                  0x00000002
+		#define PORT_FEAT_CFG_BAR1_SIZE_256K                  0x00000003
+		#define PORT_FEAT_CFG_BAR1_SIZE_512K                  0x00000004
+		#define PORT_FEAT_CFG_BAR1_SIZE_1M                    0x00000005
+		#define PORT_FEAT_CFG_BAR1_SIZE_2M                    0x00000006
+		#define PORT_FEAT_CFG_BAR1_SIZE_4M                    0x00000007
+		#define PORT_FEAT_CFG_BAR1_SIZE_8M                    0x00000008
+		#define PORT_FEAT_CFG_BAR1_SIZE_16M                   0x00000009
+		#define PORT_FEAT_CFG_BAR1_SIZE_32M                   0x0000000a
+		#define PORT_FEAT_CFG_BAR1_SIZE_64M                   0x0000000b
+		#define PORT_FEAT_CFG_BAR1_SIZE_128M                  0x0000000c
+		#define PORT_FEAT_CFG_BAR1_SIZE_256M                  0x0000000d
+		#define PORT_FEAT_CFG_BAR1_SIZE_512M                  0x0000000e
+		#define PORT_FEAT_CFG_BAR1_SIZE_1G                    0x0000000f
+	#define PORT_FEAT_CFG_BAR2_SIZE_MASK                 0x000000F0
+		#define PORT_FEAT_CFG_BAR2_SIZE_SHIFT                 4
+		#define PORT_FEAT_CFG_BAR2_SIZE_DISABLED              0x00000000
+		#define PORT_FEAT_CFG_BAR2_SIZE_64K                   0x00000010
+		#define PORT_FEAT_CFG_BAR2_SIZE_128K                  0x00000020
+		#define PORT_FEAT_CFG_BAR2_SIZE_256K                  0x00000030
+		#define PORT_FEAT_CFG_BAR2_SIZE_512K                  0x00000040
+		#define PORT_FEAT_CFG_BAR2_SIZE_1M                    0x00000050
+		#define PORT_FEAT_CFG_BAR2_SIZE_2M                    0x00000060
+		#define PORT_FEAT_CFG_BAR2_SIZE_4M                    0x00000070
+		#define PORT_FEAT_CFG_BAR2_SIZE_8M                    0x00000080
+		#define PORT_FEAT_CFG_BAR2_SIZE_16M                   0x00000090
+		#define PORT_FEAT_CFG_BAR2_SIZE_32M                   0x000000a0
+		#define PORT_FEAT_CFG_BAR2_SIZE_64M                   0x000000b0
+		#define PORT_FEAT_CFG_BAR2_SIZE_128M                  0x000000c0
+		#define PORT_FEAT_CFG_BAR2_SIZE_256M                  0x000000d0
+		#define PORT_FEAT_CFG_BAR2_SIZE_512M                  0x000000e0
+		#define PORT_FEAT_CFG_BAR2_SIZE_1G                    0x000000f0
+
+	#define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
+		#define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
+		#define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
+
+    #define PORT_FEAT_CFG_AUTOGREEEN_MASK               0x00000200
+	    #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT               9
+	    #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED            0x00000000
+	    #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED             0x00000200
+
+	#define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK                0x00000C00
+	#define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT               10
+	#define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT             0x00000000
+	#define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE                0x00000400
+	#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI               0x00000800
+	#define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH                0x00000c00
+
+	#define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
+	#define PORT_FEATURE_EN_SIZE_SHIFT                       24
+	#define PORT_FEATURE_WOL_ENABLED                         0x01000000
+	#define PORT_FEATURE_MBA_ENABLED                         0x02000000
+	#define PORT_FEATURE_MFW_ENABLED                         0x04000000
+
+	/* Advertise expansion ROM even if MBA is disabled */
+	#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
+		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
+		#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
+
+	/* Check the optic vendor via i2c against a list of approved modules
+	   in a separate nvram image */
+	#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xE0000000
+		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
+		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
+								     0x00000000
+		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
+								     0x20000000
+		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
+		#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
+
+	uint32_t wol_config;
+	/* Default is used when driver sets to "auto" mode */
+	#define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
+
+	uint32_t mba_config;
+	#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
+		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
+		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
+		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
+		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
+		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
+		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
+		#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
+
+	#define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
+	#define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
+
+    #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
+	#define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
+		#define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
+		#define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
+
+	#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000FF000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
+		#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
+	#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00F00000
+	#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
+	#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
+		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
+		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
+		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
+		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
+		#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
+	#define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3C000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
+		#define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF         0x04000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL         0x08000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF        0x0c000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL        0x10000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_1G               0x14000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_2_5G             0x18000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_10G              0x1c000000
+		#define PORT_FEATURE_MBA_LINK_SPEED_20G              0x20000000
+
+	uint32_t Reserved0;                                      /* 0x460 */
+
+	uint32_t mba_vlan_cfg;
+	#define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000FFFF
+	#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
+	#define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
+
+	uint32_t Reserved1;
+	uint32_t smbus_config;
+	#define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
+	#define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
+
+	uint32_t vf_config;
+	#define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000F
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
+		#define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
+
+	uint32_t link_config;    /* Used as HW defaults for the driver */
+
+    #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
+		#define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
+		#define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
+		#define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
+		#define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
+		#define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
+		#define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
+		#define PORT_FEATURE_FLOW_CONTROL_SAFC_RX            0x00000500
+		#define PORT_FEATURE_FLOW_CONTROL_SAFC_TX            0x00000600
+		#define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH          0x00000700
+
+    #define PORT_FEATURE_LINK_SPEED_MASK                0x000F0000
+		#define PORT_FEATURE_LINK_SPEED_SHIFT                16
+		#define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
+		#define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00010000
+		#define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00020000
+		#define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
+		#define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
+		#define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
+		#define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
+		#define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
+		#define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
+
+	#define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
+		#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
+		/* (forced) low speed switch (< 10G) */
+		#define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
+		/* (forced) high speed switch (>= 10G) */
+		#define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
+		#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
+		#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
+
+
+	/* The default for MCP link configuration,
+	   uses the same defines as link_config */
+	uint32_t mfw_wol_link_cfg;
+
+	/* The default for the driver of the second external phy,
+	   uses the same defines as link_config */
+	uint32_t link_config2;				    /* 0x47C */
+
+	/* The default for MCP of the second external phy,
+	   uses the same defines as link_config */
+	uint32_t mfw_wol_link_cfg2;				    /* 0x480 */
+
+
+	/*  EEE power saving mode */
+	uint32_t eee_power_mode;                                 /* 0x484 */
+	#define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
+	#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
+	#define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
+	#define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x00000001
+	#define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x00000002
+	#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
+
+
+	uint32_t Reserved2[16];                                  /* 0x488 */
+};
+
+/****************************************************************************
+ * Device Information                                                       *
+ ****************************************************************************/
+struct shm_dev_info {				/* size */
+
+	uint32_t    bc_rev; /* 8 bits each: major, minor, build */	       /* 4 */
+
+	struct shared_hw_cfg     shared_hw_config;	      /* 40 */
+
+	struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
+
+	struct shared_feat_cfg   shared_feature_config;		   /* 4 */
+
+	struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
+
+};
+
+struct extended_dev_info_shared_cfg {             /* NVRAM OFFSET */
+
+	/*  Threshold in celcius to start using the fan */
+	uint32_t temperature_monitor1;                           /* 0x4000 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK     0x0000007F
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT    0
+
+	/*  Threshold in celcius to shut down the board */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK    0x00007F00
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT   8
+
+	/*  EPIO of fan temperature status */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK       0x00FF0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT      16
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA         0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0      0x00010000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1      0x00020000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2      0x00030000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3      0x00040000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4      0x00050000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5      0x00060000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6      0x00070000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7      0x00080000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8      0x00090000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9      0x000a0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10     0x000b0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11     0x000c0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12     0x000d0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13     0x000e0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14     0x000f0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15     0x00100000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16     0x00110000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17     0x00120000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18     0x00130000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19     0x00140000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20     0x00150000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21     0x00160000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22     0x00170000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23     0x00180000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24     0x00190000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25     0x001a0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26     0x001b0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27     0x001c0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28     0x001d0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29     0x001e0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30     0x001f0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31     0x00200000
+
+	/*  EPIO of shut down temperature status */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK      0xFF000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT     24
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA        0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0     0x01000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1     0x02000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2     0x03000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3     0x04000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4     0x05000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5     0x06000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6     0x07000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7     0x08000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8     0x09000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9     0x0a000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10    0x0b000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11    0x0c000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12    0x0d000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13    0x0e000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14    0x0f000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15    0x10000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16    0x11000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17    0x12000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18    0x13000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19    0x14000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20    0x15000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21    0x16000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22    0x17000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23    0x18000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24    0x19000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25    0x1a000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26    0x1b000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27    0x1c000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28    0x1d000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29    0x1e000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30    0x1f000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31    0x20000000
+
+
+	/*  EPIO of shut down temperature status */
+	uint32_t temperature_monitor2;                           /* 0x4004 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK         0x0000FFFF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT        0
+
+
+	/*  MFW flavor to be used */
+	uint32_t mfw_cfg;                                        /* 0x4008 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK          0x000000FF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT         0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA            0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A             0x00000001
+
+	/*  Should NIC data query remain enabled upon last drv unload */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK     0x00000100
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT    8
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED  0x00000100
+
+	/*  Hide DCBX feature in CCM/BACS menus */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK      0x00010000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT     16
+	#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED  0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED   0x00010000
+
+	uint32_t smbus_config;                                   /* 0x400C */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK          0x000000FF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT         0
+
+	/*  Switching regulator loop gain */
+	uint32_t board_cfg;                                      /* 0x4010 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK           0x0000000F
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT          0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT     0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2             0x00000008
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4             0x00000009
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8             0x0000000a
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16            0x0000000b
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8           0x0000000c
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4           0x0000000d
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2           0x0000000e
+	#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1             0x0000000f
+
+	/*  whether shadow swim feature is supported */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK         0x00000100
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT        8
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED     0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED      0x00000100
+
+    /*  whether to show/hide SRIOV menu in CCM */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK     0x00000200
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT    9
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU          0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU          0x00000200
+
+	/*  Threshold in celcius for max continuous operation */
+	uint32_t temperature_report;                             /* 0x4014 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK           0x0000007F
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT          0
+
+	/*  Threshold in celcius for sensor caution */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK            0x00007F00
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT           8
+
+	/*  wwn node prefix to be used (unless value is 0) */
+	uint32_t wwn_prefix;                                     /* 0x4018 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK    0x000000FF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT   0
+
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK    0x0000FF00
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT   8
+
+	/*  wwn port prefix to be used (unless value is 0) */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK    0x00FF0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT   16
+
+	/*  wwn port prefix to be used (unless value is 0) */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK    0xFF000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT   24
+
+	/*  General debug nvm cfg */
+	uint32_t dbg_cfg_flags;                                  /* 0x401C */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK                 0x000FFFFF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT                0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE               0x00000001
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER     0x00000002
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7    0x00000004
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT   0x00000008
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT  0x00000010
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE   0x00000020
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT   0x00000040
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK  0x00000080
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS      0x00000100
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE       0x00000200
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ          0x00000400
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE   0x00000800
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET     0x00001000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT  0x00002000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1       0x00004000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE        0x00008000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8     0x00010000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR   0x00020000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI          0x00040000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA      0x00080000
+
+	/*  Debug signet rx threshold */
+	uint32_t dbg_rx_sigdet_threshold;                        /* 0x4020 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK       0x00000007
+	#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT      0
+
+    /*  Enable IFFE feature */
+	uint32_t iffe_features;                                  /* 0x4024 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK         0x00000001
+	#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT        0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED     0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED      0x00000001
+
+	/*  Allowable port enablement (bitmask for ports 3-1) */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK       0x0000000E
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT      1
+
+	/*  Allow iSCSI offload override */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK      0x00000010
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT     4
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED  0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED   0x00000010
+
+	/*  Allow FCoE offload override */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK       0x00000020
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT      5
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED   0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED    0x00000020
+
+	/*  Tie to adaptor */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK         0x00008000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT        15
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED     0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED      0x00008000
+
+	/*  Currently enabled port(s) (bitmask for ports 3-1) */
+	uint32_t current_iffe_mask;                              /* 0x4028 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK         0x0000000E
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT        1
+
+	/*  Current iSCSI offload  */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK       0x00000010
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT      4
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED   0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED    0x00000010
+
+	/*  Current FCoE offload  */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK        0x00000020
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT       5
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED    0x00000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED     0x00000020
+
+	/* FW set this pin to "0" (assert) these signal if either of its MAC
+	 * or PHY specific threshold values is exceeded.
+	 * Values are standard GPIO/EPIO pins.
+	 */
+	uint32_t threshold_pin;                                  /* 0x402C */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK        0x000000FF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT       0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK        0x0000FF00
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT       8
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK       0x00FF0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT      16
+
+	/* MAC die temperature threshold in Celsius. */
+	uint32_t mac_threshold_val;                              /* 0x4030 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK  0x000000FF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK  0x0000FF00
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16
+
+	/*  PHY die temperature threshold in Celsius. */
+	uint32_t phy_threshold_val;                              /* 0x4034 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK  0x000000FF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK  0x0000FF00
+	#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16
+
+	/* External pins to communicate with host.
+	 * Values are standard GPIO/EPIO pins.
+	 */
+	uint32_t host_pin;                                       /* 0x4038 */
+	#define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK         0x000000FF
+	#define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT        0
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK          0x0000FF00
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT         8
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK     0x00FF0000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT    16
+	#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK      0xFF000000
+	#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT     24
+};
+
+
+#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
+	#error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
+#endif
+
+#define FUNC_0              0
+#define FUNC_1              1
+#define FUNC_2              2
+#define FUNC_3              3
+#define FUNC_4              4
+#define FUNC_5              5
+#define FUNC_6              6
+#define FUNC_7              7
+#define E1H_FUNC_MAX            8
+#define E2_FUNC_MAX         4   /* per path */
+
+#define VN_0                0
+#define VN_1                1
+#define VN_2                2
+#define VN_3                3
+#define E1VN_MAX            1
+#define E1HVN_MAX           4
+
+#define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
+/* This value (in milliseconds) determines the frequency of the driver
+ * issuing the PULSE message code.  The firmware monitors this periodic
+ * pulse to determine when to switch to an OS-absent mode. */
+#define DRV_PULSE_PERIOD_MS     250
+
+/* This value (in milliseconds) determines how long the driver should
+ * wait for an acknowledgement from the firmware before timing out.  Once
+ * the firmware has timed out, the driver will assume there is no firmware
+ * running and there won't be any firmware-driver synchronization during a
+ * driver reset. */
+#define FW_ACK_TIME_OUT_MS      5000
+
+#define FW_ACK_POLL_TIME_MS     1
+
+#define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
+
+#define MFW_TRACE_SIGNATURE     0x54524342
+
+/****************************************************************************
+ * Driver <-> FW Mailbox                                                    *
+ ****************************************************************************/
+struct drv_port_mb {
+
+	uint32_t link_status;
+	/* Driver should update this field on any link change event */
+
+	#define LINK_STATUS_NONE				(0<<0)
+	#define LINK_STATUS_LINK_FLAG_MASK			0x00000001
+	#define LINK_STATUS_LINK_UP				0x00000001
+	#define LINK_STATUS_SPEED_AND_DUPLEX_MASK		0x0000001E
+	#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE	(0<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_10THD		(1<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD		(2<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD		(3<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_100T4		(4<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD		(5<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD		(6<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD		(7<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD		(7<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD		(8<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD		(9<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD		(9<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD		(10<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD		(10<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD		(11<<1)
+	#define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD		(11<<1)
+
+	#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK		0x00000020
+	#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020
+
+	#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040
+	#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK	0x00000080
+	#define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080
+
+	#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200
+	#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
+	#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE		0x00000800
+	#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE	0x00001000
+	#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE	0x00002000
+	#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE		0x00004000
+	#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE		0x00008000
+
+	#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK		0x00010000
+	#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00010000
+
+	#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK		0x00020000
+	#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00020000
+
+	#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
+	#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0<<18)
+	#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1<<18)
+	#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2<<18)
+	#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3<<18)
+
+	#define LINK_STATUS_SERDES_LINK				0x00100000
+
+	#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE	0x00200000
+	#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE	0x00400000
+	#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE		0x00800000
+	#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE		0x10000000
+
+	#define LINK_STATUS_PFC_ENABLED				0x20000000
+
+	#define LINK_STATUS_PHYSICAL_LINK_FLAG			0x40000000
+	#define LINK_STATUS_SFP_TX_FAULT			0x80000000
+
+	uint32_t port_stx;
+
+	uint32_t stat_nig_timer;
+
+	/* MCP firmware does not use this field */
+	uint32_t ext_phy_fw_version;
+
+};
+
+
+struct drv_func_mb {
+
+	uint32_t drv_mb_header;
+	#define DRV_MSG_CODE_MASK                       0xffff0000
+	#define DRV_MSG_CODE_LOAD_REQ                   0x10000000
+	#define DRV_MSG_CODE_LOAD_DONE                  0x11000000
+	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
+	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
+	#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
+	#define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
+	#define DRV_MSG_CODE_DCC_OK                     0x30000000
+	#define DRV_MSG_CODE_DCC_FAILURE                0x31000000
+	#define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
+	#define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
+	#define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
+	#define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
+	#define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
+	#define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
+	#define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
+
+	/*
+	 * The optic module verification command requires bootcode
+	 * v5.0.6 or later, te specific optic module verification command
+	 * requires bootcode v5.2.12 or later
+	 */
+	#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
+	#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
+	#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
+	#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
+	#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
+	#define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
+	#define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
+	#define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
+	#define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
+	#define REQ_BC_VER_4_FCOE_FEATURES              0x00070209
+
+	#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
+	#define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
+	#define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
+
+	#define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
+
+	#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
+	#define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
+	#define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
+	#define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
+	#define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
+
+	#define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
+	#define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
+
+	#define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
+
+	#define DRV_MSG_CODE_RMMOD                      0xdb000000
+	#define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f
+
+	#define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
+	#define REQ_BC_VER_4_SET_MF_BW                  0x00060202
+	#define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
+
+	#define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
+
+	#define DRV_MSG_CODE_INITIATE_FLR               0x02000000
+	#define REQ_BC_VER_4_INITIATE_FLR               0x00070213
+
+	#define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
+	#define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
+	#define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
+	#define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
+
+	#define DRV_MSG_CODE_IMG_OFFSET_REQ             0xe2000000
+	#define DRV_MSG_CODE_IMG_SIZE_REQ               0xe3000000
+
+	#define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
+
+	uint32_t drv_mb_param;
+	#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
+	#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
+
+	#define DRV_MSG_CODE_UNLOAD_NON_D3_POWER        0x00000001
+	#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002
+
+	#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
+	#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
+
+	#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ          0x00000001
+
+	uint32_t fw_mb_header;
+	#define FW_MSG_CODE_MASK                        0xffff0000
+	#define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
+	#define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
+	#define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
+	/* Load common chip is supported from bc 6.0.0  */
+	#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
+	#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
+
+	#define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
+	#define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
+	#define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
+	#define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
+	#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
+	#define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
+	#define FW_MSG_CODE_DCC_DONE                    0x30100000
+	#define FW_MSG_CODE_LLDP_DONE                   0x40100000
+	#define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
+	#define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
+	#define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
+	#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
+	#define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
+	#define FW_MSG_CODE_GET_KEY_DONE                0x80100000
+	#define FW_MSG_CODE_NO_KEY                      0x80f00000
+	#define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
+	#define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
+	#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
+	#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
+	#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
+	#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
+	#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
+	#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
+	#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
+	#define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
+	#define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
+
+	#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
+	#define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
+	#define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
+	#define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
+	#define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
+
+	#define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
+	#define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
+
+	#define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
+
+	#define FW_MSG_CODE_RMMOD_ACK                   0xdb100000
+
+	#define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
+	#define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
+
+	#define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
+
+	#define FW_MSG_CODE_FLR_ACK                     0x02000000
+	#define FW_MSG_CODE_FLR_NACK                    0x02100000
+
+	#define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
+	#define FW_MSG_CODE_LIC_RESPONSE                0xff020000
+	#define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
+	#define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
+
+	#define FW_MSG_CODE_IMG_OFFSET_RESPONSE         0xe2100000
+	#define FW_MSG_CODE_IMG_SIZE_RESPONSE           0xe3100000
+
+	#define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
+
+	uint32_t fw_mb_param;
+
+	#define FW_PARAM_INVALID_IMG                    0xffffffff
+
+	uint32_t drv_pulse_mb;
+	#define DRV_PULSE_SEQ_MASK                      0x00007fff
+	#define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
+	/*
+	 * The system time is in the format of
+	 * (year-2001)*12*32 + month*32 + day.
+	 */
+	#define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
+	/*
+	 * Indicate to the firmware not to go into the
+	 * OS-absent when it is not getting driver pulse.
+	 * This is used for debugging as well for PXE(MBA).
+	 */
+
+	uint32_t mcp_pulse_mb;
+	#define MCP_PULSE_SEQ_MASK                      0x00007fff
+	#define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
+	/* Indicates to the driver not to assert due to lack
+	 * of MCP response */
+	#define MCP_EVENT_MASK                          0xffff0000
+	#define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
+
+	uint32_t iscsi_boot_signature;
+	uint32_t iscsi_boot_block_offset;
+
+	uint32_t drv_status;
+	#define DRV_STATUS_PMF                          0x00000001
+	#define DRV_STATUS_VF_DISABLED                  0x00000002
+	#define DRV_STATUS_SET_MF_BW                    0x00000004
+	#define DRV_STATUS_LINK_EVENT                   0x00000008
+
+	#define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
+	#define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
+	#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
+	#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
+	#define DRV_STATUS_DCC_RESERVED1                0x00000800
+	#define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
+	#define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
+
+	#define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
+	#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
+	#define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
+	#define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
+	#define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
+	#define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
+	#define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
+
+	#define DRV_STATUS_DRV_INFO_REQ                 0x04000000
+
+	#define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
+
+	uint32_t virt_mac_upper;
+	#define VIRT_MAC_SIGN_MASK                      0xffff0000
+	#define VIRT_MAC_SIGNATURE                      0x564d0000
+	uint32_t virt_mac_lower;
+
+};
+
+
+/****************************************************************************
+ * Management firmware state                                                *
+ ****************************************************************************/
+/* Allocate 440 bytes for management firmware */
+#define MGMTFW_STATE_WORD_SIZE                          110
+
+struct mgmtfw_state {
+	uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
+};
+
+
+/****************************************************************************
+ * Multi-Function configuration                                             *
+ ****************************************************************************/
+struct shared_mf_cfg {
+
+	uint32_t clp_mb;
+	#define SHARED_MF_CLP_SET_DEFAULT               0x00000000
+	/* set by CLP */
+	#define SHARED_MF_CLP_EXIT                      0x00000001
+	/* set by MCP */
+	#define SHARED_MF_CLP_EXIT_DONE                 0x00010000
+
+};
+
+struct port_mf_cfg {
+
+	uint32_t dynamic_cfg;    /* device control channel */
+	#define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
+	#define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
+	#define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
+
+	uint32_t reserved[1];
+
+};
+
+struct func_mf_cfg {
+
+	uint32_t config;
+	/* E/R/I/D */
+	/* function 0 of each port cannot be hidden */
+	#define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
+
+	#define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
+	#define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
+	#define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
+	#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
+	#define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
+	#define FUNC_MF_CFG_PROTOCOL_DEFAULT \
+				FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
+
+	#define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
+	#define FUNC_MF_CFG_FUNC_DELETED                0x00000010
+
+	#define FUNC_MF_CFG_FUNC_BOOT_MASK              0x00000060
+	#define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL         0x00000000
+	#define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED      0x00000020
+	#define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED       0x00000040
+
+	/* PRI */
+	/* 0 - low priority, 3 - high priority */
+	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
+	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
+	#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
+
+	/* MINBW, MAXBW */
+	/* value range - 0..100, increments in 100Mbps */
+	#define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
+	#define FUNC_MF_CFG_MIN_BW_SHIFT                16
+	#define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
+	#define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
+	#define FUNC_MF_CFG_MAX_BW_SHIFT                24
+	#define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
+
+	uint32_t mac_upper;	    /* MAC */
+	#define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
+	#define FUNC_MF_CFG_UPPERMAC_SHIFT              0
+	#define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
+	uint32_t mac_lower;
+	#define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
+
+	uint32_t e1hov_tag;	/* VNI */
+	#define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
+	#define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
+	#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
+
+	/* afex default VLAN ID - 12 bits */
+	#define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
+	#define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
+
+	uint32_t afex_config;
+	#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
+	#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
+	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
+	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
+	#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
+	#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
+	#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
+
+	uint32_t pf_allocation;
+	/* number of vfs in function, if 0 - sriov disabled */
+	#define FUNC_MF_CFG_NUMBER_OF_VFS_MASK                      0x000000FF
+	#define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT                     0
+};
+
+enum mf_cfg_afex_vlan_mode {
+	FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
+	FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
+	FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
+};
+
+/* This structure is not applicable and should not be accessed on 57711 */
+struct func_ext_cfg {
+	uint32_t func_cfg;
+	#define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
+	#define MACP_FUNC_CFG_FLAGS_SHIFT               0
+	#define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
+	#define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
+	#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
+	#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
+    #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
+
+	uint32_t iscsi_mac_addr_upper;
+	uint32_t iscsi_mac_addr_lower;
+
+	uint32_t fcoe_mac_addr_upper;
+	uint32_t fcoe_mac_addr_lower;
+
+	uint32_t fcoe_wwn_port_name_upper;
+	uint32_t fcoe_wwn_port_name_lower;
+
+	uint32_t fcoe_wwn_node_name_upper;
+	uint32_t fcoe_wwn_node_name_lower;
+
+	uint32_t preserve_data;
+	#define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
+	#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
+	#define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
+	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
+	#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
+	#define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
+};
+
+struct mf_cfg {
+
+	struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
+	struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
+    /* 0x10*2=0x20 */
+	/* for all chips, there are 8 mf functions */
+	struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
+	/*
+	 * Extended configuration per function  - this array does not exist and
+	 * should not be accessed on 57711
+	 */
+	struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
+}; /* 0x224 */
+
+/****************************************************************************
+ * Shared Memory Region                                                     *
+ ****************************************************************************/
+struct shmem_region {		       /*   SharedMem Offset (size) */
+
+	uint32_t         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
+	#define SHR_MEM_FORMAT_REV_MASK                     0xff000000
+	#define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
+	/* validity bits */
+	#define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
+	#define SHR_MEM_VALIDITY_MB                         0x00200000
+	#define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
+	#define SHR_MEM_VALIDITY_RESERVED                   0x00000007
+	/* One licensing bit should be set */
+	#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
+	#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
+	#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
+	#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
+	/* Active MFW */
+	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
+	#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
+	#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
+	#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
+	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
+	#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
+
+	struct shm_dev_info dev_info;	     /* 0x8     (0x438) */
+
+	license_key_t       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
+
+	/* FW information (for internal FW use) */
+	uint32_t         fw_info_fio_offset;		/* 0x4a8       (0x4) */
+	struct mgmtfw_state mgmtfw_state;	/* 0x4ac     (0x1b8) */
+
+	struct drv_port_mb  port_mb[PORT_MAX];	/* 0x664 (16*2=0x20) */
+
+
+#ifdef BMAPI
+	/* This is a variable length array */
+	/* the number of function depends on the chip type */
+	struct drv_func_mb func_mb[1];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
+#else
+	/* the number of function depends on the chip type */
+	struct drv_func_mb  func_mb[];	/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
+#endif /* BMAPI */
+
+}; /* 57711 = 0x7E4 | 57712 = 0x734 */
+
+/****************************************************************************
+ * Shared Memory 2 Region                                                   *
+ ****************************************************************************/
+/* The fw_flr_ack is actually built in the following way:                   */
+/* 8 bit:  PF ack                                                           */
+/* 64 bit: VF ack                                                           */
+/* 8 bit:  ios_dis_ack                                                      */
+/* In order to maintain endianity in the mailbox hsi, we want to keep using */
+/* uint32_t. The fw must have the VF right after the PF since this is how it     */
+/* access arrays(it expects always the VF to reside after the PF, and that  */
+/* makes the calculation much easier for it. )                              */
+/* In order to answer both limitations, and keep the struct small, the code */
+/* will abuse the structure defined here to achieve the actual partition    */
+/* above                                                                    */
+/****************************************************************************/
+struct fw_flr_ack {
+	uint32_t         pf_ack;
+	uint32_t         vf_ack[1];
+	uint32_t         iov_dis_ack;
+};
+
+struct fw_flr_mb {
+	uint32_t         aggint;
+	uint32_t         opgen_addr;
+	struct fw_flr_ack ack;
+};
+
+struct eee_remote_vals {
+	uint32_t         tx_tw;
+	uint32_t         rx_tw;
+};
+
+/**** SUPPORT FOR SHMEM ARRRAYS ***
+ * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
+ * define arrays with storage types smaller then unsigned dwords.
+ * The macros below add generic support for SHMEM arrays with numeric elements
+ * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
+ * array with individual bit-filed elements accessed using shifts and masks.
+ *
+ */
+
+/* eb is the bitwidth of a single element */
+#define SHMEM_ARRAY_MASK(eb)		((1<<(eb))-1)
+#define SHMEM_ARRAY_ENTRY(i, eb)	((i)/(32/(eb)))
+
+/* the bit-position macro allows the used to flip the order of the arrays
+ * elements on a per byte or word boundary.
+ *
+ * example: an array with 8 entries each 4 bit wide. This array will fit into
+ * a single dword. The diagrmas below show the array order of the nibbles.
+ *
+ * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
+ *
+ *                |                |                |               |
+ *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
+ *                |                |                |               |
+ *
+ * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
+ *
+ *                |                |                |               |
+ *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
+ *                |                |                |               |
+ *
+ * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
+ *
+ *                |                |                |               |
+ *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
+ *                |                |                |               |
+ */
+#define SHMEM_ARRAY_BITPOS(i, eb, fb)	\
+	((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
+	(((i)%((fb)/(eb))) * (eb)))
+
+#define SHMEM_ARRAY_GET(a, i, eb, fb)					\
+	((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
+	SHMEM_ARRAY_MASK(eb))
+
+#define SHMEM_ARRAY_SET(a, i, eb, fb, val)				\
+do {									   \
+	a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<	   \
+	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
+	a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
+	SHMEM_ARRAY_BITPOS(i, eb, fb));					   \
+} while (0)
+
+
+/****START OF DCBX STRUCTURES DECLARATIONS****/
+#define DCBX_MAX_NUM_PRI_PG_ENTRIES	8
+#define DCBX_PRI_PG_BITWIDTH		4
+#define DCBX_PRI_PG_FBITS		8
+#define DCBX_PRI_PG_GET(a, i)		\
+	SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
+#define DCBX_PRI_PG_SET(a, i, val)	\
+	SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
+#define DCBX_MAX_NUM_PG_BW_ENTRIES	8
+#define DCBX_BW_PG_BITWIDTH		8
+#define DCBX_PG_BW_GET(a, i)		\
+	SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
+#define DCBX_PG_BW_SET(a, i, val)	\
+	SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
+#define DCBX_STRICT_PRI_PG		15
+#define DCBX_MAX_APP_PROTOCOL		16
+#define DCBX_MAX_APP_LOCAL	    32
+#define FCOE_APP_IDX			0
+#define ISCSI_APP_IDX			1
+#define PREDEFINED_APP_IDX_MAX		2
+
+
+/* Big/Little endian have the same representation. */
+struct dcbx_ets_feature {
+	/*
+	 * For Admin MIB - is this feature supported by the
+	 * driver | For Local MIB - should this feature be enabled.
+	 */
+	uint32_t enabled;
+	uint32_t  pg_bw_tbl[2];
+	uint32_t  pri_pg_tbl[1];
+};
+
+/* Driver structure in LE */
+struct dcbx_pfc_feature {
+#ifdef __BIG_ENDIAN
+	uint8_t pri_en_bitmap;
+	#define DCBX_PFC_PRI_0 0x01
+	#define DCBX_PFC_PRI_1 0x02
+	#define DCBX_PFC_PRI_2 0x04
+	#define DCBX_PFC_PRI_3 0x08
+	#define DCBX_PFC_PRI_4 0x10
+	#define DCBX_PFC_PRI_5 0x20
+	#define DCBX_PFC_PRI_6 0x40
+	#define DCBX_PFC_PRI_7 0x80
+	uint8_t pfc_caps;
+	uint8_t reserved;
+	uint8_t enabled;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t enabled;
+	uint8_t reserved;
+	uint8_t pfc_caps;
+	uint8_t pri_en_bitmap;
+	#define DCBX_PFC_PRI_0 0x01
+	#define DCBX_PFC_PRI_1 0x02
+	#define DCBX_PFC_PRI_2 0x04
+	#define DCBX_PFC_PRI_3 0x08
+	#define DCBX_PFC_PRI_4 0x10
+	#define DCBX_PFC_PRI_5 0x20
+	#define DCBX_PFC_PRI_6 0x40
+	#define DCBX_PFC_PRI_7 0x80
+#endif
+};
+
+struct dcbx_app_priority_entry {
+#ifdef __BIG_ENDIAN
+	uint16_t  app_id;
+	uint8_t  pri_bitmap;
+	uint8_t  appBitfield;
+	#define DCBX_APP_ENTRY_VALID         0x01
+	#define DCBX_APP_ENTRY_SF_MASK       0x30
+	#define DCBX_APP_ENTRY_SF_SHIFT      4
+	#define DCBX_APP_SF_ETH_TYPE         0x10
+	#define DCBX_APP_SF_PORT             0x20
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t appBitfield;
+	#define DCBX_APP_ENTRY_VALID         0x01
+	#define DCBX_APP_ENTRY_SF_MASK       0x30
+	#define DCBX_APP_ENTRY_SF_SHIFT      4
+	#define DCBX_APP_SF_ETH_TYPE         0x10
+	#define DCBX_APP_SF_PORT             0x20
+	uint8_t  pri_bitmap;
+	uint16_t  app_id;
+#endif
+};
+
+
+/* FW structure in BE */
+struct dcbx_app_priority_feature {
+#ifdef __BIG_ENDIAN
+	uint8_t reserved;
+	uint8_t default_pri;
+	uint8_t tc_supported;
+	uint8_t enabled;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t enabled;
+	uint8_t tc_supported;
+	uint8_t default_pri;
+	uint8_t reserved;
+#endif
+	struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
+};
+
+/* FW structure in BE */
+struct dcbx_features {
+	/* PG feature */
+	struct dcbx_ets_feature ets;
+	/* PFC feature */
+	struct dcbx_pfc_feature pfc;
+	/* APP feature */
+	struct dcbx_app_priority_feature app;
+};
+
+/* LLDP protocol parameters */
+/* FW structure in BE */
+struct lldp_params {
+#ifdef __BIG_ENDIAN
+	uint8_t  msg_fast_tx_interval;
+	uint8_t  msg_tx_hold;
+	uint8_t  msg_tx_interval;
+	uint8_t  admin_status;
+	#define LLDP_TX_ONLY  0x01
+	#define LLDP_RX_ONLY  0x02
+	#define LLDP_TX_RX    0x03
+	#define LLDP_DISABLED 0x04
+	uint8_t  reserved1;
+	uint8_t  tx_fast;
+	uint8_t  tx_crd_max;
+	uint8_t  tx_crd;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t  admin_status;
+	#define LLDP_TX_ONLY  0x01
+	#define LLDP_RX_ONLY  0x02
+	#define LLDP_TX_RX    0x03
+	#define LLDP_DISABLED 0x04
+	uint8_t  msg_tx_interval;
+	uint8_t  msg_tx_hold;
+	uint8_t  msg_fast_tx_interval;
+	uint8_t  tx_crd;
+	uint8_t  tx_crd_max;
+	uint8_t  tx_fast;
+	uint8_t  reserved1;
+#endif
+	#define REM_CHASSIS_ID_STAT_LEN 4
+	#define REM_PORT_ID_STAT_LEN 4
+	/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
+	uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
+	/* Holds remote Port ID TLV header, subtype and 9B of payload. */
+	uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
+};
+
+struct lldp_dcbx_stat {
+	#define LOCAL_CHASSIS_ID_STAT_LEN 2
+	#define LOCAL_PORT_ID_STAT_LEN 2
+	/* Holds local Chassis ID 8B payload of constant subtype 4. */
+	uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
+	/* Holds local Port ID 8B payload of constant subtype 3. */
+	uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
+	/* Number of DCBX frames transmitted. */
+	uint32_t num_tx_dcbx_pkts;
+	/* Number of DCBX frames received. */
+	uint32_t num_rx_dcbx_pkts;
+};
+
+/* ADMIN MIB - DCBX local machine default configuration. */
+struct lldp_admin_mib {
+	uint32_t     ver_cfg_flags;
+	#define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
+	#define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
+	#define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
+	#define DCBX_ETS_RECO_TX_ENABLED         0x00000008
+	#define DCBX_ETS_RECO_VALID              0x00000010
+	#define DCBX_ETS_WILLING                 0x00000020
+	#define DCBX_PFC_WILLING                 0x00000040
+	#define DCBX_APP_WILLING                 0x00000080
+	#define DCBX_VERSION_CEE                 0x00000100
+	#define DCBX_VERSION_IEEE                0x00000200
+	#define DCBX_DCBX_ENABLED                0x00000400
+	#define DCBX_CEE_VERSION_MASK            0x0000f000
+	#define DCBX_CEE_VERSION_SHIFT           12
+	#define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
+	#define DCBX_CEE_MAX_VERSION_SHIFT       16
+	struct dcbx_features     features;
+};
+
+/* REMOTE MIB - remote machine DCBX configuration. */
+struct lldp_remote_mib {
+	uint32_t prefix_seq_num;
+	uint32_t flags;
+	#define DCBX_ETS_TLV_RX                  0x00000001
+	#define DCBX_PFC_TLV_RX                  0x00000002
+	#define DCBX_APP_TLV_RX                  0x00000004
+	#define DCBX_ETS_RX_ERROR                0x00000010
+	#define DCBX_PFC_RX_ERROR                0x00000020
+	#define DCBX_APP_RX_ERROR                0x00000040
+	#define DCBX_ETS_REM_WILLING             0x00000100
+	#define DCBX_PFC_REM_WILLING             0x00000200
+	#define DCBX_APP_REM_WILLING             0x00000400
+	#define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
+	#define DCBX_REMOTE_MIB_VALID            0x00002000
+	struct dcbx_features features;
+	uint32_t suffix_seq_num;
+};
+
+/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
+struct lldp_local_mib {
+	uint32_t prefix_seq_num;
+	/* Indicates if there is mismatch with negotiation results. */
+	uint32_t error;
+	#define DCBX_LOCAL_ETS_ERROR             0x00000001
+	#define DCBX_LOCAL_PFC_ERROR             0x00000002
+	#define DCBX_LOCAL_APP_ERROR             0x00000004
+	#define DCBX_LOCAL_PFC_MISMATCH          0x00000010
+	#define DCBX_LOCAL_APP_MISMATCH          0x00000020
+	#define DCBX_REMOTE_MIB_ERROR            0x00000040
+	#define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
+	#define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
+	#define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
+	struct dcbx_features   features;
+	uint32_t suffix_seq_num;
+};
+
+struct lldp_local_mib_ext {
+	uint32_t prefix_seq_num;
+	/* APP TLV extension - 16 more entries for negotiation results*/
+	struct dcbx_app_priority_entry  app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];
+	uint32_t suffix_seq_num;
+};
+/***END OF DCBX STRUCTURES DECLARATIONS***/
+
+/***********************************************************/
+/*                         Elink section                   */
+/***********************************************************/
+#define SHMEM_LINK_CONFIG_SIZE 2
+struct shmem_lfa {
+	uint32_t req_duplex;
+	#define REQ_DUPLEX_PHY0_MASK        0x0000ffff
+	#define REQ_DUPLEX_PHY0_SHIFT       0
+	#define REQ_DUPLEX_PHY1_MASK        0xffff0000
+	#define REQ_DUPLEX_PHY1_SHIFT       16
+	uint32_t req_flow_ctrl;
+	#define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
+	#define REQ_FLOW_CTRL_PHY0_SHIFT    0
+	#define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
+	#define REQ_FLOW_CTRL_PHY1_SHIFT    16
+	uint32_t req_line_speed; /* Also determine AutoNeg */
+	#define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
+	#define REQ_LINE_SPD_PHY0_SHIFT     0
+	#define REQ_LINE_SPD_PHY1_MASK      0xffff0000
+	#define REQ_LINE_SPD_PHY1_SHIFT     16
+	uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
+	uint32_t additional_config;
+	#define REQ_FC_AUTO_ADV_MASK        0x0000ffff
+	#define REQ_FC_AUTO_ADV0_SHIFT      0
+	#define NO_LFA_DUE_TO_DCC_MASK      0x00010000
+	uint32_t lfa_sts;
+	#define LFA_LINK_FLAP_REASON_OFFSET		0
+	#define LFA_LINK_FLAP_REASON_MASK		0x000000ff
+		#define LFA_LINK_DOWN			    0x1
+		#define LFA_LOOPBACK_ENABLED		0x2
+		#define LFA_DUPLEX_MISMATCH		    0x3
+		#define LFA_MFW_IS_TOO_OLD		    0x4
+		#define LFA_LINK_SPEED_MISMATCH		0x5
+		#define LFA_FLOW_CTRL_MISMATCH		0x6
+		#define LFA_SPEED_CAP_MISMATCH		0x7
+		#define LFA_DCC_LFA_DISABLED		0x8
+		#define LFA_EEE_MISMATCH		0x9
+
+	#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET	8
+	#define LINK_FLAP_AVOIDANCE_COUNT_MASK		0x0000ff00
+
+	#define LINK_FLAP_COUNT_OFFSET			16
+	#define LINK_FLAP_COUNT_MASK			0x00ff0000
+
+	#define LFA_FLAGS_MASK				0xff000000
+	#define SHMEM_LFA_DONT_CLEAR_STAT		(1<<24)
+
+};
+
+struct shmem2_region {
+
+	uint32_t size;					/* 0x0000 */
+
+	uint32_t dcc_support;				/* 0x0004 */
+	#define SHMEM_DCC_SUPPORT_NONE                      0x00000000
+	#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
+	#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
+	#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
+	#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
+	#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
+
+	uint32_t ext_phy_fw_version2[PORT_MAX];		/* 0x0008 */
+	/*
+	 * For backwards compatibility, if the mf_cfg_addr does not exist
+	 * (the size filed is smaller than 0xc) the mf_cfg resides at the
+	 * end of struct shmem_region
+	 */
+	uint32_t mf_cfg_addr;				/* 0x0010 */
+	#define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
+
+	struct fw_flr_mb flr_mb;			/* 0x0014 */
+	uint32_t dcbx_lldp_params_offset;			/* 0x0028 */
+	#define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
+	uint32_t dcbx_neg_res_offset;			/* 0x002c */
+	#define SHMEM_DCBX_NEG_RES_NONE			0x00000000
+	uint32_t dcbx_remote_mib_offset;			/* 0x0030 */
+	#define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
+	/*
+	 * The other shmemX_base_addr holds the other path's shmem address
+	 * required for example in case of common phy init, or for path1 to know
+	 * the address of mcp debug trace which is located in offset from shmem
+	 * of path0
+	 */
+	uint32_t other_shmem_base_addr;			/* 0x0034 */
+	uint32_t other_shmem2_base_addr;			/* 0x0038 */
+	/*
+	 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
+	 * which were disabled/flred
+	 */
+	uint32_t mcp_vf_disabled[E2_VF_MAX / 32];		/* 0x003c */
+
+	/*
+	 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
+	 * VFs
+	 */
+	uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
+
+	uint32_t dcbx_lldp_dcbx_stat_offset;			/* 0x0064 */
+	#define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
+
+	/*
+	 * edebug_driver_if field is used to transfer messages between edebug
+	 * app to the driver through shmem2.
+	 *
+	 * message format:
+	 * bits 0-2 -  function number / instance of driver to perform request
+	 * bits 3-5 -  op code / is_ack?
+	 * bits 6-63 - data
+	 */
+	uint32_t edebug_driver_if[2];			/* 0x0068 */
+	#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
+	#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
+	#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
+
+	uint32_t nvm_retain_bitmap_addr;			/* 0x0070 */
+
+	/* afex support of that driver */
+	uint32_t afex_driver_support;			/* 0x0074 */
+	#define SHMEM_AFEX_VERSION_MASK                  0x100f
+	#define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
+	#define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
+
+	/* driver receives addr in scratchpad to which it should respond */
+	uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
+
+	/*
+	 * generic params from MCP to driver (value depends on the msg sent
+	 * to driver
+	 */
+	uint32_t afex_param1_to_driver[E2_FUNC_MAX];		/* 0x0088 */
+	uint32_t afex_param2_to_driver[E2_FUNC_MAX];		/* 0x0098 */
+
+	uint32_t swim_base_addr;				/* 0x0108 */
+	uint32_t swim_funcs;
+	uint32_t swim_main_cb;
+
+	/*
+	 * bitmap notifying which VIF profiles stored in nvram are enabled by
+	 * switch
+	 */
+	uint32_t afex_profiles_enabled[2];
+
+	/* generic flags controlled by the driver */
+	uint32_t drv_flags;
+	#define DRV_FLAGS_DCB_CONFIGURED		0x0
+	#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED	0x1
+	#define DRV_FLAGS_DCB_MFW_CONFIGURED	0x2
+
+    #define DRV_FLAGS_PORT_MASK	((1 << DRV_FLAGS_DCB_CONFIGURED) | \
+			(1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
+			(1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
+	/* Port offset*/
+	#define DRV_FLAGS_P0_OFFSET		0
+	#define DRV_FLAGS_P1_OFFSET		16
+	#define DRV_FLAGS_GET_PORT_OFFSET(_port)	((0 == _port) ? \
+						DRV_FLAGS_P0_OFFSET : \
+						DRV_FLAGS_P1_OFFSET)
+
+	#define DRV_FLAGS_GET_PORT_MASK(_port)	(DRV_FLAGS_PORT_MASK << \
+	DRV_FLAGS_GET_PORT_OFFSET(_port))
+
+	#define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port)	(1 << ( \
+	(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
+
+	/* pointer to extended dev_info shared data copied from nvm image */
+	uint32_t extended_dev_info_shared_addr;
+	uint32_t ncsi_oem_data_addr;
+
+	uint32_t sensor_data_addr;
+	uint32_t buffer_block_addr;
+	uint32_t sensor_data_req_update_interval;
+	uint32_t temperature_in_half_celsius;
+	uint32_t glob_struct_in_host;
+
+	uint32_t dcbx_neg_res_ext_offset;
+	#define SHMEM_DCBX_NEG_RES_EXT_NONE			0x00000000
+
+	uint32_t drv_capabilities_flag[E2_FUNC_MAX];
+	#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
+	#define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
+	#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
+	#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
+
+	uint32_t extended_dev_info_shared_cfg_size;
+
+	uint32_t dcbx_en[PORT_MAX];
+
+	/* The offset points to the multi threaded meta structure */
+	uint32_t multi_thread_data_offset;
+
+	/* address of DMAable host address holding values from the drivers */
+	uint32_t drv_info_host_addr_lo;
+	uint32_t drv_info_host_addr_hi;
+
+	/* general values written by the MFW (such as current version) */
+	uint32_t drv_info_control;
+	#define DRV_INFO_CONTROL_VER_MASK          0x000000ff
+	#define DRV_INFO_CONTROL_VER_SHIFT         0
+	#define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
+	#define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
+	uint32_t ibft_host_addr; /* initialized by option ROM */
+
+	struct eee_remote_vals eee_remote_vals[PORT_MAX];
+	uint32_t pf_allocation[E2_FUNC_MAX];
+	#define PF_ALLOACTION_MSIX_VECTORS_MASK    0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
+	#define PF_ALLOACTION_MSIX_VECTORS_SHIFT   0
+
+	/* the status of EEE auto-negotiation
+	 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
+	 * bits 19:16 the supported modes for EEE.
+	 * bits 23:20 the speeds advertised for EEE.
+	 * bits 27:24 the speeds the Link partner advertised for EEE.
+	 * The supported/adv. modes in bits 27:19 originate from the
+	 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
+	 * bit 28 when 1'b1 EEE was requested.
+	 * bit 29 when 1'b1 tx lpi was requested.
+	 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
+	 * 30:29 are 2'b11.
+	 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
+	 * value. When 1'b1 those bits contains a value times 16 microseconds.
+	 */
+	uint32_t eee_status[PORT_MAX];
+	#define SHMEM_EEE_TIMER_MASK		   0x0000ffff
+	#define SHMEM_EEE_SUPPORTED_MASK	   0x000f0000
+	#define SHMEM_EEE_SUPPORTED_SHIFT	   16
+	#define SHMEM_EEE_ADV_STATUS_MASK	   0x00f00000
+		#define SHMEM_EEE_100M_ADV	   (1<<0)
+		#define SHMEM_EEE_1G_ADV	   (1<<1)
+		#define SHMEM_EEE_10G_ADV	   (1<<2)
+	#define SHMEM_EEE_ADV_STATUS_SHIFT	   20
+	#define	SHMEM_EEE_LP_ADV_STATUS_MASK	   0x0f000000
+	#define SHMEM_EEE_LP_ADV_STATUS_SHIFT	   24
+	#define SHMEM_EEE_REQUESTED_BIT		   0x10000000
+	#define SHMEM_EEE_LPI_REQUESTED_BIT	   0x20000000
+	#define SHMEM_EEE_ACTIVE_BIT		   0x40000000
+	#define SHMEM_EEE_TIME_OUTPUT_BIT	   0x80000000
+
+	uint32_t sizeof_port_stats;
+
+	/* Link Flap Avoidance */
+	uint32_t lfa_host_addr[PORT_MAX];
+
+    /* External PHY temperature in deg C. */
+	uint32_t extphy_temps_in_celsius;
+	#define EXTPHY1_TEMP_MASK                  0x0000ffff
+	#define EXTPHY1_TEMP_SHIFT                 0
+
+	uint32_t ocdata_info_addr;			/* Offset 0x148 */
+	uint32_t drv_func_info_addr;			/* Offset 0x14C */
+	uint32_t drv_func_info_size;			/* Offset 0x150 */
+	uint32_t link_attr_sync[PORT_MAX];		/* Offset 0x154 */
+	#define LINK_ATTR_SYNC_KR2_ENABLE	(1<<0)
+};
+
+
+struct emac_stats {
+	uint32_t     rx_stat_ifhcinoctets;
+	uint32_t     rx_stat_ifhcinbadoctets;
+	uint32_t     rx_stat_etherstatsfragments;
+	uint32_t     rx_stat_ifhcinucastpkts;
+	uint32_t     rx_stat_ifhcinmulticastpkts;
+	uint32_t     rx_stat_ifhcinbroadcastpkts;
+	uint32_t     rx_stat_dot3statsfcserrors;
+	uint32_t     rx_stat_dot3statsalignmenterrors;
+	uint32_t     rx_stat_dot3statscarriersenseerrors;
+	uint32_t     rx_stat_xonpauseframesreceived;
+	uint32_t     rx_stat_xoffpauseframesreceived;
+	uint32_t     rx_stat_maccontrolframesreceived;
+	uint32_t     rx_stat_xoffstateentered;
+	uint32_t     rx_stat_dot3statsframestoolong;
+	uint32_t     rx_stat_etherstatsjabbers;
+	uint32_t     rx_stat_etherstatsundersizepkts;
+	uint32_t     rx_stat_etherstatspkts64octets;
+	uint32_t     rx_stat_etherstatspkts65octetsto127octets;
+	uint32_t     rx_stat_etherstatspkts128octetsto255octets;
+	uint32_t     rx_stat_etherstatspkts256octetsto511octets;
+	uint32_t     rx_stat_etherstatspkts512octetsto1023octets;
+	uint32_t     rx_stat_etherstatspkts1024octetsto1522octets;
+	uint32_t     rx_stat_etherstatspktsover1522octets;
+
+	uint32_t     rx_stat_falsecarriererrors;
+
+	uint32_t     tx_stat_ifhcoutoctets;
+	uint32_t     tx_stat_ifhcoutbadoctets;
+	uint32_t     tx_stat_etherstatscollisions;
+	uint32_t     tx_stat_outxonsent;
+	uint32_t     tx_stat_outxoffsent;
+	uint32_t     tx_stat_flowcontroldone;
+	uint32_t     tx_stat_dot3statssinglecollisionframes;
+	uint32_t     tx_stat_dot3statsmultiplecollisionframes;
+	uint32_t     tx_stat_dot3statsdeferredtransmissions;
+	uint32_t     tx_stat_dot3statsexcessivecollisions;
+	uint32_t     tx_stat_dot3statslatecollisions;
+	uint32_t     tx_stat_ifhcoutucastpkts;
+	uint32_t     tx_stat_ifhcoutmulticastpkts;
+	uint32_t     tx_stat_ifhcoutbroadcastpkts;
+	uint32_t     tx_stat_etherstatspkts64octets;
+	uint32_t     tx_stat_etherstatspkts65octetsto127octets;
+	uint32_t     tx_stat_etherstatspkts128octetsto255octets;
+	uint32_t     tx_stat_etherstatspkts256octetsto511octets;
+	uint32_t     tx_stat_etherstatspkts512octetsto1023octets;
+	uint32_t     tx_stat_etherstatspkts1024octetsto1522octets;
+	uint32_t     tx_stat_etherstatspktsover1522octets;
+	uint32_t     tx_stat_dot3statsinternalmactransmiterrors;
+};
+
+
+struct bmac1_stats {
+	uint32_t	tx_stat_gtpkt_lo;
+	uint32_t	tx_stat_gtpkt_hi;
+	uint32_t	tx_stat_gtxpf_lo;
+	uint32_t	tx_stat_gtxpf_hi;
+	uint32_t	tx_stat_gtfcs_lo;
+	uint32_t	tx_stat_gtfcs_hi;
+	uint32_t	tx_stat_gtmca_lo;
+	uint32_t	tx_stat_gtmca_hi;
+	uint32_t	tx_stat_gtbca_lo;
+	uint32_t	tx_stat_gtbca_hi;
+	uint32_t	tx_stat_gtfrg_lo;
+	uint32_t	tx_stat_gtfrg_hi;
+	uint32_t	tx_stat_gtovr_lo;
+	uint32_t	tx_stat_gtovr_hi;
+	uint32_t	tx_stat_gt64_lo;
+	uint32_t	tx_stat_gt64_hi;
+	uint32_t	tx_stat_gt127_lo;
+	uint32_t	tx_stat_gt127_hi;
+	uint32_t	tx_stat_gt255_lo;
+	uint32_t	tx_stat_gt255_hi;
+	uint32_t	tx_stat_gt511_lo;
+	uint32_t	tx_stat_gt511_hi;
+	uint32_t	tx_stat_gt1023_lo;
+	uint32_t	tx_stat_gt1023_hi;
+	uint32_t	tx_stat_gt1518_lo;
+	uint32_t	tx_stat_gt1518_hi;
+	uint32_t	tx_stat_gt2047_lo;
+	uint32_t	tx_stat_gt2047_hi;
+	uint32_t	tx_stat_gt4095_lo;
+	uint32_t	tx_stat_gt4095_hi;
+	uint32_t	tx_stat_gt9216_lo;
+	uint32_t	tx_stat_gt9216_hi;
+	uint32_t	tx_stat_gt16383_lo;
+	uint32_t	tx_stat_gt16383_hi;
+	uint32_t	tx_stat_gtmax_lo;
+	uint32_t	tx_stat_gtmax_hi;
+	uint32_t	tx_stat_gtufl_lo;
+	uint32_t	tx_stat_gtufl_hi;
+	uint32_t	tx_stat_gterr_lo;
+	uint32_t	tx_stat_gterr_hi;
+	uint32_t	tx_stat_gtbyt_lo;
+	uint32_t	tx_stat_gtbyt_hi;
+
+	uint32_t	rx_stat_gr64_lo;
+	uint32_t	rx_stat_gr64_hi;
+	uint32_t	rx_stat_gr127_lo;
+	uint32_t	rx_stat_gr127_hi;
+	uint32_t	rx_stat_gr255_lo;
+	uint32_t	rx_stat_gr255_hi;
+	uint32_t	rx_stat_gr511_lo;
+	uint32_t	rx_stat_gr511_hi;
+	uint32_t	rx_stat_gr1023_lo;
+	uint32_t	rx_stat_gr1023_hi;
+	uint32_t	rx_stat_gr1518_lo;
+	uint32_t	rx_stat_gr1518_hi;
+	uint32_t	rx_stat_gr2047_lo;
+	uint32_t	rx_stat_gr2047_hi;
+	uint32_t	rx_stat_gr4095_lo;
+	uint32_t	rx_stat_gr4095_hi;
+	uint32_t	rx_stat_gr9216_lo;
+	uint32_t	rx_stat_gr9216_hi;
+	uint32_t	rx_stat_gr16383_lo;
+	uint32_t	rx_stat_gr16383_hi;
+	uint32_t	rx_stat_grmax_lo;
+	uint32_t	rx_stat_grmax_hi;
+	uint32_t	rx_stat_grpkt_lo;
+	uint32_t	rx_stat_grpkt_hi;
+	uint32_t	rx_stat_grfcs_lo;
+	uint32_t	rx_stat_grfcs_hi;
+	uint32_t	rx_stat_grmca_lo;
+	uint32_t	rx_stat_grmca_hi;
+	uint32_t	rx_stat_grbca_lo;
+	uint32_t	rx_stat_grbca_hi;
+	uint32_t	rx_stat_grxcf_lo;
+	uint32_t	rx_stat_grxcf_hi;
+	uint32_t	rx_stat_grxpf_lo;
+	uint32_t	rx_stat_grxpf_hi;
+	uint32_t	rx_stat_grxuo_lo;
+	uint32_t	rx_stat_grxuo_hi;
+	uint32_t	rx_stat_grjbr_lo;
+	uint32_t	rx_stat_grjbr_hi;
+	uint32_t	rx_stat_grovr_lo;
+	uint32_t	rx_stat_grovr_hi;
+	uint32_t	rx_stat_grflr_lo;
+	uint32_t	rx_stat_grflr_hi;
+	uint32_t	rx_stat_grmeg_lo;
+	uint32_t	rx_stat_grmeg_hi;
+	uint32_t	rx_stat_grmeb_lo;
+	uint32_t	rx_stat_grmeb_hi;
+	uint32_t	rx_stat_grbyt_lo;
+	uint32_t	rx_stat_grbyt_hi;
+	uint32_t	rx_stat_grund_lo;
+	uint32_t	rx_stat_grund_hi;
+	uint32_t	rx_stat_grfrg_lo;
+	uint32_t	rx_stat_grfrg_hi;
+	uint32_t	rx_stat_grerb_lo;
+	uint32_t	rx_stat_grerb_hi;
+	uint32_t	rx_stat_grfre_lo;
+	uint32_t	rx_stat_grfre_hi;
+	uint32_t	rx_stat_gripj_lo;
+	uint32_t	rx_stat_gripj_hi;
+};
+
+struct bmac2_stats {
+	uint32_t	tx_stat_gtpk_lo; /* gtpok */
+	uint32_t	tx_stat_gtpk_hi; /* gtpok */
+	uint32_t	tx_stat_gtxpf_lo; /* gtpf */
+	uint32_t	tx_stat_gtxpf_hi; /* gtpf */
+	uint32_t	tx_stat_gtpp_lo; /* NEW BMAC2 */
+	uint32_t	tx_stat_gtpp_hi; /* NEW BMAC2 */
+	uint32_t	tx_stat_gtfcs_lo;
+	uint32_t	tx_stat_gtfcs_hi;
+	uint32_t	tx_stat_gtuca_lo; /* NEW BMAC2 */
+	uint32_t	tx_stat_gtuca_hi; /* NEW BMAC2 */
+	uint32_t	tx_stat_gtmca_lo;
+	uint32_t	tx_stat_gtmca_hi;
+	uint32_t	tx_stat_gtbca_lo;
+	uint32_t	tx_stat_gtbca_hi;
+	uint32_t	tx_stat_gtovr_lo;
+	uint32_t	tx_stat_gtovr_hi;
+	uint32_t	tx_stat_gtfrg_lo;
+	uint32_t	tx_stat_gtfrg_hi;
+	uint32_t	tx_stat_gtpkt1_lo; /* gtpkt */
+	uint32_t	tx_stat_gtpkt1_hi; /* gtpkt */
+	uint32_t	tx_stat_gt64_lo;
+	uint32_t	tx_stat_gt64_hi;
+	uint32_t	tx_stat_gt127_lo;
+	uint32_t	tx_stat_gt127_hi;
+	uint32_t	tx_stat_gt255_lo;
+	uint32_t	tx_stat_gt255_hi;
+	uint32_t	tx_stat_gt511_lo;
+	uint32_t	tx_stat_gt511_hi;
+	uint32_t	tx_stat_gt1023_lo;
+	uint32_t	tx_stat_gt1023_hi;
+	uint32_t	tx_stat_gt1518_lo;
+	uint32_t	tx_stat_gt1518_hi;
+	uint32_t	tx_stat_gt2047_lo;
+	uint32_t	tx_stat_gt2047_hi;
+	uint32_t	tx_stat_gt4095_lo;
+	uint32_t	tx_stat_gt4095_hi;
+	uint32_t	tx_stat_gt9216_lo;
+	uint32_t	tx_stat_gt9216_hi;
+	uint32_t	tx_stat_gt16383_lo;
+	uint32_t	tx_stat_gt16383_hi;
+	uint32_t	tx_stat_gtmax_lo;
+	uint32_t	tx_stat_gtmax_hi;
+	uint32_t	tx_stat_gtufl_lo;
+	uint32_t	tx_stat_gtufl_hi;
+	uint32_t	tx_stat_gterr_lo;
+	uint32_t	tx_stat_gterr_hi;
+	uint32_t	tx_stat_gtbyt_lo;
+	uint32_t	tx_stat_gtbyt_hi;
+
+	uint32_t	rx_stat_gr64_lo;
+	uint32_t	rx_stat_gr64_hi;
+	uint32_t	rx_stat_gr127_lo;
+	uint32_t	rx_stat_gr127_hi;
+	uint32_t	rx_stat_gr255_lo;
+	uint32_t	rx_stat_gr255_hi;
+	uint32_t	rx_stat_gr511_lo;
+	uint32_t	rx_stat_gr511_hi;
+	uint32_t	rx_stat_gr1023_lo;
+	uint32_t	rx_stat_gr1023_hi;
+	uint32_t	rx_stat_gr1518_lo;
+	uint32_t	rx_stat_gr1518_hi;
+	uint32_t	rx_stat_gr2047_lo;
+	uint32_t	rx_stat_gr2047_hi;
+	uint32_t	rx_stat_gr4095_lo;
+	uint32_t	rx_stat_gr4095_hi;
+	uint32_t	rx_stat_gr9216_lo;
+	uint32_t	rx_stat_gr9216_hi;
+	uint32_t	rx_stat_gr16383_lo;
+	uint32_t	rx_stat_gr16383_hi;
+	uint32_t	rx_stat_grmax_lo;
+	uint32_t	rx_stat_grmax_hi;
+	uint32_t	rx_stat_grpkt_lo;
+	uint32_t	rx_stat_grpkt_hi;
+	uint32_t	rx_stat_grfcs_lo;
+	uint32_t	rx_stat_grfcs_hi;
+	uint32_t	rx_stat_gruca_lo;
+	uint32_t	rx_stat_gruca_hi;
+	uint32_t	rx_stat_grmca_lo;
+	uint32_t	rx_stat_grmca_hi;
+	uint32_t	rx_stat_grbca_lo;
+	uint32_t	rx_stat_grbca_hi;
+	uint32_t	rx_stat_grxpf_lo; /* grpf */
+	uint32_t	rx_stat_grxpf_hi; /* grpf */
+	uint32_t	rx_stat_grpp_lo;
+	uint32_t	rx_stat_grpp_hi;
+	uint32_t	rx_stat_grxuo_lo; /* gruo */
+	uint32_t	rx_stat_grxuo_hi; /* gruo */
+	uint32_t	rx_stat_grjbr_lo;
+	uint32_t	rx_stat_grjbr_hi;
+	uint32_t	rx_stat_grovr_lo;
+	uint32_t	rx_stat_grovr_hi;
+	uint32_t	rx_stat_grxcf_lo; /* grcf */
+	uint32_t	rx_stat_grxcf_hi; /* grcf */
+	uint32_t	rx_stat_grflr_lo;
+	uint32_t	rx_stat_grflr_hi;
+	uint32_t	rx_stat_grpok_lo;
+	uint32_t	rx_stat_grpok_hi;
+	uint32_t	rx_stat_grmeg_lo;
+	uint32_t	rx_stat_grmeg_hi;
+	uint32_t	rx_stat_grmeb_lo;
+	uint32_t	rx_stat_grmeb_hi;
+	uint32_t	rx_stat_grbyt_lo;
+	uint32_t	rx_stat_grbyt_hi;
+	uint32_t	rx_stat_grund_lo;
+	uint32_t	rx_stat_grund_hi;
+	uint32_t	rx_stat_grfrg_lo;
+	uint32_t	rx_stat_grfrg_hi;
+	uint32_t	rx_stat_grerb_lo; /* grerrbyt */
+	uint32_t	rx_stat_grerb_hi; /* grerrbyt */
+	uint32_t	rx_stat_grfre_lo; /* grfrerr */
+	uint32_t	rx_stat_grfre_hi; /* grfrerr */
+	uint32_t	rx_stat_gripj_lo;
+	uint32_t	rx_stat_gripj_hi;
+};
+
+struct mstat_stats {
+	struct {
+		/* OTE MSTAT on E3 has a bug where this register's contents are
+		 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
+		 */
+		uint32_t tx_gtxpok_lo;
+		uint32_t tx_gtxpok_hi;
+		uint32_t tx_gtxpf_lo;
+		uint32_t tx_gtxpf_hi;
+		uint32_t tx_gtxpp_lo;
+		uint32_t tx_gtxpp_hi;
+		uint32_t tx_gtfcs_lo;
+		uint32_t tx_gtfcs_hi;
+		uint32_t tx_gtuca_lo;
+		uint32_t tx_gtuca_hi;
+		uint32_t tx_gtmca_lo;
+		uint32_t tx_gtmca_hi;
+		uint32_t tx_gtgca_lo;
+		uint32_t tx_gtgca_hi;
+		uint32_t tx_gtpkt_lo;
+		uint32_t tx_gtpkt_hi;
+		uint32_t tx_gt64_lo;
+		uint32_t tx_gt64_hi;
+		uint32_t tx_gt127_lo;
+		uint32_t tx_gt127_hi;
+		uint32_t tx_gt255_lo;
+		uint32_t tx_gt255_hi;
+		uint32_t tx_gt511_lo;
+		uint32_t tx_gt511_hi;
+		uint32_t tx_gt1023_lo;
+		uint32_t tx_gt1023_hi;
+		uint32_t tx_gt1518_lo;
+		uint32_t tx_gt1518_hi;
+		uint32_t tx_gt2047_lo;
+		uint32_t tx_gt2047_hi;
+		uint32_t tx_gt4095_lo;
+		uint32_t tx_gt4095_hi;
+		uint32_t tx_gt9216_lo;
+		uint32_t tx_gt9216_hi;
+		uint32_t tx_gt16383_lo;
+		uint32_t tx_gt16383_hi;
+		uint32_t tx_gtufl_lo;
+		uint32_t tx_gtufl_hi;
+		uint32_t tx_gterr_lo;
+		uint32_t tx_gterr_hi;
+		uint32_t tx_gtbyt_lo;
+		uint32_t tx_gtbyt_hi;
+		uint32_t tx_collisions_lo;
+		uint32_t tx_collisions_hi;
+		uint32_t tx_singlecollision_lo;
+		uint32_t tx_singlecollision_hi;
+		uint32_t tx_multiplecollisions_lo;
+		uint32_t tx_multiplecollisions_hi;
+		uint32_t tx_deferred_lo;
+		uint32_t tx_deferred_hi;
+		uint32_t tx_excessivecollisions_lo;
+		uint32_t tx_excessivecollisions_hi;
+		uint32_t tx_latecollisions_lo;
+		uint32_t tx_latecollisions_hi;
+	} stats_tx;
+
+	struct {
+		uint32_t rx_gr64_lo;
+		uint32_t rx_gr64_hi;
+		uint32_t rx_gr127_lo;
+		uint32_t rx_gr127_hi;
+		uint32_t rx_gr255_lo;
+		uint32_t rx_gr255_hi;
+		uint32_t rx_gr511_lo;
+		uint32_t rx_gr511_hi;
+		uint32_t rx_gr1023_lo;
+		uint32_t rx_gr1023_hi;
+		uint32_t rx_gr1518_lo;
+		uint32_t rx_gr1518_hi;
+		uint32_t rx_gr2047_lo;
+		uint32_t rx_gr2047_hi;
+		uint32_t rx_gr4095_lo;
+		uint32_t rx_gr4095_hi;
+		uint32_t rx_gr9216_lo;
+		uint32_t rx_gr9216_hi;
+		uint32_t rx_gr16383_lo;
+		uint32_t rx_gr16383_hi;
+		uint32_t rx_grpkt_lo;
+		uint32_t rx_grpkt_hi;
+		uint32_t rx_grfcs_lo;
+		uint32_t rx_grfcs_hi;
+		uint32_t rx_gruca_lo;
+		uint32_t rx_gruca_hi;
+		uint32_t rx_grmca_lo;
+		uint32_t rx_grmca_hi;
+		uint32_t rx_grbca_lo;
+		uint32_t rx_grbca_hi;
+		uint32_t rx_grxpf_lo;
+		uint32_t rx_grxpf_hi;
+		uint32_t rx_grxpp_lo;
+		uint32_t rx_grxpp_hi;
+		uint32_t rx_grxuo_lo;
+		uint32_t rx_grxuo_hi;
+		uint32_t rx_grovr_lo;
+		uint32_t rx_grovr_hi;
+		uint32_t rx_grxcf_lo;
+		uint32_t rx_grxcf_hi;
+		uint32_t rx_grflr_lo;
+		uint32_t rx_grflr_hi;
+		uint32_t rx_grpok_lo;
+		uint32_t rx_grpok_hi;
+		uint32_t rx_grbyt_lo;
+		uint32_t rx_grbyt_hi;
+		uint32_t rx_grund_lo;
+		uint32_t rx_grund_hi;
+		uint32_t rx_grfrg_lo;
+		uint32_t rx_grfrg_hi;
+		uint32_t rx_grerb_lo;
+		uint32_t rx_grerb_hi;
+		uint32_t rx_grfre_lo;
+		uint32_t rx_grfre_hi;
+
+		uint32_t rx_alignmenterrors_lo;
+		uint32_t rx_alignmenterrors_hi;
+		uint32_t rx_falsecarrier_lo;
+		uint32_t rx_falsecarrier_hi;
+		uint32_t rx_llfcmsgcnt_lo;
+		uint32_t rx_llfcmsgcnt_hi;
+	} stats_rx;
+};
+
+union mac_stats {
+	struct emac_stats	emac_stats;
+	struct bmac1_stats	bmac1_stats;
+	struct bmac2_stats	bmac2_stats;
+	struct mstat_stats	mstat_stats;
+};
+
+
+struct mac_stx {
+	/* in_bad_octets */
+	uint32_t     rx_stat_ifhcinbadoctets_hi;
+	uint32_t     rx_stat_ifhcinbadoctets_lo;
+
+	/* out_bad_octets */
+	uint32_t     tx_stat_ifhcoutbadoctets_hi;
+	uint32_t     tx_stat_ifhcoutbadoctets_lo;
+
+	/* crc_receive_errors */
+	uint32_t     rx_stat_dot3statsfcserrors_hi;
+	uint32_t     rx_stat_dot3statsfcserrors_lo;
+	/* alignment_errors */
+	uint32_t     rx_stat_dot3statsalignmenterrors_hi;
+	uint32_t     rx_stat_dot3statsalignmenterrors_lo;
+	/* carrier_sense_errors */
+	uint32_t     rx_stat_dot3statscarriersenseerrors_hi;
+	uint32_t     rx_stat_dot3statscarriersenseerrors_lo;
+	/* false_carrier_detections */
+	uint32_t     rx_stat_falsecarriererrors_hi;
+	uint32_t     rx_stat_falsecarriererrors_lo;
+
+	/* runt_packets_received */
+	uint32_t     rx_stat_etherstatsundersizepkts_hi;
+	uint32_t     rx_stat_etherstatsundersizepkts_lo;
+	/* jabber_packets_received */
+	uint32_t     rx_stat_dot3statsframestoolong_hi;
+	uint32_t     rx_stat_dot3statsframestoolong_lo;
+
+	/* error_runt_packets_received */
+	uint32_t     rx_stat_etherstatsfragments_hi;
+	uint32_t     rx_stat_etherstatsfragments_lo;
+	/* error_jabber_packets_received */
+	uint32_t     rx_stat_etherstatsjabbers_hi;
+	uint32_t     rx_stat_etherstatsjabbers_lo;
+
+	/* control_frames_received */
+	uint32_t     rx_stat_maccontrolframesreceived_hi;
+	uint32_t     rx_stat_maccontrolframesreceived_lo;
+	uint32_t     rx_stat_mac_xpf_hi;
+	uint32_t     rx_stat_mac_xpf_lo;
+	uint32_t     rx_stat_mac_xcf_hi;
+	uint32_t     rx_stat_mac_xcf_lo;
+
+	/* xoff_state_entered */
+	uint32_t     rx_stat_xoffstateentered_hi;
+	uint32_t     rx_stat_xoffstateentered_lo;
+	/* pause_xon_frames_received */
+	uint32_t     rx_stat_xonpauseframesreceived_hi;
+	uint32_t     rx_stat_xonpauseframesreceived_lo;
+	/* pause_xoff_frames_received */
+	uint32_t     rx_stat_xoffpauseframesreceived_hi;
+	uint32_t     rx_stat_xoffpauseframesreceived_lo;
+	/* pause_xon_frames_transmitted */
+	uint32_t     tx_stat_outxonsent_hi;
+	uint32_t     tx_stat_outxonsent_lo;
+	/* pause_xoff_frames_transmitted */
+	uint32_t     tx_stat_outxoffsent_hi;
+	uint32_t     tx_stat_outxoffsent_lo;
+	/* flow_control_done */
+	uint32_t     tx_stat_flowcontroldone_hi;
+	uint32_t     tx_stat_flowcontroldone_lo;
+
+	/* ether_stats_collisions */
+	uint32_t     tx_stat_etherstatscollisions_hi;
+	uint32_t     tx_stat_etherstatscollisions_lo;
+	/* single_collision_transmit_frames */
+	uint32_t     tx_stat_dot3statssinglecollisionframes_hi;
+	uint32_t     tx_stat_dot3statssinglecollisionframes_lo;
+	/* multiple_collision_transmit_frames */
+	uint32_t     tx_stat_dot3statsmultiplecollisionframes_hi;
+	uint32_t     tx_stat_dot3statsmultiplecollisionframes_lo;
+	/* deferred_transmissions */
+	uint32_t     tx_stat_dot3statsdeferredtransmissions_hi;
+	uint32_t     tx_stat_dot3statsdeferredtransmissions_lo;
+	/* excessive_collision_frames */
+	uint32_t     tx_stat_dot3statsexcessivecollisions_hi;
+	uint32_t     tx_stat_dot3statsexcessivecollisions_lo;
+	/* late_collision_frames */
+	uint32_t     tx_stat_dot3statslatecollisions_hi;
+	uint32_t     tx_stat_dot3statslatecollisions_lo;
+
+	/* frames_transmitted_64_bytes */
+	uint32_t     tx_stat_etherstatspkts64octets_hi;
+	uint32_t     tx_stat_etherstatspkts64octets_lo;
+	/* frames_transmitted_65_127_bytes */
+	uint32_t     tx_stat_etherstatspkts65octetsto127octets_hi;
+	uint32_t     tx_stat_etherstatspkts65octetsto127octets_lo;
+	/* frames_transmitted_128_255_bytes */
+	uint32_t     tx_stat_etherstatspkts128octetsto255octets_hi;
+	uint32_t     tx_stat_etherstatspkts128octetsto255octets_lo;
+	/* frames_transmitted_256_511_bytes */
+	uint32_t     tx_stat_etherstatspkts256octetsto511octets_hi;
+	uint32_t     tx_stat_etherstatspkts256octetsto511octets_lo;
+	/* frames_transmitted_512_1023_bytes */
+	uint32_t     tx_stat_etherstatspkts512octetsto1023octets_hi;
+	uint32_t     tx_stat_etherstatspkts512octetsto1023octets_lo;
+	/* frames_transmitted_1024_1522_bytes */
+	uint32_t     tx_stat_etherstatspkts1024octetsto1522octets_hi;
+	uint32_t     tx_stat_etherstatspkts1024octetsto1522octets_lo;
+	/* frames_transmitted_1523_9022_bytes */
+	uint32_t     tx_stat_etherstatspktsover1522octets_hi;
+	uint32_t     tx_stat_etherstatspktsover1522octets_lo;
+	uint32_t     tx_stat_mac_2047_hi;
+	uint32_t     tx_stat_mac_2047_lo;
+	uint32_t     tx_stat_mac_4095_hi;
+	uint32_t     tx_stat_mac_4095_lo;
+	uint32_t     tx_stat_mac_9216_hi;
+	uint32_t     tx_stat_mac_9216_lo;
+	uint32_t     tx_stat_mac_16383_hi;
+	uint32_t     tx_stat_mac_16383_lo;
+
+	/* internal_mac_transmit_errors */
+	uint32_t     tx_stat_dot3statsinternalmactransmiterrors_hi;
+	uint32_t     tx_stat_dot3statsinternalmactransmiterrors_lo;
+
+	/* if_out_discards */
+	uint32_t     tx_stat_mac_ufl_hi;
+	uint32_t     tx_stat_mac_ufl_lo;
+};
+
+
+#define MAC_STX_IDX_MAX                     2
+
+struct host_port_stats {
+	uint32_t            host_port_stats_counter;
+
+	struct mac_stx mac_stx[MAC_STX_IDX_MAX];
+
+	uint32_t            brb_drop_hi;
+	uint32_t            brb_drop_lo;
+
+	uint32_t            not_used; /* obsolete as of MFW 7.2.1 */
+
+	uint32_t            pfc_frames_tx_hi;
+	uint32_t            pfc_frames_tx_lo;
+	uint32_t            pfc_frames_rx_hi;
+	uint32_t            pfc_frames_rx_lo;
+
+	uint32_t            eee_lpi_count_hi;
+	uint32_t            eee_lpi_count_lo;
+};
+
+
+struct host_func_stats {
+	uint32_t     host_func_stats_start;
+
+	uint32_t     total_bytes_received_hi;
+	uint32_t     total_bytes_received_lo;
+
+	uint32_t     total_bytes_transmitted_hi;
+	uint32_t     total_bytes_transmitted_lo;
+
+	uint32_t     total_unicast_packets_received_hi;
+	uint32_t     total_unicast_packets_received_lo;
+
+	uint32_t     total_multicast_packets_received_hi;
+	uint32_t     total_multicast_packets_received_lo;
+
+	uint32_t     total_broadcast_packets_received_hi;
+	uint32_t     total_broadcast_packets_received_lo;
+
+	uint32_t     total_unicast_packets_transmitted_hi;
+	uint32_t     total_unicast_packets_transmitted_lo;
+
+	uint32_t     total_multicast_packets_transmitted_hi;
+	uint32_t     total_multicast_packets_transmitted_lo;
+
+	uint32_t     total_broadcast_packets_transmitted_hi;
+	uint32_t     total_broadcast_packets_transmitted_lo;
+
+	uint32_t     valid_bytes_received_hi;
+	uint32_t     valid_bytes_received_lo;
+
+	uint32_t     host_func_stats_end;
+};
+
+/* VIC definitions */
+#define VICSTATST_UIF_INDEX 2
+
+/*
+ * stats collected for afex.
+ * NOTE: structure is exactly as expected to be received by the switch.
+ *       order must remain exactly as is unless protocol changes !
+ */
+struct afex_stats {
+	uint32_t tx_unicast_frames_hi;
+	uint32_t tx_unicast_frames_lo;
+	uint32_t tx_unicast_bytes_hi;
+	uint32_t tx_unicast_bytes_lo;
+	uint32_t tx_multicast_frames_hi;
+	uint32_t tx_multicast_frames_lo;
+	uint32_t tx_multicast_bytes_hi;
+	uint32_t tx_multicast_bytes_lo;
+	uint32_t tx_broadcast_frames_hi;
+	uint32_t tx_broadcast_frames_lo;
+	uint32_t tx_broadcast_bytes_hi;
+	uint32_t tx_broadcast_bytes_lo;
+	uint32_t tx_frames_discarded_hi;
+	uint32_t tx_frames_discarded_lo;
+	uint32_t tx_frames_dropped_hi;
+	uint32_t tx_frames_dropped_lo;
+
+	uint32_t rx_unicast_frames_hi;
+	uint32_t rx_unicast_frames_lo;
+	uint32_t rx_unicast_bytes_hi;
+	uint32_t rx_unicast_bytes_lo;
+	uint32_t rx_multicast_frames_hi;
+	uint32_t rx_multicast_frames_lo;
+	uint32_t rx_multicast_bytes_hi;
+	uint32_t rx_multicast_bytes_lo;
+	uint32_t rx_broadcast_frames_hi;
+	uint32_t rx_broadcast_frames_lo;
+	uint32_t rx_broadcast_bytes_hi;
+	uint32_t rx_broadcast_bytes_lo;
+	uint32_t rx_frames_discarded_hi;
+	uint32_t rx_frames_discarded_lo;
+	uint32_t rx_frames_dropped_hi;
+	uint32_t rx_frames_dropped_lo;
+};
+
+/* To maintain backward compatibility between FW and drivers, new elements */
+/* should be added to the end of the structure. */
+
+/* Per  Port Statistics    */
+struct port_info {
+	uint32_t size; /* size of this structure (i.e. sizeof(port_info))  */
+	uint32_t enabled;      /* 0 =Disabled, 1= Enabled */
+	uint32_t link_speed;   /* multiplier of 100Mb */
+	uint32_t wol_support;  /* WoL Support (i.e. Non-Zero if WOL supported ) */
+	uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/
+	uint32_t flex10;     /* Flex10 mode enabled. non zero = yes */
+	uint32_t rx_drops;  /* RX Discards. Counters roll over, never reset */
+	uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI.
+				   This is flagged by Consumer as an error. */
+	uint32_t rx_uncast_lo;   /* RX Unicast Packets. Free running counters: */
+	uint32_t rx_uncast_hi;   /* RX Unicast Packets. Free running counters: */
+	uint32_t rx_mcast_lo;    /* RX Multicast Packets  */
+	uint32_t rx_mcast_hi;    /* RX Multicast Packets  */
+	uint32_t rx_bcast_lo;    /* RX Broadcast Packets  */
+	uint32_t rx_bcast_hi;    /* RX Broadcast Packets  */
+	uint32_t tx_uncast_lo;   /* TX Unicast Packets   */
+	uint32_t tx_uncast_hi;   /* TX Unicast Packets   */
+	uint32_t tx_mcast_lo;    /* TX Multicast Packets  */
+	uint32_t tx_mcast_hi;    /* TX Multicast Packets  */
+	uint32_t tx_bcast_lo;    /* TX Broadcast Packets  */
+	uint32_t tx_bcast_hi;    /* TX Broadcast Packets  */
+	uint32_t tx_errors;      /* TX Errors              */
+	uint32_t tx_discards;    /* TX Discards          */
+	uint32_t rx_frames_lo;   /* RX Frames received  */
+	uint32_t rx_frames_hi;   /* RX Frames received  */
+	uint32_t rx_bytes_lo;    /* RX Bytes received    */
+	uint32_t rx_bytes_hi;    /* RX Bytes received    */
+	uint32_t tx_frames_lo;   /* TX Frames sent      */
+	uint32_t tx_frames_hi;   /* TX Frames sent      */
+	uint32_t tx_bytes_lo;    /* TX Bytes sent        */
+	uint32_t tx_bytes_hi;    /* TX Bytes sent        */
+	uint32_t link_status;  /* Port P Link Status. 1:0 bit for port enabled.
+				1:1 bit for link good,
+				2:1 Set if link changed between last poll. */
+	uint32_t tx_pfc_frames_lo;   /* PFC Frames sent.    */
+	uint32_t tx_pfc_frames_hi;   /* PFC Frames sent.    */
+	uint32_t rx_pfc_frames_lo;   /* PFC Frames Received. */
+	uint32_t rx_pfc_frames_hi;   /* PFC Frames Received. */
+};
+
+
+#define BCM_5710_FW_MAJOR_VERSION			7
+#define BCM_5710_FW_MINOR_VERSION			2
+#define BCM_5710_FW_REVISION_VERSION		51
+#define BCM_5710_FW_ENGINEERING_VERSION		0
+#define BCM_5710_FW_COMPILE_FLAGS			1
+
+
+/*
+ * attention bits $$KEEP_ENDIANNESS$$
+ */
+struct atten_sp_status_block
+{
+	uint32_t attn_bits /* 16 bit of attention signal lines */;
+	uint32_t attn_bits_ack /* 16 bit of attention signal ack */;
+	uint8_t status_block_id /* status block id */;
+	uint8_t reserved0 /* resreved for padding */;
+	uint16_t attn_bits_index /* attention bits running index */;
+	uint32_t reserved1 /* resreved for padding */;
+};
+
+
+/*
+ * The eth aggregative context of Cstorm
+ */
+struct cstorm_eth_ag_context
+{
+	uint32_t __reserved0[10];
+};
+
+
+/*
+ * dmae command structure
+ */
+struct dmae_command
+{
+	uint32_t opcode;
+#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode	Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */
+#define DMAE_COMMAND_SRC_SHIFT 0
+#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode	The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None  */
+#define DMAE_COMMAND_DST_SHIFT 1
+#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode	The destination of the completion: 0-PCIe 1-GRC */
+#define DMAE_COMMAND_C_DST_SHIFT 3
+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode	Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word  */
+#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode	Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word  */
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode	The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
+#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode	swapping mode. */
+#define DMAE_COMMAND_ENDIANITY_SHIFT 9
+#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode	Which network port ID to present to the PCI request interface */
+#define DMAE_COMMAND_PORT_SHIFT 11
+#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode	reset crc result */
+#define DMAE_COMMAND_CRC_RESET_SHIFT 12
+#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode	reset source address in next go */
+#define DMAE_COMMAND_SRC_RESET_SHIFT 13
+#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode	reset dest address in next go */
+#define DMAE_COMMAND_DST_RESET_SHIFT 14
+#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode	vnic number E2 and onwards source vnic */
+#define DMAE_COMMAND_E1HVN_SHIFT 15
+#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode	E2 and onwards dest vnic */
+#define DMAE_COMMAND_DST_VN_SHIFT 17
+#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode	E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */
+#define DMAE_COMMAND_C_FUNC_SHIFT 19
+#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode	E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */
+#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
+#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode	 */
+#define DMAE_COMMAND_RESERVED0_SHIFT 22
+	uint32_t src_addr_lo /* source address low/grc address */;
+	uint32_t src_addr_hi /* source address hi */;
+	uint32_t dst_addr_lo /* dest address low/grc address */;
+	uint32_t dst_addr_hi /* dest address hi */;
+#if defined(__BIG_ENDIAN)
+	uint16_t opcode_iov;
+#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	source VF id */
+#define DMAE_COMMAND_SRC_VFID_SHIFT 0
+#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
+#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	 */
+#define DMAE_COMMAND_RESERVED1_SHIFT 7
+#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	destination VF id */
+#define DMAE_COMMAND_DST_VFID_SHIFT 8
+#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF_SHIFT 14
+#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	 */
+#define DMAE_COMMAND_RESERVED2_SHIFT 15
+	uint16_t len /* copy length */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t len /* copy length */;
+	uint16_t opcode_iov;
+#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	source VF id */
+#define DMAE_COMMAND_SRC_VFID_SHIFT 0
+#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	selects the source function PF-0, VF-1 */
+#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
+#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	 */
+#define DMAE_COMMAND_RESERVED1_SHIFT 7
+#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	destination VF id */
+#define DMAE_COMMAND_DST_VFID_SHIFT 8
+#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	selects the destination function PF-0, VF-1 */
+#define DMAE_COMMAND_DST_VFPF_SHIFT 14
+#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility	 */
+#define DMAE_COMMAND_RESERVED2_SHIFT 15
+#endif
+	uint32_t comp_addr_lo /* completion address low/grc address */;
+	uint32_t comp_addr_hi /* completion address hi */;
+	uint32_t comp_val /* value to write to completion address */;
+	uint32_t crc32 /* crc32 result */;
+	uint32_t crc32_c /* crc32_c result */;
+#if defined(__BIG_ENDIAN)
+	uint16_t crc16_c /* crc16_c result */;
+	uint16_t crc16 /* crc16 result */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t crc16 /* crc16 result */;
+	uint16_t crc16_c /* crc16_c result */;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t reserved3;
+	uint16_t crc_t10 /* crc_t10 result */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t crc_t10 /* crc_t10 result */;
+	uint16_t reserved3;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t xsum8 /* checksum8 result */;
+	uint16_t xsum16 /* checksum16 result */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t xsum16 /* checksum16 result */;
+	uint16_t xsum8 /* checksum8 result */;
+#endif
+};
+
+
+/*
+ * common data for all protocols
+ */
+struct doorbell_hdr
+{
+	uint8_t header;
+#define DOORBELL_HDR_RX (0x1<<0) /* BitField header	1 for rx doorbell, 0 for tx doorbell */
+#define DOORBELL_HDR_RX_SHIFT 0
+#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header	0 for normal doorbell, 1 for advertise wnd doorbell */
+#define DOORBELL_HDR_DB_TYPE_SHIFT 1
+#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header	rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */
+#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
+#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header	connection type */
+#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
+};
+
+/*
+ * Ethernet doorbell
+ */
+struct eth_tx_doorbell
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t npackets /* number of data bytes that were added in the doorbell */;
+	uint8_t params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params	number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params	tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params	doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+	struct doorbell_hdr hdr;
+#elif defined(__LITTLE_ENDIAN)
+	struct doorbell_hdr hdr;
+	uint8_t params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params	number of buffer descriptors that were added in the doorbell */
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params	tx fin command flag */
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params	doorbell queue spare flag */
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+	uint16_t npackets /* number of data bytes that were added in the doorbell */;
+#endif
+};
+
+
+/*
+ * 3 lines. status block $$KEEP_ENDIANNESS$$
+ */
+struct hc_status_block_e1x
+{
+	uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;
+	uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
+	uint32_t rsrv[11];
+};
+
+/*
+ * host status block
+ */
+struct host_hc_status_block_e1x
+{
+	struct hc_status_block_e1x sb /* fast path indices */;
+};
+
+
+/*
+ * 3 lines. status block $$KEEP_ENDIANNESS$$
+ */
+struct hc_status_block_e2
+{
+	uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;
+	uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
+	uint32_t reserved[11];
+};
+
+/*
+ * host status block
+ */
+struct host_hc_status_block_e2
+{
+	struct hc_status_block_e2 sb /* fast path indices */;
+};
+
+
+/*
+ * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$
+ */
+struct hc_sp_status_block
+{
+	uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;
+	uint16_t running_index /* Status Block running index */;
+	uint16_t rsrv;
+	uint32_t rsrv1;
+};
+
+/*
+ * host status block
+ */
+struct host_sp_status_block
+{
+	struct atten_sp_status_block atten_status_block /* attention bits section */;
+	struct hc_sp_status_block sp_sb /* slow path indices */;
+};
+
+
+/*
+ * IGU driver acknowledgment register
+ */
+union igu_ack_register
+{
+	struct {
+#if defined(__BIG_ENDIAN)
+		uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags	0-15: non default status blocks, 16: default status block */
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags	0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags	if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags	interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags	 */
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+		uint16_t status_block_index /* status block index acknowledgement */;
+#elif defined(__LITTLE_ENDIAN)
+		uint16_t status_block_index /* status block index acknowledgement */;
+		uint16_t sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags	0-15: non default status blocks, 16: default status block */
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags	0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags	if set, acknowledges status block index */
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags	interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags	 */
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+#endif
+	} sb;
+	uint32_t raw_data;
+};
+
+
+/*
+ * IGU driver acknowledgement register
+ */
+struct igu_backward_compatible
+{
+	uint32_t sb_id_and_flags;
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags	 */
+#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags	 */
+#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags	0-3:storm id, 4: attn status block (valid in default sb only) */
+#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags	if set, acknowledges status block index */
+#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags	interrupt enable/disable/nop: use IGU_INT_xxx constants */
+#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags	 */
+#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
+	uint32_t reserved_2;
+};
+
+
+/*
+ * IGU driver acknowledgement register
+ */
+struct igu_regular
+{
+	uint32_t sb_id_and_flags;
+#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_SB_INDEX_SHIFT 0
+#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_RESERVED0_SHIFT 20
+#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags	21-23 (use enum igu_seg_access) */
+#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
+#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_BUPDATE_SHIFT 24
+#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags	interrupt enable/disable/nop (use enum igu_int_cmd) */
+#define IGU_REGULAR_ENABLE_INT_SHIFT 25
+#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_RESERVED_1_SHIFT 27
+#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
+#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
+#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags	 */
+#define IGU_REGULAR_BCLEANUP_SHIFT 31
+	uint32_t reserved_2;
+};
+
+/*
+ * IGU driver acknowledgement register
+ */
+union igu_consprod_reg
+{
+	struct igu_regular regular;
+	struct igu_backward_compatible backward_compatible;
+};
+
+
+/*
+ * Igu control commands
+ */
+enum igu_ctrl_cmd
+{
+	IGU_CTRL_CMD_TYPE_RD,
+	IGU_CTRL_CMD_TYPE_WR,
+	MAX_IGU_CTRL_CMD};
+
+
+/*
+ * Control register for the IGU command register
+ */
+struct igu_ctrl_reg
+{
+	uint32_t ctrl_data;
+#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data	 */
+#define IGU_CTRL_REG_ADDRESS_SHIFT 0
+#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data	 */
+#define IGU_CTRL_REG_FID_SHIFT 12
+#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data	 */
+#define IGU_CTRL_REG_RESERVED_SHIFT 19
+#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data	 (use enum igu_ctrl_cmd) */
+#define IGU_CTRL_REG_TYPE_SHIFT 20
+#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data	 */
+#define IGU_CTRL_REG_UNUSED_SHIFT 21
+};
+
+
+/*
+ * Igu interrupt command
+ */
+enum igu_int_cmd
+{
+	IGU_INT_ENABLE,
+	IGU_INT_DISABLE,
+	IGU_INT_NOP,
+	IGU_INT_NOP2,
+	MAX_IGU_INT_CMD};
+
+
+/*
+ * Igu segments
+ */
+enum igu_seg_access
+{
+	IGU_SEG_ACCESS_NORM,
+	IGU_SEG_ACCESS_DEF,
+	IGU_SEG_ACCESS_ATTN,
+	MAX_IGU_SEG_ACCESS};
+
+
+/*
+ * Parser parsing flags field
+ */
+struct parsing_flags
+{
+	uint16_t flags;
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags	0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
+#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags	0 or 1 */
+#define PARSING_FLAGS_VLAN_SHIFT 1
+#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags	0 or 1 */
+#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags	0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
+#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags	0=no IP options / extension headers. 1=IP options / extension header exist */
+#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags	0=non-fragmented, 1=fragmented */
+#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags	0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */
+#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags	0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */
+#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags	0=no TCP options. 1=TCP options */
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags	According to the TCP header options parsing */
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
+#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags	connection match in searcher indication */
+#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
+#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags	LLC SNAP indication */
+#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
+#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags	 */
+#define PARSING_FLAGS_RESERVED0_SHIFT 14
+};
+
+
+/*
+ * Parsing flags for TCP ACK type
+ */
+enum prs_flags_ack_type
+{
+	PRS_FLAG_PUREACK_PIGGY,
+	PRS_FLAG_PUREACK_PURE,
+	MAX_PRS_FLAGS_ACK_TYPE};
+
+
+/*
+ * Parsing flags for Ethernet address type
+ */
+enum prs_flags_eth_addr_type
+{
+	PRS_FLAG_ETHTYPE_NON_UNICAST,
+	PRS_FLAG_ETHTYPE_UNICAST,
+	MAX_PRS_FLAGS_ETH_ADDR_TYPE};
+
+
+/*
+ * Parsing flags for over-ethernet protocol
+ */
+enum prs_flags_over_eth
+{
+	PRS_FLAG_OVERETH_UNKNOWN,
+	PRS_FLAG_OVERETH_IPV4,
+	PRS_FLAG_OVERETH_IPV6,
+	PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
+	MAX_PRS_FLAGS_OVER_ETH};
+
+
+/*
+ * Parsing flags for over-IP protocol
+ */
+enum prs_flags_over_ip
+{
+	PRS_FLAG_OVERIP_UNKNOWN,
+	PRS_FLAG_OVERIP_TCP,
+	PRS_FLAG_OVERIP_UDP,
+	MAX_PRS_FLAGS_OVER_IP};
+
+
+/*
+ * SDM operation gen command (generate aggregative interrupt)
+ */
+struct sdm_op_gen
+{
+	uint32_t command;
+#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type	thread ID/aggr interrupt number/counter depending on the completion type */
+#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
+#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type	Direct messages to CM / PCI switch are not supported in operation_gen completion */
+#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
+#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type	bit index in aggregated interrupt vector */
+#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
+#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type	 */
+#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
+#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type	 */
+#define SDM_OP_GEN_RESERVED_SHIFT 17
+};
+
+
+/*
+ * Timers connection context
+ */
+struct timers_block_context
+{
+	uint32_t __reserved_0 /* data of client 0 of the timers block*/;
+	uint32_t __reserved_1 /* data of client 1 of the timers block*/;
+	uint32_t __reserved_2 /* data of client 2 of the timers block*/;
+	uint32_t flags;
+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags	number of active timers running */
+#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags	flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */
+#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
+#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags	 */
+#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
+};
+
+
+/*
+ * The eth aggregative context of Tstorm
+ */
+struct tstorm_eth_ag_context
+{
+	uint32_t __reserved0[14];
+};
+
+
+/*
+ * The eth aggregative context of Ustorm
+ */
+struct ustorm_eth_ag_context
+{
+	uint32_t __reserved0;
+#if defined(__BIG_ENDIAN)
+	uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+	uint8_t __reserved2;
+	uint16_t __reserved1;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t __reserved1;
+	uint8_t __reserved2;
+	uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
+#endif
+	uint32_t __reserved3[6];
+};
+
+
+/*
+ * The eth aggregative context of Xstorm
+ */
+struct xstorm_eth_ag_context
+{
+	uint32_t reserved0;
+#if defined(__BIG_ENDIAN)
+	uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+	uint8_t reserved2;
+	uint16_t reserved1;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t reserved1;
+	uint8_t reserved2;
+	uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
+#endif
+	uint32_t reserved3[30];
+};
+
+
+/*
+ * doorbell message sent to the chip
+ */
+struct doorbell
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t zero_fill2 /* driver must zero this field! */;
+	uint8_t zero_fill1 /* driver must zero this field! */;
+	struct doorbell_hdr header;
+#elif defined(__LITTLE_ENDIAN)
+	struct doorbell_hdr header;
+	uint8_t zero_fill1 /* driver must zero this field! */;
+	uint16_t zero_fill2 /* driver must zero this field! */;
+#endif
+};
+
+
+/*
+ * doorbell message sent to the chip
+ */
+struct doorbell_set_prod
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t prod /* Producer index to be set */;
+	uint8_t zero_fill1 /* driver must zero this field! */;
+	struct doorbell_hdr header;
+#elif defined(__LITTLE_ENDIAN)
+	struct doorbell_hdr header;
+	uint8_t zero_fill1 /* driver must zero this field! */;
+	uint16_t prod /* Producer index to be set */;
+#endif
+};
+
+
+struct regpair
+{
+	uint32_t lo /* low word for reg-pair */;
+	uint32_t hi /* high word for reg-pair */;
+};
+
+
+struct regpair_native
+{
+	uint32_t lo /* low word for reg-pair */;
+	uint32_t hi /* high word for reg-pair */;
+};
+
+
+/*
+ * Classify rule opcodes in E2/E3
+ */
+enum classify_rule
+{
+	CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,
+	CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,
+	CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,
+	MAX_CLASSIFY_RULE};
+
+
+/*
+ * Classify rule types in E2/E3
+ */
+enum classify_rule_action_type
+{
+	CLASSIFY_RULE_REMOVE,
+	CLASSIFY_RULE_ADD,
+	MAX_CLASSIFY_RULE_ACTION_TYPE};
+
+
+/*
+ * client init ramrod data $$KEEP_ENDIANNESS$$
+ */
+struct client_init_general_data
+{
+	uint8_t client_id /* client_id */;
+	uint8_t statistics_counter_id /* statistics counter id */;
+	uint8_t statistics_en_flg /* statistics en flg */;
+	uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;
+	uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
+	uint8_t sp_client_id /* the slow path rings client Id. */;
+	uint16_t mtu /* Host MTU from client config */;
+	uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;
+	uint8_t func_id /* PCI function ID (0-71) */;
+	uint8_t cos /* The connection cos, if applicable */;
+	uint8_t traffic_type;
+	uint32_t reserved0;
+};
+
+
+/*
+ * client init rx data $$KEEP_ENDIANNESS$$
+ */
+struct client_init_rx_data
+{
+	uint8_t tpa_en;
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable	tpa enable flg ipv4 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable	tpa enable flg ipv6 */
+#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
+#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable	tpa mode (LRO or GRO) (use enum tpa_mode) */
+#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
+#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable	 */
+#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
+	uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;
+	uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;
+	uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;
+	uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;
+	uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
+	uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;
+	uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;
+	uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;
+	uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;
+	uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;
+	uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;
+	uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;
+	uint8_t status_block_id /* rx status block id */;
+	uint8_t rx_sb_index_number /* status block indices */;
+	uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
+	uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
+	uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
+	uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;
+	uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
+	uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;
+	uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;
+	struct regpair bd_page_base /* BD page base address at the host */;
+	struct regpair sge_page_base /* SGE page base address at the host */;
+	struct regpair cqe_page_base /* Completion queue base address */;
+	uint8_t is_leading_rss;
+	uint8_t is_approx_mcast;
+	uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
+	uint16_t state;
+#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state	drop all unicast packets */
+#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state	accept all unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state	accept all unmatched unicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
+#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state	drop all multicast packets */
+#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
+#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state	accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
+#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state	accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
+#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state	accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
+#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state	 */
+#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
+	uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;
+	uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;
+	uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;
+	uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;
+	uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
+	uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
+	uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */;
+	uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
+	uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
+	uint32_t reserved6[2];
+};
+
+/*
+ * client init tx data $$KEEP_ENDIANNESS$$
+ */
+struct client_init_tx_data
+{
+	uint8_t enforce_security_flg /* if set, security checks will be made for this connection */;
+	uint8_t tx_status_block_id /* the number of status block to update */;
+	uint8_t tx_sb_index_number /* the index to use inside the status block */;
+	uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;
+	uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;
+	uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;
+	uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
+	struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */;
+	uint16_t state;
+#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state	accept all unicast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
+#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state	accept all multicast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
+#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state	accept all broadcast packets (subject to vlan) */
+#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
+#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state	accept packets matched only by MAC (without checking vlan) */
+#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
+#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state	 */
+#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
+	uint8_t default_vlan_flg /* is default vlan valid for this client. */;
+	uint8_t force_default_pri_flg /* if set, force default priority */;
+	uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;
+	uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;
+	uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;
+	uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;
+};
+
+/*
+ * client init ramrod data $$KEEP_ENDIANNESS$$
+ */
+struct client_init_ramrod_data
+{
+	struct client_init_general_data general /* client init general data */;
+	struct client_init_rx_data rx /* client init rx data */;
+	struct client_init_tx_data tx /* client init tx data */;
+};
+
+
+/*
+ * client update ramrod data $$KEEP_ENDIANNESS$$
+ */
+struct client_update_ramrod_data
+{
+	uint8_t client_id /* the client to update */;
+	uint8_t func_id /* PCI function ID this client belongs to (0-71) */;
+	uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;
+	uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;
+	uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;
+	uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;
+	uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;
+	uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;
+	uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
+	uint8_t activate_change_flg /* If set, activate_flg will be checked */;
+	uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
+	uint8_t default_vlan_enable_flg;
+	uint8_t default_vlan_change_flg;
+	uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
+	uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
+	uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
+	uint8_t silent_vlan_change_flg;
+	uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;
+	uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;
+	uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;
+	uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;
+	uint32_t reserved1;
+	uint32_t echo /* echo value to be sent to driver on event ring */;
+};
+
+
+/*
+ * The eth storm context of Cstorm
+ */
+struct cstorm_eth_st_context
+{
+	uint32_t __reserved0[4];
+};
+
+
+struct double_regpair
+{
+	uint32_t regpair0_lo /* low word for reg-pair0 */;
+	uint32_t regpair0_hi /* high word for reg-pair0 */;
+	uint32_t regpair1_lo /* low word for reg-pair1 */;
+	uint32_t regpair1_hi /* high word for reg-pair1 */;
+};
+
+
+/*
+ * Ethernet address typesm used in ethernet tx BDs
+ */
+enum eth_addr_type
+{
+	UNKNOWN_ADDRESS,
+	UNICAST_ADDRESS,
+	MULTICAST_ADDRESS,
+	BROADCAST_ADDRESS,
+	MAX_ETH_ADDR_TYPE};
+
+
+/*
+ *  $$KEEP_ENDIANNESS$$
+ */
+struct eth_classify_cmd_header
+{
+	uint8_t cmd_general_data;
+#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data	should this cmd be applied for Rx */
+#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
+#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data	should this cmd be applied for Tx */
+#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
+#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data	command opcode for MAC/VLAN/PAIR (use enum classify_rule) */
+#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
+#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data	 (use enum classify_rule_action_type) */
+#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
+#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data	 */
+#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
+	uint8_t func_id /* the function id */;
+	uint8_t client_id;
+	uint8_t reserved1;
+};
+
+
+/*
+ * header for eth classification config ramrod $$KEEP_ENDIANNESS$$
+ */
+struct eth_classify_header
+{
+	uint8_t rule_cnt /* number of rules in classification config ramrod */;
+	uint8_t reserved0;
+	uint16_t reserved1;
+	uint32_t echo /* echo value to be sent to driver on event ring */;
+};
+
+
+/*
+ * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$
+ */
+struct eth_classify_mac_cmd
+{
+	struct eth_classify_cmd_header header;
+	uint16_t reserved0;
+	uint16_t inner_mac;
+	uint16_t mac_lsb;
+	uint16_t mac_mid;
+	uint16_t mac_msb;
+	uint16_t reserved1;
+};
+
+
+/*
+ * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$
+ */
+struct eth_classify_pair_cmd
+{
+	struct eth_classify_cmd_header header;
+	uint16_t reserved0;
+	uint16_t inner_mac;
+	uint16_t mac_lsb;
+	uint16_t mac_mid;
+	uint16_t mac_msb;
+	uint16_t vlan;
+};
+
+
+/*
+ * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$
+ */
+struct eth_classify_vlan_cmd
+{
+	struct eth_classify_cmd_header header;
+	uint32_t reserved0;
+	uint32_t reserved1;
+	uint16_t reserved2;
+	uint16_t vlan;
+};
+
+/*
+ * union for eth classification rule $$KEEP_ENDIANNESS$$
+ */
+union eth_classify_rule_cmd
+{
+	struct eth_classify_mac_cmd mac;
+	struct eth_classify_vlan_cmd vlan;
+	struct eth_classify_pair_cmd pair;
+};
+
+/*
+ * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ */
+struct eth_classify_rules_ramrod_data
+{
+	struct eth_classify_header header;
+	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
+};
+
+
+/*
+ * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$
+ */
+struct eth_common_ramrod_data
+{
+	uint32_t client_id /* id of this client. (5 bits are used) */;
+	uint32_t reserved1;
+};
+
+
+/*
+ * The eth storm context of Ustorm
+ */
+struct ustorm_eth_st_context
+{
+	uint32_t reserved0[52];
+};
+
+/*
+ * The eth storm context of Tstorm
+ */
+struct tstorm_eth_st_context
+{
+	uint32_t __reserved0[28];
+};
+
+/*
+ * The eth storm context of Xstorm
+ */
+struct xstorm_eth_st_context
+{
+	uint32_t reserved0[60];
+};
+
+/*
+ * Ethernet connection context
+ */
+struct eth_context
+{
+	struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;
+	struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;
+	struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;
+	struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;
+	struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;
+	struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;
+	struct timers_block_context timers_context /* Timers block context */;
+	struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;
+	struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;
+};
+
+
+/*
+ * union for sgl and raw data.
+ */
+union eth_sgl_or_raw_data
+{
+	uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;
+	uint32_t raw_data[4] /* raw data from Tstorm to the driver. */;
+};
+
+/*
+ * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$
+ */
+struct eth_end_agg_rx_cqe
+{
+	uint8_t type_error_flags;
+#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags	 (use enum eth_rx_cqe_type) */
+#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
+#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags	 (use enum eth_rx_fp_sel) */
+#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
+#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags	 */
+#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
+	uint8_t reserved1;
+	uint8_t queue_index /* The aggregation queue index of this packet */;
+	uint8_t reserved2;
+	uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;
+	uint16_t num_of_coalesced_segs /* Num of coalesced segments. */;
+	uint16_t pkt_len /* Packet length */;
+	uint8_t pure_ack_count /* Number of pure acks coalesced. */;
+	uint8_t reserved3;
+	uint16_t reserved4;
+	union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
+	uint32_t reserved5[8];
+};
+
+
+/*
+ * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$
+ */
+struct eth_fast_path_rx_cqe
+{
+	uint8_t type_error_flags;
+#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags	 (use enum eth_rx_cqe_type) */
+#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags	 (use enum eth_rx_fp_sel) */
+#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags	Physical layer errors */
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags	IP checksum error */
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags	TCP/UDP checksum error */
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags	 */
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
+	uint8_t status_flags;
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags	 (use enum eth_rss_hash_type) */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags	RSS hashing on/off */
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags	if set to 1, this is a broadcast packet */
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags	if set to 1, the MAC address was matched in the tstorm CAM search */
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags	IP checksum validation was not performed (if packet is not IPv4) */
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags	TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
+	uint8_t queue_index /* The aggregation queue index of this packet */;
+	uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;
+	uint32_t rss_hash_result /* RSS toeplitz hash result */;
+	uint16_t vlan_tag /* Ethernet VLAN tag field */;
+	uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;
+	uint16_t len_on_bd /* Number of bytes placed on the BD */;
+	struct parsing_flags pars_flags;
+	union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
+	uint32_t reserved1[8];
+};
+
+
+/*
+ * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$
+ */
+struct eth_filter_rules_cmd
+{
+	uint8_t cmd_general_data;
+#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data	should this cmd be applied for Rx */
+#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
+#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data	should this cmd be applied for Tx */
+#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
+#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data	 */
+#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
+	uint8_t func_id /* the function id */;
+	uint8_t client_id /* the client id */;
+	uint8_t reserved1;
+	uint16_t state;
+#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state	drop all unicast packets */
+#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state	accept all unicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state	accept all unmatched unicast packets */
+#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
+#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state	drop all multicast packets */
+#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
+#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state	accept all multicast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
+#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state	accept all broadcast packets (subject to vlan) */
+#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
+#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state	accept packets matched only by MAC (without checking vlan) */
+#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
+#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state	 */
+#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
+	uint16_t reserved3;
+	struct regpair reserved4;
+};
+
+
+/*
+ * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$
+ */
+struct eth_filter_rules_ramrod_data
+{
+	struct eth_classify_header header;
+	struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
+};
+
+
+/*
+ * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
+ */
+struct eth_general_rules_ramrod_data
+{
+	struct eth_classify_header header;
+	union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
+};
+
+
+/*
+ * The data for Halt ramrod
+ */
+struct eth_halt_ramrod_data
+{
+	uint32_t client_id /* id of this client. (5 bits are used) */;
+	uint32_t reserved0;
+};
+
+
+/*
+ * destination and source mac address.
+ */
+struct eth_mac_addresses
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t dst_mid /* destination mac address 16 middle bits */;
+	uint16_t dst_lo /* destination mac address 16 low bits */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t dst_lo /* destination mac address 16 low bits */;
+	uint16_t dst_mid /* destination mac address 16 middle bits */;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t src_lo /* source mac address 16 low bits */;
+	uint16_t dst_hi /* destination mac address 16 high bits */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t dst_hi /* destination mac address 16 high bits */;
+	uint16_t src_lo /* source mac address 16 low bits */;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t src_hi /* source mac address 16 high bits */;
+	uint16_t src_mid /* source mac address 16 middle bits */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t src_mid /* source mac address 16 middle bits */;
+	uint16_t src_hi /* source mac address 16 high bits */;
+#endif
+};
+
+
+/*
+ * tunneling related data.
+ */
+struct eth_tunnel_data
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t dst_mid /* destination mac address 16 middle bits */;
+	uint16_t dst_lo /* destination mac address 16 low bits */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t dst_lo /* destination mac address 16 low bits */;
+	uint16_t dst_mid /* destination mac address 16 middle bits */;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
+	uint16_t dst_hi /* destination mac address 16 high bits */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t dst_hi /* destination mac address 16 high bits */;
+	uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
+#endif
+#if defined(__BIG_ENDIAN)
+	uint8_t flags;
+#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags	Set in case outer IP header is ipV6 */
+#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
+#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags	Should be set with 0 */
+#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
+	uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
+	uint16_t pseudo_csum /* Pseudo checksum with  length  field=0 */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t pseudo_csum /* Pseudo checksum with  length  field=0 */;
+	uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
+	uint8_t flags;
+#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags	Set in case outer IP header is ipV6 */
+#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
+#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags	Should be set with 0 */
+#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
+#endif
+};
+
+/*
+ * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).
+ */
+union eth_mac_addr_or_tunnel_data
+{
+	struct eth_mac_addresses mac_addr /* destination and source mac addresses. */;
+	struct eth_tunnel_data tunnel_data /* tunneling related data. */;
+};
+
+
+/*
+ * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$
+ */
+struct eth_multicast_rules_cmd
+{
+	uint8_t cmd_general_data;
+#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data	should this cmd be applied for Rx */
+#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
+#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data	should this cmd be applied for Tx */
+#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
+#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data	1 for add rule, 0 for remove rule */
+#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
+#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data	 */
+#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
+	uint8_t func_id /* the function id */;
+	uint8_t bin_id /* the bin to add this function to (0-255) */;
+	uint8_t engine_id /* the approximate multicast engine id */;
+	uint32_t reserved2;
+	struct regpair reserved3;
+};
+
+
+/*
+ * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$
+ */
+struct eth_multicast_rules_ramrod_data
+{
+	struct eth_classify_header header;
+	struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
+};
+
+
+/*
+ * Place holder for ramrods protocol specific data
+ */
+struct ramrod_data
+{
+	uint32_t data_lo;
+	uint32_t data_hi;
+};
+
+/*
+ * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
+ */
+union eth_ramrod_data
+{
+	struct ramrod_data general;
+};
+
+
+/*
+ * RSS toeplitz hash type, as reported in CQE
+ */
+enum eth_rss_hash_type
+{
+	DEFAULT_HASH_TYPE,
+	IPV4_HASH_TYPE,
+	TCP_IPV4_HASH_TYPE,
+	IPV6_HASH_TYPE,
+	TCP_IPV6_HASH_TYPE,
+	VLAN_PRI_HASH_TYPE,
+	E1HOV_PRI_HASH_TYPE,
+	DSCP_HASH_TYPE,
+	MAX_ETH_RSS_HASH_TYPE};
+
+
+/*
+ * Ethernet RSS mode
+ */
+enum eth_rss_mode
+{
+	ETH_RSS_MODE_DISABLED,
+	ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */,
+	ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
+	ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */,
+	ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */,
+	ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */,
+	MAX_ETH_RSS_MODE};
+
+
+/*
+ * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$
+ */
+struct eth_rss_update_ramrod_data
+{
+	uint8_t rss_engine_id;
+	uint8_t capabilities;
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities	configuration of the IpV4 2-tupple capability */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities	configuration of the IpV4 4-tupple capability for TCP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities	configuration of the IpV4 4-tupple capability for UDP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities	configuration of the IpV6 2-tupple capability */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities	configuration of the IpV6 4-tupple capability for TCP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities	configuration of the IpV6 4-tupple capability for UDP */
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
+#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities	configuration of the 5-tupple capability */
+#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities	if set update the rss keys */
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
+	uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
+	uint8_t rss_mode /* The RSS mode for this function */;
+	uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
+	uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
+	uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;
+	uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;
+	uint32_t echo;
+	uint32_t reserved3;
+};
+
+
+/*
+ * The eth Rx Buffer Descriptor
+ */
+struct eth_rx_bd
+{
+	uint32_t addr_lo /* Single continuous buffer low pointer */;
+	uint32_t addr_hi /* Single continuous buffer high pointer */;
+};
+
+
+/*
+ * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$
+ */
+struct common_ramrod_eth_rx_cqe
+{
+	uint8_t ramrod_type;
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type	 (use enum eth_rx_cqe_type) */
+#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
+#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type	 */
+#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type	 */
+#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
+	uint8_t conn_type /* only 3 bits are used */;
+	uint16_t reserved1 /* protocol specific data */;
+	uint32_t conn_and_cmd_data;
+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data	 */
+#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data	command id of the ramrod- use RamrodCommandIdEnum */
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
+	struct ramrod_data protocol_data /* protocol specific data */;
+	uint32_t echo;
+	uint32_t reserved2[11];
+};
+
+/*
+ * Rx Last CQE in page (in ETH)
+ */
+struct eth_rx_cqe_next_page
+{
+	uint32_t addr_lo /* Next page low pointer */;
+	uint32_t addr_hi /* Next page high pointer */;
+	uint32_t reserved[14];
+};
+
+/*
+ * union for all eth rx cqe types (fix their sizes)
+ */
+union eth_rx_cqe
+{
+	struct eth_fast_path_rx_cqe fast_path_cqe;
+	struct common_ramrod_eth_rx_cqe ramrod_cqe;
+	struct eth_rx_cqe_next_page next_page_cqe;
+	struct eth_end_agg_rx_cqe end_agg_cqe;
+};
+
+
+/*
+ * Values for RX ETH CQE type field
+ */
+enum eth_rx_cqe_type
+{
+	RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,
+	RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,
+	RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,
+	RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,
+	MAX_ETH_RX_CQE_TYPE};
+
+
+/*
+ * Type of SGL/Raw field in ETH RX fast path CQE
+ */
+enum eth_rx_fp_sel
+{
+	ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,
+	ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,
+	MAX_ETH_RX_FP_SEL};
+
+
+/*
+ * The eth Rx SGE Descriptor
+ */
+struct eth_rx_sge
+{
+	uint32_t addr_lo /* Single continuous buffer low pointer */;
+	uint32_t addr_hi /* Single continuous buffer high pointer */;
+};
+
+
+/*
+ * common data for all protocols $$KEEP_ENDIANNESS$$
+ */
+struct spe_hdr
+{
+	uint32_t conn_and_cmd_data;
+#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data	 */
+#define SPE_HDR_CID_SHIFT 0
+#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data	command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id  */
+#define SPE_HDR_CMD_ID_SHIFT 24
+	uint16_t type;
+#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type	connection type. (3 bits are used) (use enum connection_type) */
+#define SPE_HDR_CONN_TYPE_SHIFT 0
+#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type	 */
+#define SPE_HDR_FUNCTION_ID_SHIFT 8
+	uint16_t reserved1;
+};
+
+/*
+ * specific data for ethernet slow path element
+ */
+union eth_specific_data
+{
+	uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
+	struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */;
+	struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */;
+	struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;
+	struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;
+	struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;
+	struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;
+	struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;
+	struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;
+};
+
+/*
+ * Ethernet slow path element
+ */
+struct eth_spe
+{
+	struct spe_hdr hdr /* common data for all protocols */;
+	union eth_specific_data data /* data specific to ethernet protocol */;
+};
+
+
+/*
+ * Ethernet command ID for slow path elements
+ */
+enum eth_spqe_cmd_id
+{
+	RAMROD_CMD_ID_ETH_UNUSED,
+	RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,
+	RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,
+	RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,
+	RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,
+	RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,
+	RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,
+	RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,
+	RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,
+	RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
+	RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
+	RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
+	RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,
+	RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,
+	MAX_ETH_SPQE_CMD_ID};
+
+
+/*
+ * eth tpa update command
+ */
+enum eth_tpa_update_command
+{
+	TPA_UPDATE_NONE_COMMAND /* nop command */,
+	TPA_UPDATE_ENABLE_COMMAND /* enable command */,
+	TPA_UPDATE_DISABLE_COMMAND /* disable command */,
+	MAX_ETH_TPA_UPDATE_COMMAND};
+
+
+/*
+ * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header
+ */
+enum eth_tunnel_lso_inc_ip_id
+{
+	EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,
+	INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,
+	MAX_ETH_TUNNEL_LSO_INC_IP_ID};
+
+
+/*
+ * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.
+ */
+enum eth_tunnel_non_lso_csum_location
+{
+	CSUM_ON_PKT /* checksum is on the packet. */,
+	CSUM_ON_BD /* checksum is on the BD. */,
+	MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};
+
+
+/*
+ * Tx regular BD structure $$KEEP_ENDIANNESS$$
+ */
+struct eth_tx_bd
+{
+	uint32_t addr_lo /* Single continuous buffer low pointer */;
+	uint32_t addr_hi /* Single continuous buffer high pointer */;
+	uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;
+	uint16_t nbytes /* Size of the data represented by the BD */;
+	uint8_t reserved[4] /* keeps same size as other eth tx bd types */;
+};
+
+
+/*
+ * structure for easy accessibility to assembler
+ */
+struct eth_tx_bd_flags
+{
+	uint8_t as_bitfield;
+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield	IP CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
+#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield	L4 CKSUM flag,Relevant in START */
+#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
+#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield	00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */
+#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
+#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield	Start of packet BD */
+#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
+#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield	flag that indicates that the current packet is a udp packet */
+#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
+#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield	LSO flag, Relevant in START */
+#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
+#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield	set in case ipV6 packet, Relevant in START */
+#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
+};
+
+/*
+ * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$
+ */
+struct eth_tx_start_bd
+{
+	uint64_t addr;
+	uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;
+	uint16_t nbytes /* Size of the data represented by the BD */;
+	uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;
+	struct eth_tx_bd_flags bd_flags;
+	uint8_t general_data;
+#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data	contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */
+#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data	force vlan mode according to bds (vlan mode can change accroding to global configuration) */
+#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
+#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data	Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */
+#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
+#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data	set in case of tunneling encapsulated packet */
+#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
+};
+
+/*
+ * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$
+ */
+struct eth_tx_parse_bd_e1x
+{
+	uint16_t global_data;
+#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data	IP header Offset in WORDs from start of packet */
+#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data	marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data	 */
+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data	 */
+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
+#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data	an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
+#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data	reserved bit, should be set with 0 */
+#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
+	uint8_t tcp_flags;
+#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags	End of data flag */
+#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
+#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags	Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
+#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags	Reset connection flag */
+#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
+#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags	Push flag */
+#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
+#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags	Acknowledgment number valid flag */
+#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags	Urgent pointer valid flag */
+#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
+#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags	ECN-Echo */
+#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
+#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags	Congestion Window Reduced */
+#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
+	uint8_t ip_hlen_w /* IP header length in WORDs */;
+	uint16_t total_hlen_w /* IP+TCP+ETH */;
+	uint16_t tcp_pseudo_csum /* Checksum of pseudo header with  length  field=0 */;
+	uint16_t lso_mss /* for LSO mode */;
+	uint16_t ip_id /* for LSO mode */;
+	uint32_t tcp_send_seq /* for LSO mode */;
+};
+
+/*
+ * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$
+ */
+struct eth_tx_parse_bd_e2
+{
+	union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;
+	uint32_t parsing_data;
+#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data	TCP/UDP header Offset in WORDs from start of packet */
+#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data	TCP header size in DOUBLE WORDS */
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data	a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */
+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
+#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data	for LSO mode */
+#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data	marks ethernet address type (use enum eth_addr_type) */
+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
+};
+
+/*
+ * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$
+ */
+struct eth_tx_parse_2nd_bd
+{
+	uint16_t global_data;
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data	Outer IP header offset in WORDs (16-bit) from start of packet */
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
+#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data	should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
+#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data	 */
+#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
+#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data	an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
+#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
+#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data	Set in case UDP header exists in tunnel outer hedears. */
+#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data	Outer IP header length in WORDs (16-bit). Valid only for IpV4. */
+#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
+#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data	should be set with 0 */
+#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
+	uint16_t reserved2;
+	uint8_t tcp_flags;
+#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags	End of data flag */
+#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
+#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags	Synchronize sequence numbers flag */
+#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
+#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags	Reset connection flag */
+#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
+#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags	Push flag */
+#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
+#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags	Acknowledgment number valid flag */
+#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
+#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags	Urgent pointer valid flag */
+#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
+#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags	ECN-Echo */
+#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
+#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags	Congestion Window Reduced */
+#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
+	uint8_t reserved3;
+	uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;
+	uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;
+	uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;
+	uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;
+	uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;
+};
+
+/*
+ * The last BD in the BD memory will hold a pointer to the next BD memory
+ */
+struct eth_tx_next_bd
+{
+	uint32_t addr_lo /* Single continuous buffer low pointer */;
+	uint32_t addr_hi /* Single continuous buffer high pointer */;
+	uint8_t reserved[8] /* keeps same size as other eth tx bd types */;
+};
+
+/*
+ * union for 4 Bd types
+ */
+union eth_tx_bd_types
+{
+	struct eth_tx_start_bd start_bd /* the first bd in a packets */;
+	struct eth_tx_bd reg_bd /* the common bd */;
+	struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;
+	struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;
+	struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;
+	struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;
+};
+
+/*
+ * array of 13 bds as appears in the eth xstorm context
+ */
+struct eth_tx_bds_array
+{
+	union eth_tx_bd_types bds[13];
+};
+
+
+/*
+ * VLAN mode on TX BDs
+ */
+enum eth_tx_vlan_type
+{
+	X_ETH_NO_VLAN,
+	X_ETH_OUTBAND_VLAN,
+	X_ETH_INBAND_VLAN,
+	X_ETH_FW_ADDED_VLAN /* Driver should not use this! */,
+	MAX_ETH_TX_VLAN_TYPE};
+
+
+/*
+ * Ethernet VLAN filtering mode in E1x
+ */
+enum eth_vlan_filter_mode
+{
+	ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */,
+	ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,
+	ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,
+	MAX_ETH_VLAN_FILTER_MODE};
+
+
+/*
+ * MAC filtering configuration command header $$KEEP_ENDIANNESS$$
+ */
+struct mac_configuration_hdr
+{
+	uint8_t length /* number of entries valid in this command (6 bits) */;
+	uint8_t offset /* offset of the first entry in the list */;
+	uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;
+	uint32_t echo /* echo value to be sent to driver on event ring */;
+};
+
+/*
+ * MAC address in list for ramrod $$KEEP_ENDIANNESS$$
+ */
+struct mac_configuration_entry
+{
+	uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
+	uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
+	uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
+	uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;
+	uint8_t pf_id /* The pf id, for multi function mode */;
+	uint8_t flags;
+#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags	configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */
+#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
+#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags	If set, this MAC also belongs to RDMA client */
+#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
+#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags	 (use enum eth_vlan_filter_mode) */
+#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
+#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags	BitField flags  0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
+#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags	BitField flags   0 - not broadcast 1 - broadcast. relevant only to everest1 */
+#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
+#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags	 */
+#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
+	uint16_t reserved0;
+	uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;
+};
+
+/*
+ * MAC filtering configuration command
+ */
+struct mac_configuration_cmd
+{
+	struct mac_configuration_hdr hdr /* header */;
+	struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;
+};
+
+
+/*
+ * Set-MAC command type (in E1x)
+ */
+enum set_mac_action_type
+{
+	T_ETH_MAC_COMMAND_INVALIDATE,
+	T_ETH_MAC_COMMAND_SET,
+	MAX_SET_MAC_ACTION_TYPE};
+
+
+/*
+ * Ethernet TPA Modes
+ */
+enum tpa_mode
+{
+	TPA_LRO /* LRO mode TPA */,
+	TPA_GRO /* GRO mode TPA */,
+	MAX_TPA_MODE};
+
+
+/*
+ * tpa update ramrod data $$KEEP_ENDIANNESS$$
+ */
+struct tpa_update_ramrod_data
+{
+	uint8_t update_ipv4 /* none, enable or disable */;
+	uint8_t update_ipv6 /* none, enable or disable */;
+	uint8_t client_id /* client init flow control data */;
+	uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
+	uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
+	uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;
+	uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
+	uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;
+	uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
+	uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
+	uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;
+	uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;
+	uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
+	uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
+};
+
+
+/*
+ * approximate-match multicast filtering for E1H per function in Tstorm
+ */
+struct tstorm_eth_approximate_match_multicast_filtering
+{
+	uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;
+};
+
+
+/*
+ * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$
+ */
+struct tstorm_eth_function_common_config
+{
+	uint16_t config_flags;
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags	configuration of the port RSS IpV4 2-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags	configuration of the port RSS IpV4 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags	configuration of the port RSS IpV4 2-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags	configuration of the port RSS IpV6 4-tupple capability */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags	RSS mode of operation (use enum eth_rss_mode) */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags	0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */
+#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags	 */
+#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
+	uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
+	uint8_t reserved1;
+	uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;
+};
+
+
+/*
+ * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$
+ */
+struct tstorm_eth_mac_filter_config
+{
+	uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;
+	uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;
+	uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;
+	uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;
+	uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;
+	uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */;
+	uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;
+};
+
+
+/*
+ * tx only queue init ramrod data $$KEEP_ENDIANNESS$$
+ */
+struct tx_queue_init_ramrod_data
+{
+	struct client_init_general_data general /* client init general data */;
+	struct client_init_tx_data tx /* client init tx data */;
+};
+
+
+/*
+ * Three RX producers for ETH
+ */
+union ustorm_eth_rx_producers
+{
+	struct {
+#if defined(__BIG_ENDIAN)
+		uint16_t bd_prod /* Producer of the RX BD ring */;
+		uint16_t cqe_prod /* Producer of the RX CQE ring */;
+#elif defined(__LITTLE_ENDIAN)
+		uint16_t cqe_prod /* Producer of the RX CQE ring */;
+		uint16_t bd_prod /* Producer of the RX BD ring */;
+#endif
+#if defined(__BIG_ENDIAN)
+		uint16_t reserved;
+		uint16_t sge_prod /* Producer of the RX SGE ring */;
+#elif defined(__LITTLE_ENDIAN)
+		uint16_t sge_prod /* Producer of the RX SGE ring */;
+		uint16_t reserved;
+#endif
+	} prod;
+	uint32_t raw_data[2];
+};
+
+
+/*
+ * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$
+ */
+struct afex_vif_list_ramrod_data
+{
+	uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;
+	uint8_t func_bit_map /* the function bit map to set */;
+	uint16_t vif_list_index /* the VIF list, in a per pf vector  to add this function to */;
+	uint8_t func_to_clear /* the func id to clear in case of clear func mode */;
+	uint8_t echo;
+	uint16_t reserved1;
+};
+
+
+/*
+ * cfc delete event data  $$KEEP_ENDIANNESS$$
+ */
+struct cfc_del_event_data
+{
+	uint32_t cid /* cid of deleted connection */;
+	uint32_t reserved0;
+	uint32_t reserved1;
+};
+
+
+/*
+ * per-port SAFC demo variables
+ */
+struct cmng_flags_per_port
+{
+	uint32_t cmng_enables;
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes	if set, enable fairness between vnics */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes	if set, enable rate shaping between vnics */
+#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes	if set, enable fairness between COSes */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes	 (use enum fairness_mode) */
+#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
+#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes	reserved */
+#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
+	uint32_t __reserved1;
+};
+
+
+/*
+ * per-port rate shaping variables
+ */
+struct rate_shaping_vars_per_port
+{
+	uint32_t rs_periodic_timeout /* timeout of periodic timer */;
+	uint32_t rs_threshold /* threshold, below which we start to stop queues */;
+};
+
+/*
+ * per-port fairness variables
+ */
+struct fairness_vars_per_port
+{
+	uint32_t upper_bound /* Quota for a protocol/vnic */;
+	uint32_t fair_threshold /* almost-empty threshold */;
+	uint32_t fairness_timeout /* timeout of fairness timer */;
+	uint32_t reserved0;
+};
+
+/*
+ * per-port SAFC variables
+ */
+struct safc_struct_per_port
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t __reserved1;
+	uint8_t __reserved0;
+	uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
+	uint8_t __reserved0;
+	uint16_t __reserved1;
+#endif
+	uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;
+	uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;
+};
+
+/*
+ * Per-port congestion management variables
+ */
+struct cmng_struct_per_port
+{
+	struct rate_shaping_vars_per_port rs_vars;
+	struct fairness_vars_per_port fair_vars;
+	struct safc_struct_per_port safc_vars;
+	struct cmng_flags_per_port flags;
+};
+
+/*
+ * a single rate shaping counter. can be used as protocol or vnic counter
+ */
+struct rate_shaping_counter
+{
+	uint32_t quota /* Quota for a protocol/vnic */;
+#if defined(__BIG_ENDIAN)
+	uint16_t __reserved0;
+	uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
+	uint16_t __reserved0;
+#endif
+};
+
+/*
+ * per-vnic rate shaping variables
+ */
+struct rate_shaping_vars_per_vn
+{
+	struct rate_shaping_counter vn_counter /* per-vnic counter */;
+};
+
+/*
+ * per-vnic fairness variables
+ */
+struct fairness_vars_per_vn
+{
+	uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;
+	uint32_t vn_credit_delta /* used for incrementing the credit */;
+	uint32_t __reserved0;
+};
+
+/*
+ * cmng port init state
+ */
+struct cmng_vnic
+{
+	struct rate_shaping_vars_per_vn vnic_max_rate[4];
+	struct fairness_vars_per_vn vnic_min_rate[4];
+};
+
+/*
+ * cmng port init state
+ */
+struct cmng_init
+{
+	struct cmng_struct_per_port port;
+	struct cmng_vnic vnic;
+};
+
+
+/*
+ * driver parameters for congestion management init, all rates are in Mbps
+ */
+struct cmng_init_input
+{
+	uint32_t port_rate;
+	uint16_t vnic_min_rate[4] /* rates are in Mbps */;
+	uint16_t vnic_max_rate[4] /* rates are in Mbps */;
+	uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;
+	uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
+	struct cmng_flags_per_port flags;
+};
+
+
+/*
+ * Protocol-common command ID for slow path elements
+ */
+enum common_spqe_cmd_id
+{
+	RAMROD_CMD_ID_COMMON_UNUSED,
+	RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,
+	RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,
+	RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,
+	RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,
+	RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
+	RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,
+	RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
+	RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
+	RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,
+	RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+	MAX_COMMON_SPQE_CMD_ID};
+
+
+/*
+ * Per-protocol connection types
+ */
+enum connection_type
+{
+	ETH_CONNECTION_TYPE /* Ethernet */,
+	TOE_CONNECTION_TYPE /* TOE */,
+	RDMA_CONNECTION_TYPE /* RDMA */,
+	ISCSI_CONNECTION_TYPE /* iSCSI */,
+	FCOE_CONNECTION_TYPE /* FCoE */,
+	RESERVED_CONNECTION_TYPE_0,
+	RESERVED_CONNECTION_TYPE_1,
+	RESERVED_CONNECTION_TYPE_2,
+	NONE_CONNECTION_TYPE /* General- used for common slow path */,
+	MAX_CONNECTION_TYPE};
+
+
+/*
+ * Cos modes
+ */
+enum cos_mode
+{
+	OVERRIDE_COS /* Firmware deduce cos according to DCB */,
+	STATIC_COS /* Firmware has constant queues per CoS */,
+	FW_WRR /* Firmware keep fairness between different CoSes */,
+	MAX_COS_MODE};
+
+
+/*
+ * Dynamic HC counters set by the driver
+ */
+struct hc_dynamic_drv_counter
+{
+	uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;
+};
+
+/*
+ * zone A per-queue data
+ */
+struct cstorm_queue_zone_data
+{
+	struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;
+	struct regpair reserved[2];
+};
+
+
+/*
+ * Vf-PF channel data in cstorm ram (non-triggered zone)
+ */
+struct vf_pf_channel_zone_data
+{
+	uint32_t msg_addr_lo /* the message address on VF memory */;
+	uint32_t msg_addr_hi /* the message address on VF memory */;
+};
+
+/*
+ * zone for VF non-triggered data
+ */
+struct non_trigger_vf_zone
+{
+	struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;
+};
+
+/*
+ * Vf-PF channel trigger zone in cstorm ram
+ */
+struct vf_pf_channel_zone_trigger
+{
+	uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address.  */;
+};
+
+/*
+ * zone that triggers the in-bound interrupt
+ */
+struct trigger_vf_zone
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t reserved1;
+	uint8_t reserved0;
+	struct vf_pf_channel_zone_trigger vf_pf_channel;
+#elif defined(__LITTLE_ENDIAN)
+	struct vf_pf_channel_zone_trigger vf_pf_channel;
+	uint8_t reserved0;
+	uint16_t reserved1;
+#endif
+	uint32_t reserved2;
+};
+
+/*
+ * zone B per-VF data
+ */
+struct cstorm_vf_zone_data
+{
+	struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;
+	struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;
+};
+
+
+/*
+ * Dynamic host coalescing init parameters, per state machine
+ */
+struct dynamic_hc_sm_config
+{
+	uint32_t threshold[3] /* thresholds of number of outstanding bytes */;
+	uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;
+	uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;
+	uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;
+	uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;
+	uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;
+};
+
+/*
+ * Dynamic host coalescing init parameters
+ */
+struct dynamic_hc_config
+{
+	struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;
+};
+
+
+struct e2_integ_data
+{
+#if defined(__BIG_ENDIAN)
+	uint8_t flags;
+#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags	integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
+#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags	flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX_SHIFT 1
+#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags	flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX_SHIFT 2
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags	flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags	flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
+#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags	 */
+#define E2_INTEG_DATA_RESERVED_SHIFT 5
+	uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
+	uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
+	uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
+	uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
+	uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
+	uint8_t flags;
+#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags	integration testing enabled */
+#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
+#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags	flag indicating this connection will transmit on loopback */
+#define E2_INTEG_DATA_LB_TX_SHIFT 1
+#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags	flag indicating this connection will transmit according to cos field */
+#define E2_INTEG_DATA_COS_TX_SHIFT 2
+#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags	flag indicating this connection will activate the opportunistic QM credit flow */
+#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags	flag indicating this connection will release the door bell queue (DQ) */
+#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
+#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags	 */
+#define E2_INTEG_DATA_RESERVED_SHIFT 5
+#endif
+#if defined(__BIG_ENDIAN)
+	uint16_t reserved3;
+	uint8_t reserved2;
+	uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t ramEn /* context area reserved for reading enable bit from ram */;
+	uint8_t reserved2;
+	uint16_t reserved3;
+#endif
+};
+
+
+/*
+ * set mac event data  $$KEEP_ENDIANNESS$$
+ */
+struct eth_event_data
+{
+	uint32_t echo /* set mac echo data to return to driver */;
+	uint32_t reserved0;
+	uint32_t reserved1;
+};
+
+
+/*
+ * pf-vf event data  $$KEEP_ENDIANNESS$$
+ */
+struct vf_pf_event_data
+{
+	uint8_t vf_id /* VF ID (0-63) */;
+	uint8_t reserved0;
+	uint16_t reserved1;
+	uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;
+	uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;
+};
+
+/*
+ * VF FLR event data  $$KEEP_ENDIANNESS$$
+ */
+struct vf_flr_event_data
+{
+	uint8_t vf_id /* VF ID (0-63) */;
+	uint8_t reserved0;
+	uint16_t reserved1;
+	uint32_t reserved2;
+	uint32_t reserved3;
+};
+
+/*
+ * malicious VF event data  $$KEEP_ENDIANNESS$$
+ */
+struct malicious_vf_event_data
+{
+	uint8_t vf_id /* VF ID (0-63) */;
+	uint8_t err_id /* reason for malicious notification */;
+	uint16_t reserved1;
+	uint32_t reserved2;
+	uint32_t reserved3;
+};
+
+/*
+ * vif list event data  $$KEEP_ENDIANNESS$$
+ */
+struct vif_list_event_data
+{
+	uint8_t func_bit_map /* bit map of pf indice */;
+	uint8_t echo;
+	uint16_t reserved0;
+	uint32_t reserved1;
+	uint32_t reserved2;
+};
+
+/*
+ * function update event data  $$KEEP_ENDIANNESS$$
+ */
+struct function_update_event_data
+{
+	uint8_t echo;
+	uint8_t reserved;
+	uint16_t reserved0;
+	uint32_t reserved1;
+	uint32_t reserved2;
+};
+
+/*
+ * union for all event ring message types
+ */
+union event_data
+{
+	struct vf_pf_event_data vf_pf_event /* vf-pf event data */;
+	struct eth_event_data eth_event /* set mac event data */;
+	struct cfc_del_event_data cfc_del_event /* cfc delete event data */;
+	struct vf_flr_event_data vf_flr_event /* vf flr event data */;
+	struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;
+	struct vif_list_event_data vif_list_event /* vif list event data */;
+	struct function_update_event_data function_update_event /* function update event data */;
+};
+
+
+/*
+ * per PF event ring data
+ */
+struct event_ring_data
+{
+	struct regpair_native base_addr /* ring base address */;
+#if defined(__BIG_ENDIAN)
+	uint8_t index_id /* index ID within the status block */;
+	uint8_t sb_id /* status block ID */;
+	uint16_t producer /* event ring producer */;
+#elif defined(__LITTLE_ENDIAN)
+	uint16_t producer /* event ring producer */;
+	uint8_t sb_id /* status block ID */;
+	uint8_t index_id /* index ID within the status block */;
+#endif
+	uint32_t reserved0;
+};
+
+
+/*
+ * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$
+ */
+struct event_ring_msg
+{
+	uint8_t opcode;
+	uint8_t error /* error on the mesasage */;
+	uint16_t reserved1;
+	union event_data data /* message data (96 bits data) */;
+};
+
+/*
+ * event ring next page element (128 bits)
+ */
+struct event_ring_next
+{
+	struct regpair addr /* Address of the next page of the ring */;
+	uint32_t reserved[2];
+};
+
+/*
+ * union for event ring element types (each element is 128 bits)
+ */
+union event_ring_elem
+{
+	struct event_ring_msg message /* event ring message */;
+	struct event_ring_next next_page /* event ring next page */;
+};
+
+
+/*
+ * Common event ring opcodes
+ */
+enum event_ring_opcode
+{
+	EVENT_RING_OPCODE_VF_PF_CHANNEL,
+	EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,
+	EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,
+	EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,
+	EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
+	EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,
+	EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
+	EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
+	EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,
+	EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,
+	EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,
+	EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,
+	EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,
+	EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,
+	EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,
+	EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,
+	EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
+	EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
+	EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
+	MAX_EVENT_RING_OPCODE};
+
+
+/*
+ * Modes for fairness algorithm
+ */
+enum fairness_mode
+{
+	FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,
+	FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,
+	MAX_FAIRNESS_MODE};
+
+
+/*
+ * Priority and cos $$KEEP_ENDIANNESS$$
+ */
+struct priority_cos
+{
+	uint8_t priority /* Priority */;
+	uint8_t cos /* Cos */;
+	uint16_t reserved1;
+};
+
+/*
+ * The data for flow control configuration $$KEEP_ENDIANNESS$$
+ */
+struct flow_control_configuration
+{
+	struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;
+	uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;
+	uint8_t dcb_version /* DCB version Increase by one on each DCB update */;
+	uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;
+	uint8_t reserved1;
+	uint32_t reserved2;
+};
+
+
+/*
+ *  $$KEEP_ENDIANNESS$$
+ */
+struct function_start_data
+{
+	uint8_t function_mode /* the function mode */;
+	uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independant function mode. (E2/E3 Only) */;
+	uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;
+	uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
+	uint8_t path_id;
+	uint8_t network_cos_mode /* The cos mode for network traffic. */;
+	uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;
+	uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
+	uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
+	uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
+	uint16_t reserved1[2];
+};
+
+
+/*
+ *  $$KEEP_ENDIANNESS$$
+ */
+struct function_update_data
+{
+	uint8_t vif_id_change_flg /* If set, vif_id will be checked */;
+	uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;
+	uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;
+	uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;
+	uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
+	uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;
+	uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;
+	uint8_t network_cos_mode /* The cos mode for network traffic. */;
+	uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;
+	uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;
+	uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;
+	uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;
+	uint8_t echo;
+	uint8_t reserved1;
+	uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */;
+	uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
+	uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
+	uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
+	uint32_t reserved3;
+};
+
+
+/*
+ * FW version stored in the Xstorm RAM
+ */
+struct fw_version
+{
+#if defined(__BIG_ENDIAN)
+	uint8_t engineering /* firmware current engineering version */;
+	uint8_t revision /* firmware current revision version */;
+	uint8_t minor /* firmware current minor version */;
+	uint8_t major /* firmware current major version */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t major /* firmware current major version */;
+	uint8_t minor /* firmware current minor version */;
+	uint8_t revision /* firmware current revision version */;
+	uint8_t engineering /* firmware current engineering version */;
+#endif
+	uint32_t flags;
+#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags	if set, this is optimized ASM */
+#define FW_VERSION_OPTIMIZED_SHIFT 0
+#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags	if set, this is big-endien ASM */
+#define FW_VERSION_BIG_ENDIEN_SHIFT 1
+#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags	1 - E1H */
+#define FW_VERSION_CHIP_VERSION_SHIFT 2
+#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags	 */
+#define __FW_VERSION_RESERVED_SHIFT 4
+};
+
+
+/*
+ * GRE RSS Mode
+ */
+enum gre_rss_mode
+{
+	GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */,
+	GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */,
+	NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */,
+	MAX_GRE_RSS_MODE};
+
+
+/*
+ * GRE Tunnel Mode
+ */
+enum gre_tunnel_type
+{
+	NO_GRE_TUNNEL,
+	NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */,
+	L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */,
+	IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */,
+	MAX_GRE_TUNNEL_TYPE};
+
+
+/*
+ * Dynamic Host-Coalescing - Driver(host) counters
+ */
+struct hc_dynamic_sb_drv_counters
+{
+	uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;
+};
+
+
+/*
+ * 2 bytes. configuration/state parameters for a single protocol index
+ */
+struct hc_index_data
+{
+#if defined(__BIG_ENDIAN)
+	uint8_t flags;
+#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags	Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID_SHIFT 0
+#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags	if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags	if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
+#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags	 */
+#define HC_INDEX_DATA_RESERVE_SHIFT 3
+	uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
+	uint8_t flags;
+#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags	Index to a state machine. Can be 0 or 1 */
+#define HC_INDEX_DATA_SM_ID_SHIFT 0
+#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags	if set, host coalescing would be done for this index */
+#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags	if set, dynamic HC will be done for this index */
+#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
+#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags	 */
+#define HC_INDEX_DATA_RESERVE_SHIFT 3
+#endif
+};
+
+
+/*
+ * HC state-machine
+ */
+struct hc_status_block_sm
+{
+#if defined(__BIG_ENDIAN)
+	uint8_t igu_seg_id;
+	uint8_t igu_sb_id /* sb_id within the IGU */;
+	uint8_t timer_value /* Determines the time_to_expire */;
+	uint8_t __flags;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t __flags;
+	uint8_t timer_value /* Determines the time_to_expire */;
+	uint8_t igu_sb_id /* sb_id within the IGU */;
+	uint8_t igu_seg_id;
+#endif
+	uint32_t time_to_expire /* The time in which it expects to wake up */;
+};
+
+/*
+ * hold PCI identification variables- used in various places in firmware
+ */
+struct pci_entity
+{
+#if defined(__BIG_ENDIAN)
+	uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
+	uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
+	uint8_t vnic_id /* Virtual NIC ID (0-3) */;
+	uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
+	uint8_t vnic_id /* Virtual NIC ID (0-3) */;
+	uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
+	uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
+#endif
+};
+
+/*
+ * The fast-path status block meta-data, common to all chips
+ */
+struct hc_sb_data
+{
+	struct regpair_native host_sb_addr /* Host status block address */;
+	struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;
+	struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+#if defined(__BIG_ENDIAN)
+	uint8_t rsrv0;
+	uint8_t state;
+	uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
+	uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
+	uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
+	uint8_t state;
+	uint8_t rsrv0;
+#endif
+	struct regpair_native rsrv1[2];
+};
+
+
+/*
+ * Segment types for host coaslescing
+ */
+enum hc_segment
+{
+	HC_REGULAR_SEGMENT,
+	HC_DEFAULT_SEGMENT,
+	MAX_HC_SEGMENT};
+
+
+/*
+ * The fast-path status block meta-data
+ */
+struct hc_sp_status_block_data
+{
+	struct regpair_native host_sb_addr /* Host status block address */;
+#if defined(__BIG_ENDIAN)
+	uint8_t rsrv1;
+	uint8_t state;
+	uint8_t igu_seg_id /* segment id of the IGU */;
+	uint8_t igu_sb_id /* sb_id within the IGU */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t igu_sb_id /* sb_id within the IGU */;
+	uint8_t igu_seg_id /* segment id of the IGU */;
+	uint8_t state;
+	uint8_t rsrv1;
+#endif
+	struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
+};
+
+
+/*
+ * The fast-path status block meta-data
+ */
+struct hc_status_block_data_e1x
+{
+	struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;
+	struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+};
+
+
+/*
+ * The fast-path status block meta-data
+ */
+struct hc_status_block_data_e2
+{
+	struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;
+	struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
+};
+
+
+/*
+ * IGU block operartion modes (in Everest2)
+ */
+enum igu_mode
+{
+	HC_IGU_BC_MODE /* Backward compatible mode */,
+	HC_IGU_NBC_MODE /* Non-backward compatible mode */,
+	MAX_IGU_MODE};
+
+
+/*
+ * IP versions
+ */
+enum ip_ver
+{
+	IP_V4,
+	IP_V6,
+	MAX_IP_VER};
+
+
+/*
+ * Malicious VF error ID
+ */
+enum malicious_vf_error_id
+{
+	VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,
+	ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,
+	ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,
+	ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,
+	ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,
+	ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,
+	ETH_TOO_MANY_BDS /* Tx packet has too many BDs */,
+	ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,
+	ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,
+	ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,
+	ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,
+	ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,
+	ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,
+	ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,
+	MAX_MALICIOUS_VF_ERROR_ID};
+
+
+/*
+ * Multi-function modes
+ */
+enum mf_mode
+{
+	SINGLE_FUNCTION,
+	MULTI_FUNCTION_SD /* Switch dependent (vlan based) */,
+	MULTI_FUNCTION_SI /* Switch independent (mac based) */,
+	MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,
+	MAX_MF_MODE};
+
+
+/*
+ * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$
+ */
+struct tstorm_per_pf_stats
+{
+	struct regpair rcv_error_bytes /* number of bytes received with errors */;
+};
+
+/*
+ *  $$KEEP_ENDIANNESS$$
+ */
+struct per_pf_stats
+{
+	struct tstorm_per_pf_stats tstorm_pf_statistics;
+};
+
+
+/*
+ * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$
+ */
+struct tstorm_per_port_stats
+{
+	uint32_t mac_discard /* number of packets with mac errors */;
+	uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;
+	uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;
+	uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;
+	uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;
+	uint32_t reserved;
+};
+
+/*
+ *  $$KEEP_ENDIANNESS$$
+ */
+struct per_port_stats
+{
+	struct tstorm_per_port_stats tstorm_port_statistics;
+};
+
+
+/*
+ * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$
+ */
+struct tstorm_per_queue_stats
+{
+	struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;
+	uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;
+	uint32_t checksum_discard /* number of total packets received with checksum error */;
+	struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;
+	uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;
+	uint32_t pkts_too_big_discard /* number of too long packets received */;
+	struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;
+	uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;
+	uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;
+	uint16_t no_buff_discard;
+	uint16_t reserved0;
+	uint32_t reserved1;
+};
+
+/*
+ * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$
+ */
+struct ustorm_per_queue_stats
+{
+	struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;
+	struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;
+	struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;
+	uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
+	uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
+	uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
+	uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;
+	struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */;
+	uint32_t coalesced_events /* the number of aggregations */;
+	uint32_t coalesced_aborts /* the number of exception which avoid aggregation */;
+};
+
+/*
+ * Protocol-common statistics collected by the Xstorm (per client)  $$KEEP_ENDIANNESS$$
+ */
+struct xstorm_per_queue_stats
+{
+	struct regpair ucast_bytes_sent /* number of total bytes sent without errors */;
+	struct regpair mcast_bytes_sent /* number of total bytes sent without errors */;
+	struct regpair bcast_bytes_sent /* number of total bytes sent without errors */;
+	uint32_t ucast_pkts_sent /* number of total packets sent without errors */;
+	uint32_t mcast_pkts_sent /* number of total packets sent without errors */;
+	uint32_t bcast_pkts_sent /* number of total packets sent without errors */;
+	uint32_t error_drop_pkts /* number of total packets drooped due to errors */;
+};
+
+/*
+ *  $$KEEP_ENDIANNESS$$
+ */
+struct per_queue_stats
+{
+	struct tstorm_per_queue_stats tstorm_queue_statistics;
+	struct ustorm_per_queue_stats ustorm_queue_statistics;
+	struct xstorm_per_queue_stats xstorm_queue_statistics;
+};
+
+
+/*
+ * FW version stored in first line of pram $$KEEP_ENDIANNESS$$
+ */
+struct pram_fw_version
+{
+	uint8_t major /* firmware current major version */;
+	uint8_t minor /* firmware current minor version */;
+	uint8_t revision /* firmware current revision version */;
+	uint8_t engineering /* firmware current engineering version */;
+	uint8_t flags;
+#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags	if set, this is optimized ASM */
+#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
+#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags	storm_id identification */
+#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
+#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags	if set, this is big-endien ASM */
+#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
+#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */
+#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
+#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags	 */
+#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
+};
+
+
+/*
+ * Ethernet slow path element
+ */
+union protocol_common_specific_data
+{
+	uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
+	struct regpair phy_address /* SPE physical address */;
+	struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;
+	struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;
+};
+
+/*
+ * The send queue element
+ */
+struct protocol_common_spe
+{
+	struct spe_hdr hdr /* SPE header */;
+	union protocol_common_specific_data data /* data specific to common protocol */;
+};
+
+
+/*
+ * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$
+ */
+struct set_timesync_ramrod_data
+{
+	uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;
+	uint8_t offset_cmd /* Timesync Offset Command */;
+	uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;
+	uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;
+	uint32_t drift_adjust_period /* Drift Adjust Period (in us) */;
+	struct regpair offset_delta /* Timesync Offset Delta (in ns) */;
+};
+
+
+/*
+ * The send queue element
+ */
+struct slow_path_element
+{
+	struct spe_hdr hdr /* common data for all protocols */;
+	struct regpair protocol_data /* additional data specific to the protocol */;
+};
+
+
+/*
+ * Protocol-common statistics counter $$KEEP_ENDIANNESS$$
+ */
+struct stats_counter
+{
+	uint16_t xstats_counter /* xstorm statistics counter */;
+	uint16_t reserved0;
+	uint32_t reserved1;
+	uint16_t tstats_counter /* tstorm statistics counter */;
+	uint16_t reserved2;
+	uint32_t reserved3;
+	uint16_t ustats_counter /* ustorm statistics counter */;
+	uint16_t reserved4;
+	uint32_t reserved5;
+	uint16_t cstats_counter /* ustorm statistics counter */;
+	uint16_t reserved6;
+	uint32_t reserved7;
+};
+
+
+/*
+ *  $$KEEP_ENDIANNESS$$
+ */
+struct stats_query_entry
+{
+	uint8_t kind;
+	uint8_t index /* queue index */;
+	uint16_t funcID /* the func the statistic will send to */;
+	uint32_t reserved;
+	struct regpair address /* pxp address */;
+};
+
+/*
+ * statistic command $$KEEP_ENDIANNESS$$
+ */
+struct stats_query_cmd_group
+{
+	struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
+};
+
+
+/*
+ * statistic command header $$KEEP_ENDIANNESS$$
+ */
+struct stats_query_header
+{
+	uint8_t cmd_num /* command number */;
+	uint8_t reserved0;
+	uint16_t drv_stats_counter;
+	uint32_t reserved1;
+	struct regpair stats_counters_addrs /* stats counter */;
+};
+
+
+/*
+ * Types of statistcis query entry
+ */
+enum stats_query_type
+{
+	STATS_TYPE_QUEUE,
+	STATS_TYPE_PORT,
+	STATS_TYPE_PF,
+	STATS_TYPE_TOE,
+	STATS_TYPE_FCOE,
+	MAX_STATS_QUERY_TYPE};
+
+
+/*
+ * Indicate of the function status block state
+ */
+enum status_block_state
+{
+	SB_DISABLED,
+	SB_ENABLED,
+	SB_CLEANED,
+	MAX_STATUS_BLOCK_STATE};
+
+
+/*
+ * Storm IDs (including attentions for IGU related enums)
+ */
+enum storm_id
+{
+	USTORM_ID,
+	CSTORM_ID,
+	XSTORM_ID,
+	TSTORM_ID,
+	ATTENTION_ID,
+	MAX_STORM_ID};
+
+
+/*
+ * Taffic types used in ETS and flow control algorithms
+ */
+enum traffic_type
+{
+	LLFC_TRAFFIC_TYPE_NW /* Networking */,
+	LLFC_TRAFFIC_TYPE_FCOE /* FCoE */,
+	LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,
+	MAX_TRAFFIC_TYPE};
+
+
+/*
+ * zone A per-queue data
+ */
+struct tstorm_queue_zone_data
+{
+	struct regpair reserved[4];
+};
+
+
+/*
+ * zone B per-VF data
+ */
+struct tstorm_vf_zone_data
+{
+	struct regpair reserved;
+};
+
+
+/*
+ * Add or Subtract Value for Set Timesync Ramrod
+ */
+enum ts_add_sub_value
+{
+	TS_SUB_VALUE /* Subtract Value */,
+	TS_ADD_VALUE /* Add Value */,
+	MAX_TS_ADD_SUB_VALUE};
+
+
+/*
+ * Drift-Adjust Commands for Set Timesync Ramrod
+ */
+enum ts_drift_adjust_cmd
+{
+	TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,
+	TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,
+	TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,
+	MAX_TS_DRIFT_ADJUST_CMD};
+
+
+/*
+ * Offset Commands for Set Timesync Ramrod
+ */
+enum ts_offset_cmd
+{
+	TS_OFFSET_KEEP /* Keep Offset at current values */,
+	TS_OFFSET_INC /* Increase Offset by Offset Delta */,
+	TS_OFFSET_DEC /* Decrease Offset by Offset Delta */,
+	MAX_TS_OFFSET_CMD};
+
+
+/*
+ * zone A per-queue data
+ */
+struct ustorm_queue_zone_data
+{
+	union ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;
+	struct regpair reserved[3];
+};
+
+
+/*
+ * zone B per-VF data
+ */
+struct ustorm_vf_zone_data
+{
+	struct regpair reserved;
+};
+
+
+/*
+ * data per VF-PF channel
+ */
+struct vf_pf_channel_data
+{
+#if defined(__BIG_ENDIAN)
+	uint16_t reserved0;
+	uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
+	uint8_t state /* channel state (ready / waiting for ack) */;
+#elif defined(__LITTLE_ENDIAN)
+	uint8_t state /* channel state (ready / waiting for ack) */;
+	uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
+	uint16_t reserved0;
+#endif
+	uint32_t reserved1;
+};
+
+
+/*
+ * State of VF-PF channel
+ */
+enum vf_pf_channel_state
+{
+	VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,
+	VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,
+	MAX_VF_PF_CHANNEL_STATE};
+
+
+/*
+ * vif_list_rule_kind
+ */
+enum vif_list_rule_kind
+{
+	VIF_LIST_RULE_SET,
+	VIF_LIST_RULE_GET,
+	VIF_LIST_RULE_CLEAR_ALL,
+	VIF_LIST_RULE_CLEAR_FUNC,
+	MAX_VIF_LIST_RULE_KIND};
+
+
+/*
+ * zone A per-queue data
+ */
+struct xstorm_queue_zone_data
+{
+	struct regpair reserved[4];
+};
+
+
+/*
+ * zone B per-VF data
+ */
+struct xstorm_vf_zone_data
+{
+	struct regpair reserved;
+};
+
+
+#endif /* ECORE_HSI_H */
+
diff --git a/lib/librte_pmd_bcm/ecore_init.h b/lib/librte_pmd_bcm/ecore_init.h
new file mode 100644
index 0000000..3cca0ab
--- /dev/null
+++ b/lib/librte_pmd_bcm/ecore_init.h
@@ -0,0 +1,842 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ECORE_INIT_H
+#define ECORE_INIT_H
+
+/* Init operation types and structures */
+enum {
+	OP_RD = 0x1,	/* read a single register */
+	OP_WR,		/* write a single register */
+	OP_SW,		/* copy a string to the device */
+	OP_ZR,		/* clear memory */
+	OP_ZP,		/* unzip then copy with DMAE */
+	OP_WR_64,	/* write 64 bit pattern */
+	OP_WB,		/* copy a string using DMAE */
+	OP_WB_ZR,	/* Clear a string using DMAE or indirect-wr */
+	OP_IF_MODE_OR,  /* Skip the following ops if all init modes don't match */
+	OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */
+	OP_IF_PHASE,
+	OP_RT,
+	OP_DELAY,
+	OP_VERIFY,
+	OP_MAX
+};
+
+enum {
+	STAGE_START,
+	STAGE_END,
+};
+
+/* Returns the index of start or end of a specific block stage in ops array*/
+#define BLOCK_OPS_IDX(block, stage, end) \
+	(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
+
+
+/* structs for the various opcodes */
+struct raw_op {
+	uint32_t op:8;
+	uint32_t offset:24;
+	uint32_t raw_data;
+};
+
+struct op_read {
+	uint32_t op:8;
+	uint32_t offset:24;
+	uint32_t val;
+};
+
+struct op_write {
+	uint32_t op:8;
+	uint32_t offset:24;
+	uint32_t val;
+};
+
+struct op_arr_write {
+	uint32_t op:8;
+	uint32_t offset:24;
+#ifdef __BIG_ENDIAN
+	uint16_t data_len;
+	uint16_t data_off;
+#else /* __LITTLE_ENDIAN */
+	uint16_t data_off;
+	uint16_t data_len;
+#endif
+};
+
+struct op_zero {
+	uint32_t op:8;
+	uint32_t offset:24;
+	uint32_t len;
+};
+
+struct op_if_mode {
+	uint32_t op:8;
+	uint32_t cmd_offset:24;
+	uint32_t mode_bit_map;
+};
+
+struct op_if_phase {
+	uint32_t op:8;
+	uint32_t cmd_offset:24;
+	uint32_t phase_bit_map;
+};
+
+struct op_delay {
+	uint32_t op:8;
+	uint32_t reserved:24;
+	uint32_t delay;
+};
+
+union init_op {
+	struct op_read		read;
+	struct op_write		write;
+	struct op_arr_write	arr_wr;
+	struct op_zero		zero;
+	struct raw_op		raw;
+	struct op_if_mode	if_mode;
+	struct op_if_phase	if_phase;
+	struct op_delay		delay;
+};
+
+
+/* Init Phases */
+enum {
+	PHASE_COMMON,
+	PHASE_PORT0,
+	PHASE_PORT1,
+	PHASE_PF0,
+	PHASE_PF1,
+	PHASE_PF2,
+	PHASE_PF3,
+	PHASE_PF4,
+	PHASE_PF5,
+	PHASE_PF6,
+	PHASE_PF7,
+	NUM_OF_INIT_PHASES
+};
+
+/* Init Modes */
+enum {
+	MODE_ASIC                      = 0x00000001,
+	MODE_FPGA                      = 0x00000002,
+	MODE_EMUL                      = 0x00000004,
+	MODE_E2                        = 0x00000008,
+	MODE_E3                        = 0x00000010,
+	MODE_PORT2                     = 0x00000020,
+	MODE_PORT4                     = 0x00000040,
+	MODE_SF                        = 0x00000080,
+	MODE_MF                        = 0x00000100,
+	MODE_MF_SD                     = 0x00000200,
+	MODE_MF_SI                     = 0x00000400,
+	MODE_MF_AFEX                   = 0x00000800,
+	MODE_E3_A0                     = 0x00001000,
+	MODE_E3_B0                     = 0x00002000,
+	MODE_COS3                      = 0x00004000,
+	MODE_COS6                      = 0x00008000,
+	MODE_LITTLE_ENDIAN             = 0x00010000,
+	MODE_BIG_ENDIAN                = 0x00020000,
+};
+
+/* Init Blocks */
+enum {
+	BLOCK_ATC,
+	BLOCK_BRB1,
+	BLOCK_CCM,
+	BLOCK_CDU,
+	BLOCK_CFC,
+	BLOCK_CSDM,
+	BLOCK_CSEM,
+	BLOCK_DBG,
+	BLOCK_DMAE,
+	BLOCK_DORQ,
+	BLOCK_HC,
+	BLOCK_IGU,
+	BLOCK_MISC,
+	BLOCK_NIG,
+	BLOCK_PBF,
+	BLOCK_PGLUE_B,
+	BLOCK_PRS,
+	BLOCK_PXP2,
+	BLOCK_PXP,
+	BLOCK_QM,
+	BLOCK_SRC,
+	BLOCK_TCM,
+	BLOCK_TM,
+	BLOCK_TSDM,
+	BLOCK_TSEM,
+	BLOCK_UCM,
+	BLOCK_UPB,
+	BLOCK_USDM,
+	BLOCK_USEM,
+	BLOCK_XCM,
+	BLOCK_XPB,
+	BLOCK_XSDM,
+	BLOCK_XSEM,
+	BLOCK_MISC_AEU,
+	NUM_OF_INIT_BLOCKS
+};
+
+
+
+
+
+
+
+
+/* Vnics per mode */
+#define ECORE_PORT2_MODE_NUM_VNICS 4
+
+
+/* QM queue numbers */
+#define ECORE_ETH_Q		0
+#define ECORE_TOE_Q		3
+#define ECORE_TOE_ACK_Q		6
+#define ECORE_ISCSI_Q		9
+#define ECORE_ISCSI_ACK_Q	11
+#define ECORE_FCOE_Q		10
+
+/* Vnics per mode */
+#define ECORE_PORT4_MODE_NUM_VNICS 2
+
+/* COS offset for port1 in E3 B0 4port mode */
+#define ECORE_E3B0_PORT1_COS_OFFSET 3
+
+/* QM Register addresses */
+#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\
+	(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
+#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\
+	(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
+#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\
+	(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
+
+/* extracts the QM queue number for the specified port and vnic */
+#define ECORE_PF_Q_NUM(q_num, port, vnic)\
+	((((port) << 1) | (vnic)) * 16 + (q_num))
+
+
+/* Maps the specified queue to the specified COS */
+static inline void ecore_map_q_cos(struct bcm_softc *sc, uint32_t q_num, uint32_t new_cos)
+{
+	/* find current COS mapping */
+	uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);
+
+	/* check if queue->COS mapping has changed */
+	if (curr_cos != new_cos) {
+		uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;
+		uint32_t reg_addr, reg_bit_map, vnic;
+
+		/* update parameters for 4port mode */
+		if (INIT_MODE_FLAGS(sc) & MODE_PORT4) {
+			num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
+			if (PORT_ID(sc)) {
+				curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
+				new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
+			}
+		}
+
+		/* change queue mapping for each VNIC */
+		for (vnic = 0; vnic < num_vnics; vnic++) {
+			uint32_t pf_q_num =
+				ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);
+			uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
+
+			/* overwrite queue->VOQ mapping */
+			REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
+
+			/* clear queue bit from current COS bit map */
+			reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
+			reg_bit_map = REG_RD(sc, reg_addr);
+			REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
+
+			/* set queue bit in new COS bit map */
+			reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
+			reg_bit_map = REG_RD(sc, reg_addr);
+			REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
+
+			/* set/clear queue bit in command-queue bit map
+			(E2/E3A0 only, valid COS values are 0/1) */
+			if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) {
+				reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);
+				reg_bit_map = REG_RD(sc, reg_addr);
+				q_bit_map = 1 << (2 * (pf_q_num & 0xf));
+				reg_bit_map = new_cos ?
+					      (reg_bit_map | q_bit_map) :
+					      (reg_bit_map & (~q_bit_map));
+				REG_WR(sc, reg_addr, reg_bit_map);
+			}
+		}
+	}
+}
+
+/* Configures the QM according to the specified per-traffic-type COSes */
+static inline void ecore_dcb_config_qm(struct bcm_softc *sc, enum cos_mode mode,
+				       struct priority_cos *traffic_cos)
+{
+	ecore_map_q_cos(sc, ECORE_FCOE_Q,
+			traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
+	ecore_map_q_cos(sc, ECORE_ISCSI_Q,
+			traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
+	ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q,
+		traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
+	if (mode != STATIC_COS) {
+		/* required only in OVERRIDE_COS mode */
+		ecore_map_q_cos(sc, ECORE_ETH_Q,
+				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
+		ecore_map_q_cos(sc, ECORE_TOE_Q,
+				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
+		ecore_map_q_cos(sc, ECORE_TOE_ACK_Q,
+				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
+	}
+}
+
+
+/*
+ * congestion managment port init api description
+ * the api works as follows:
+ * the driver should pass the cmng_init_input struct, the port_init function
+ * will prepare the required internal ram structure which will be passed back
+ * to the driver (cmng_init) that will write it into the internal ram.
+ *
+ * IMPORTANT REMARKS:
+ * 1. the cmng_init struct does not represent the contiguous internal ram
+ *    structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
+ *    offset in order to write the port sub struct and the
+ *    PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
+ *    words - don't use memcpy!).
+ * 2. although the cmng_init struct is filled for the maximal vnic number
+ *    possible, the driver should only write the valid vnics into the internal
+ *    ram according to the appropriate port mode.
+ */
+#define BITS_TO_BYTES(x) ((x)/8)
+
+/* CMNG constants, as derived from system spec calculations */
+
+/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
+#define DEF_MIN_RATE 100
+
+/* resolution of the rate shaping timer - 400 usec */
+#define RS_PERIODIC_TIMEOUT_USEC 400
+
+/*
+ *  number of bytes in single QM arbitration cycle -
+ *  coefficient for calculating the fairness timer
+ */
+#define QM_ARB_BYTES 160000
+
+/* resolution of Min algorithm 1:100 */
+#define MIN_RES 100
+
+/*
+ *  how many bytes above threshold for
+ *  the minimal credit of Min algorithm
+ */
+#define MIN_ABOVE_THRESH 32768
+
+/*
+ *  Fairness algorithm integration time coefficient -
+ *  for calculating the actual Tfair
+ */
+#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
+
+/* Memory of fairness algorithm - 2 cycles */
+#define FAIR_MEM 2
+#define SAFC_TIMEOUT_USEC 52
+
+#define SDM_TICKS 4
+
+
+static inline void ecore_init_max(const struct cmng_init_input *input_data,
+				  uint32_t r_param, struct cmng_init *ram_data)
+{
+	uint32_t vnic;
+	struct cmng_vnic *vdata = &ram_data->vnic;
+	struct cmng_struct_per_port *pdata = &ram_data->port;
+	/*
+	 * rate shaping per-port variables
+	 *  100 micro seconds in SDM ticks = 25
+	 *  since each tick is 4 microSeconds
+	 */
+
+	pdata->rs_vars.rs_periodic_timeout =
+	RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
+
+	/* this is the threshold below which no timer arming will occur.
+	 *  1.25 coefficient is for the threshold to be a little bigger
+	 *  then the real time to compensate for timer in-accuracy
+	 */
+	pdata->rs_vars.rs_threshold =
+	(5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
+
+	/* rate shaping per-vnic variables */
+	for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
+		/* global vnic counter */
+		vdata->vnic_max_rate[vnic].vn_counter.rate =
+		input_data->vnic_max_rate[vnic];
+		/*
+		 * maximal Mbps for this vnic
+		 * the quota in each timer period - number of bytes
+		 * transmitted in this period
+		 */
+		vdata->vnic_max_rate[vnic].vn_counter.quota =
+			RS_PERIODIC_TIMEOUT_USEC *
+			(uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
+	}
+
+}
+
+static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate,
+				  struct rate_shaping_vars_per_vn *ram_data)
+{
+	/* global vnic counter */
+	ram_data->vn_counter.rate = vnic_max_rate;
+
+	/*
+	* maximal Mbps for this vnic
+	* the quota in each timer period - number of bytes
+	* transmitted in this period
+	*/
+	ram_data->vn_counter.quota =
+		RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8;
+}
+
+static inline void ecore_init_min(const struct cmng_init_input *input_data,
+				  uint32_t r_param, struct cmng_init *ram_data)
+{
+	uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
+	struct cmng_vnic *vdata = &ram_data->vnic;
+	struct cmng_struct_per_port *pdata = &ram_data->port;
+
+	/* this is the resolution of the fairness timer */
+	fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
+
+	/*
+	 * fairness per-port variables
+	 * for 10G it is 1000usec. for 1G it is 10000usec.
+	 */
+	tFair = T_FAIR_COEF / input_data->port_rate;
+
+	/* this is the threshold below which we won't arm the timer anymore */
+	pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
+
+	/*
+	 *  we multiply by 1e3/8 to get bytes/msec. We don't want the credits
+	 *  to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
+	 */
+	pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
+
+	/* since each tick is 4 microSeconds */
+	pdata->fair_vars.fairness_timeout =
+				fair_periodic_timeout_usec / SDM_TICKS;
+
+	/* calculate sum of weights */
+	vnicWeightSum = 0;
+
+	for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++)
+		vnicWeightSum += input_data->vnic_min_rate[vnic];
+
+	/* global vnic counter */
+	if (vnicWeightSum > 0) {
+		/* fairness per-vnic variables */
+		for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
+			/*
+			 *  this is the credit for each period of the fairness
+			 *  algorithm - number of bytes in T_FAIR (this vnic
+			 *  share of the port rate)
+			 */
+			vdata->vnic_min_rate[vnic].vn_credit_delta =
+				((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 *
+				(T_FAIR_COEF / (8 * 100 * vnicWeightSum)));
+			if (vdata->vnic_min_rate[vnic].vn_credit_delta <
+			    pdata->fair_vars.fair_threshold +
+			    MIN_ABOVE_THRESH) {
+				vdata->vnic_min_rate[vnic].vn_credit_delta =
+					pdata->fair_vars.fair_threshold +
+					MIN_ABOVE_THRESH;
+			}
+		}
+	}
+}
+
+static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,
+				     struct cmng_init *ram_data)
+{
+	uint32_t vnic, cos;
+	uint32_t cosWeightSum = 0;
+	struct cmng_vnic *vdata = &ram_data->vnic;
+	struct cmng_struct_per_port *pdata = &ram_data->port;
+
+	for (cos = 0; cos < MAX_COS_NUMBER; cos++)
+		cosWeightSum += input_data->cos_min_rate[cos];
+
+	if (cosWeightSum > 0) {
+
+		for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {
+			/*
+			 *  Since cos and vnic shouldn't work together the rate
+			 *  to divide between the coses is the port rate.
+			 */
+			uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
+			for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
+				/*
+				 * this is the credit for each period of
+				 * the fairness algorithm - number of bytes
+				 * in T_FAIR (this cos share of the vnic rate)
+				 */
+				ccd[cos] =
+				    ((uint32_t)input_data->cos_min_rate[cos] * 100 *
+				    (T_FAIR_COEF / (8 * 100 * cosWeightSum)));
+				 if (ccd[cos] < pdata->fair_vars.fair_threshold
+						+ MIN_ABOVE_THRESH) {
+					ccd[cos] =
+					    pdata->fair_vars.fair_threshold +
+					    MIN_ABOVE_THRESH;
+				}
+			}
+		}
+	}
+}
+
+static inline void ecore_init_safc(struct cmng_init *ram_data)
+{
+	/* in microSeconds */
+	ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
+}
+
+/* Congestion management port init */
+static inline void ecore_init_cmng(const struct cmng_init_input *input_data,
+				   struct cmng_init *ram_data)
+{
+	uint32_t r_param;
+	ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));
+
+	ram_data->port.flags = input_data->flags;
+
+	/*
+	 *  number of bytes transmitted in a rate of 10Gbps
+	 *  in one usec = 1.25KB.
+	 */
+	r_param = BITS_TO_BYTES(input_data->port_rate);
+	ecore_init_max(input_data, r_param, ram_data);
+	ecore_init_min(input_data, r_param, ram_data);
+	ecore_init_fw_wrr(input_data, ram_data);
+	ecore_init_safc(ram_data);
+}
+
+
+
+
+/* Returns the index of start or end of a specific block stage in ops array*/
+#define BLOCK_OPS_IDX(block, stage, end) \
+			(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
+
+
+#define INITOP_SET		0	/* set the HW directly */
+#define INITOP_CLEAR		1	/* clear the HW directly */
+#define INITOP_INIT		2	/* set the init-value array */
+
+/****************************************************************************
+* ILT management
+****************************************************************************/
+struct ilt_line {
+	ecore_dma_addr_t page_mapping;
+	void *page;
+	uint32_t size;
+};
+
+struct ilt_client_info {
+	uint32_t page_size;
+	uint16_t start;
+	uint16_t end;
+	uint16_t client_num;
+	uint16_t flags;
+#define ILT_CLIENT_SKIP_INIT	0x1
+#define ILT_CLIENT_SKIP_MEM	0x2
+};
+
+struct ecore_ilt {
+	uint32_t start_line;
+	struct ilt_line		*lines;
+	struct ilt_client_info	clients[4];
+#define ILT_CLIENT_CDU	0
+#define ILT_CLIENT_QM	1
+#define ILT_CLIENT_SRC	2
+#define ILT_CLIENT_TM	3
+};
+
+/****************************************************************************
+* SRC configuration
+****************************************************************************/
+struct src_ent {
+	uint8_t opaque[56];
+	uint64_t next;
+};
+
+/****************************************************************************
+* Parity configuration
+****************************************************************************/
+#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \
+{ \
+	block##_REG_##block##_PRTY_MASK, \
+	block##_REG_##block##_PRTY_STS_CLR, \
+	en_mask, {m1h, m2, m3}, #block \
+}
+
+#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \
+{ \
+	block##_REG_##block##_PRTY_MASK_0, \
+	block##_REG_##block##_PRTY_STS_CLR_0, \
+	en_mask, {m1h, m2, m3}, #block"_0" \
+}
+
+#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \
+{ \
+	block##_REG_##block##_PRTY_MASK_1, \
+	block##_REG_##block##_PRTY_STS_CLR_1, \
+	en_mask, {m1h, m2, m3}, #block"_1" \
+}
+
+static const struct {
+	uint32_t mask_addr;
+	uint32_t sts_clr_addr;
+	uint32_t en_mask;		/* Mask to enable parity attentions */
+	struct {
+		uint32_t e1h;	/* 57711 */
+		uint32_t e2;		/* 57712 */
+		uint32_t e3;		/* 578xx */
+	} reg_mask;		/* Register mask (all valid bits) */
+	char name[8];		/* Block's longest name is 7 characters long
+				 * (name + suffix)
+				 */
+} ecore_blocks_parity_data[] = {
+	/* bit 19 masked */
+	/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
+	/* bit 5,18,20-31 */
+	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
+	/* bit 5 */
+	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);	*/
+	/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
+	/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
+
+	/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
+	 * want to handle "system kill" flow at the moment.
+	 */
+	BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,
+			0x7ffffff),
+	BLOCK_PRTY_INFO_0(PXP2,	0xffffffff, 0xffffffff, 0xffffffff,
+			  0xffffffff),
+	BLOCK_PRTY_INFO_1(PXP2,	0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),
+	BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),
+	BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),
+	BLOCK_PRTY_INFO_0(NIG,	0xffffffff, 0, 0xffffffff, 0xffffffff),
+	BLOCK_PRTY_INFO_1(NIG,	0xffff, 0, 0xff, 0xffff),
+	BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),
+	BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
+	BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),
+	BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),
+	BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),
+	BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
+	{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
+		GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
+		{0xf, 0xf, 0xf}, "UPB"},
+	{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
+		GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
+		{0xf, 0xf, 0xf}, "XPB"},
+	BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
+	BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
+	BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),
+	BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
+	BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
+	BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
+	BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
+	BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),
+	BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),
+	BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
+	BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
+	BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
+	BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
+	BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+	BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+	BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
+	BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
+	BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+	BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),
+	BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+	BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),
+	BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+	BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),
+	BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+	BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),
+};
+
+
+/* [28] MCP Latched rom_parity
+ * [29] MCP Latched ump_rx_parity
+ * [30] MCP Latched ump_tx_parity
+ * [31] MCP Latched scpad_parity
+ */
+#define MISC_AEU_ENABLE_MCP_PRTY_BITS	\
+	(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
+	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
+	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
+	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+
+/* Below registers control the MCP parity attention output. When
+ * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
+ * enabled, when cleared - disabled.
+ */
+static const uint32_t mcp_attn_ctl_regs[] = {
+	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
+	MISC_REG_AEU_ENABLE4_NIG_0,
+	MISC_REG_AEU_ENABLE4_PXP_0,
+	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
+	MISC_REG_AEU_ENABLE4_NIG_1,
+	MISC_REG_AEU_ENABLE4_PXP_1
+};
+
+static inline void ecore_set_mcp_parity(struct bcm_softc *sc, uint8_t enable)
+{
+	uint32_t i;
+	uint32_t reg_val;
+
+	for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
+		reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);
+
+		if (enable)
+			reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
+		else
+			reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
+
+		REG_WR(sc, mcp_attn_ctl_regs[i], reg_val);
+	}
+}
+
+static inline uint32_t ecore_parity_reg_mask(struct bcm_softc *sc, int idx)
+{
+	if (CHIP_IS_E1H(sc))
+		return ecore_blocks_parity_data[idx].reg_mask.e1h;
+	else if (CHIP_IS_E2(sc))
+		return ecore_blocks_parity_data[idx].reg_mask.e2;
+	else /* CHIP_IS_E3 */
+		return ecore_blocks_parity_data[idx].reg_mask.e3;
+}
+
+static inline void ecore_disable_blocks_parity(struct bcm_softc *sc)
+{
+	uint32_t i;
+
+	for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+		uint32_t dis_mask = ecore_parity_reg_mask(sc, i);
+
+		if (dis_mask) {
+			REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
+			       dis_mask);
+			ECORE_MSG("Setting parity mask "
+						 "for %s to\t\t0x%x",
+				    ecore_blocks_parity_data[i].name, dis_mask);
+		}
+	}
+
+	/* Disable MCP parity attentions */
+	ecore_set_mcp_parity(sc, FALSE);
+}
+
+/**
+ * Clear the parity error status registers.
+ */
+static inline void ecore_clear_blocks_parity(struct bcm_softc *sc)
+{
+	uint32_t i;
+	uint32_t reg_val, mcp_aeu_bits =
+		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
+		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
+		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
+		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
+
+	/* Clear SEM_FAST parities */
+	REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+	REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+	REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+	REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+
+	for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+		uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
+
+		if (reg_mask) {
+			reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
+					 sts_clr_addr);
+			if (reg_val & reg_mask)
+				ECORE_MSG(sc,
+					   "Parity errors in %s: 0x%x",
+					   ecore_blocks_parity_data[i].name,
+					   reg_val & reg_mask);
+		}
+	}
+
+	/* Check if there were parity attentions in MCP */
+	reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
+	if (reg_val & mcp_aeu_bits)
+		ECORE_MSG("Parity error in MCP: 0x%x",
+			   reg_val & mcp_aeu_bits);
+
+	/* Clear parity attentions in MCP:
+	 * [7]  clears Latched rom_parity
+	 * [8]  clears Latched ump_rx_parity
+	 * [9]  clears Latched ump_tx_parity
+	 * [10] clears Latched scpad_parity (both ports)
+	 */
+	REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
+}
+
+static inline void ecore_enable_blocks_parity(struct bcm_softc *sc)
+{
+	uint32_t i;
+
+	for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
+		uint32_t reg_mask = ecore_parity_reg_mask(sc, i);
+
+		if (reg_mask)
+			REG_WR(sc, ecore_blocks_parity_data[i].mask_addr,
+				ecore_blocks_parity_data[i].en_mask & reg_mask);
+	}
+
+	/* Enable MCP parity attentions */
+	ecore_set_mcp_parity(sc, TRUE);
+}
+
+
+#endif /* ECORE_INIT_H */
+
diff --git a/lib/librte_pmd_bcm/ecore_init_ops.h b/lib/librte_pmd_bcm/ecore_init_ops.h
new file mode 100644
index 0000000..003dce5
--- /dev/null
+++ b/lib/librte_pmd_bcm/ecore_init_ops.h
@@ -0,0 +1,886 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ECORE_INIT_OPS_H
+#define ECORE_INIT_OPS_H
+
+static int ecore_gunzip(struct bcm_softc *sc, const uint8_t *zbuf, int len);
+static void ecore_write_dmae_phys_len(struct bcm_softc *sc,
+				      ecore_dma_addr_t phys_addr, uint32_t addr,
+				      uint32_t len);
+
+static void ecore_init_str_wr(struct bcm_softc *sc, uint32_t addr,
+			      const uint32_t *data, uint32_t len)
+{
+	uint32_t i;
+
+	for (i = 0; i < len; i++)
+		REG_WR(sc, addr + i*4, data[i]);
+}
+
+static void ecore_write_big_buf(struct bcm_softc *sc, uint32_t addr, uint32_t len)
+{
+	if (DMAE_READY(sc))
+		ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
+
+	else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+}
+
+static void ecore_init_fill(struct bcm_softc *sc, uint32_t addr, int fill,
+			    uint32_t len)
+{
+	uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
+	uint32_t buf_len32 = buf_len/4;
+	uint32_t i;
+
+	ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len);
+
+	for (i = 0; i < len; i += buf_len32) {
+		uint32_t cur_len = min(buf_len32, len - i);
+
+		ecore_write_big_buf(sc, addr + i*4, cur_len);
+	}
+}
+
+static void ecore_write_big_buf_wb(struct bcm_softc *sc, uint32_t addr, uint32_t len)
+{
+	if (DMAE_READY(sc))
+		ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
+
+	else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
+}
+
+static void ecore_init_wr_64(struct bcm_softc *sc, uint32_t addr,
+			     const uint32_t *data, uint32_t len64)
+{
+	uint32_t buf_len32 = FW_BUF_SIZE/4;
+	uint32_t len = len64*2;
+	uint64_t data64 = 0;
+	uint32_t i;
+
+	/* 64 bit value is in a blob: first low DWORD, then high DWORD */
+	data64 = HILO_U64((*(data + 1)), (*data));
+
+	len64 = min((uint32_t)(FW_BUF_SIZE/8), len64);
+	for (i = 0; i < len64; i++) {
+		uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i;
+
+		*pdata = data64;
+	}
+
+	for (i = 0; i < len; i += buf_len32) {
+		uint32_t cur_len = min(buf_len32, len - i);
+
+		ecore_write_big_buf_wb(sc, addr + i*4, cur_len);
+	}
+}
+
+/*********************************************************
+   There are different blobs for each PRAM section.
+   In addition, each blob write operation is divided into a few operations
+   in order to decrease the amount of phys. contiguous buffer needed.
+   Thus, when we select a blob the address may be with some offset
+   from the beginning of PRAM section.
+   The same holds for the INT_TABLE sections.
+**********************************************************/
+#define IF_IS_INT_TABLE_ADDR(base, addr) \
+			if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
+
+#define IF_IS_PRAM_ADDR(base, addr) \
+			if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
+
+static const uint8_t *ecore_sel_blob(struct bcm_softc *sc, uint32_t addr,
+				const uint8_t *data)
+{
+	IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
+		data = INIT_TSEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
+			data = INIT_CSEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
+			data = INIT_USEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
+			data = INIT_XSEM_INT_TABLE_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
+			data = INIT_TSEM_PRAM_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
+			data = INIT_CSEM_PRAM_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
+			data = INIT_USEM_PRAM_DATA(sc);
+	else
+		IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
+			data = INIT_XSEM_PRAM_DATA(sc);
+
+	return data;
+}
+
+static void ecore_init_wr_wb(struct bcm_softc *sc, uint32_t addr,
+			     const uint32_t *data, uint32_t len)
+{
+	if (DMAE_READY(sc))
+		VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
+
+	else ecore_init_str_wr(sc, addr, data, len);
+}
+
+static void ecore_wr_64(struct bcm_softc *sc, uint32_t reg, uint32_t val_lo,
+			uint32_t val_hi)
+{
+	uint32_t wb_write[2];
+
+	wb_write[0] = val_lo;
+	wb_write[1] = val_hi;
+	REG_WR_DMAE_LEN(sc, reg, wb_write, 2);
+}
+
+static void ecore_init_wr_zp(struct bcm_softc *sc, uint32_t addr, uint32_t len,
+			     uint32_t blob_off)
+{
+	const uint8_t *data = NULL;
+	int rc;
+	uint32_t i;
+
+	data = ecore_sel_blob(sc, addr, data) + blob_off*4;
+
+	rc = ecore_gunzip(sc, data, len);
+	if (rc)
+		return;
+
+	/* gunzip_outlen is in dwords */
+	len = GUNZIP_OUTLEN(sc);
+	for (i = 0; i < len; i++)
+		((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t)
+				ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]);
+
+	ecore_write_big_buf_wb(sc, addr, len);
+}
+
+static void ecore_init_block(struct bcm_softc *sc, uint32_t block, uint32_t stage)
+{
+	uint16_t op_start =
+		INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
+						     STAGE_START)];
+	uint16_t op_end =
+		INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
+						     STAGE_END)];
+	const union init_op *op;
+	uint32_t op_idx, op_type, addr, len;
+	const uint32_t *data, *data_base;
+
+	/* If empty block */
+	if (op_start == op_end)
+		return;
+
+	data_base = INIT_DATA(sc);
+
+	for (op_idx = op_start; op_idx < op_end; op_idx++) {
+
+		op = (const union init_op *)&(INIT_OPS(sc)[op_idx]);
+		/* Get generic data */
+		op_type = op->raw.op;
+		addr = op->raw.offset;
+		/* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
+		 * OP_WR64 (we assume that op_arr_write and op_write have the
+		 * same structure).
+		 */
+		len = op->arr_wr.data_len;
+		data = data_base + op->arr_wr.data_off;
+
+		switch (op_type) {
+		case OP_RD:
+			REG_RD(sc, addr);
+			break;
+		case OP_WR:
+			REG_WR(sc, addr, op->write.val);
+			break;
+		case OP_SW:
+			ecore_init_str_wr(sc, addr, data, len);
+			break;
+		case OP_WB:
+			ecore_init_wr_wb(sc, addr, data, len);
+			break;
+		case OP_ZR:
+		case OP_WB_ZR:
+			ecore_init_fill(sc, addr, 0, op->zero.len);
+			break;
+		case OP_ZP:
+			ecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off);
+			break;
+		case OP_WR_64:
+			ecore_init_wr_64(sc, addr, data, len);
+			break;
+		case OP_IF_MODE_AND:
+			/* if any of the flags doesn't match, skip the
+			 * conditional block.
+			 */
+			if ((INIT_MODE_FLAGS(sc) &
+				op->if_mode.mode_bit_map) !=
+				op->if_mode.mode_bit_map)
+				op_idx += op->if_mode.cmd_offset;
+			break;
+		case OP_IF_MODE_OR:
+			/* if all the flags don't match, skip the conditional
+			 * block.
+			 */
+			if ((INIT_MODE_FLAGS(sc) &
+				op->if_mode.mode_bit_map) == 0)
+				op_idx += op->if_mode.cmd_offset;
+			break;
+		    /* the following opcodes are unused at the moment. */
+		case OP_IF_PHASE:
+		case OP_RT:
+		case OP_DELAY:
+		case OP_VERIFY:
+		default:
+			/* Should never get here! */
+
+			break;
+		}
+	}
+}
+
+
+/****************************************************************************
+* PXP Arbiter
+****************************************************************************/
+/*
+ * This code configures the PCI read/write arbiter
+ * which implements a weighted round robin
+ * between the virtual queues in the chip.
+ *
+ * The values were derived for each PCI max payload and max request size.
+ * since max payload and max request size are only known at run time,
+ * this is done as a separate init stage.
+ */
+
+#define NUM_WR_Q			13
+#define NUM_RD_Q			29
+#define MAX_RD_ORD			3
+#define MAX_WR_ORD			2
+
+/* configuration for one arbiter queue */
+struct arb_line {
+	int l;
+	int add;
+	int ubound;
+};
+
+/* derived configuration for each read queue for each max request size */
+static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
+/* 1 */	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+	{ {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
+	{ {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
+	{ {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
+	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
+/* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 64, 6},  {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+/* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
+	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
+};
+
+/* derived configuration for each write queue for each max request size */
+static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
+/* 1 */	{ {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
+	{ {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
+	{ {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+	{ {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+	{ {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+	{ {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
+	{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
+	{ {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+	{ {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
+/* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
+	{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
+	{ {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
+	{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
+};
+
+/* register addresses for read queues */
+static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
+/* 1 */	{PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
+		PXP2_REG_RQ_BW_RD_UBOUND0},
+	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+		PXP2_REG_PSWRQ_BW_UB1},
+	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+		PXP2_REG_PSWRQ_BW_UB2},
+	{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+		PXP2_REG_PSWRQ_BW_UB3},
+	{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
+		PXP2_REG_RQ_BW_RD_UBOUND4},
+	{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
+		PXP2_REG_RQ_BW_RD_UBOUND5},
+	{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+		PXP2_REG_PSWRQ_BW_UB6},
+	{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+		PXP2_REG_PSWRQ_BW_UB7},
+	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+		PXP2_REG_PSWRQ_BW_UB8},
+/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+		PXP2_REG_PSWRQ_BW_UB9},
+	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+		PXP2_REG_PSWRQ_BW_UB10},
+	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+		PXP2_REG_PSWRQ_BW_UB11},
+	{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
+		PXP2_REG_RQ_BW_RD_UBOUND12},
+	{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
+		PXP2_REG_RQ_BW_RD_UBOUND13},
+	{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
+		PXP2_REG_RQ_BW_RD_UBOUND14},
+	{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
+		PXP2_REG_RQ_BW_RD_UBOUND15},
+	{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
+		PXP2_REG_RQ_BW_RD_UBOUND16},
+	{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
+		PXP2_REG_RQ_BW_RD_UBOUND17},
+	{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
+		PXP2_REG_RQ_BW_RD_UBOUND18},
+/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
+		PXP2_REG_RQ_BW_RD_UBOUND19},
+	{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
+		PXP2_REG_RQ_BW_RD_UBOUND20},
+	{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
+		PXP2_REG_RQ_BW_RD_UBOUND22},
+	{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
+		PXP2_REG_RQ_BW_RD_UBOUND23},
+	{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
+		PXP2_REG_RQ_BW_RD_UBOUND24},
+	{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
+		PXP2_REG_RQ_BW_RD_UBOUND25},
+	{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
+		PXP2_REG_RQ_BW_RD_UBOUND26},
+	{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
+		PXP2_REG_RQ_BW_RD_UBOUND27},
+	{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+		PXP2_REG_PSWRQ_BW_UB28}
+};
+
+/* register addresses for write queues */
+static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
+/* 1 */	{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
+		PXP2_REG_PSWRQ_BW_UB1},
+	{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
+		PXP2_REG_PSWRQ_BW_UB2},
+	{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
+		PXP2_REG_PSWRQ_BW_UB3},
+	{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
+		PXP2_REG_PSWRQ_BW_UB6},
+	{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
+		PXP2_REG_PSWRQ_BW_UB7},
+	{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
+		PXP2_REG_PSWRQ_BW_UB8},
+	{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
+		PXP2_REG_PSWRQ_BW_UB9},
+	{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
+		PXP2_REG_PSWRQ_BW_UB10},
+	{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
+		PXP2_REG_PSWRQ_BW_UB11},
+/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
+		PXP2_REG_PSWRQ_BW_UB28},
+	{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
+		PXP2_REG_RQ_BW_WR_UBOUND29},
+	{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
+		PXP2_REG_RQ_BW_WR_UBOUND30}
+};
+
+static void ecore_init_pxp_arb(struct bcm_softc *sc, int r_order,
+			       int w_order)
+{
+	uint32_t val, i;
+
+	if (r_order > MAX_RD_ORD) {
+		ECORE_MSG("read order of %d  order adjusted to %d",
+			   r_order, MAX_RD_ORD);
+		r_order = MAX_RD_ORD;
+	}
+	if (w_order > MAX_WR_ORD) {
+		ECORE_MSG("write order of %d  order adjusted to %d",
+			   w_order, MAX_WR_ORD);
+		w_order = MAX_WR_ORD;
+	}
+	if (CHIP_REV_IS_FPGA(sc)) {
+		ECORE_MSG("write order adjusted to 1 for FPGA");
+		w_order = 0;
+	}
+	ECORE_MSG("read order %d  write order %d", r_order, w_order);
+
+	for (i = 0; i < NUM_RD_Q-1; i++) {
+		REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
+		REG_WR(sc, read_arb_addr[i].add,
+		       read_arb_data[i][r_order].add);
+		REG_WR(sc, read_arb_addr[i].ubound,
+		       read_arb_data[i][r_order].ubound);
+	}
+
+	for (i = 0; i < NUM_WR_Q-1; i++) {
+		if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
+		    (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
+
+			REG_WR(sc, write_arb_addr[i].l,
+			       write_arb_data[i][w_order].l);
+
+			REG_WR(sc, write_arb_addr[i].add,
+			       write_arb_data[i][w_order].add);
+
+			REG_WR(sc, write_arb_addr[i].ubound,
+			       write_arb_data[i][w_order].ubound);
+		} else {
+
+			val = REG_RD(sc, write_arb_addr[i].l);
+			REG_WR(sc, write_arb_addr[i].l,
+			       val | (write_arb_data[i][w_order].l << 10));
+
+			val = REG_RD(sc, write_arb_addr[i].add);
+			REG_WR(sc, write_arb_addr[i].add,
+			       val | (write_arb_data[i][w_order].add << 10));
+
+			val = REG_RD(sc, write_arb_addr[i].ubound);
+			REG_WR(sc, write_arb_addr[i].ubound,
+			       val | (write_arb_data[i][w_order].ubound << 7));
+		}
+	}
+
+	val =  write_arb_data[NUM_WR_Q-1][w_order].add;
+	val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
+	val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
+	REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
+
+	val =  read_arb_data[NUM_RD_Q-1][r_order].add;
+	val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
+	val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
+	REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
+
+	REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
+	REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
+	REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
+	REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
+
+	if (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD))
+		REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
+
+	if (CHIP_IS_E3(sc))
+		REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
+	else if (CHIP_IS_E2(sc))
+		REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
+	else
+		REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
+
+	/*    MPS      w_order     optimal TH      presently TH
+	 *    128         0             0               2
+	 *    256         1             1               3
+	 *    >=512       2             2               3
+	 */
+	/* DMAE is special */
+	if (!CHIP_IS_E1H(sc)) {
+		/* E2 can use optimal TH */
+		val = w_order;
+		REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
+	} else {
+		val = ((w_order == 0) ? 2 : 3);
+		REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
+	}
+
+	REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
+	REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
+
+	/* Validate number of tags suppoted by device */
+#define PCIE_REG_PCIER_TL_HDR_FC_ST		0x2980
+	val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);
+	val &= 0xFF;
+	if (val <= 0x20)
+		REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
+}
+
+/****************************************************************************
+* ILT management
+****************************************************************************/
+/*
+ * This codes hides the low level HW interaction for ILT management and
+ * configuration. The API consists of a shadow ILT table which is set by the
+ * driver and a set of routines to use it to configure the HW.
+ *
+ */
+
+/* ILT HW init operations */
+
+/* ILT memory management operations */
+#define ILT_MEMOP_ALLOC		0
+#define ILT_MEMOP_FREE		1
+
+/* the phys address is shifted right 12 bits and has an added
+ * 1=valid bit added to the 53rd bit
+ * then since this is a wide register(TM)
+ * we split it into two 32 bit writes
+ */
+#define ILT_ADDR1(x)		((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
+#define ILT_ADDR2(x)		((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
+#define ILT_RANGE(f, l)		(((l) << 10) | f)
+
+static int ecore_ilt_line_mem_op(struct bcm_softc *sc,
+				 struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i)
+{
+#define ECORE_ILT_NAMESIZE 10
+	char str[ECORE_ILT_NAMESIZE];
+
+	if (memop == ILT_MEMOP_FREE) {
+		ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
+		return 0;
+	}
+	snprintf(str, ECORE_ILT_NAMESIZE, "ILT_%d_%d", cli_num, i);
+	ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str);
+	if (!line->page)
+		return -1;
+	line->size = size;
+	return 0;
+}
+
+
+static int ecore_ilt_client_mem_op(struct bcm_softc *sc, int cli_num,
+				   uint8_t memop)
+{
+	int i, rc = 0;
+	struct ecore_ilt *ilt = SC_ILT(sc);
+	struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
+
+	if (!ilt || !ilt->lines)
+		return -1;
+
+	if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
+		return 0;
+
+	for (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
+		rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
+					   ilt_cli->page_size, memop, cli_num, i);
+	}
+	return rc;
+}
+
+static inline int ecore_ilt_mem_op_cnic(struct bcm_softc *sc, uint8_t memop)
+{
+	int rc = 0;
+
+	if (CONFIGURE_NIC_MODE(sc))
+		rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
+	if (!rc)
+		rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
+
+	return rc;
+}
+
+static int ecore_ilt_mem_op(struct bcm_softc *sc, uint8_t memop)
+{
+	int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
+	if (!rc)
+		rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop);
+	if (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
+		rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
+
+	return rc;
+}
+
+static void ecore_ilt_line_wr(struct bcm_softc *sc, int abs_idx,
+			      ecore_dma_addr_t page_mapping)
+{
+	uint32_t reg;
+
+	reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
+
+	ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
+}
+
+static void ecore_ilt_line_init_op(struct bcm_softc *sc,
+				   struct ecore_ilt *ilt, int idx, uint8_t initop)
+{
+	ecore_dma_addr_t	null_mapping;
+	int abs_idx = ilt->start_line + idx;
+
+	switch (initop) {
+	case INITOP_INIT:
+		/* set in the init-value array */
+	case INITOP_SET:
+		ecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping);
+		break;
+	case INITOP_CLEAR:
+		null_mapping = 0;
+		ecore_ilt_line_wr(sc, abs_idx, null_mapping);
+		break;
+	}
+}
+
+static void ecore_ilt_boundry_init_op(struct bcm_softc *sc,
+				      struct ilt_client_info *ilt_cli,
+				      uint32_t ilt_start)
+{
+	uint32_t start_reg = 0;
+	uint32_t end_reg = 0;
+
+	/* The boundary is either SET or INIT,
+	   CLEAR => SET and for now SET ~~ INIT */
+
+	/* find the appropriate regs */
+	switch (ilt_cli->client_num) {
+		case ILT_CLIENT_CDU:
+			start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
+			end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
+			break;
+		case ILT_CLIENT_QM:
+			start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
+			end_reg = PXP2_REG_RQ_QM_LAST_ILT;
+			break;
+		case ILT_CLIENT_SRC:
+			start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
+			end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
+			break;
+		case ILT_CLIENT_TM:
+			start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
+			end_reg = PXP2_REG_RQ_TM_LAST_ILT;
+			break;
+	}
+	REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
+	REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
+}
+
+static void ecore_ilt_client_init_op_ilt(struct bcm_softc *sc,
+					 struct ecore_ilt *ilt,
+					 struct ilt_client_info *ilt_cli,
+					 uint8_t initop)
+{
+	int i;
+
+	if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
+		return;
+
+	for (i = ilt_cli->start; i <= ilt_cli->end; i++)
+		ecore_ilt_line_init_op(sc, ilt, i, initop);
+
+	/* init/clear the ILT boundries */
+	ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line);
+}
+
+static void ecore_ilt_client_init_op(struct bcm_softc *sc,
+				     struct ilt_client_info *ilt_cli, uint8_t initop)
+{
+	struct ecore_ilt *ilt = SC_ILT(sc);
+
+	ecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop);
+}
+
+static void ecore_ilt_client_id_init_op(struct bcm_softc *sc,
+					int cli_num, uint8_t initop)
+{
+	struct ecore_ilt *ilt = SC_ILT(sc);
+	struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
+
+	ecore_ilt_client_init_op(sc, ilt_cli, initop);
+}
+
+static inline void ecore_ilt_init_op_cnic(struct bcm_softc *sc, uint8_t initop)
+{
+	if (CONFIGURE_NIC_MODE(sc))
+		ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
+	ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
+}
+
+static void ecore_ilt_init_op(struct bcm_softc *sc, uint8_t initop)
+{
+	ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
+	ecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop);
+	if (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
+		ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
+}
+
+static void ecore_ilt_init_client_psz(struct bcm_softc *sc, int cli_num,
+				      uint32_t psz_reg, uint8_t initop)
+{
+	struct ecore_ilt *ilt = SC_ILT(sc);
+	struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
+
+	if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
+		return;
+
+	switch (initop) {
+	case INITOP_INIT:
+		/* set in the init-value array */
+	case INITOP_SET:
+		REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12));
+		break;
+	case INITOP_CLEAR:
+		break;
+	}
+}
+
+/*
+ * called during init common stage, ilt clients should be initialized
+ * prioir to calling this function
+ */
+static void ecore_ilt_init_page_size(struct bcm_softc *sc, uint8_t initop)
+{
+	ecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU,
+				  PXP2_REG_RQ_CDU_P_SIZE, initop);
+	ecore_ilt_init_client_psz(sc, ILT_CLIENT_QM,
+				  PXP2_REG_RQ_QM_P_SIZE, initop);
+	ecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC,
+				  PXP2_REG_RQ_SRC_P_SIZE, initop);
+	ecore_ilt_init_client_psz(sc, ILT_CLIENT_TM,
+				  PXP2_REG_RQ_TM_P_SIZE, initop);
+}
+
+/****************************************************************************
+* QM initializations
+****************************************************************************/
+#define QM_QUEUES_PER_FUNC	16
+#define QM_INIT_MIN_CID_COUNT	31
+#define QM_INIT(cid_cnt)	(cid_cnt > QM_INIT_MIN_CID_COUNT)
+
+/* called during init port stage */
+static void ecore_qm_init_cid_count(struct bcm_softc *sc, int qm_cid_count,
+				    uint8_t initop)
+{
+	int port = SC_PORT(sc);
+
+	if (QM_INIT(qm_cid_count)) {
+		switch (initop) {
+		case INITOP_INIT:
+			/* set in the init-value array */
+		case INITOP_SET:
+			REG_WR(sc, QM_REG_CONNNUM_0 + port*4,
+			       qm_cid_count/16 - 1);
+			break;
+		case INITOP_CLEAR:
+			break;
+		}
+	}
+}
+
+static void ecore_qm_set_ptr_table(struct bcm_softc *sc, int qm_cid_count,
+				   uint32_t base_reg, uint32_t reg)
+{
+	int i;
+	uint32_t wb_data[2] = {0, 0};
+	for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
+		REG_WR(sc, base_reg + i*4,
+		       qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
+		ecore_init_wr_wb(sc, reg + i*8,
+				 wb_data, 2);
+	}
+}
+
+/* called during init common stage */
+static void ecore_qm_init_ptr_table(struct bcm_softc *sc, int qm_cid_count,
+				    uint8_t initop)
+{
+	if (!QM_INIT(qm_cid_count))
+		return;
+
+	switch (initop) {
+	case INITOP_INIT:
+		/* set in the init-value array */
+	case INITOP_SET:
+		ecore_qm_set_ptr_table(sc, qm_cid_count,
+				       QM_REG_BASEADDR, QM_REG_PTRTBL);
+		if (CHIP_IS_E1H(sc))
+			ecore_qm_set_ptr_table(sc, qm_cid_count,
+					       QM_REG_BASEADDR_EXT_A,
+					       QM_REG_PTRTBL_EXT_A);
+		break;
+	case INITOP_CLEAR:
+		break;
+	}
+}
+
+/****************************************************************************
+* SRC initializations
+****************************************************************************/
+#ifdef ECORE_L5
+/* called during init func stage */
+static void ecore_src_init_t2(struct bcm_softc *sc, struct src_ent *t2,
+			      ecore_dma_addr_t t2_mapping, int src_cid_count)
+{
+	int i;
+	int port = SC_PORT(sc);
+
+	/* Initialize T2 */
+	for (i = 0; i < src_cid_count-1; i++)
+		t2[i].next = (uint64_t)(t2_mapping +
+			     (i+1)*sizeof(struct src_ent));
+
+	/* tell the searcher where the T2 table is */
+	REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
+
+	ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
+		    U64_LO(t2_mapping), U64_HI(t2_mapping));
+
+	ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
+		    U64_LO((uint64_t)t2_mapping +
+			   (src_cid_count-1) * sizeof(struct src_ent)),
+		    U64_HI((uint64_t)t2_mapping +
+			   (src_cid_count-1) * sizeof(struct src_ent)));
+}
+#endif
+#endif /* ECORE_INIT_OPS_H */
diff --git a/lib/librte_pmd_bcm/ecore_mfw_req.h b/lib/librte_pmd_bcm/ecore_mfw_req.h
new file mode 100644
index 0000000..5b043ce
--- /dev/null
+++ b/lib/librte_pmd_bcm/ecore_mfw_req.h
@@ -0,0 +1,207 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ECORE_MFW_REQ_H
+#define ECORE_MFW_REQ_H
+
+
+
+#define PORT_0              0
+#define PORT_1              1
+#define PORT_MAX            2
+#define NVM_PATH_MAX        2
+
+/* FCoE capabilities required from the driver */
+struct fcoe_capabilities {
+	uint32_t capability1;
+	/* Maximum number of I/Os per connection */
+	#define FCOE_IOS_PER_CONNECTION_MASK    0x0000ffff
+	#define FCOE_IOS_PER_CONNECTION_SHIFT   0
+	/* Maximum number of Logins per port */
+	#define FCOE_LOGINS_PER_PORT_MASK       0xffff0000
+	#define FCOE_LOGINS_PER_PORT_SHIFT   16
+
+	uint32_t capability2;
+	/* Maximum number of exchanges */
+	#define FCOE_NUMBER_OF_EXCHANGES_MASK   0x0000ffff
+	#define FCOE_NUMBER_OF_EXCHANGES_SHIFT  0
+	/* Maximum NPIV WWN per port */
+	#define FCOE_NPIV_WWN_PER_PORT_MASK     0xffff0000
+	#define FCOE_NPIV_WWN_PER_PORT_SHIFT    16
+
+	uint32_t capability3;
+	/* Maximum number of targets supported */
+	#define FCOE_TARGETS_SUPPORTED_MASK     0x0000ffff
+	#define FCOE_TARGETS_SUPPORTED_SHIFT    0
+	/* Maximum number of outstanding commands across all connections */
+	#define FCOE_OUTSTANDING_COMMANDS_MASK  0xffff0000
+	#define FCOE_OUTSTANDING_COMMANDS_SHIFT 16
+
+	uint32_t capability4;
+	#define FCOE_CAPABILITY4_STATEFUL      		0x00000001
+	#define FCOE_CAPABILITY4_STATELESS     		0x00000002
+	#define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID  	0x00000004
+};
+
+struct glob_ncsi_oem_data
+{
+	uint32_t driver_version;
+	uint32_t unused[3];
+	struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];
+};
+
+/* current drv_info version */
+#define DRV_INFO_CUR_VER 2
+
+/* drv_info op codes supported */
+enum drv_info_opcode {
+	ETH_STATS_OPCODE,
+	FCOE_STATS_OPCODE,
+	ISCSI_STATS_OPCODE
+};
+
+#define ETH_STAT_INFO_VERSION_LEN	12
+/*  Per PCI Function Ethernet Statistics required from the driver */
+struct eth_stats_info {
+	/* Function's Driver Version. padded to 12 */
+	char version[ETH_STAT_INFO_VERSION_LEN];
+	/* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
+	uint8_t mac_local[8];
+	uint8_t mac_add1[8];		/* Additional Programmed MAC Addr 1. */
+	uint8_t mac_add2[8];		/* Additional Programmed MAC Addr 2. */
+	uint32_t mtu_size;		/* MTU Size. Note   : Negotiated MTU */
+	uint32_t feature_flags;	/* Feature_Flags. */
+#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK		0x01
+#define FEATURE_ETH_LSO_MASK			0x02
+#define FEATURE_ETH_BOOTMODE_MASK		0x1C
+#define FEATURE_ETH_BOOTMODE_SHIFT		2
+#define FEATURE_ETH_BOOTMODE_NONE		(0x0 << 2)
+#define FEATURE_ETH_BOOTMODE_PXE		(0x1 << 2)
+#define FEATURE_ETH_BOOTMODE_ISCSI		(0x2 << 2)
+#define FEATURE_ETH_BOOTMODE_FCOE		(0x3 << 2)
+#define FEATURE_ETH_TOE_MASK			0x20
+	uint32_t lso_max_size;	/* LSO MaxOffloadSize. */
+	uint32_t lso_min_seg_cnt;	/* LSO MinSegmentCount. */
+	/* Num Offloaded Connections TCP_IPv4. */
+	uint32_t ipv4_ofld_cnt;
+	/* Num Offloaded Connections TCP_IPv6. */
+	uint32_t ipv6_ofld_cnt;
+	uint32_t promiscuous_mode;	/* Promiscuous Mode. non-zero true */
+	uint32_t txq_size;		/* TX Descriptors Queue Size */
+	uint32_t rxq_size;		/* RX Descriptors Queue Size */
+	/* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
+	uint32_t txq_avg_depth;
+	/* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
+	uint32_t rxq_avg_depth;
+	/* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
+	uint32_t iov_offload;
+	/* Number of NetQueue/VMQ Config'd. */
+	uint32_t netq_cnt;
+	uint32_t vf_cnt;		/* Num VF assigned to this PF. */
+};
+
+/*  Per PCI Function FCOE Statistics required from the driver */
+struct fcoe_stats_info {
+	uint8_t version[12];		/* Function's Driver Version. */
+	uint8_t mac_local[8];	/* Locally Admin Addr. */
+	uint8_t mac_add1[8];		/* Additional Programmed MAC Addr 1. */
+	uint8_t mac_add2[8];		/* Additional Programmed MAC Addr 2. */
+	/* QoS Priority (per 802.1p). 0-7255 */
+	uint32_t qos_priority;
+	uint32_t txq_size;		/* FCoE TX Descriptors Queue Size. */
+	uint32_t rxq_size;		/* FCoE RX Descriptors Queue Size. */
+	/* FCoE TX Descriptor Queue Avg Depth. */
+	uint32_t txq_avg_depth;
+	/* FCoE RX Descriptors Queue Avg Depth. */
+	uint32_t rxq_avg_depth;
+	uint32_t rx_frames_lo;	/* FCoE RX Frames received. */
+	uint32_t rx_frames_hi;	/* FCoE RX Frames received. */
+	uint32_t rx_bytes_lo;	/* FCoE RX Bytes received. */
+	uint32_t rx_bytes_hi;	/* FCoE RX Bytes received. */
+	uint32_t tx_frames_lo;	/* FCoE TX Frames sent. */
+	uint32_t tx_frames_hi;	/* FCoE TX Frames sent. */
+	uint32_t tx_bytes_lo;	/* FCoE TX Bytes sent. */
+	uint32_t tx_bytes_hi;	/* FCoE TX Bytes sent. */
+	uint32_t rx_fcs_errors;	/* number of receive packets with FCS errors */
+	uint32_t rx_fc_crc_errors;	/* number of FC frames with CRC errors*/
+	uint32_t fip_login_failures;	/* number of FCoE/FIP Login failures */
+};
+
+/* Per PCI  Function iSCSI Statistics required from the driver*/
+struct iscsi_stats_info {
+	uint8_t version[12];		/* Function's Driver Version. */
+	uint8_t mac_local[8];	/* Locally Admin iSCSI MAC Addr. */
+	uint8_t mac_add1[8];		/* Additional Programmed MAC Addr 1. */
+	/* QoS Priority (per 802.1p). 0-7255 */
+	uint32_t qos_priority;
+
+	uint8_t initiator_name[64];	/* iSCSI Boot Initiator Node name. */
+
+	uint8_t ww_port_name[64];	/* iSCSI World wide port name */
+
+	uint8_t boot_target_name[64];/* iSCSI Boot Target Name. */
+
+	uint8_t boot_target_ip[16];	/* iSCSI Boot Target IP. */
+	uint32_t boot_target_portal;	/* iSCSI Boot Target Portal. */
+	uint8_t boot_init_ip[16];	/* iSCSI Boot Initiator IP Address. */
+	uint32_t max_frame_size;	/* Max Frame Size. bytes */
+	uint32_t txq_size;		/* PDU TX Descriptors Queue Size. */
+	uint32_t rxq_size;		/* PDU RX Descriptors Queue Size. */
+
+	uint32_t txq_avg_depth;	/*PDU TX Descriptor Queue Avg Depth. */
+	uint32_t rxq_avg_depth;	/*PDU RX Descriptors Queue Avg Depth. */
+	uint32_t rx_pdus_lo;		/* iSCSI PDUs received. */
+	uint32_t rx_pdus_hi;		/* iSCSI PDUs received. */
+
+	uint32_t rx_bytes_lo;	/* iSCSI RX Bytes received. */
+	uint32_t rx_bytes_hi;	/* iSCSI RX Bytes received. */
+	uint32_t tx_pdus_lo;		/* iSCSI PDUs sent. */
+	uint32_t tx_pdus_hi;		/* iSCSI PDUs sent. */
+
+	uint32_t tx_bytes_lo;	/* iSCSI PDU TX Bytes sent. */
+	uint32_t tx_bytes_hi;	/* iSCSI PDU TX Bytes sent. */
+	uint32_t pcp_prior_map_tbl;	/*C-PCP to S-PCP Priority MapTable.
+				9 nibbles, the position of each nibble
+				represents the C-PCP value, the value
+				of the nibble = S-PCP value.*/
+};
+
+union drv_info_to_mcp {
+	struct eth_stats_info		ether_stat;
+	struct fcoe_stats_info		fcoe_stat;
+	struct iscsi_stats_info		iscsi_stat;
+};
+
+
+#endif /* ECORE_MFW_REQ_H */
+
diff --git a/lib/librte_pmd_bcm/ecore_reg.h b/lib/librte_pmd_bcm/ecore_reg.h
new file mode 100644
index 0000000..6f3ccee
--- /dev/null
+++ b/lib/librte_pmd_bcm/ecore_reg.h
@@ -0,0 +1,3664 @@
+/*-
+ * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
+ *
+ * Eric Davis        <edavis@broadcom.com>
+ * David Christensen <davidch@broadcom.com>
+ * Gary Zambrano     <zambrano@broadcom.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of Broadcom Corporation nor the name of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written consent.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ECORE_REG_H
+#define ECORE_REG_H
+
+
+#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \
+	(0x1<<0)
+#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \
+	(0x1<<2)
+#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \
+	(0x1<<5)
+#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \
+	(0x1<<3)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \
+	(0x1<<4)
+#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \
+	(0x1<<1)
+#define ATC_REG_ATC_INIT_DONE \
+	0x1100bcUL
+#define ATC_REG_ATC_INT_STS_CLR \
+	0x1101c0UL
+#define ATC_REG_ATC_PRTY_MASK \
+	0x1101d8UL
+#define ATC_REG_ATC_PRTY_STS_CLR \
+	0x1101d0UL
+#define BRB1_REG_BRB1_INT_MASK \
+	0x60128UL
+#define BRB1_REG_BRB1_PRTY_MASK \
+	0x60138UL
+#define BRB1_REG_BRB1_PRTY_STS_CLR \
+	0x60130UL
+#define BRB1_REG_MAC_GUARANTIED_0 \
+	0x601e8UL
+#define BRB1_REG_MAC_GUARANTIED_1 \
+	0x60240UL
+#define BRB1_REG_NUM_OF_FULL_BLOCKS \
+	0x60090UL
+#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \
+	0x60078UL
+#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \
+	0x60068UL
+#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \
+	0x60094UL
+#define CCM_REG_CCM_INT_MASK \
+	0xd01e4UL
+#define CCM_REG_CCM_PRTY_MASK \
+	0xd01f4UL
+#define CCM_REG_CCM_PRTY_STS_CLR \
+	0xd01ecUL
+#define CDU_REG_CDU_GLOBAL_PARAMS \
+	0x101020UL
+#define CDU_REG_CDU_INT_MASK \
+	0x10103cUL
+#define CDU_REG_CDU_PRTY_MASK \
+	0x10104cUL
+#define CDU_REG_CDU_PRTY_STS_CLR \
+	0x101044UL
+#define CFC_REG_AC_INIT_DONE \
+	0x104078UL
+#define CFC_REG_CAM_INIT_DONE \
+	0x10407cUL
+#define CFC_REG_CFC_INT_MASK \
+	0x104108UL
+#define CFC_REG_CFC_INT_STS_CLR \
+	0x104100UL
+#define CFC_REG_CFC_PRTY_MASK \
+	0x104118UL
+#define CFC_REG_CFC_PRTY_STS_CLR \
+	0x104110UL
+#define CFC_REG_DEBUG0 \
+	0x104050UL
+#define CFC_REG_INIT_REG \
+	0x10404cUL
+#define CFC_REG_LL_INIT_DONE \
+	0x104074UL
+#define CFC_REG_NUM_LCIDS_INSIDE_PF \
+	0x104120UL
+#define CFC_REG_STRONG_ENABLE_PF \
+	0x104128UL
+#define CFC_REG_WEAK_ENABLE_PF \
+	0x104124UL
+#define CSDM_REG_CSDM_INT_MASK_0 \
+	0xc229cUL
+#define CSDM_REG_CSDM_INT_MASK_1 \
+	0xc22acUL
+#define CSDM_REG_CSDM_PRTY_MASK \
+	0xc22bcUL
+#define CSDM_REG_CSDM_PRTY_STS_CLR \
+	0xc22b4UL
+#define CSEM_REG_CSEM_INT_MASK_0 \
+	0x200110UL
+#define CSEM_REG_CSEM_INT_MASK_1 \
+	0x200120UL
+#define CSEM_REG_CSEM_PRTY_MASK_0 \
+	0x200130UL
+#define CSEM_REG_CSEM_PRTY_MASK_1 \
+	0x200140UL
+#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \
+	0x200128UL
+#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \
+	0x200138UL
+#define CSEM_REG_FAST_MEMORY \
+	0x220000UL
+#define CSEM_REG_INT_TABLE \
+	0x200400UL
+#define CSEM_REG_PASSIVE_BUFFER \
+	0x202000UL
+#define CSEM_REG_PRAM \
+	0x240000UL
+#define CSEM_REG_VFPF_ERR_NUM \
+	0x200380UL
+#define DBG_REG_DBG_PRTY_MASK \
+	0xc0a8UL
+#define DBG_REG_DBG_PRTY_STS_CLR \
+	0xc0a0UL
+#define DMAE_REG_BACKWARD_COMP_EN \
+	0x10207cUL
+#define DMAE_REG_CMD_MEM \
+	0x102400UL
+#define DMAE_REG_DMAE_INT_MASK \
+	0x102054UL
+#define DMAE_REG_DMAE_PRTY_MASK \
+	0x102064UL
+#define DMAE_REG_DMAE_PRTY_STS_CLR \
+	0x10205cUL
+#define DMAE_REG_GO_C0 \
+	0x102080UL
+#define DMAE_REG_GO_C1 \
+	0x102084UL
+#define DMAE_REG_GO_C10 \
+	0x102088UL
+#define DMAE_REG_GO_C11 \
+	0x10208cUL
+#define DMAE_REG_GO_C12 \
+	0x102090UL
+#define DMAE_REG_GO_C13 \
+	0x102094UL
+#define DMAE_REG_GO_C14 \
+	0x102098UL
+#define DMAE_REG_GO_C15 \
+	0x10209cUL
+#define DMAE_REG_GO_C2 \
+	0x1020a0UL
+#define DMAE_REG_GO_C3 \
+	0x1020a4UL
+#define DMAE_REG_GO_C4 \
+	0x1020a8UL
+#define DMAE_REG_GO_C5 \
+	0x1020acUL
+#define DMAE_REG_GO_C6 \
+	0x1020b0UL
+#define DMAE_REG_GO_C7 \
+	0x1020b4UL
+#define DMAE_REG_GO_C8 \
+	0x1020b8UL
+#define DMAE_REG_GO_C9 \
+	0x1020bcUL
+#define DORQ_REG_DORQ_INT_MASK \
+	0x170180UL
+#define DORQ_REG_DORQ_INT_STS_CLR \
+	0x170178UL
+#define DORQ_REG_DORQ_PRTY_MASK \
+	0x170190UL
+#define DORQ_REG_DORQ_PRTY_STS_CLR \
+	0x170188UL
+#define DORQ_REG_DPM_CID_OFST \
+	0x170030UL
+#define DORQ_REG_MAX_RVFID_SIZE \
+	0x1701ecUL
+#define DORQ_REG_NORM_CID_OFST \
+	0x17002cUL
+#define DORQ_REG_PF_USAGE_CNT \
+	0x1701d0UL
+#define DORQ_REG_VF_NORM_CID_BASE \
+	0x1701a0UL
+#define DORQ_REG_VF_NORM_CID_OFST \
+	0x1701f4UL
+#define DORQ_REG_VF_NORM_CID_WND_SIZE \
+	0x1701a4UL
+#define DORQ_REG_VF_NORM_MAX_CID_COUNT \
+	0x1701e4UL
+#define DORQ_REG_VF_NORM_VF_BASE \
+	0x1701a8UL
+#define DORQ_REG_VF_TYPE_MASK_0 \
+	0x170218UL
+#define DORQ_REG_VF_TYPE_MAX_MCID_0 \
+	0x1702d8UL
+#define DORQ_REG_VF_TYPE_MIN_MCID_0 \
+	0x170298UL
+#define DORQ_REG_VF_TYPE_VALUE_0 \
+	0x170258UL
+#define DORQ_REG_VF_USAGE_CNT \
+	0x170320UL
+#define DORQ_REG_VF_USAGE_CT_LIMIT \
+	0x170340UL
+#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \
+	(0x1<<4)
+#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \
+	(0x1<<0)
+#define HC_CONFIG_0_REG_INT_LINE_EN_0 \
+	(0x1<<3)
+#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \
+	(0x1<<7)
+#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \
+	(0x1<<2)
+#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \
+	(0x1<<1)
+#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \
+	(0x1<<0)
+#define HC_REG_ATTN_MSG0_ADDR_L \
+	0x108018UL
+#define HC_REG_ATTN_MSG1_ADDR_L \
+	0x108020UL
+#define HC_REG_COMMAND_REG \
+	0x108180UL
+#define HC_REG_CONFIG_0 \
+	0x108000UL
+#define HC_REG_CONFIG_1 \
+	0x108004UL
+#define HC_REG_HC_PRTY_MASK \
+	0x1080a0UL
+#define HC_REG_HC_PRTY_STS_CLR \
+	0x108098UL
+#define HC_REG_INT_MASK \
+	0x108108UL
+#define HC_REG_LEADING_EDGE_0 \
+	0x108040UL
+#define HC_REG_MAIN_MEMORY \
+	0x108800UL
+#define HC_REG_MAIN_MEMORY_SIZE \
+	152
+#define HC_REG_TRAILING_EDGE_0 \
+	0x108044UL
+#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \
+	(0x1<<1)
+#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \
+	(0x1<<0)
+#define IGU_REG_ATTENTION_ACK_BITS \
+	0x130108UL
+#define IGU_REG_ATTN_MSG_ADDR_H \
+	0x13011cUL
+#define IGU_REG_ATTN_MSG_ADDR_L \
+	0x130120UL
+#define IGU_REG_BLOCK_CONFIGURATION \
+	0x130000UL
+#define IGU_REG_COMMAND_REG_32LSB_DATA \
+	0x130124UL
+#define IGU_REG_COMMAND_REG_CTRL \
+	0x13012cUL
+#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \
+	0x130200UL
+#define IGU_REG_IGU_PRTY_MASK \
+	0x1300a8UL
+#define IGU_REG_IGU_PRTY_STS_CLR \
+	0x1300a0UL
+#define IGU_REG_LEADING_EDGE_LATCH \
+	0x130134UL
+#define IGU_REG_MAPPING_MEMORY \
+	0x131000UL
+#define IGU_REG_MAPPING_MEMORY_SIZE \
+	136
+#define IGU_REG_PBA_STATUS_LSB \
+	0x130138UL
+#define IGU_REG_PBA_STATUS_MSB \
+	0x13013cUL
+#define IGU_REG_PCI_PF_MSIX_EN \
+	0x130144UL
+#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \
+	0x130148UL
+#define IGU_REG_PCI_PF_MSI_EN \
+	0x130140UL
+#define IGU_REG_PENDING_BITS_STATUS \
+	0x130300UL
+#define IGU_REG_PF_CONFIGURATION \
+	0x130154UL
+#define IGU_REG_PROD_CONS_MEMORY \
+	0x132000UL
+#define IGU_REG_RESET_MEMORIES \
+	0x130158UL
+#define IGU_REG_SB_INT_BEFORE_MASK_LSB \
+	0x13015cUL
+#define IGU_REG_SB_INT_BEFORE_MASK_MSB \
+	0x130160UL
+#define IGU_REG_SB_MASK_LSB \
+	0x130164UL
+#define IGU_REG_SB_MASK_MSB \
+	0x130168UL
+#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \
+	0x130800UL
+#define IGU_REG_TRAILING_EDGE_LATCH \
+	0x130104UL
+#define IGU_REG_VF_CONFIGURATION \
+	0x130170UL
+#define MCP_REG_MCPR_ACCESS_LOCK \
+	0x8009c
+#define MCP_REG_MCPR_GP_INPUTS \
+	0x800c0
+#define MCP_REG_MCPR_GP_OENABLE \
+	0x800c8
+#define MCP_REG_MCPR_GP_OUTPUTS \
+	0x800c4
+#define MCP_REG_MCPR_IMC_COMMAND \
+	0x85900
+#define MCP_REG_MCPR_IMC_DATAREG0 \
+	0x85920
+#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \
+	0x85904
+#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \
+	0x86424
+#define MCP_REG_MCPR_NVM_ADDR \
+	0x8640c
+#define MCP_REG_MCPR_NVM_CFG4 \
+	0x8642c
+#define MCP_REG_MCPR_NVM_COMMAND \
+	0x86400
+#define MCP_REG_MCPR_NVM_READ \
+	0x86410
+#define MCP_REG_MCPR_NVM_SW_ARB \
+	0x86420
+#define MCP_REG_MCPR_NVM_WRITE \
+	0x86408
+#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \
+	(0x1<<1)
+#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \
+	(0x1<<0)
+#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \
+	0xa42cUL
+#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \
+	0xa438UL
+#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \
+	0xa444UL
+#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \
+	0xa450UL
+#define MISC_REG_AEU_AFTER_INVERT_4_MCP \
+	0xa458UL
+#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \
+	0xa700UL
+#define MISC_REG_AEU_CLR_LATCH_SIGNAL \
+	0xa45cUL
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \
+	0xa06cUL
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \
+	0xa07cUL
+#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \
+	0xa08cUL
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \
+	0xa10cUL
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \
+	0xa11cUL
+#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \
+	0xa12cUL
+#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \
+	0xa078UL
+#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \
+	0xa118UL
+#define MISC_REG_AEU_ENABLE4_NIG_0 \
+	0xa0f8UL
+#define MISC_REG_AEU_ENABLE4_NIG_1 \
+	0xa198UL
+#define MISC_REG_AEU_ENABLE4_PXP_0 \
+	0xa108UL
+#define MISC_REG_AEU_ENABLE4_PXP_1 \
+	0xa1a8UL
+#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \
+	0xa688UL
+#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \
+	0xa6b0UL
+#define MISC_REG_AEU_GENERAL_ATTN_0 \
+	0xa000UL
+#define MISC_REG_AEU_GENERAL_ATTN_1 \
+	0xa004UL
+#define MISC_REG_AEU_GENERAL_ATTN_10 \
+	0xa028UL
+#define MISC_REG_AEU_GENERAL_ATTN_11 \
+	0xa02cUL
+#define MISC_REG_AEU_GENERAL_ATTN_12 \
+	0xa030UL
+#define MISC_REG_AEU_GENERAL_ATTN_2 \
+	0xa008UL
+#define MISC_REG_AEU_GENERAL_ATTN_3 \
+	0xa00cUL
+#define MISC_REG_AEU_GENERAL_ATTN_4 \
+	0xa010UL
+#define MISC_REG_AEU_GENERAL_ATTN_5 \
+	0xa014UL
+#define MISC_REG_AEU_GENERAL_ATTN_6 \
+	0xa018UL
+#define MISC_REG_AEU_GENERAL_ATTN_7 \
+	0xa01cUL
+#define MISC_REG_AEU_GENERAL_ATTN_8 \
+	0xa020UL
+#define MISC_REG_AEU_GENERAL_ATTN_9 \
+	0xa024UL
+#define MISC_REG_AEU_GENERAL_MASK \
+	0xa61cUL
+#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \
+	0xa060UL
+#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \
+	0xa064UL
+#define MISC_REG_BOND_ID \
+	0xa400UL
+#define MISC_REG_CHIP_NUM \
+	0xa408UL
+#define MISC_REG_CHIP_REV \
+	0xa40cUL
+#define MISC_REG_CHIP_TYPE \
+	0xac60UL
+#define MISC_REG_CHIP_TYPE_57811_MASK \
+	(1<<1)
+#define MISC_REG_CPMU_LP_DR_ENABLE \
+	0xa858UL
+#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \
+	0xa84cUL
+#define MISC_REG_CPMU_LP_IDLE_THR_P0 \
+	0xa8a0UL
+#define MISC_REG_CPMU_LP_MASK_ENT_P0 \
+	0xa880UL
+#define MISC_REG_CPMU_LP_MASK_EXT_P0 \
+	0xa888UL
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \
+	0xa8b8UL
+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \
+	0xa8bcUL
+#define MISC_REG_DRIVER_CONTROL_1 \
+	0xa510UL
+#define MISC_REG_DRIVER_CONTROL_7 \
+	0xa3c8UL
+#define MISC_REG_FOUR_PORT_PATH_SWAP \
+	0xa75cUL
+#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \
+	0xa738UL
+#define MISC_REG_FOUR_PORT_PORT_SWAP \
+	0xa754UL
+#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \
+	0xa734UL
+#define MISC_REG_GENERIC_CR_0 \
+	0xa460UL
+#define MISC_REG_GENERIC_CR_1 \
+	0xa464UL
+#define MISC_REG_GENERIC_POR_1 \
+	0xa474UL
+#define MISC_REG_GEN_PURP_HWG \
+	0xa9a0UL
+#define MISC_REG_GPIO \
+	0xa490UL
+#define MISC_REG_GPIO_EVENT_EN \
+	0xa2bcUL
+#define MISC_REG_GPIO_INT \
+	0xa494UL
+#define MISC_REG_GRC_RSV_ATTN \
+	0xa3c0UL
+#define MISC_REG_GRC_TIMEOUT_ATTN \
+	0xa3c4UL
+#define MISC_REG_LCPLL_E40_PWRDWN \
+	0xaa74UL
+#define MISC_REG_LCPLL_E40_RESETB_ANA \
+	0xaa78UL
+#define MISC_REG_LCPLL_E40_RESETB_DIG \
+	0xaa7cUL
+#define MISC_REG_MISC_INT_MASK \
+	0xa388UL
+#define MISC_REG_MISC_PRTY_MASK \
+	0xa398UL
+#define MISC_REG_MISC_PRTY_STS_CLR \
+	0xa390UL
+#define MISC_REG_PORT4MODE_EN \
+	0xa750UL
+#define MISC_REG_PORT4MODE_EN_OVWR \
+	0xa720UL
+#define MISC_REG_RESET_REG_1 \
+	0xa580UL
+#define MISC_REG_RESET_REG_2 \
+	0xa590UL
+#define MISC_REG_SHARED_MEM_ADDR \
+	0xa2b4UL
+#define MISC_REG_SPIO \
+	0xa4fcUL
+#define MISC_REG_SPIO_EVENT_EN \
+	0xa2b8UL
+#define MISC_REG_SPIO_INT \
+	0xa500UL
+#define MISC_REG_TWO_PORT_PATH_SWAP \
+	0xa758UL
+#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \
+	0xa72cUL
+#define MISC_REG_UNPREPARED \
+	0xa424UL
+#define MISC_REG_WC0_CTRL_PHY_ADDR \
+	0xa9ccUL
+#define MISC_REG_WC0_RESET \
+	0xac30UL
+#define MISC_REG_XMAC_CORE_PORT_MODE \
+	0xa964UL
+#define MISC_REG_XMAC_PHY_PORT_MODE \
+	0xa960UL
+#define MSTAT_REG_RX_STAT_GR64_LO \
+	0x200UL
+#define MSTAT_REG_TX_STAT_GTXPOK_LO \
+	0UL
+#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \
+	(0x1<<0)
+#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \
+	(0x1<<0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \
+	(0x1<<0)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \
+	(0x1<<9)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \
+	(0x1<<15)
+#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \
+	(0xf<<18)
+#define NIG_REG_BMAC0_IN_EN \
+	0x100acUL
+#define NIG_REG_BMAC0_OUT_EN \
+	0x100e0UL
+#define NIG_REG_BMAC0_PAUSE_OUT_EN \
+	0x10110UL
+#define NIG_REG_BMAC0_REGS_OUT_EN \
+	0x100e8UL
+#define NIG_REG_BRB0_PAUSE_IN_EN \
+	0x100c4UL
+#define NIG_REG_BRB1_PAUSE_IN_EN \
+	0x100c8UL
+#define NIG_REG_DEBUG_PACKET_LB \
+	0x10800UL
+#define NIG_REG_EGRESS_DRAIN0_MODE \
+	0x10060UL
+#define NIG_REG_EGRESS_EMAC0_OUT_EN \
+	0x10120UL
+#define NIG_REG_EGRESS_EMAC0_PORT \
+	0x10058UL
+#define NIG_REG_EMAC0_IN_EN \
+	0x100a4UL
+#define NIG_REG_EMAC0_PAUSE_OUT_EN \
+	0x10118UL
+#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \
+	0x10494UL
+#define NIG_REG_INGRESS_BMAC0_MEM \
+	0x10c00UL
+#define NIG_REG_INGRESS_BMAC1_MEM \
+	0x11000UL
+#define NIG_REG_INGRESS_EOP_LB_EMPTY \
+	0x104e0UL
+#define NIG_REG_INGRESS_EOP_LB_FIFO \
+	0x104e4UL
+#define NIG_REG_LATCH_BC_0 \
+	0x16210UL
+#define NIG_REG_LATCH_STATUS_0 \
+	0x18000UL
+#define NIG_REG_LED_10G_P0 \
+	0x10320UL
+#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \
+	0x10318UL
+#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \
+	0x10310UL
+#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \
+	0x10308UL
+#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \
+	0x102f8UL
+#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \
+	0x10300UL
+#define NIG_REG_LED_MODE_P0 \
+	0x102f0UL
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \
+	0x16070UL
+#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \
+	0x16074UL
+#define NIG_REG_LLFC_ENABLE_0 \
+	0x16208UL
+#define NIG_REG_LLFC_ENABLE_1 \
+	0x1620cUL
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \
+	0x16058UL
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \
+	0x1605cUL
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \
+	0x16060UL
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \
+	0x16064UL
+#define NIG_REG_LLFC_OUT_EN_0 \
+	0x160c8UL
+#define NIG_REG_LLFC_OUT_EN_1 \
+	0x160ccUL
+#define NIG_REG_LLH0_BRB1_DRV_MASK \
+	0x10244UL
+#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \
+	0x16048UL
+#define NIG_REG_LLH0_BRB1_NOT_MCP \
+	0x1025cUL
+#define NIG_REG_LLH0_CLS_TYPE \
+	0x16080UL
+#define NIG_REG_LLH0_FUNC_EN \
+	0x160fcUL
+#define NIG_REG_LLH0_FUNC_MEM \
+	0x16180UL
+#define NIG_REG_LLH0_FUNC_MEM_ENABLE \
+	0x16140UL
+#define NIG_REG_LLH0_FUNC_VLAN_ID \
+	0x16100UL
+#define NIG_REG_LLH0_XCM_MASK \
+	0x10130UL
+#define NIG_REG_LLH1_BRB1_NOT_MCP \
+	0x102dcUL
+#define NIG_REG_LLH1_CLS_TYPE \
+	0x16084UL
+#define NIG_REG_LLH1_FUNC_MEM \
+	0x161c0UL
+#define NIG_REG_LLH1_FUNC_MEM_ENABLE \
+	0x16160UL
+#define NIG_REG_LLH1_FUNC_MEM_SIZE \
+	16
+#define NIG_REG_LLH1_MF_MODE \
+	0x18614UL
+#define NIG_REG_LLH1_XCM_MASK \
+	0x10134UL
+#define NIG_REG_LLH_E1HOV_MODE \
+	0x160d8UL
+#define NIG_REG_LLH_MF_MODE \
+	0x16024UL
+#define NIG_REG_MASK_INTERRUPT_PORT0 \
+	0x10330UL
+#define NIG_REG_MASK_INTERRUPT_PORT1 \
+	0x10334UL
+#define NIG_REG_NIG_EMAC0_EN \
+	0x1003cUL
+#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \
+	0x10044UL
+#define NIG_REG_NIG_INT_STS_CLR_0 \
+	0x103b4UL
+#define NIG_REG_NIG_PRTY_MASK \
+	0x103dcUL
+#define NIG_REG_NIG_PRTY_MASK_0 \
+	0x183c8UL
+#define NIG_REG_NIG_PRTY_MASK_1 \
+	0x183d8UL
+#define NIG_REG_NIG_PRTY_STS_CLR \
+	0x103d4UL
+#define NIG_REG_NIG_PRTY_STS_CLR_0 \
+	0x183c0UL
+#define NIG_REG_NIG_PRTY_STS_CLR_1 \
+	0x183d0UL
+#define NIG_REG_P0_HDRS_AFTER_BASIC \
+	0x18038UL
+#define NIG_REG_P0_HWPFC_ENABLE \
+	0x18078UL
+#define NIG_REG_P0_LLH_FUNC_MEM2 \
+	0x18480UL
+#define NIG_REG_P0_MAC_IN_EN \
+	0x185acUL
+#define NIG_REG_P0_MAC_OUT_EN \
+	0x185b0UL
+#define NIG_REG_P0_MAC_PAUSE_OUT_EN \
+	0x185b4UL
+#define NIG_REG_P0_PKT_PRIORITY_TO_COS \
+	0x18054UL
+#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \
+	0x18058UL
+#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \
+	0x1805cUL
+#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \
+	0x186b0UL
+#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \
+	0x186b4UL
+#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \
+	0x186b8UL
+#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \
+	0x186bcUL
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \
+	0x180f0UL
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
+	0x18688UL
+#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
+	0x1868cUL
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \
+	0x180e8UL
+#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
+	0x180ecUL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \
+	0x1810cUL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \
+	0x18110UL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \
+	0x18114UL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \
+	0x18118UL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \
+	0x1811cUL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \
+	0x186a0UL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \
+	0x186a4UL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \
+	0x186a8UL
+#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \
+	0x186acUL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \
+	0x180f8UL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \
+	0x180fcUL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \
+	0x18100UL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \
+	0x18104UL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \
+	0x18108UL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \
+	0x18690UL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \
+	0x18694UL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \
+	0x18698UL
+#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \
+	0x1869cUL
+#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \
+	0x180f4UL
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \
+	0x180e4UL
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \
+	0x18680UL
+#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \
+	0x18684UL
+#define NIG_REG_P1_HDRS_AFTER_BASIC \
+	0x1818cUL
+#define NIG_REG_P1_HWPFC_ENABLE \
+	0x181d0UL
+#define NIG_REG_P1_LLH_FUNC_MEM2 \
+	0x184c0UL
+#define NIG_REG_P1_MAC_IN_EN \
+	0x185c0UL
+#define NIG_REG_P1_MAC_OUT_EN \
+	0x185c4UL
+#define NIG_REG_P1_MAC_PAUSE_OUT_EN \
+	0x185c8UL
+#define NIG_REG_P1_PKT_PRIORITY_TO_COS \
+	0x181a8UL
+#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \
+	0x181acUL
+#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \
+	0x181b0UL
+#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \
+	0x186f8UL
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
+	0x186e8UL
+#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
+	0x186ecUL
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \
+	0x18234UL
+#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
+	0x18238UL
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \
+	0x18258UL
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \
+	0x1825cUL
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \
+	0x18260UL
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \
+	0x18264UL
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \
+	0x18268UL
+#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \
+	0x186f4UL
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \
+	0x18244UL
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \
+	0x18248UL
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \
+	0x1824cUL
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \
+	0x18250UL
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \
+	0x18254UL
+#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \
+	0x186f0UL
+#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \
+	0x18240UL
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \
+	0x186e0UL
+#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \
+	0x186e4UL
+#define NIG_REG_PAUSE_ENABLE_0 \
+	0x160c0UL
+#define NIG_REG_PAUSE_ENABLE_1 \
+	0x160c4UL
+#define NIG_REG_PORT_SWAP \
+	0x10394UL
+#define NIG_REG_PPP_ENABLE_0 \
+	0x160b0UL
+#define NIG_REG_PPP_ENABLE_1 \
+	0x160b4UL
+#define NIG_REG_PRS_REQ_IN_EN \
+	0x100b8UL
+#define NIG_REG_SERDES0_CTRL_MD_DEVAD \
+	0x10370UL
+#define NIG_REG_SERDES0_CTRL_MD_ST \
+	0x1036cUL
+#define NIG_REG_SERDES0_CTRL_PHY_ADDR \
+	0x10374UL
+#define NIG_REG_SERDES0_STATUS_LINK_STATUS \
+	0x10578UL
+#define NIG_REG_STAT0_BRB_DISCARD \
+	0x105f0UL
+#define NIG_REG_STAT0_BRB_TRUNCATE \
+	0x105f8UL
+#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \
+	0x10750UL
+#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \
+	0x10760UL
+#define NIG_REG_STAT1_BRB_DISCARD \
+	0x10628UL
+#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \
+	0x107a0UL
+#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \
+	0x107b0UL
+#define NIG_REG_STAT2_BRB_OCTET \
+	0x107e0UL
+#define NIG_REG_STATUS_INTERRUPT_PORT0 \
+	0x10328UL
+#define NIG_REG_STRAP_OVERRIDE \
+	0x10398UL
+#define NIG_REG_XCM0_OUT_EN \
+	0x100f0UL
+#define NIG_REG_XCM1_OUT_EN \
+	0x100f4UL
+#define NIG_REG_XGXS0_CTRL_MD_DEVAD \
+	0x1033cUL
+#define NIG_REG_XGXS0_CTRL_MD_ST \
+	0x10338UL
+#define NIG_REG_XGXS0_CTRL_PHY_ADDR \
+	0x10340UL
+#define NIG_REG_XGXS0_STATUS_LINK10G \
+	0x10680UL
+#define NIG_REG_XGXS0_STATUS_LINK_STATUS \
+	0x10684UL
+#define NIG_REG_XGXS_LANE_SEL_P0 \
+	0x102e8UL
+#define NIG_REG_XGXS_SERDES0_MODE_SEL \
+	0x102e0UL
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \
+	(0x1<<0)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \
+	(0x1<<9)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \
+	(0x1<<15)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \
+	(0xf<<18)
+#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \
+	18
+#define PBF_REG_COS0_UPPER_BOUND \
+	0x15c05cUL
+#define PBF_REG_COS0_UPPER_BOUND_P0 \
+	0x15c2ccUL
+#define PBF_REG_COS0_UPPER_BOUND_P1 \
+	0x15c2e4UL
+#define PBF_REG_COS0_WEIGHT \
+	0x15c054UL
+#define PBF_REG_COS0_WEIGHT_P0 \
+	0x15c2a8UL
+#define PBF_REG_COS0_WEIGHT_P1 \
+	0x15c2c0UL
+#define PBF_REG_COS1_UPPER_BOUND \
+	0x15c060UL
+#define PBF_REG_COS1_WEIGHT \
+	0x15c058UL
+#define PBF_REG_COS1_WEIGHT_P0 \
+	0x15c2acUL
+#define PBF_REG_COS1_WEIGHT_P1 \
+	0x15c2c4UL
+#define PBF_REG_COS2_WEIGHT_P0 \
+	0x15c2b0UL
+#define PBF_REG_COS2_WEIGHT_P1 \
+	0x15c2c8UL
+#define PBF_REG_COS3_WEIGHT_P0 \
+	0x15c2b4UL
+#define PBF_REG_COS4_WEIGHT_P0 \
+	0x15c2b8UL
+#define PBF_REG_COS5_WEIGHT_P0 \
+	0x15c2bcUL
+#define PBF_REG_CREDIT_LB_Q \
+	0x140338UL
+#define PBF_REG_CREDIT_Q0 \
+	0x14033cUL
+#define PBF_REG_CREDIT_Q1 \
+	0x140340UL
+#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \
+	0x14005cUL
+#define PBF_REG_DISABLE_PF \
+	0x1402e8UL
+#define PBF_REG_DISABLE_VF \
+	0x1402ecUL
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \
+	0x15c288UL
+#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \
+	0x15c28cUL
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \
+	0x15c278UL
+#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \
+	0x15c27cUL
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \
+	0x15c280UL
+#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \
+	0x15c284UL
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \
+	0x15c2a0UL
+#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \
+	0x15c2a4UL
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \
+	0x15c270UL
+#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \
+	0x15c274UL
+#define PBF_REG_ETS_ENABLED \
+	0x15c050UL
+#define PBF_REG_HDRS_AFTER_BASIC \
+	0x15c0a8UL
+#define PBF_REG_HDRS_AFTER_TAG_0 \
+	0x15c0b8UL
+#define PBF_REG_HIGH_PRIORITY_COS_NUM \
+	0x15c04cUL
+#define PBF_REG_INIT_CRD_LB_Q \
+	0x15c248UL
+#define PBF_REG_INIT_CRD_Q0 \
+	0x15c230UL
+#define PBF_REG_INIT_CRD_Q1 \
+	0x15c234UL
+#define PBF_REG_INIT_P0 \
+	0x140004UL
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \
+	0x140354UL
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \
+	0x140358UL
+#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \
+	0x14035cUL
+#define PBF_REG_MUST_HAVE_HDRS \
+	0x15c0c4UL
+#define PBF_REG_NUM_STRICT_ARB_SLOTS \
+	0x15c064UL
+#define PBF_REG_P0_ARB_THRSH \
+	0x1400e4UL
+#define PBF_REG_P0_CREDIT \
+	0x140200UL
+#define PBF_REG_P0_INIT_CRD \
+	0x1400d0UL
+#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \
+	0x140308UL
+#define PBF_REG_P0_PAUSE_ENABLE \
+	0x140014UL
+#define PBF_REG_P0_TQ_LINES_FREED_CNT \
+	0x1402f0UL
+#define PBF_REG_P0_TQ_OCCUPANCY \
+	0x1402fcUL
+#define PBF_REG_P1_CREDIT \
+	0x140208UL
+#define PBF_REG_P1_INIT_CRD \
+	0x1400d4UL
+#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \
+	0x14030cUL
+#define PBF_REG_P1_TQ_LINES_FREED_CNT \
+	0x1402f4UL
+#define PBF_REG_P1_TQ_OCCUPANCY \
+	0x140300UL
+#define PBF_REG_P4_CREDIT \
+	0x140210UL
+#define PBF_REG_P4_INIT_CRD \
+	0x1400e0UL
+#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \
+	0x140310UL
+#define PBF_REG_P4_TQ_LINES_FREED_CNT \
+	0x1402f8UL
+#define PBF_REG_P4_TQ_OCCUPANCY \
+	0x140304UL
+#define PBF_REG_PBF_INT_MASK \
+	0x1401d4UL
+#define PBF_REG_PBF_PRTY_MASK \
+	0x1401e4UL
+#define PBF_REG_PBF_PRTY_STS_CLR \
+	0x1401dcUL
+#define PBF_REG_TAG_ETHERTYPE_0 \
+	0x15c090UL
+#define PBF_REG_TAG_LEN_0 \
+	0x15c09cUL
+#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \
+	0x14038cUL
+#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \
+	0x140390UL
+#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \
+	0x140394UL
+#define PBF_REG_TQ_OCCUPANCY_LB_Q \
+	0x1403a8UL
+#define PBF_REG_TQ_OCCUPANCY_Q0 \
+	0x1403acUL
+#define PBF_REG_TQ_OCCUPANCY_Q1 \
+	0x1403b0UL
+#define PB_REG_PB_INT_MASK \
+	0x28UL
+#define PB_REG_PB_PRTY_MASK \
+	0x38UL
+#define PB_REG_PB_PRTY_STS_CLR \
+	0x30UL
+#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \
+	(0x1<<0)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \
+	(0x1<<8)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \
+	(0x1<<1)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \
+	(0x1<<6)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \
+	(0x1<<7)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \
+	(0x1<<4)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \
+	(0x1<<3)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \
+	(0x1<<5)
+#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \
+	(0x1<<2)
+#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \
+	0x9418UL
+#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
+	0x9478UL
+#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \
+	0x947cUL
+#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \
+	0x9480UL
+#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \
+	0x9474UL
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
+	0x942cUL
+#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
+	0x9430UL
+#define PGLUE_B_REG_INTERNAL_VFID_ENABLE \
+	0x9438UL
+#define PGLUE_B_REG_PGLUE_B_INT_STS \
+	0x9298UL
+#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \
+	0x929cUL
+#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \
+	0x92b4UL
+#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \
+	0x92acUL
+#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \
+	0x9458UL
+#define PGLUE_B_REG_TAGS_63_32 \
+	0x9244UL
+#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \
+	0x9470UL
+#define PRS_REG_A_PRSU_20 \
+	0x40134UL
+#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \
+	0x4011cUL
+#define PRS_REG_E1HOV_MODE \
+	0x401c8UL
+#define PRS_REG_HDRS_AFTER_BASIC \
+	0x40238UL
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \
+	0x40270UL
+#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \
+	0x40290UL
+#define PRS_REG_HDRS_AFTER_TAG_0 \
+	0x40248UL
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \
+	0x40280UL
+#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \
+	0x402a0UL
+#define PRS_REG_MUST_HAVE_HDRS \
+	0x40254UL
+#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \
+	0x4028cUL
+#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \
+	0x402acUL
+#define PRS_REG_NIC_MODE \
+	0x40138UL
+#define PRS_REG_NUM_OF_PACKETS \
+	0x40124UL
+#define PRS_REG_PRS_PRTY_MASK \
+	0x401a4UL
+#define PRS_REG_PRS_PRTY_STS_CLR \
+	0x4019cUL
+#define PRS_REG_TAG_ETHERTYPE_0 \
+	0x401d4UL
+#define PRS_REG_TAG_LEN_0 \
+	0x4022cUL
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \
+	(0x1<<19)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \
+	(0x1<<20)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \
+	(0x1<<22)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \
+	(0x1<<23)
+#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \
+	(0x1<<24)
+#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \
+	(0x1<<7)
+#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \
+	(0x1<<7)
+#define PXP2_REG_PGL_ADDR_88_F0 \
+	0x120534UL
+#define PXP2_REG_PGL_ADDR_88_F1 \
+	0x120544UL
+#define PXP2_REG_PGL_ADDR_8C_F0 \
+	0x120538UL
+#define PXP2_REG_PGL_ADDR_8C_F1 \
+	0x120548UL
+#define PXP2_REG_PGL_ADDR_90_F0 \
+	0x12053cUL
+#define PXP2_REG_PGL_ADDR_90_F1 \
+	0x12054cUL
+#define PXP2_REG_PGL_ADDR_94_F0 \
+	0x120540UL
+#define PXP2_REG_PGL_ADDR_94_F1 \
+	0x120550UL
+#define PXP2_REG_PGL_EXP_ROM2 \
+	0x120808UL
+#define PXP2_REG_PGL_PRETEND_FUNC_F0 \
+	0x120674UL
+#define PXP2_REG_PGL_PRETEND_FUNC_F1 \
+	0x120678UL
+#define PXP2_REG_PGL_TAGS_LIMIT \
+	0x1205a8UL
+#define PXP2_REG_PSWRQ_BW_ADD1 \
+	0x1201c0UL
+#define PXP2_REG_PSWRQ_BW_ADD10 \
+	0x1201e4UL
+#define PXP2_REG_PSWRQ_BW_ADD11 \
+	0x1201e8UL
+#define PXP2_REG_PSWRQ_BW_ADD2 \
+	0x1201c4UL
+#define PXP2_REG_PSWRQ_BW_ADD28 \
+	0x120228UL
+#define PXP2_REG_PSWRQ_BW_ADD3 \
+	0x1201c8UL
+#define PXP2_REG_PSWRQ_BW_ADD6 \
+	0x1201d4UL
+#define PXP2_REG_PSWRQ_BW_ADD7 \
+	0x1201d8UL
+#define PXP2_REG_PSWRQ_BW_ADD8 \
+	0x1201dcUL
+#define PXP2_REG_PSWRQ_BW_ADD9 \
+	0x1201e0UL
+#define PXP2_REG_PSWRQ_BW_L1 \
+	0x1202b0UL
+#define PXP2_REG_PSWRQ_BW_L10 \
+	0x1202d4UL
+#define PXP2_REG_PSWRQ_BW_L11 \
+	0x1202d8UL
+#define PXP2_REG_PSWRQ_BW_L2 \
+	0x1202b4UL
+#define PXP2_REG_PSWRQ_BW_L28 \
+	0x120318UL
+#define PXP2_REG_PSWRQ_BW_L3 \
+	0x1202b8UL
+#define PXP2_REG_PSWRQ_BW_L6 \
+	0x1202c4UL
+#define PXP2_REG_PSWRQ_BW_L7 \
+	0x1202c8UL
+#define PXP2_REG_PSWRQ_BW_L8 \
+	0x1202ccUL
+#define PXP2_REG_PSWRQ_BW_L9 \
+	0x1202d0UL
+#define PXP2_REG_PSWRQ_BW_RD \
+	0x120324UL
+#define PXP2_REG_PSWRQ_BW_UB1 \
+	0x120238UL
+#define PXP2_REG_PSWRQ_BW_UB10 \
+	0x12025cUL
+#define PXP2_REG_PSWRQ_BW_UB11 \
+	0x120260UL
+#define PXP2_REG_PSWRQ_BW_UB2 \
+	0x12023cUL
+#define PXP2_REG_PSWRQ_BW_UB28 \
+	0x1202a0UL
+#define PXP2_REG_PSWRQ_BW_UB3 \
+	0x120240UL
+#define PXP2_REG_PSWRQ_BW_UB6 \
+	0x12024cUL
+#define PXP2_REG_PSWRQ_BW_UB7 \
+	0x120250UL
+#define PXP2_REG_PSWRQ_BW_UB8 \
+	0x120254UL
+#define PXP2_REG_PSWRQ_BW_UB9 \
+	0x120258UL
+#define PXP2_REG_PSWRQ_BW_WR \
+	0x120328UL
+#define PXP2_REG_PSWRQ_CDU0_L2P \
+	0x120000UL
+#define PXP2_REG_PSWRQ_QM0_L2P \
+	0x120038UL
+#define PXP2_REG_PSWRQ_SRC0_L2P \
+	0x120054UL
+#define PXP2_REG_PSWRQ_TM0_L2P \
+	0x12001cUL
+#define PXP2_REG_PXP2_INT_MASK_0 \
+	0x120578UL
+#define PXP2_REG_PXP2_INT_MASK_1 \
+	0x120614UL
+#define PXP2_REG_PXP2_INT_STS_0 \
+	0x12056cUL
+#define PXP2_REG_PXP2_INT_STS_1 \
+	0x120608UL
+#define PXP2_REG_PXP2_INT_STS_CLR_0 \
+	0x120570UL
+#define PXP2_REG_PXP2_PRTY_MASK_0 \
+	0x120588UL
+#define PXP2_REG_PXP2_PRTY_MASK_1 \
+	0x120598UL
+#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \
+	0x120580UL
+#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \
+	0x120590UL
+#define PXP2_REG_RD_BLK_CNT \
+	0x120418UL
+#define PXP2_REG_RD_CDURD_SWAP_MODE \
+	0x120404UL
+#define PXP2_REG_RD_DISABLE_INPUTS \
+	0x120374UL
+#define PXP2_REG_RD_INIT_DONE \
+	0x120370UL
+#define PXP2_REG_RD_PBF_SWAP_MODE \
+	0x1203f4UL
+#define PXP2_REG_RD_PORT_IS_IDLE_0 \
+	0x12041cUL
+#define PXP2_REG_RD_PORT_IS_IDLE_1 \
+	0x120420UL
+#define PXP2_REG_RD_QM_SWAP_MODE \
+	0x1203f8UL
+#define PXP2_REG_RD_SRC_SWAP_MODE \
+	0x120400UL
+#define PXP2_REG_RD_SR_CNT \
+	0x120414UL
+#define PXP2_REG_RD_START_INIT \
+	0x12036cUL
+#define PXP2_REG_RD_TM_SWAP_MODE \
+	0x1203fcUL
+#define PXP2_REG_RQ_BW_RD_ADD0 \
+	0x1201bcUL
+#define PXP2_REG_RQ_BW_RD_ADD12 \
+	0x1201ecUL
+#define PXP2_REG_RQ_BW_RD_ADD13 \
+	0x1201f0UL
+#define PXP2_REG_RQ_BW_RD_ADD14 \
+	0x1201f4UL
+#define PXP2_REG_RQ_BW_RD_ADD15 \
+	0x1201f8UL
+#define PXP2_REG_RQ_BW_RD_ADD16 \
+	0x1201fcUL
+#define PXP2_REG_RQ_BW_RD_ADD17 \
+	0x120200UL
+#define PXP2_REG_RQ_BW_RD_ADD18 \
+	0x120204UL
+#define PXP2_REG_RQ_BW_RD_ADD19 \
+	0x120208UL
+#define PXP2_REG_RQ_BW_RD_ADD20 \
+	0x12020cUL
+#define PXP2_REG_RQ_BW_RD_ADD22 \
+	0x120210UL
+#define PXP2_REG_RQ_BW_RD_ADD23 \
+	0x120214UL
+#define PXP2_REG_RQ_BW_RD_ADD24 \
+	0x120218UL
+#define PXP2_REG_RQ_BW_RD_ADD25 \
+	0x12021cUL
+#define PXP2_REG_RQ_BW_RD_ADD26 \
+	0x120220UL
+#define PXP2_REG_RQ_BW_RD_ADD27 \
+	0x120224UL
+#define PXP2_REG_RQ_BW_RD_ADD4 \
+	0x1201ccUL
+#define PXP2_REG_RQ_BW_RD_ADD5 \
+	0x1201d0UL
+#define PXP2_REG_RQ_BW_RD_L0 \
+	0x1202acUL
+#define PXP2_REG_RQ_BW_RD_L12 \
+	0x1202dcUL
+#define PXP2_REG_RQ_BW_RD_L13 \
+	0x1202e0UL
+#define PXP2_REG_RQ_BW_RD_L14 \
+	0x1202e4UL
+#define PXP2_REG_RQ_BW_RD_L15 \
+	0x1202e8UL
+#define PXP2_REG_RQ_BW_RD_L16 \
+	0x1202ecUL
+#define PXP2_REG_RQ_BW_RD_L17 \
+	0x1202f0UL
+#define PXP2_REG_RQ_BW_RD_L18 \
+	0x1202f4UL
+#define PXP2_REG_RQ_BW_RD_L19 \
+	0x1202f8UL
+#define PXP2_REG_RQ_BW_RD_L20 \
+	0x1202fcUL
+#define PXP2_REG_RQ_BW_RD_L22 \
+	0x120300UL
+#define PXP2_REG_RQ_BW_RD_L23 \
+	0x120304UL
+#define PXP2_REG_RQ_BW_RD_L24 \
+	0x120308UL
+#define PXP2_REG_RQ_BW_RD_L25 \
+	0x12030cUL
+#define PXP2_REG_RQ_BW_RD_L26 \
+	0x120310UL
+#define PXP2_REG_RQ_BW_RD_L27 \
+	0x120314UL
+#define PXP2_REG_RQ_BW_RD_L4 \
+	0x1202bcUL
+#define PXP2_REG_RQ_BW_RD_L5 \
+	0x1202c0UL
+#define PXP2_REG_RQ_BW_RD_UBOUND0 \
+	0x120234UL
+#define PXP2_REG_RQ_BW_RD_UBOUND12 \
+	0x120264UL
+#define PXP2_REG_RQ_BW_RD_UBOUND13 \
+	0x120268UL
+#define PXP2_REG_RQ_BW_RD_UBOUND14 \
+	0x12026cUL
+#define PXP2_REG_RQ_BW_RD_UBOUND15 \
+	0x120270UL
+#define PXP2_REG_RQ_BW_RD_UBOUND16 \
+	0x120274UL
+#define PXP2_REG_RQ_BW_RD_UBOUND17 \
+	0x120278UL
+#define PXP2_REG_RQ_BW_RD_UBOUND18 \
+	0x12027cUL
+#define PXP2_REG_RQ_BW_RD_UBOUND19 \
+	0x120280UL
+#define PXP2_REG_RQ_BW_RD_UBOUND20 \
+	0x120284UL
+#define PXP2_REG_RQ_BW_RD_UBOUND22 \
+	0x120288UL
+#define PXP2_REG_RQ_BW_RD_UBOUND23 \
+	0x12028cUL
+#define PXP2_REG_RQ_BW_RD_UBOUND24 \
+	0x120290UL
+#define PXP2_REG_RQ_BW_RD_UBOUND25 \
+	0x120294UL
+#define PXP2_REG_RQ_BW_RD_UBOUND26 \
+	0x120298UL
+#define PXP2_REG_RQ_BW_RD_UBOUND27 \
+	0x12029cUL
+#define PXP2_REG_RQ_BW_RD_UBOUND4 \
+	0x120244UL
+#define PXP2_REG_RQ_BW_RD_UBOUND5 \
+	0x120248UL
+#define PXP2_REG_RQ_BW_WR_ADD29 \
+	0x12022cUL
+#define PXP2_REG_RQ_BW_WR_ADD30 \
+	0x120230UL
+#define PXP2_REG_RQ_BW_WR_L29 \
+	0x12031cUL
+#define PXP2_REG_RQ_BW_WR_L30 \
+	0x120320UL
+#define PXP2_REG_RQ_BW_WR_UBOUND29 \
+	0x1202a4UL
+#define PXP2_REG_RQ_BW_WR_UBOUND30 \
+	0x1202a8UL
+#define PXP2_REG_RQ_CDU_ENDIAN_M \
+	0x1201a0UL
+#define PXP2_REG_RQ_CDU_FIRST_ILT \
+	0x12061cUL
+#define PXP2_REG_RQ_CDU_LAST_ILT \
+	0x120620UL
+#define PXP2_REG_RQ_CDU_P_SIZE \
+	0x120018UL
+#define PXP2_REG_RQ_CFG_DONE \
+	0x1201b4UL
+#define PXP2_REG_RQ_DBG_ENDIAN_M \
+	0x1201a4UL
+#define PXP2_REG_RQ_DISABLE_INPUTS \
+	0x120330UL
+#define PXP2_REG_RQ_DRAM_ALIGN \
+	0x1205b0UL
+#define PXP2_REG_RQ_DRAM_ALIGN_RD \
+	0x12092cUL
+#define PXP2_REG_RQ_DRAM_ALIGN_SEL \
+	0x120930UL
+#define PXP2_REG_RQ_HC_ENDIAN_M \
+	0x1201a8UL
+#define PXP2_REG_RQ_ONCHIP_AT \
+	0x122000UL
+#define PXP2_REG_RQ_ONCHIP_AT_B0 \
+	0x128000UL
+#define PXP2_REG_RQ_PDR_LIMIT \
+	0x12033cUL
+#define PXP2_REG_RQ_QM_ENDIAN_M \
+	0x120194UL
+#define PXP2_REG_RQ_QM_FIRST_ILT \
+	0x120634UL
+#define PXP2_REG_RQ_QM_LAST_ILT \
+	0x120638UL
+#define PXP2_REG_RQ_QM_P_SIZE \
+	0x120050UL
+#define PXP2_REG_RQ_RBC_DONE \
+	0x1201b0UL
+#define PXP2_REG_RQ_RD_MBS0 \
+	0x120160UL
+#define PXP2_REG_RQ_RD_MBS1 \
+	0x120168UL
+#define PXP2_REG_RQ_SRC_ENDIAN_M \
+	0x12019cUL
+#define PXP2_REG_RQ_SRC_FIRST_ILT \
+	0x12063cUL
+#define PXP2_REG_RQ_SRC_LAST_ILT \
+	0x120640UL
+#define PXP2_REG_RQ_SRC_P_SIZE \
+	0x12006cUL
+#define PXP2_REG_RQ_TM_ENDIAN_M \
+	0x120198UL
+#define PXP2_REG_RQ_TM_FIRST_ILT \
+	0x120644UL
+#define PXP2_REG_RQ_TM_LAST_ILT \
+	0x120648UL
+#define PXP2_REG_RQ_TM_P_SIZE \
+	0x120034UL
+#define PXP2_REG_RQ_WR_MBS0 \
+	0x12015cUL
+#define PXP2_REG_RQ_WR_MBS1 \
+	0x120164UL
+#define PXP2_REG_WR_CDU_MPS \
+	0x1205f0UL
+#define PXP2_REG_WR_CSDM_MPS \
+	0x1205d0UL
+#define PXP2_REG_WR_DBG_MPS \
+	0x1205e8UL
+#define PXP2_REG_WR_DMAE_MPS \
+	0x1205ecUL
+#define PXP2_REG_WR_HC_MPS \
+	0x1205c8UL
+#define PXP2_REG_WR_QM_MPS \
+	0x1205dcUL
+#define PXP2_REG_WR_SRC_MPS \
+	0x1205e4UL
+#define PXP2_REG_WR_TM_MPS \
+	0x1205e0UL
+#define PXP2_REG_WR_TSDM_MPS \
+	0x1205d4UL
+#define PXP2_REG_WR_USDMDP_TH \
+	0x120348UL
+#define PXP2_REG_WR_USDM_MPS \
+	0x1205ccUL
+#define PXP2_REG_WR_XSDM_MPS \
+	0x1205d8UL
+#define PXP_REG_HST_DISCARD_DOORBELLS \
+	0x1030a4UL
+#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \
+	0x1030a8UL
+#define PXP_REG_HST_ZONE_PERMISSION_TABLE \
+	0x103400UL
+#define PXP_REG_PXP_INT_MASK_0 \
+	0x103074UL
+#define PXP_REG_PXP_INT_MASK_1 \
+	0x103084UL
+#define PXP_REG_PXP_INT_STS_CLR_0 \
+	0x10306cUL
+#define PXP_REG_PXP_INT_STS_CLR_1 \
+	0x10307cUL
+#define PXP_REG_PXP_PRTY_MASK \
+	0x103094UL
+#define PXP_REG_PXP_PRTY_STS_CLR \
+	0x10308cUL
+#define QM_REG_BASEADDR \
+	0x168900UL
+#define QM_REG_BASEADDR_EXT_A \
+	0x16e100UL
+#define QM_REG_BYTECRDCMDQ_0 \
+	0x16e6e8UL
+#define QM_REG_CONNNUM_0 \
+	0x168020UL
+#define QM_REG_PF_EN \
+	0x16e70cUL
+#define QM_REG_PF_USG_CNT_0 \
+	0x16e040UL
+#define QM_REG_PTRTBL \
+	0x168a00UL
+#define QM_REG_PTRTBL_EXT_A \
+	0x16e200UL
+#define QM_REG_QM_INT_MASK \
+	0x168444UL
+#define QM_REG_QM_PRTY_MASK \
+	0x168454UL
+#define QM_REG_QM_PRTY_STS_CLR \
+	0x16844cUL
+#define QM_REG_QVOQIDX_0 \
+	0x1680f4UL
+#define QM_REG_SOFT_RESET \
+	0x168428UL
+#define QM_REG_VOQQMASK_0_LSB \
+	0x168240UL
+#define SEM_FAST_REG_PARITY_RST \
+	0x18840UL
+#define SRC_REG_COUNTFREE0 \
+	0x40500UL
+#define SRC_REG_FIRSTFREE0 \
+	0x40510UL
+#define SRC_REG_KEYSEARCH_0 \
+	0x40458UL
+#define SRC_REG_KEYSEARCH_1 \
+	0x4045cUL
+#define SRC_REG_KEYSEARCH_2 \
+	0x40460UL
+#define SRC_REG_KEYSEARCH_3 \
+	0x40464UL
+#define SRC_REG_KEYSEARCH_4 \
+	0x40468UL
+#define SRC_REG_KEYSEARCH_5 \
+	0x4046cUL
+#define SRC_REG_KEYSEARCH_6 \
+	0x40470UL
+#define SRC_REG_KEYSEARCH_7 \
+	0x40474UL
+#define SRC_REG_KEYSEARCH_8 \
+	0x40478UL
+#define SRC_REG_KEYSEARCH_9 \
+	0x4047cUL
+#define SRC_REG_LASTFREE0 \
+	0x40530UL
+#define SRC_REG_NUMBER_HASH_BITS0 \
+	0x40400UL
+#define SRC_REG_SOFT_RST \
+	0x4049cUL
+#define SRC_REG_SRC_PRTY_MASK \
+	0x404c8UL
+#define SRC_REG_SRC_PRTY_STS_CLR \
+	0x404c0UL
+#define TCM_REG_PRS_IFEN \
+	0x50020UL
+#define TCM_REG_TCM_INT_MASK \
+	0x501dcUL
+#define TCM_REG_TCM_PRTY_MASK \
+	0x501ecUL
+#define TCM_REG_TCM_PRTY_STS_CLR \
+	0x501e4UL
+#define TM_REG_EN_LINEAR0_TIMER \
+	0x164014UL
+#define TM_REG_LIN0_MAX_ACTIVE_CID \
+	0x164048UL
+#define TM_REG_LIN0_NUM_SCANS \
+	0x1640a0UL
+#define TM_REG_LIN0_SCAN_ON \
+	0x1640d0UL
+#define TM_REG_LIN0_SCAN_TIME \
+	0x16403cUL
+#define TM_REG_LIN0_VNIC_UC \
+	0x164128UL
+#define TM_REG_TM_INT_MASK \
+	0x1640fcUL
+#define TM_REG_TM_PRTY_MASK \
+	0x16410cUL
+#define TM_REG_TM_PRTY_STS_CLR \
+	0x164104UL
+#define TSDM_REG_ENABLE_IN1 \
+	0x42238UL
+#define TSDM_REG_TSDM_INT_MASK_0 \
+	0x4229cUL
+#define TSDM_REG_TSDM_INT_MASK_1 \
+	0x422acUL
+#define TSDM_REG_TSDM_PRTY_MASK \
+	0x422bcUL
+#define TSDM_REG_TSDM_PRTY_STS_CLR \
+	0x422b4UL
+#define TSEM_REG_FAST_MEMORY \
+	0x1a0000UL
+#define TSEM_REG_INT_TABLE \
+	0x180400UL
+#define TSEM_REG_PASSIVE_BUFFER \
+	0x181000UL
+#define TSEM_REG_PRAM \
+	0x1c0000UL
+#define TSEM_REG_TSEM_INT_MASK_0 \
+	0x180100UL
+#define TSEM_REG_TSEM_INT_MASK_1 \
+	0x180110UL
+#define TSEM_REG_TSEM_PRTY_MASK_0 \
+	0x180120UL
+#define TSEM_REG_TSEM_PRTY_MASK_1 \
+	0x180130UL
+#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \
+	0x180118UL
+#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \
+	0x180128UL
+#define TSEM_REG_VFPF_ERR_NUM \
+	0x180380UL
+#define UCM_REG_UCM_INT_MASK \
+	0xe01d4UL
+#define UCM_REG_UCM_PRTY_MASK \
+	0xe01e4UL
+#define UCM_REG_UCM_PRTY_STS_CLR \
+	0xe01dcUL
+#define UMAC_COMMAND_CONFIG_REG_HD_ENA \
+	(0x1<<10)
+#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \
+	(0x1<<28)
+#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \
+	(0x1<<15)
+#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \
+	(0x1<<24)
+#define UMAC_COMMAND_CONFIG_REG_PAD_EN \
+	(0x1<<5)
+#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \
+	(0x1<<8)
+#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \
+	(0x1<<4)
+#define UMAC_COMMAND_CONFIG_REG_RX_ENA \
+	(0x1<<1)
+#define UMAC_COMMAND_CONFIG_REG_SW_RESET \
+	(0x1<<13)
+#define UMAC_COMMAND_CONFIG_REG_TX_ENA \
+	(0x1<<0)
+#define UMAC_REG_COMMAND_CONFIG \
+	0x8UL
+#define UMAC_REG_EEE_WAKE_TIMER \
+	0x6cUL
+#define UMAC_REG_MAC_ADDR0 \
+	0xcUL
+#define UMAC_REG_MAC_ADDR1 \
+	0x10UL
+#define UMAC_REG_MAXFR \
+	0x14UL
+#define UMAC_REG_UMAC_EEE_CTRL \
+	0x64UL
+#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \
+	(0x1<<3)
+#define USDM_REG_USDM_INT_MASK_0 \
+	0xc42a0UL
+#define USDM_REG_USDM_INT_MASK_1 \
+	0xc42b0UL
+#define USDM_REG_USDM_PRTY_MASK \
+	0xc42c0UL
+#define USDM_REG_USDM_PRTY_STS_CLR \
+	0xc42b8UL
+#define USEM_REG_FAST_MEMORY \
+	0x320000UL
+#define USEM_REG_INT_TABLE \
+	0x300400UL
+#define USEM_REG_PASSIVE_BUFFER \
+	0x302000UL
+#define USEM_REG_PRAM \
+	0x340000UL
+#define USEM_REG_USEM_INT_MASK_0 \
+	0x300110UL
+#define USEM_REG_USEM_INT_MASK_1 \
+	0x300120UL
+#define USEM_REG_USEM_PRTY_MASK_0 \
+	0x300130UL
+#define USEM_REG_USEM_PRTY_MASK_1 \
+	0x300140UL
+#define USEM_REG_USEM_PRTY_STS_CLR_0 \
+	0x300128UL
+#define USEM_REG_USEM_PRTY_STS_CLR_1 \
+	0x300138UL
+#define USEM_REG_VFPF_ERR_NUM \
+	0x300380UL
+#define VFC_MEMORIES_RST_REG_CAM_RST \
+	(0x1<<0)
+#define VFC_MEMORIES_RST_REG_RAM_RST \
+	(0x1<<1)
+#define VFC_REG_MEMORIES_RST \
+	0x1943cUL
+#define XCM_REG_XCM_INT_MASK \
+	0x202b4UL
+#define XCM_REG_XCM_PRTY_MASK \
+	0x202c4UL
+#define XCM_REG_XCM_PRTY_STS_CLR \
+	0x202bcUL
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \
+	(0x1<<0)
+#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \
+	(0x1<<1)
+#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \
+	(0x1<<2)
+#define XMAC_CTRL_REG_RX_EN \
+	(0x1<<1)
+#define XMAC_CTRL_REG_SOFT_RESET \
+	(0x1<<6)
+#define XMAC_CTRL_REG_TX_EN \
+	(0x1<<0)
+#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \
+	(0x1<<7)
+#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \
+	(0x1<<18)
+#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \
+	(0x1<<17)
+#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \
+	(0x1<<1)
+#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \
+	(0x1<<0)
+#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \
+	(0x1<<3)
+#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \
+	(0x1<<4)
+#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \
+	(0x1<<5)
+#define XMAC_REG_CLEAR_RX_LSS_STATUS \
+	0x60UL
+#define XMAC_REG_CTRL \
+	0UL
+#define XMAC_REG_CTRL_SA_HI \
+	0x2cUL
+#define XMAC_REG_CTRL_SA_LO \
+	0x28UL
+#define XMAC_REG_EEE_CTRL \
+	0xd8UL
+#define XMAC_REG_EEE_TIMERS_HI \
+	0xe4UL
+#define XMAC_REG_PAUSE_CTRL \
+	0x68UL
+#define XMAC_REG_PFC_CTRL \
+	0x70UL
+#define XMAC_REG_PFC_CTRL_HI \
+	0x74UL
+#define XMAC_REG_RX_LSS_CTRL \
+	0x50UL
+#define XMAC_REG_RX_LSS_STATUS \
+	0x58UL
+#define XMAC_REG_RX_MAX_SIZE \
+	0x40UL
+#define XMAC_REG_TX_CTRL \
+	0x20UL
+#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \
+	(0x1<<0)
+#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \
+	(0x1<<1)
+#define XSDM_REG_OPERATION_GEN \
+	0x1664c4UL
+#define XSDM_REG_XSDM_INT_MASK_0 \
+	0x16629cUL
+#define XSDM_REG_XSDM_INT_MASK_1 \
+	0x1662acUL
+#define XSDM_REG_XSDM_PRTY_MASK \
+	0x1662bcUL
+#define XSDM_REG_XSDM_PRTY_STS_CLR \
+	0x1662b4UL
+#define XSEM_REG_FAST_MEMORY \
+	0x2a0000UL
+#define XSEM_REG_INT_TABLE \
+	0x280400UL
+#define XSEM_REG_PASSIVE_BUFFER \
+	0x282000UL
+#define XSEM_REG_PRAM \
+	0x2c0000UL
+#define XSEM_REG_VFPF_ERR_NUM \
+	0x280380UL
+#define XSEM_REG_XSEM_INT_MASK_0 \
+	0x280110UL
+#define XSEM_REG_XSEM_INT_MASK_1 \
+	0x280120UL
+#define XSEM_REG_XSEM_PRTY_MASK_0 \
+	0x280130UL
+#define XSEM_REG_XSEM_PRTY_MASK_1 \
+	0x280140UL
+#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \
+	0x280128UL
+#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \
+	0x280138UL
+#define MCPR_ACCESS_LOCK_LOCK			     (1L<<31)
+#define MCPR_IMC_COMMAND_ENABLE			    (1L<<31)
+#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT	    16
+#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT	    28
+#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT  8
+#define MCPR_NVM_ACCESS_ENABLE_EN		     (1L<<0)
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN		     (1L<<1)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE		     (0xffffffL<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE		     (0x7L<<0)
+#define MCPR_NVM_COMMAND_DOIT			     (1L<<4)
+#define MCPR_NVM_COMMAND_DONE			     (1L<<3)
+#define MCPR_NVM_COMMAND_FIRST			     (1L<<7)
+#define MCPR_NVM_COMMAND_LAST			     (1L<<8)
+#define MCPR_NVM_COMMAND_WR			     (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_ARB1		     (1L<<9)
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1		     (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1		     (1L<<1)
+
+
+#define BIGMAC_REGISTER_BMAC_CONTROL	    (0x00<<3)
+#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL   (0x01<<3)
+#define BIGMAC_REGISTER_CNT_MAX_SIZE	    (0x05<<3)
+#define BIGMAC_REGISTER_RX_CONTROL	    (0x21<<3)
+#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS    (0x46<<3)
+#define BIGMAC_REGISTER_RX_LSS_STATUS	    (0x43<<3)
+#define BIGMAC_REGISTER_RX_MAX_SIZE	    (0x23<<3)
+#define BIGMAC_REGISTER_RX_STAT_GR64	    (0x26<<3)
+#define BIGMAC_REGISTER_RX_STAT_GRIPJ	    (0x42<<3)
+#define BIGMAC_REGISTER_TX_CONTROL	    (0x07<<3)
+#define BIGMAC_REGISTER_TX_MAX_SIZE	    (0x09<<3)
+#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD  (0x0A<<3)
+#define BIGMAC_REGISTER_TX_SOURCE_ADDR	    (0x08<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTBYT	    (0x20<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTPKT	    (0x0C<<3)
+#define BIGMAC2_REGISTER_BMAC_CONTROL	    (0x00<<3)
+#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL  (0x01<<3)
+#define BIGMAC2_REGISTER_CNT_MAX_SIZE	    (0x05<<3)
+#define BIGMAC2_REGISTER_PFC_CONTROL	    (0x06<<3)
+#define BIGMAC2_REGISTER_RX_CONTROL	    (0x3A<<3)
+#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS   (0x62<<3)
+#define BIGMAC2_REGISTER_RX_LSS_STAT	    (0x3E<<3)
+#define BIGMAC2_REGISTER_RX_MAX_SIZE	    (0x3C<<3)
+#define BIGMAC2_REGISTER_RX_STAT_GR64	    (0x40<<3)
+#define BIGMAC2_REGISTER_RX_STAT_GRIPJ	    (0x5f<<3)
+#define BIGMAC2_REGISTER_TX_CONTROL	    (0x1C<<3)
+#define BIGMAC2_REGISTER_TX_MAX_SIZE	    (0x1E<<3)
+#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL   (0x20<<3)
+#define BIGMAC2_REGISTER_TX_SOURCE_ADDR	    (0x1D<<3)
+#define BIGMAC2_REGISTER_TX_STAT_GTBYT	    (0x39<<3)
+#define BIGMAC2_REGISTER_TX_STAT_GTPOK	    (0x22<<3)
+
+
+#define EMAC_LED_1000MB_OVERRIDE		   (1L<<1)
+#define EMAC_LED_100MB_OVERRIDE			   (1L<<2)
+#define EMAC_LED_10MB_OVERRIDE			   (1L<<3)
+#define EMAC_LED_OVERRIDE			   (1L<<0)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS	       (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22	       (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45	       (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22	       (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45	       (1L<<26)
+#define EMAC_MDIO_COMM_DATA			   (0xffffL<<0)
+#define EMAC_MDIO_COMM_START_BUSY		   (1L<<29)
+#define EMAC_MDIO_MODE_AUTO_POLL		   (1L<<4)
+#define EMAC_MDIO_MODE_CLAUSE_45		   (1L<<31)
+#define EMAC_MDIO_MODE_CLOCK_CNT		   (0x3ffL<<16)
+#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT	   16
+#define EMAC_MDIO_STATUS_10MB			   (1L<<1)
+#define EMAC_MODE_25G_MODE			   (1L<<5)
+#define EMAC_MODE_HALF_DUPLEX			   (1L<<1)
+#define EMAC_MODE_PORT_GMII		       (2L<<2)
+#define EMAC_MODE_PORT_MII		       (1L<<2)
+#define EMAC_MODE_PORT_MII_10M		       (3L<<2)
+#define EMAC_MODE_RESET				   (1L<<0)
+#define EMAC_REG_EMAC_LED					  0xc
+#define EMAC_REG_EMAC_MAC_MATCH					  0x10
+#define EMAC_REG_EMAC_MDIO_COMM					  0xac
+#define EMAC_REG_EMAC_MDIO_MODE					  0xb4
+#define EMAC_REG_EMAC_MDIO_STATUS				  0xb0
+#define EMAC_REG_EMAC_MODE					  0x0
+#define EMAC_REG_EMAC_RX_MODE					  0xc8
+#define EMAC_REG_EMAC_RX_MTU_SIZE				  0x9c
+#define EMAC_REG_EMAC_RX_STAT_AC				  0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_28				  0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT				  23
+#define EMAC_REG_EMAC_TX_MODE					  0xbc
+#define EMAC_REG_EMAC_TX_STAT_AC				  0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT				  22
+#define EMAC_REG_RX_PFC_MODE					  0x320
+#define EMAC_REG_RX_PFC_MODE_PRIORITIES			  (1L<<2)
+#define EMAC_REG_RX_PFC_MODE_RX_EN			  (1L<<1)
+#define EMAC_REG_RX_PFC_MODE_TX_EN			  (1L<<0)
+#define EMAC_REG_RX_PFC_PARAM					  0x324
+#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT		  0
+#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT	  16
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD			    0x328
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT		(0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT			    0x330
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT		(0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD			    0x32c
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT		(0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XON_SENT			    0x334
+#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT		(0xffff<<0)
+#define EMAC_RX_MODE_FLOW_EN			   (1L<<2)
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL		   (1L<<3)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG		   (1L<<10)
+#define EMAC_RX_MODE_PROMISCUOUS		   (1L<<8)
+#define EMAC_RX_MODE_RESET			   (1L<<0)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA		   (1L<<31)
+#define EMAC_TX_MODE_EXT_PAUSE_EN		   (1L<<3)
+#define EMAC_TX_MODE_FLOW_EN			   (1L<<4)
+#define EMAC_TX_MODE_RESET			   (1L<<0)
+
+
+#define MISC_REGISTERS_GPIO_0			 0
+#define MISC_REGISTERS_GPIO_1			 1
+#define MISC_REGISTERS_GPIO_2			 2
+#define MISC_REGISTERS_GPIO_3			 3
+#define MISC_REGISTERS_GPIO_CLR_POS		 16
+#define MISC_REGISTERS_GPIO_FLOAT		 (0xffL<<24)
+#define MISC_REGISTERS_GPIO_FLOAT_POS		 24
+#define MISC_REGISTERS_GPIO_HIGH		 1
+#define MISC_REGISTERS_GPIO_INPUT_HI_Z		 2
+#define MISC_REGISTERS_GPIO_INT_CLR_POS		 24
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR	 0
+#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET	 1
+#define MISC_REGISTERS_GPIO_INT_SET_POS		 16
+#define MISC_REGISTERS_GPIO_LOW			 0
+#define MISC_REGISTERS_GPIO_OUTPUT_HIGH		 1
+#define MISC_REGISTERS_GPIO_OUTPUT_LOW		 0
+#define MISC_REGISTERS_GPIO_PORT_SHIFT		 4
+#define MISC_REGISTERS_GPIO_SET_POS		 8
+#define MISC_REGISTERS_RESET_REG_1_CLEAR				0x588
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1				(0x1<<0)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \
+	(0x1<<19)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC \
+	(0x1<<29)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP \
+	(0x1<<26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \
+	(0x1<<27)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM \
+	(0x1<<17)
+#define MISC_REGISTERS_RESET_REG_1_SET					0x584
+#define MISC_REGISTERS_RESET_REG_2_CLEAR				0x598
+#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \
+	(0x1<<24)
+#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \
+	(0x1<<25)
+#define MISC_REGISTERS_RESET_REG_2_PGLC \
+	(0x1<<19)
+#define MISC_REGISTERS_RESET_REG_2_RST_ATC \
+	(0x1<<17)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0				(0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1				(0x1<<1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0				(0x1<<2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \
+	(0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1				(0x1<<3)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \
+	(0x1<<15)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC				(0x1<<4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B		(0x1<<6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE		(0x1<<8)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU		(0x1<<7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE	(0x1<<5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \
+	(0x1<<11)
+#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \
+	(0x1<<13)
+#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \
+	(0x1<<16)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN				(0x1<<9)
+#define MISC_REGISTERS_RESET_REG_2_SET					0x594
+#define MISC_REGISTERS_RESET_REG_2_UMAC0 \
+	(0x1<<20)
+#define MISC_REGISTERS_RESET_REG_2_UMAC1 \
+	(0x1<<21)
+#define MISC_REGISTERS_RESET_REG_2_XMAC \
+	(0x1<<22)
+#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \
+	(0x1<<23)
+#define MISC_REGISTERS_RESET_REG_3_CLEAR				0x5a8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ		(0x1<<1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN		(0x1<<2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD	(0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW		(0x1<<0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ		(0x1<<5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN		(0x1<<6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD		(0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW		(0x1<<4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB	(0x1<<8)
+#define MISC_REGISTERS_RESET_REG_3_SET					0x5a4
+#define MISC_SPIO_CLR_POS	       16
+#define MISC_SPIO_FLOAT		       (0xffL<<24)
+#define MISC_SPIO_FLOAT_POS	       24
+#define MISC_SPIO_INPUT_HI_Z	       2
+#define MISC_SPIO_INT_OLD_SET_POS      16
+#define MISC_SPIO_OUTPUT_HIGH	       1
+#define MISC_SPIO_OUTPUT_LOW	       0
+#define MISC_SPIO_SET_POS	       8
+#define MISC_SPIO_SPIO4		       0x10
+#define MISC_SPIO_SPIO5		       0x20
+#define HW_LOCK_MAX_RESOURCE_VALUE		 31
+#define HW_LOCK_RESOURCE_DRV_FLAGS		 10
+#define HW_LOCK_RESOURCE_GPIO			 1
+#define HW_LOCK_RESOURCE_NVRAM			 12
+#define HW_LOCK_RESOURCE_PORT0_ATT_MASK		 3
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0	 8
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1	 9
+#define HW_LOCK_RESOURCE_RECOVERY_REG		 11
+#define HW_LOCK_RESOURCE_RESET			 5
+#define HW_LOCK_RESOURCE_SPIO			 2
+
+
+#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT		      (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR		      (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT		      (0x1<<19)
+#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR		      (0x1<<18)
+#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT		      (0x1<<31)
+#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR		      (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT		      (0x1<<9)
+#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR		      (0x1<<8)
+#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT		      (0x1<<7)
+#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR		      (0x1<<6)
+#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT		      (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR		      (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT		      (0x1<<1)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR		      (0x1<<0)
+#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR		      (0x1<<18)
+#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT		      (0x1<<11)
+#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR		      (0x1<<10)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT	      (0x1<<13)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR	      (0x1<<12)
+#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0		      (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR		      (0x1<<12)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY	      (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY	      (0x1UL<<31)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY	      (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY	      (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT		      (0x1<<15)
+#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR		      (0x1<<14)
+#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR		      (0x1<<14)
+#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR	      (0x1<<20)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT	      (0x1UL<<31)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR	      (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR		      (0x1<<0)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT		      (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR		      (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT   (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR   (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT		      (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR		      (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT		      (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR		      (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR	      (0x1<<22)
+#define AEU_INPUTS_ATTN_BITS_SPIO5			      (0x1<<15)
+#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT		      (0x1<<27)
+#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR		      (0x1<<26)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT	      (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR	      (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT		      (0x1<<25)
+#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR		      (0x1<<24)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT		      (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR		      (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT		      (0x1<<23)
+#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR		      (0x1<<22)
+#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT		      (0x1<<27)
+#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR		      (0x1<<26)
+#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT		      (0x1<<21)
+#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR		      (0x1<<20)
+#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT		      (0x1<<25)
+#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR		      (0x1<<24)
+#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR	      (0x1<<16)
+#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT		      (0x1<<9)
+#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR		      (0x1<<8)
+#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT		      (0x1<<7)
+#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR		      (0x1<<6)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT		      (0x1<<11)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR		      (0x1<<10)
+#define HW_PRTY_ASSERT_SET_0 \
+(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR	    |\
+  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR   |\
+  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR     |\
+  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
+  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
+  AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
+  AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
+#define HW_PRTY_ASSERT_SET_1 \
+(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR		 |\
+  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR		  |\
+  AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR		  |\
+  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR		  |\
+  AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
+  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR		  |\
+  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR		  |\
+  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR	  |\
+  AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
+#define HW_PRTY_ASSERT_SET_2 \
+(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR	     |\
+  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR		      |\
+  AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
+  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR		      |\
+  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR		      |\
+  AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR	      |\
+  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR		      |\
+  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
+#define HW_PRTY_ASSERT_SET_3 \
+(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY	     | \
+  AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY      | \
+  AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY      | \
+  AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+#define HW_PRTY_ASSERT_SET_4 \
+(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\
+  AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
+#define HW_INTERRUT_ASSERT_SET_0 \
+(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT  |\
+  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT   |\
+  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\
+  AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT   |\
+  AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
+#define HW_INTERRUT_ASSERT_SET_1 \
+(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT	    |\
+  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT   |\
+  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT     |\
+  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT      |\
+  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT    |\
+  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT     |\
+  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT      |\
+  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT    |\
+  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT      |\
+  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT     |\
+  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
+#define HW_INTERRUT_ASSERT_SET_2 \
+(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT	       |\
+  AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT			|\
+  AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT			|\
+  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT			|\
+  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT		|\
+  AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT	|\
+  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
+
+
+#define RESERVED_GENERAL_ATTENTION_BIT_0	0
+
+#define EVEREST_GEN_ATTN_IN_USE_MASK		0x7ffe0
+#define EVEREST_LATCHED_ATTN_IN_USE_MASK	0xffe00000
+
+#define RESERVED_GENERAL_ATTENTION_BIT_6	6
+#define RESERVED_GENERAL_ATTENTION_BIT_7	7
+#define RESERVED_GENERAL_ATTENTION_BIT_8	8
+#define RESERVED_GENERAL_ATTENTION_BIT_9	9
+#define RESERVED_GENERAL_ATTENTION_BIT_10	10
+#define RESERVED_GENERAL_ATTENTION_BIT_11	11
+#define RESERVED_GENERAL_ATTENTION_BIT_12	12
+#define RESERVED_GENERAL_ATTENTION_BIT_13	13
+#define RESERVED_GENERAL_ATTENTION_BIT_14	14
+#define RESERVED_GENERAL_ATTENTION_BIT_15	15
+#define RESERVED_GENERAL_ATTENTION_BIT_16	16
+#define RESERVED_GENERAL_ATTENTION_BIT_17	17
+#define RESERVED_GENERAL_ATTENTION_BIT_18	18
+#define RESERVED_GENERAL_ATTENTION_BIT_19	19
+#define RESERVED_GENERAL_ATTENTION_BIT_20	20
+#define RESERVED_GENERAL_ATTENTION_BIT_21	21
+
+/* storm asserts attention bits */
+#define TSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_7
+#define USTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_8
+#define CSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_9
+#define XSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_10
+
+/* mcp error attention bit */
+#define MCP_FATAL_ASSERT_ATTENTION_BIT	      RESERVED_GENERAL_ATTENTION_BIT_11
+
+/*E1H NIG status sync attention mapped to group 4-7*/
+#define LINK_SYNC_ATTENTION_BIT_FUNC_0	    RESERVED_GENERAL_ATTENTION_BIT_12
+#define LINK_SYNC_ATTENTION_BIT_FUNC_1	    RESERVED_GENERAL_ATTENTION_BIT_13
+#define LINK_SYNC_ATTENTION_BIT_FUNC_2	    RESERVED_GENERAL_ATTENTION_BIT_14
+#define LINK_SYNC_ATTENTION_BIT_FUNC_3	    RESERVED_GENERAL_ATTENTION_BIT_15
+#define LINK_SYNC_ATTENTION_BIT_FUNC_4	    RESERVED_GENERAL_ATTENTION_BIT_16
+#define LINK_SYNC_ATTENTION_BIT_FUNC_5	    RESERVED_GENERAL_ATTENTION_BIT_17
+#define LINK_SYNC_ATTENTION_BIT_FUNC_6	    RESERVED_GENERAL_ATTENTION_BIT_18
+#define LINK_SYNC_ATTENTION_BIT_FUNC_7	    RESERVED_GENERAL_ATTENTION_BIT_19
+
+	/* Used For Error Recovery: changing this will require more \
+	changes in code that assume
+ * error recovery uses general attn bit20 ! */
+#define ERROR_RECOVERY_ATTENTION_BIT \
+	RESERVED_GENERAL_ATTENTION_BIT_20
+#define RESERVED_ATTENTION_BIT \
+	RESERVED_GENERAL_ATTENTION_BIT_21
+
+#define LATCHED_ATTN_RBCR			23
+#define LATCHED_ATTN_RBCT			24
+#define LATCHED_ATTN_RBCN			25
+#define LATCHED_ATTN_RBCU			26
+#define LATCHED_ATTN_RBCP			27
+#define LATCHED_ATTN_TIMEOUT_GRC		28
+#define LATCHED_ATTN_RSVD_GRC			29
+#define LATCHED_ATTN_ROM_PARITY_MCP		30
+#define LATCHED_ATTN_UM_RX_PARITY_MCP		31
+#define LATCHED_ATTN_UM_TX_PARITY_MCP		32
+#define LATCHED_ATTN_SCPAD_PARITY_MCP		33
+
+#define GENERAL_ATTEN_WORD(atten_name)	       ((94 + atten_name) / 32)
+#define GENERAL_ATTEN_OFFSET(atten_name)       (1UL << ((94 + atten_name) % 32))
+
+
+/*
+ * This file defines GRC base address for every block.
+ * This file is included by chipsim, asm microcode and cpp microcode.
+ * These values are used in Design.xml on regBase attribute
+ * Use the base with the generated offsets of specific registers.
+ */
+
+#define GRCBASE_PXPCS	    0x000000
+#define GRCBASE_PCICONFIG   0x002000
+#define GRCBASE_PCIREG	    0x002400
+#define GRCBASE_EMAC0	    0x008000
+#define GRCBASE_EMAC1	    0x008400
+#define GRCBASE_DBU		0x008800
+#define GRCBASE_PGLUE_B	    0x009000
+#define GRCBASE_MISC	    0x00A000
+#define GRCBASE_DBG		0x00C000
+#define GRCBASE_NIG		0x010000
+#define GRCBASE_XCM		0x020000
+#define GRCBASE_PRS	    0x040000
+#define GRCBASE_SRCH	    0x040400
+#define GRCBASE_TSDM	    0x042000
+#define GRCBASE_TCM		0x050000
+#define GRCBASE_BRB1	    0x060000
+#define GRCBASE_MCP		0x080000
+#define GRCBASE_UPB		0x0C1000
+#define GRCBASE_CSDM	    0x0C2000
+#define GRCBASE_USDM	    0x0C4000
+#define GRCBASE_CCM		0x0D0000
+#define GRCBASE_UCM		0x0E0000
+#define GRCBASE_CDU		0x101000
+#define GRCBASE_DMAE	    0x102000
+#define GRCBASE_PXP		0x103000
+#define GRCBASE_CFC		0x104000
+#define GRCBASE_HC		0x108000
+#define GRCBASE_ATC		0x110000
+#define GRCBASE_PXP2	    0x120000
+#define GRCBASE_IGU	    0x130000
+#define GRCBASE_PBF	    0x140000
+#define GRCBASE_UMAC0	    0x160000
+#define GRCBASE_UMAC1	    0x160400
+#define GRCBASE_XPB	    0x161000
+#define GRCBASE_MSTAT0	    0x162000
+#define GRCBASE_MSTAT1	    0x162800
+#define GRCBASE_XMAC0	    0x163000
+#define GRCBASE_XMAC1	    0x163800
+#define GRCBASE_TIMERS	    0x164000
+#define GRCBASE_XSDM	    0x166000
+#define GRCBASE_QM		0x168000
+#define GRCBASE_QM_4PORT    0x168000
+#define GRCBASE_DQ		0x170000
+#define GRCBASE_TSEM	    0x180000
+#define GRCBASE_CSEM	    0x200000
+#define GRCBASE_XSEM	    0x280000
+#define GRCBASE_XSEM_4PORT  0x280000
+#define GRCBASE_USEM	    0x300000
+#define GRCBASE_MCP_A	    0x380000
+#define GRCBASE_MISC_AEU    GRCBASE_MISC
+#define GRCBASE_Tstorm	    GRCBASE_TSEM
+#define GRCBASE_Cstorm	    GRCBASE_CSEM
+#define GRCBASE_Xstorm	    GRCBASE_XSEM
+#define GRCBASE_Ustorm	    GRCBASE_USEM
+
+
+/* offset of configuration space in the pci core register */
+#define PCICFG_OFFSET					0x2000
+#define PCICFG_VENDOR_ID_OFFSET				0x00
+#define PCICFG_DEVICE_ID_OFFSET				0x02
+#define PCICFG_COMMAND_OFFSET				0x04
+#define PCICFG_COMMAND_IO_SPACE			(1<<0)
+#define PCICFG_COMMAND_MEM_SPACE		(1<<1)
+#define PCICFG_COMMAND_BUS_MASTER		(1<<2)
+#define PCICFG_COMMAND_SPECIAL_CYCLES		(1<<3)
+#define PCICFG_COMMAND_MWI_CYCLES		(1<<4)
+#define PCICFG_COMMAND_VGA_SNOOP		(1<<5)
+#define PCICFG_COMMAND_PERR_ENA			(1<<6)
+#define PCICFG_COMMAND_STEPPING			(1<<7)
+#define PCICFG_COMMAND_SERR_ENA			(1<<8)
+#define PCICFG_COMMAND_FAST_B2B			(1<<9)
+#define PCICFG_COMMAND_INT_DISABLE		(1<<10)
+#define PCICFG_COMMAND_RESERVED			(0x1f<<11)
+#define PCICFG_STATUS_OFFSET				0x06
+#define PCICFG_REVISION_ID_OFFSET			0x08
+#define PCICFG_REVESION_ID_MASK			0xff
+#define PCICFG_REVESION_ID_ERROR_VAL		0xff
+#define PCICFG_CACHE_LINE_SIZE				0x0c
+#define PCICFG_LATENCY_TIMER				0x0d
+#define PCICFG_HEADER_TYPE				0x0e
+#define PCICFG_HEADER_TYPE_NORMAL	   0
+#define PCICFG_HEADER_TYPE_BRIDGE	   1
+#define PCICFG_HEADER_TYPE_CARDBUS	   2
+#define PCICFG_BAR_1_LOW				0x10
+#define PCICFG_BAR_1_HIGH				0x14
+#define PCICFG_BAR_2_LOW				0x18
+#define PCICFG_BAR_2_HIGH				0x1c
+#define PCICFG_BAR_3_LOW				0x20
+#define PCICFG_BAR_3_HIGH				0x24
+#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET		0x2c
+#define PCICFG_SUBSYSTEM_ID_OFFSET			0x2e
+#define PCICFG_INT_LINE					0x3c
+#define PCICFG_INT_PIN					0x3d
+#define PCICFG_PM_CAPABILITY				0x48
+#define PCICFG_PM_CAPABILITY_VERSION		(0x3<<16)
+#define PCICFG_PM_CAPABILITY_CLOCK		(1<<19)
+#define PCICFG_PM_CAPABILITY_RESERVED		(1<<20)
+#define PCICFG_PM_CAPABILITY_DSI		(1<<21)
+#define PCICFG_PM_CAPABILITY_AUX_CURRENT	(0x7<<22)
+#define PCICFG_PM_CAPABILITY_D1_SUPPORT		(1<<25)
+#define PCICFG_PM_CAPABILITY_D2_SUPPORT		(1<<26)
+#define PCICFG_PM_CAPABILITY_PME_IN_D0		(1<<27)
+#define PCICFG_PM_CAPABILITY_PME_IN_D1		(1<<28)
+#define PCICFG_PM_CAPABILITY_PME_IN_D2		(1<<29)
+#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT	(1<<30)
+#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD	(1<<31)
+#define PCICFG_PM_CSR_OFFSET				0x4c
+#define PCICFG_PM_CSR_STATE			(0x3<<0)
+#define PCICFG_PM_CSR_PME_ENABLE		(1<<8)
+#define PCICFG_PM_CSR_PME_STATUS		(1<<15)
+#define PCICFG_VPD_FLAG_ADDR_OFFSET			0x50
+#define PCICFG_VPD_DATA_OFFSET				0x54
+#define PCICFG_MSI_CAP_ID_OFFSET			0x58
+#define PCICFG_MSI_CONTROL_ENABLE		(0x1<<16)
+#define PCICFG_MSI_CONTROL_MCAP			(0x7<<17)
+#define PCICFG_MSI_CONTROL_MENA			(0x7<<20)
+#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP	(0x1<<23)
+#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE	(0x1<<24)
+#define PCICFG_MSI_ADDR_LOW_OFFSET			0x5c
+#define PCICFG_MSI_ADDR_HIGH_OFFSET			0x60
+#define PCICFG_MSI_DATA_OFFSET				0x64
+#define PCICFG_GRC_ADDRESS				0x78
+#define PCICFG_GRC_DATA					0x80
+#define PCICFG_ME_REGISTER		    0x98
+#define PCICFG_MSIX_CAP_ID_OFFSET			0xa0
+#define PCICFG_MSIX_CONTROL_TABLE_SIZE		(0x7ff<<16)
+#define PCICFG_MSIX_CONTROL_RESERVED		(0x7<<27)
+#define PCICFG_MSIX_CONTROL_FUNC_MASK		(0x1<<30)
+#define PCICFG_MSIX_CONTROL_MSIX_ENABLE		(0x1<<31)
+
+#define PCICFG_DEVICE_CONTROL				0xb4
+#define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND   (1<<21)
+#define PCICFG_DEVICE_STATUS				0xb6
+#define PCICFG_DEVICE_STATUS_CORR_ERR_DET	(1<<0)
+#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET	(1<<1)
+#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET	(1<<2)
+#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET	(1<<3)
+#define PCICFG_DEVICE_STATUS_AUX_PWR_DET	(1<<4)
+#define PCICFG_DEVICE_STATUS_NO_PEND		(1<<5)
+#define PCICFG_LINK_CONTROL				0xbc
+
+
+/* config_2 offset */
+#define GRC_CONFIG_2_SIZE_REG				0x408
+#define PCI_CONFIG_2_BAR1_SIZE			(0xfL<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_DISABLED		(0L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64K		(1L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128K		(2L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256K		(3L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512K		(4L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1M		(5L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_2M		(6L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_4M		(7L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_8M		(8L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_16M		(9L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_32M		(10L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64M		(11L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128M		(12L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256M		(13L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512M		(14L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1G		(15L<<0)
+#define PCI_CONFIG_2_BAR1_64ENA			(1L<<4)
+#define PCI_CONFIG_2_EXP_ROM_RETRY		(1L<<5)
+#define PCI_CONFIG_2_CFG_CYCLE_RETRY		(1L<<6)
+#define PCI_CONFIG_2_FIRST_CFG_DONE		(1L<<7)
+#define PCI_CONFIG_2_EXP_ROM_SIZE		(0xffL<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED	(0L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2K		(1L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4K		(2L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8K		(3L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16K		(4L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32K		(5L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_64K		(6L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_128K		(7L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_256K		(8L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_512K		(9L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_1M		(10L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2M		(11L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4M		(12L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8M		(13L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16M		(14L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32M		(15L<<8)
+#define PCI_CONFIG_2_BAR_PREFETCH		(1L<<16)
+#define PCI_CONFIG_2_RESERVED0			(0x7fffL<<17)
+
+/* config_3 offset */
+#define GRC_CONFIG_3_SIZE_REG				0x40c
+#define PCI_CONFIG_3_STICKY_BYTE			(0xffL<<0)
+#define PCI_CONFIG_3_FORCE_PME			(1L<<24)
+#define PCI_CONFIG_3_PME_STATUS			(1L<<25)
+#define PCI_CONFIG_3_PME_ENABLE			(1L<<26)
+#define PCI_CONFIG_3_PM_STATE			(0x3L<<27)
+#define PCI_CONFIG_3_VAUX_PRESET			(1L<<30)
+#define PCI_CONFIG_3_PCI_POWER			(1L<<31)
+
+#define GRC_REG_DEVICE_CONTROL		    0x4d8
+#define PCIE_SRIOV_DISABLE_IN_PROGRESS \
+	(1 << 29) /*When VF Enable is cleared(after it was previously set),
+ this register will read a value of 1, indicating that all the
+ VFs that belong to this PF should be flushed.
+ Software should clear this bit within 1 second of VF Enable
+ being set by writing a 1 to it, so that VFs are visible to the system again.
+							WC */
+#define PCIE_FLR_IN_PROGRESS \
+	(1 << 27) /*When FLR is initiated, this register will read a \
+	value of 1 indicating that the
+ Function is in FLR state. Func can be brought out of FLR state either by
+ writing 1 to this register (at least 50 ms after FLR was initiated),
+ or it can also be cleared automatically after 55 ms if auto_clear bit
+ in private reg space is set. This bit also exists in VF register space
+							WC */
+
+#define GRC_BAR2_CONFIG					0x4e0
+#define PCI_CONFIG_2_BAR2_SIZE			(0xfL<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_DISABLED		(0L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64K		(1L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128K		(2L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256K		(3L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512K		(4L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1M		(5L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_2M		(6L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_4M		(7L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_8M		(8L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_16M		(9L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_32M		(10L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64M		(11L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128M		(12L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256M		(13L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512M		(14L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1G		(15L<<0)
+#define PCI_CONFIG_2_BAR2_64ENA			(1L<<4)
+
+#define GRC_BAR3_CONFIG					0x4f4
+#define PCI_CONFIG_2_BAR3_SIZE			(0xfL<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_DISABLED		(0L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_64K		(1L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_128K		(2L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_256K		(3L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_512K		(4L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_1M		(5L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_2M		(6L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_4M		(7L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_8M		(8L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_16M		(9L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_32M		(10L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_64M		(11L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_128M		(12L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_256M		(13L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_512M		(14L<<0)
+#define PCI_CONFIG_2_BAR3_SIZE_1G		(15L<<0)
+#define PCI_CONFIG_2_BAR3_64ENA			(1L<<4)
+
+#define PCI_PM_DATA_A					0x410
+#define PCI_PM_DATA_B					0x414
+#define PCI_ID_VAL1					0x434
+#define PCI_ID_VAL2					0x438
+#define PCI_ID_VAL3					0x43c
+#define PCI_ID_VAL3_REVISION_ID_ERROR		  (0xffL<<24)
+
+
+#define GRC_CONFIG_REG_VF_BAR_REG_1		0x608
+#define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE	0xf
+
+#define GRC_CONFIG_REG_VF_MSIX_CONTROL		    0x61C
+#define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \
+	0x3F  /*This field resides in VF only and does not exist in PF.
+ This register controls the read value of the MSIX_CONTROL[10:0] register
+ in the VF configuration space. A value of "00000000011" indicates
+ a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ
+ define in version.v */
+
+#define GRC_CONFIG_REG_PF_INIT_VF		0x624
+#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \
+	0xf /*First VF_NUM for PF is encoded in this register.
+ The number of VFs assigned to a PF is assumed to be a multiple of 8.
+	Software should program these bits based on Total Number of VFs \
+	programmed for each PF.
+ Since registers from 0x000-0x7ff are spilt across functions, each PF will have
+ the same location for the same 4 bits*/
+
+#define PXPCS_TL_CONTROL_5			0x814
+#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN	   (1 << 29) /*WC*/
+#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN	   (1 << 28)   /*WC*/
+#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN   (1 << 27)   /*WC*/
+#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN	   (1 << 26)   /*WC*/
+#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR  (1 << 25)   /*WC*/
+#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW	   (1 << 24)   /*WC*/
+#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN	   (1 << 23)   /*RO*/
+#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN	   (1 << 22)   /*RO*/
+#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE   (1 << 21)   /*WC*/
+#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG  (1 << 20)   /*WC*/
+#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1   (1 << 19)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1   (1 << 18)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_ECRC1   (1 << 17)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1   (1 << 16)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1   (1 << 15)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1  (1 << 14)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1    (1 << 13)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1    (1 << 12)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1	   (1 << 11)   /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1   (1 << 10)   /*WC*/
+#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT	   (1 << 9)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT	   (1 << 8)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_ECRC    (1 << 7)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP	   (1 << 6)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW	   (1 << 5)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL   (1 << 4)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT     (1 << 3)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT     (1 << 2)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL	   (1 << 1)    /*WC*/
+#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP	   (1 << 0)    /*WC*/
+
+
+#define PXPCS_TL_FUNC345_STAT	   0x854
+#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4    (1 << 29)   /* WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \
+	(1 << 28) /* Unsupported Request Error Status in function4, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \
+	(1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \
+	(1 << 26) /* Malformed TLP Status Status in function 4, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \
+	(1 << 25) /* Receiver Overflow Status Status in function 4, if \
+	set, generate pcie_err_attn output when this error is seen.. WC \
+	*/
+#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \
+	(1 << 24) /* Unexpected Completion Status Status in function 4, \
+	if set, generate pcie_err_attn output when this error is seen. WC \
+	*/
+#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \
+	(1 << 23) /* Receive UR Statusin function 4. If set, generate \
+	pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \
+	(1 << 22) /* Completer Timeout Status Status in function 4, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \
+	(1 << 21) /* Flow Control Protocol Error Status Status in \
+	function 4, if set, generate pcie_err_attn output when this error \
+	is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \
+	(1 << 20) /* Poisoned Error Status Status in function 4, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3    (1 << 19)   /* WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \
+	(1 << 18) /* Unsupported Request Error Status in function3, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \
+	(1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \
+	(1 << 16) /* Malformed TLP Status Status in function 3, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \
+	(1 << 15) /* Receiver Overflow Status Status in function 3, if \
+	set, generate pcie_err_attn output when this error is seen.. WC \
+	*/
+#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \
+	(1 << 14) /* Unexpected Completion Status Status in function 3, \
+	if set, generate pcie_err_attn output when this error is seen. WC \
+	*/
+#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \
+	(1 << 13) /* Receive UR Statusin function 3. If set, generate \
+	pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \
+	(1 << 12) /* Completer Timeout Status Status in function 3, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \
+	(1 << 11) /* Flow Control Protocol Error Status Status in \
+	function 3, if set, generate pcie_err_attn output when this error \
+	is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \
+	(1 << 10) /* Poisoned Error Status Status in function 3, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2    (1 << 9)    /* WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \
+	(1 << 8) /* Unsupported Request Error Status for Function 2, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \
+	(1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \
+	(1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \
+	(1 << 5) /* Receiver Overflow Status Status for Function 2, if \
+	set, generate pcie_err_attn output when this error is seen.. WC \
+	*/
+#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \
+	(1 << 4) /* Unexpected Completion Status Status for Function 2, \
+	if set, generate pcie_err_attn output when this error is seen. WC \
+	*/
+#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \
+	(1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
+	pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \
+	(1 << 2) /* Completer Timeout Status Status for Function 2, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \
+	(1 << 1) /* Flow Control Protocol Error Status Status for \
+	Function 2, if set, generate pcie_err_attn output when this error \
+	is seen. WC */
+#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \
+	(1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+
+
+#define PXPCS_TL_FUNC678_STAT  0x85C
+#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7    (1 << 29)   /*	 WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \
+	(1 << 28) /* Unsupported Request Error Status in function7, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \
+	(1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \
+	(1 << 26) /* Malformed TLP Status Status in function 7, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \
+	(1 << 25) /* Receiver Overflow Status Status in function 7, if \
+	set, generate pcie_err_attn output when this error is seen.. WC \
+	*/
+#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \
+	(1 << 24) /* Unexpected Completion Status Status in function 7, \
+	if set, generate pcie_err_attn output when this error is seen. WC \
+	*/
+#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \
+	(1 << 23) /* Receive UR Statusin function 7. If set, generate \
+	pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \
+	(1 << 22) /* Completer Timeout Status Status in function 7, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \
+	(1 << 21) /* Flow Control Protocol Error Status Status in \
+	function 7, if set, generate pcie_err_attn output when this error \
+	is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \
+	(1 << 20) /* Poisoned Error Status Status in function 7, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6    (1 << 19)    /*	  WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \
+	(1 << 18) /* Unsupported Request Error Status in function6, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \
+	(1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \
+	(1 << 16) /* Malformed TLP Status Status in function 6, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \
+	(1 << 15) /* Receiver Overflow Status Status in function 6, if \
+	set, generate pcie_err_attn output when this error is seen.. WC \
+	*/
+#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \
+	(1 << 14) /* Unexpected Completion Status Status in function 6, \
+	if set, generate pcie_err_attn output when this error is seen. WC \
+	*/
+#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \
+	(1 << 13) /* Receive UR Statusin function 6. If set, generate \
+	pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \
+	(1 << 12) /* Completer Timeout Status Status in function 6, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \
+	(1 << 11) /* Flow Control Protocol Error Status Status in \
+	function 6, if set, generate pcie_err_attn output when this error \
+	is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \
+	(1 << 10) /* Poisoned Error Status Status in function 6, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5    (1 << 9) /*    WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \
+	(1 << 8) /* Unsupported Request Error Status for Function 5, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \
+	(1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \
+	(1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \
+	(1 << 5) /* Receiver Overflow Status Status for Function 5, if \
+	set, generate pcie_err_attn output when this error is seen.. WC \
+	*/
+#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \
+	(1 << 4) /* Unexpected Completion Status Status for Function 5, \
+	if set, generate pcie_err_attn output when this error is seen. WC \
+	*/
+#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \
+	(1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
+	pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \
+	(1 << 2) /* Completer Timeout Status Status for Function 5, if \
+	set, generate pcie_err_attn output when this error is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \
+	(1 << 1) /* Flow Control Protocol Error Status Status for \
+	Function 5, if set, generate pcie_err_attn output when this error \
+	is seen. WC */
+#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \
+	(1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
+	generate pcie_err_attn output when this error is seen.. WC */
+
+
+#define BAR_USTRORM_INTMEM				0x400000
+#define BAR_CSTRORM_INTMEM				0x410000
+#define BAR_XSTRORM_INTMEM				0x420000
+#define BAR_TSTRORM_INTMEM				0x430000
+
+/* for accessing the IGU in case of status block ACK */
+#define BAR_IGU_INTMEM					0x440000
+
+#define BAR_DOORBELL_OFFSET				0x800000
+
+#define BAR_ME_REGISTER					0x450000
+#define ME_REG_PF_NUM_SHIFT		0
+#define ME_REG_PF_NUM \
+	(7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
+#define ME_REG_VF_VALID			(1<<8)
+#define ME_REG_VF_NUM_SHIFT		9
+#define ME_REG_VF_NUM_MASK		(0x3f<<ME_REG_VF_NUM_SHIFT)
+#define VF_ID(x)			((x & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT)
+#define ME_REG_VF_ERR			(0x1<<3)
+#define ME_REG_ABS_PF_NUM_SHIFT		16
+#define ME_REG_ABS_PF_NUM \
+	(7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
+
+
+#define PXP_VF_ADRR_NUM_QUEUES		136
+#define PXP_ADDR_QUEUE_SIZE			32
+#define PXP_ADDR_REG_SIZE			512
+
+
+#define PXP_VF_ADDR_IGU_START		0
+#define PXP_VF_ADDR_IGU_SIZE		(0x3000)
+#define PXP_VF_ADDR_IGU_END \
+	((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
+
+#define PXP_VF_ADDR_USDM_QUEUES_START		0x3000
+#define PXP_VF_ADDR_USDM_QUEUES_SIZE \
+	(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
+#define PXP_VF_ADDR_USDM_QUEUES_END \
+	((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
+
+#define PXP_VF_ADDR_CSDM_QUEUES_START		0x4100
+#define PXP_VF_ADDR_CSDM_QUEUES_SIZE \
+	(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
+#define PXP_VF_ADDR_CSDM_QUEUES_END \
+	((PXP_VF_ADDR_CSDM_QUEUES_START) + (PXP_VF_ADDR_CSDM_QUEUES_SIZE) - 1)
+
+#define PXP_VF_ADDR_XSDM_QUEUES_START		0x5200
+#define PXP_VF_ADDR_XSDM_QUEUES_SIZE \
+	(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
+#define PXP_VF_ADDR_XSDM_QUEUES_END \
+	((PXP_VF_ADDR_XSDM_QUEUES_START) + (PXP_VF_ADDR_XSDM_QUEUES_SIZE) - 1)
+
+#define PXP_VF_ADDR_TSDM_QUEUES_START		0x6300
+#define PXP_VF_ADDR_TSDM_QUEUES_SIZE \
+	(PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
+#define PXP_VF_ADDR_TSDM_QUEUES_END \
+	((PXP_VF_ADDR_TSDM_QUEUES_START) + (PXP_VF_ADDR_TSDM_QUEUES_SIZE) - 1)
+
+#define PXP_VF_ADDR_USDM_GLOBAL_START		0x7400
+#define PXP_VF_ADDR_USDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
+#define PXP_VF_ADDR_USDM_GLOBAL_END \
+	((PXP_VF_ADDR_USDM_GLOBAL_START) + (PXP_VF_ADDR_USDM_GLOBAL_SIZE) - 1)
+
+#define PXP_VF_ADDR_CSDM_GLOBAL_START		0x7600
+#define PXP_VF_ADDR_CSDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
+#define PXP_VF_ADDR_CSDM_GLOBAL_END \
+	((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
+
+#define PXP_VF_ADDR_XSDM_GLOBAL_START		0x7800
+#define PXP_VF_ADDR_XSDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
+#define PXP_VF_ADDR_XSDM_GLOBAL_END \
+	((PXP_VF_ADDR_XSDM_GLOBAL_START) + (PXP_VF_ADDR_XSDM_GLOBAL_SIZE) - 1)
+
+#define PXP_VF_ADDR_TSDM_GLOBAL_START		0x7a00
+#define PXP_VF_ADDR_TSDM_GLOBAL_SIZE		(PXP_ADDR_REG_SIZE)
+#define PXP_VF_ADDR_TSDM_GLOBAL_END \
+	((PXP_VF_ADDR_TSDM_GLOBAL_START) + (PXP_VF_ADDR_TSDM_GLOBAL_SIZE) - 1)
+
+#define PXP_VF_ADDR_DB_START				0x7c00
+#define PXP_VF_ADDR_DB_SIZE					(0x200)
+#define PXP_VF_ADDR_DB_END \
+	((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
+
+#define PXP_VF_ADDR_GRC_START				0x7e00
+#define PXP_VF_ADDR_GRC_SIZE				(0x200)
+#define PXP_VF_ADDR_GRC_END \
+	((PXP_VF_ADDR_GRC_START) + (PXP_VF_ADDR_GRC_SIZE) - 1)
+
+#define PXP_VF_ADDR_DORQ_START				(0x0)
+#define PXP_VF_ADDR_DORQ_SIZE				(0xffffffff)
+#define PXP_VF_ADDR_DORQ_END				(0xffffffff)
+
+#define PXP_BAR_GRC		0
+#define PXP_BAR_TSDM	0
+#define PXP_BAR_USDM	0
+#define PXP_BAR_XSDM	0
+#define PXP_BAR_CSDM	0
+#define PXP_BAR_IGU		0
+#define PXP_BAR_DQ		1
+
+#define PXP_VF_BAR_IGU	0
+#define PXP_VF_BAR_USDM_QUEUES	0
+#define PXP_VF_BAR_TSDM_QUEUES	0
+#define PXP_VF_BAR_XSDM_QUEUES	0
+#define PXP_VF_BAR_CSDM_QUEUES	0
+#define PXP_VF_BAR_USDM_GLOBAL	0
+#define PXP_VF_BAR_TSDM_GLOBAL	0
+#define PXP_VF_BAR_XSDM_GLOBAL	0
+#define PXP_VF_BAR_CSDM_GLOBAL	0
+#define PXP_VF_BAR_DB	0
+#define PXP_VF_BAR_GRC	0
+#define PXP_VF_BAR_DORQ	1
+
+/* PCI CAPABILITIES*/
+
+#define PCI_CAP_PCIE				0x10	/*PCIe capability ID*/
+
+#define PCIE_DEV_CAPS				0x04
+
+#define PCIE_DEV_CTRL				0x08
+#define PCIE_DEV_CTRL_FLR				0x8000;
+
+#define PCIE_DEV_STATUS				0x0A
+
+#define PCI_CAP_MSIX				0x11	/*MSI-X capability ID*/
+#define PCI_MSIX_CONTROL_SHIFT			16
+#define PCI_MSIX_TABLE_SIZE_MASK		0x07FF
+#define PCI_MSIX_TABLE_ENABLE_MASK		0x8000
+
+
+#define MDIO_REG_BANK_CL73_IEEEB0			0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL		0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN	0x0200
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN		0x1000
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST	0x8000
+
+#define MDIO_REG_BANK_CL73_IEEEB1			0x10
+#define MDIO_CL73_IEEEB1_AN_ADV1			0x00
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE			0x0400
+#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC		0x0800
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH		0x0C00
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK		0x0C00
+#define MDIO_CL73_IEEEB1_AN_ADV2				0x01
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M		0x0000
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX		0x0020
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4		0x0040
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR		0x0080
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1			0x03
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE		0x0400
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC		0x0800
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH		0x0C00
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK		0x0C00
+#define MDIO_CL73_IEEEB1_AN_LP_ADV2			0x04
+
+#define MDIO_REG_BANK_RX0				0x80b0
+#define MDIO_RX0_RX_STATUS				0x10
+#define MDIO_RX0_RX_STATUS_SIGDET			0x8000
+#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE			0x1000
+#define MDIO_RX0_RX_EQ_BOOST				0x1c
+#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define MDIO_REG_BANK_RX1				0x80c0
+#define MDIO_RX1_RX_EQ_BOOST				0x1c
+#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define MDIO_REG_BANK_RX2				0x80d0
+#define MDIO_RX2_RX_EQ_BOOST				0x1c
+#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define MDIO_REG_BANK_RX3				0x80e0
+#define MDIO_RX3_RX_EQ_BOOST				0x1c
+#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL		0x10
+
+#define MDIO_REG_BANK_RX_ALL				0x80f0
+#define MDIO_RX_ALL_RX_EQ_BOOST				0x1c
+#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
+#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL	0x10
+
+#define MDIO_REG_BANK_TX0				0x8060
+#define MDIO_TX0_TX_DRIVER				0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T			1
+
+#define MDIO_REG_BANK_TX1				0x8070
+#define MDIO_TX1_TX_DRIVER				0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T			1
+
+#define MDIO_REG_BANK_TX2				0x8080
+#define MDIO_TX2_TX_DRIVER				0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T			1
+
+#define MDIO_REG_BANK_TX3				0x8090
+#define MDIO_TX3_TX_DRIVER				0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT		12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT		8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT		4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT		1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T			1
+
+#define MDIO_REG_BANK_XGXS_BLOCK0			0x8000
+#define MDIO_BLOCK0_XGXS_CONTROL			0x10
+
+#define MDIO_REG_BANK_XGXS_BLOCK1			0x8010
+#define MDIO_BLOCK1_LANE_CTRL0				0x15
+#define MDIO_BLOCK1_LANE_CTRL1				0x16
+#define MDIO_BLOCK1_LANE_CTRL2				0x17
+#define MDIO_BLOCK1_LANE_PRBS				0x19
+
+#define MDIO_REG_BANK_XGXS_BLOCK2			0x8100
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP			0x10
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE		0x8000
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE	0x4000
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP		0x11
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE		0x8000
+#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G	0x14
+#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS	0x0001
+#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS	0x0010
+#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE		0x15
+
+#define MDIO_REG_BANK_GP_STATUS				0x8120
+#define MDIO_GP_STATUS_TOP_AN_STATUS1				0x1B
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE	0x0001
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE	0x0002
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS		0x0004
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS		0x0008
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE	0x0010
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE	0x0020
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE	0x0040
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE	0x0080
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK		0x3f00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M		0x0000
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M		0x0100
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G		0x0200
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G		0x0300
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G		0x0400
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G		0x0500
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG	0x0600
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4	0x0700
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG	0x0800
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G	0x0900
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G		0x0A00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G		0x0B00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G		0x0C00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX	0x0D00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4	0x0E00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR	0x0F00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI	0x1B00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS	0x1E00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI	0x1F00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2	0x3900
+
+
+#define MDIO_REG_BANK_10G_PARALLEL_DETECT		0x8130
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS		0x10
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK		0x8000
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL		0x11
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN	0x1
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK		0x13
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT		(0xb71<<1)
+
+#define MDIO_REG_BANK_SERDES_DIGITAL			0x8300
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1			0x10
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE			0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF			0x0002
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN		0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT	0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET			0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE			0x0020
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2			0x11
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN			0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR			0x0040
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1			0x14
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII			0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK			0x0002
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX			0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK			0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT			3
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G			0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G			0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M			0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M			0x0000
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2			0x15
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED			0x0002
+#define MDIO_SERDES_DIGITAL_MISC1				0x18
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK			0xE000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M			0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M			0x2000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M			0x4000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M			0x6000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M			0x8000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL			0x0010
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK			0x000f
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G			0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G			0x0001
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G			0x0002
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG			0x0003
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4			0x0004
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G			0x0005
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G			0x0006
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G			0x0007
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G			0x0008
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G			0x0009
+
+#define MDIO_REG_BANK_OVER_1G				0x8320
+#define MDIO_OVER_1G_DIGCTL_3_4					0x14
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK				0xffe0
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT				5
+#define MDIO_OVER_1G_UP1					0x19
+#define MDIO_OVER_1G_UP1_2_5G						0x0001
+#define MDIO_OVER_1G_UP1_5G						0x0002
+#define MDIO_OVER_1G_UP1_6G						0x0004
+#define MDIO_OVER_1G_UP1_10G						0x0010
+#define MDIO_OVER_1G_UP1_10GH						0x0008
+#define MDIO_OVER_1G_UP1_12G						0x0020
+#define MDIO_OVER_1G_UP1_12_5G						0x0040
+#define MDIO_OVER_1G_UP1_13G						0x0080
+#define MDIO_OVER_1G_UP1_15G						0x0100
+#define MDIO_OVER_1G_UP1_16G						0x0200
+#define MDIO_OVER_1G_UP2					0x1A
+#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK				0x0007
+#define MDIO_OVER_1G_UP2_IDRIVER_MASK					0x0038
+#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK				0x03C0
+#define MDIO_OVER_1G_UP3					0x1B
+#define MDIO_OVER_1G_UP3_HIGIG2						0x0001
+#define MDIO_OVER_1G_LP_UP1					0x1C
+#define MDIO_OVER_1G_LP_UP2					0x1D
+#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK				0x03ff
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK				0x0780
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT				7
+#define MDIO_OVER_1G_LP_UP3						0x1E
+
+#define MDIO_REG_BANK_REMOTE_PHY			0x8330
+#define MDIO_REMOTE_PHY_MISC_RX_STATUS				0x10
+#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG	0x0010
+#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG	0x0600
+
+#define MDIO_REG_BANK_BAM_NEXT_PAGE			0x8350
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL			0x10
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE			0x0001
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN			0x0002
+
+#define MDIO_REG_BANK_CL73_USERB0		0x8370
+#define MDIO_CL73_USERB0_CL73_UCTRL				0x10
+#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL			0x0002
+#define MDIO_CL73_USERB0_CL73_USTAT1				0x11
+#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK			0x0100
+#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37		0x0400
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1				0x12
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN				0x8000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN		0x4000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN		0x2000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3				0x14
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR			0x0001
+
+#define MDIO_REG_BANK_AER_BLOCK			0xFFD0
+#define MDIO_AER_BLOCK_AER_REG					0x1E
+
+#define MDIO_REG_BANK_COMBO_IEEE0		0xFFE0
+#define MDIO_COMBO_IEEE0_MII_CONTROL				0x10
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK			0x2040
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10			0x0000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100			0x2000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000			0x0040
+#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX				0x0100
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN				0x0200
+#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN				0x1000
+#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK				0x4000
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESET				0x8000
+#define MDIO_COMBO_IEEE0_MII_STATUS				0x11
+#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS				0x0004
+#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE			0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV				0x14
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX			0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX			0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK			0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE			0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC			0x0080
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC			0x0100
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH			0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE				0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1		0x15
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE	0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK		0x4000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK	0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE	0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH	0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP	0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP	0x0020
+/*WhenthelinkpartnerisinSGMIImode(bit0=1), then
+bit15=link, bit12=duplex, bits11:10=speed, bit14=acknowledge.
+Theotherbitsarereservedandshouldbezero*/
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE	0x0001
+
+
+#define MDIO_PMA_DEVAD			0x1
+/*ieee*/
+#define MDIO_PMA_REG_CTRL		0x0
+#define MDIO_PMA_REG_STATUS		0x1
+#define MDIO_PMA_REG_10G_CTRL2		0x7
+#define MDIO_PMA_REG_TX_DISABLE		0x0009
+#define MDIO_PMA_REG_RX_SD		0xa
+/*bcm*/
+#define MDIO_PMA_REG_BCM_CTRL		0x0096
+#define MDIO_PMA_REG_FEC_CTRL		0x00ab
+#define MDIO_PMA_LASI_RXCTRL		0x9000
+#define MDIO_PMA_LASI_TXCTRL		0x9001
+#define MDIO_PMA_LASI_CTRL		0x9002
+#define MDIO_PMA_LASI_RXSTAT		0x9003
+#define MDIO_PMA_LASI_TXSTAT		0x9004
+#define MDIO_PMA_LASI_STAT		0x9005
+#define MDIO_PMA_REG_PHY_IDENTIFIER	0xc800
+#define MDIO_PMA_REG_DIGITAL_CTRL	0xc808
+#define MDIO_PMA_REG_DIGITAL_STATUS	0xc809
+#define MDIO_PMA_REG_TX_POWER_DOWN	0xca02
+#define MDIO_PMA_REG_CMU_PLL_BYPASS	0xca09
+#define MDIO_PMA_REG_MISC_CTRL		0xca0a
+#define MDIO_PMA_REG_GEN_CTRL		0xca10
+#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP	0x0188
+#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET		0x018a
+#define MDIO_PMA_REG_M8051_MSGIN_REG	0xca12
+#define MDIO_PMA_REG_M8051_MSGOUT_REG	0xca13
+#define MDIO_PMA_REG_ROM_VER1		0xca19
+#define MDIO_PMA_REG_ROM_VER2		0xca1a
+#define MDIO_PMA_REG_EDC_FFE_MAIN	0xca1b
+#define MDIO_PMA_REG_PLL_BANDWIDTH	0xca1d
+#define MDIO_PMA_REG_PLL_CTRL		0xca1e
+#define MDIO_PMA_REG_MISC_CTRL0		0xca23
+#define MDIO_PMA_REG_LRM_MODE		0xca3f
+#define MDIO_PMA_REG_CDR_BANDWIDTH	0xca46
+#define MDIO_PMA_REG_MISC_CTRL1		0xca85
+
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL		0x8000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK	0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE		0x0000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE	0x0004
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS	0x0008
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED		0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT	0x8002
+#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR	0x8003
+#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF	0xc820
+#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
+#define MDIO_PMA_REG_8726_TX_CTRL1		0xca01
+#define MDIO_PMA_REG_8726_TX_CTRL2		0xca05
+
+#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR	0x8005
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF	0x8007
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
+#define MDIO_PMA_REG_8727_MISC_CTRL		0x8309
+#define MDIO_PMA_REG_8727_TX_CTRL1		0xca02
+#define MDIO_PMA_REG_8727_TX_CTRL2		0xca05
+#define MDIO_PMA_REG_8727_PCS_OPT_CTRL		0xc808
+#define MDIO_PMA_REG_8727_GPIO_CTRL		0xc80e
+#define MDIO_PMA_REG_8727_PCS_GP		0xc842
+#define MDIO_PMA_REG_8727_OPT_CFG_REG		0xc8e4
+
+#define MDIO_AN_REG_8727_MISC_CTRL		0x8309
+#define MDIO_PMA_REG_8073_CHIP_REV			0xc801
+#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS		0xc820
+#define MDIO_PMA_REG_8073_XAUI_WA			0xc841
+#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL		0xcd08
+
+#define MDIO_PMA_REG_7101_RESET		0xc000
+#define MDIO_PMA_REG_7107_LED_CNTL	0xc007
+#define MDIO_PMA_REG_7107_LINK_LED_CNTL	0xc009
+#define MDIO_PMA_REG_7101_VER1		0xc026
+#define MDIO_PMA_REG_7101_VER2		0xc027
+
+#define MDIO_PMA_REG_8481_PMD_SIGNAL	0xa811
+#define MDIO_PMA_REG_8481_LED1_MASK	0xa82c
+#define MDIO_PMA_REG_8481_LED2_MASK	0xa82f
+#define MDIO_PMA_REG_8481_LED3_MASK	0xa832
+#define MDIO_PMA_REG_8481_LED3_BLINK	0xa834
+#define MDIO_PMA_REG_8481_LED5_MASK			0xa838
+#define MDIO_PMA_REG_8481_SIGNAL_MASK	0xa835
+#define MDIO_PMA_REG_8481_LINK_SIGNAL	0xa83b
+#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK	0x800
+#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT	11
+
+
+#define MDIO_WIS_DEVAD			0x2
+/*bcm*/
+#define MDIO_WIS_REG_LASI_CNTL		0x9002
+#define MDIO_WIS_REG_LASI_STATUS	0x9005
+
+#define MDIO_PCS_DEVAD			0x3
+#define MDIO_PCS_REG_STATUS		0x0020
+#define MDIO_PCS_REG_LASI_STATUS	0x9005
+#define MDIO_PCS_REG_7101_DSP_ACCESS	0xD000
+#define MDIO_PCS_REG_7101_SPI_MUX	0xD008
+#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR	0xE12A
+#define MDIO_PCS_REG_7101_SPI_RESET_BIT	(5)
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR	0xE02A
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD	 (0xC7)
+#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
+#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
+
+
+#define MDIO_XS_DEVAD			0x4
+#define MDIO_XS_REG_STATUS		0x0001
+#define MDIO_XS_PLL_SEQUENCER		0x8000
+#define MDIO_XS_SFX7101_XGXS_TEST1	0xc00a
+
+#define MDIO_XS_8706_REG_BANK_RX0	0x80bc
+#define MDIO_XS_8706_REG_BANK_RX1	0x80cc
+#define MDIO_XS_8706_REG_BANK_RX2	0x80dc
+#define MDIO_XS_8706_REG_BANK_RX3	0x80ec
+#define MDIO_XS_8706_REG_BANK_RXA	0x80fc
+
+#define MDIO_XS_REG_8073_RX_CTRL_PCIE	0x80FA
+
+#define MDIO_AN_DEVAD			0x7
+/*ieee*/
+#define MDIO_AN_REG_CTRL		0x0000
+#define MDIO_AN_REG_STATUS		0x0001
+#define MDIO_AN_REG_STATUS_AN_COMPLETE		0x0020
+#define MDIO_AN_REG_ADV_PAUSE		0x0010
+#define MDIO_AN_REG_ADV_PAUSE_PAUSE		0x0400
+#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC	0x0800
+#define MDIO_AN_REG_ADV_PAUSE_BOTH		0x0C00
+#define MDIO_AN_REG_ADV_PAUSE_MASK		0x0C00
+#define MDIO_AN_REG_ADV			0x0011
+#define MDIO_AN_REG_ADV2		0x0012
+#define MDIO_AN_REG_LP_AUTO_NEG		0x0013
+#define MDIO_AN_REG_LP_AUTO_NEG2	0x0014
+#define MDIO_AN_REG_MASTER_STATUS	0x0021
+#define MDIO_AN_REG_EEE_ADV		0x003c
+#define MDIO_AN_REG_LP_EEE_ADV		0x003d
+/*bcm*/
+#define MDIO_AN_REG_LINK_STATUS		0x8304
+#define MDIO_AN_REG_CL37_CL73		0x8370
+#define MDIO_AN_REG_CL37_AN		0xffe0
+#define MDIO_AN_REG_CL37_FC_LD		0xffe4
+#define		MDIO_AN_REG_CL37_FC_LP		0xffe5
+#define		MDIO_AN_REG_1000T_STATUS	0xffea
+
+#define MDIO_AN_REG_8073_2_5G		0x8329
+#define MDIO_AN_REG_8073_BAM		0x8350
+
+#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL	0x0020
+#define MDIO_AN_REG_8481_LEGACY_MII_CTRL	0xffe0
+#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G	0x40
+#define MDIO_AN_REG_8481_LEGACY_MII_STATUS	0xffe1
+#define MDIO_AN_REG_8481_LEGACY_AN_ADV		0xffe4
+#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION	0xffe6
+#define MDIO_AN_REG_8481_1000T_CTRL		0xffe9
+#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL	0xfff0
+#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF	0x0008
+#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW	0xfff5
+#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS	0xfff7
+#define MDIO_AN_REG_8481_AUX_CTRL		0xfff8
+#define MDIO_AN_REG_8481_LEGACY_SHADOW		0xfffc
+
+/* BCM84823 only */
+#define MDIO_CTL_DEVAD			0x1e
+#define MDIO_CTL_REG_84823_MEDIA		0x401a
+#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK		0x0018
+	/* These pins configure the BCM84823 interface to MAC after reset. */
+#define MDIO_CTL_REG_84823_CTRL_MAC_XFI			0x0008
+#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M		0x0010
+	/* These pins configure the BCM84823 interface to Line after reset. */
+#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK		0x0060
+#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L		0x0020
+#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI		0x0040
+	/* When this pin is active high during reset, 10GBASE-T core is power
+	 * down, When it is active low the 10GBASE-T is power up
+	 */
+#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN	0x0080
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK		0x0100
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER	0x0000
+#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER		0x0100
+#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G			0x1000
+#define MDIO_CTL_REG_84823_USER_CTRL_REG			0x4005
+#define MDIO_CTL_REG_84823_USER_CTRL_CMS			0x0080
+#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH		0xa82b
+#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ	0x2f
+#define MDIO_PMA_REG_84823_CTL_LED_CTL_1			0xa8e3
+#define MDIO_PMA_REG_84833_CTL_LED_CTL_1			0xa8ec
+#define MDIO_PMA_REG_84823_LED3_STRETCH_EN			0x0080
+
+/* BCM84833 only */
+#define MDIO_84833_TOP_CFG_FW_REV			0x400f
+#define MDIO_84833_TOP_CFG_FW_EEE		0x10b1
+#define MDIO_84833_TOP_CFG_FW_NO_EEE		0x1f81
+#define MDIO_84833_TOP_CFG_XGPHY_STRAP1			0x401a
+#define MDIO_84833_SUPER_ISOLATE		0x8000
+/* These are mailbox register set used by 84833. */
+#define MDIO_84833_TOP_CFG_SCRATCH_REG0			0x4005
+#define MDIO_84833_TOP_CFG_SCRATCH_REG1			0x4006
+#define MDIO_84833_TOP_CFG_SCRATCH_REG2			0x4007
+#define MDIO_84833_TOP_CFG_SCRATCH_REG3			0x4008
+#define MDIO_84833_TOP_CFG_SCRATCH_REG4			0x4009
+#define MDIO_84833_TOP_CFG_SCRATCH_REG26		0x4037
+#define MDIO_84833_TOP_CFG_SCRATCH_REG27		0x4038
+#define MDIO_84833_TOP_CFG_SCRATCH_REG28		0x4039
+#define MDIO_84833_TOP_CFG_SCRATCH_REG29		0x403a
+#define MDIO_84833_TOP_CFG_SCRATCH_REG30		0x403b
+#define MDIO_84833_TOP_CFG_SCRATCH_REG31		0x403c
+#define MDIO_84833_CMD_HDLR_COMMAND	MDIO_84833_TOP_CFG_SCRATCH_REG0
+#define MDIO_84833_CMD_HDLR_STATUS	MDIO_84833_TOP_CFG_SCRATCH_REG26
+#define MDIO_84833_CMD_HDLR_DATA1	MDIO_84833_TOP_CFG_SCRATCH_REG27
+#define MDIO_84833_CMD_HDLR_DATA2	MDIO_84833_TOP_CFG_SCRATCH_REG28
+#define MDIO_84833_CMD_HDLR_DATA3	MDIO_84833_TOP_CFG_SCRATCH_REG29
+#define MDIO_84833_CMD_HDLR_DATA4	MDIO_84833_TOP_CFG_SCRATCH_REG30
+#define MDIO_84833_CMD_HDLR_DATA5	MDIO_84833_TOP_CFG_SCRATCH_REG31
+
+/* Mailbox command set used by 84833. */
+#define PHY84833_CMD_SET_PAIR_SWAP			0x8001
+#define PHY84833_CMD_GET_EEE_MODE			0x8008
+#define PHY84833_CMD_SET_EEE_MODE			0x8009
+#define PHY84833_CMD_GET_CURRENT_TEMP			0x8031
+/* Mailbox status set used by 84833. */
+#define PHY84833_STATUS_CMD_RECEIVED			0x0001
+#defin