From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 07CD511C5 for ; Thu, 5 Mar 2015 17:55:42 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 05 Mar 2015 08:55:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,348,1422950400"; d="scan'208";a="675674230" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 05 Mar 2015 08:55:40 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t25GtbJa000493; Fri, 6 Mar 2015 00:55:37 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t25GtaFi016054; Fri, 6 Mar 2015 00:55:38 +0800 Received: (from dayuqiu@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t25GtY19016050; Fri, 6 Mar 2015 00:55:34 +0800 From: Michael Qiu To: dev@dpdk.org Date: Fri, 6 Mar 2015 00:55:30 +0800 Message-Id: <1425574530-16019-1-git-send-email-michael.qiu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1425561339-13300-2-git-send-email-michael.qiu@intel.com> References: <1425561339-13300-2-git-send-email-michael.qiu@intel.com> Subject: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Mar 2015 16:55:43 -0000 CC rte_hash.o Error: unsupported instruction `crc32' The root cause is that i686 platform does not support 'crc32q' Need make it only available in x86_64 platform Signed-off-by: Michael Qiu --- v2 --> v1: Make crc32 instruction only works in X86 platform lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h index d28bb2a..c0a789e 100644 --- a/lib/librte_hash/rte_hash_crc.h +++ b/lib/librte_hash/rte_hash_crc.h @@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val) return crc; } +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64 static inline uint32_t crc32c_sse42_u32(uint32_t data, uint32_t init_val) { @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val) : [data] "rm" (data)); return init_val; } +#endif +#ifdef RTE_ARCH_X86_64 static inline uint32_t crc32c_sse42_u64(uint64_t data, uint64_t init_val) { @@ -383,7 +386,9 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val) : [data] "rm" (data)); return init_val; } +#endif +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64 static inline uint32_t crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) { @@ -397,6 +402,7 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) init_val = crc32c_sse42_u32(d.u32[1], init_val); return init_val; } +#endif #define CRC32_SW (1U << 0) #define CRC32_SSE42 (1U << 1) @@ -455,8 +461,10 @@ rte_hash_crc_init_alg(void) static inline uint32_t rte_hash_crc_4byte(uint32_t data, uint32_t init_val) { +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u32(data, init_val); +#endif return crc32c_1word(data, init_val); } @@ -476,11 +484,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) static inline uint32_t rte_hash_crc_8byte(uint64_t data, uint32_t init_val) { +#ifdef RTE_ARCH_X86_64 if (likely(crc32_alg == CRC32_SSE42_x64)) return crc32c_sse42_u64(data, init_val); +#endif +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u64_mimic(data, init_val); +#endif return crc32c_2words(data, init_val); } -- 1.9.3