From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 46D8A379E for ; Mon, 23 Mar 2015 09:43:16 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP; 23 Mar 2015 01:43:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,451,1422950400"; d="scan'208";a="544827004" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga003.jf.intel.com with ESMTP; 23 Mar 2015 01:43:14 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t2N8hChh020891; Mon, 23 Mar 2015 16:43:12 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t2N8h9sb024566; Mon, 23 Mar 2015 16:43:11 +0800 Received: (from dayuqiu@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t2N8h8Cs024562; Mon, 23 Mar 2015 16:43:08 +0800 From: Michael Qiu To: dev@dpdk.org Date: Mon, 23 Mar 2015 16:43:07 +0800 Message-Id: <1427100187-24532-1-git-send-email-michael.qiu@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dpdk-dev] [PATCH] librte_hash: Fix crc32 error when complie i686 in x86_64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Mar 2015 08:43:16 -0000 When compile target i686 in platform x86_64, the stud fuction will be called, and return zero. This patch fix this issue. Signed-off-by: Michael Qiu --- lib/librte_hash/rte_hash_crc.h | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-) diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h index 3dcd362..1cd626c 100644 --- a/lib/librte_hash/rte_hash_crc.h +++ b/lib/librte_hash/rte_hash_crc.h @@ -366,7 +366,6 @@ crc32c_2words(uint64_t data, uint32_t init_val) } #if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64) - static inline uint32_t crc32c_sse42_u32(uint32_t data, uint32_t init_val) { @@ -390,27 +389,9 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) init_val = crc32c_sse42_u32(d.u32[1], init_val); return init_val; } - -#else - -static inline uint32_t -crc32c_sse42_u32(__rte_unused uint32_t data, - __rte_unused uint32_t init_val) -{ - return 0; -} - -static inline uint32_t -crc32c_sse42_u64_mimic(__rte_unused uint32_t data, - __rte_unused uint32_t init_val) -{ - return 0; -} - #endif #ifdef RTE_ARCH_X86_64 - static inline uint32_t crc32c_sse42_u64(uint64_t data, uint64_t init_val) { @@ -420,16 +401,6 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val) : [data] "rm" (data)); return init_val; } - -#else - -static inline uint32_t -crc32c_sse42_u64(__rte_unused uint64_t data, - __rte_unused uint64_t init_val) -{ - return 0; -} - #endif #define CRC32_SW (1U << 0) @@ -489,8 +460,10 @@ rte_hash_crc_init_alg(void) static inline uint32_t rte_hash_crc_4byte(uint32_t data, uint32_t init_val) { +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u32(data, init_val); +#endif return crc32c_1word(data, init_val); } @@ -510,11 +483,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) static inline uint32_t rte_hash_crc_8byte(uint64_t data, uint32_t init_val) { +#ifdef RTE_ARCH_X86_64 if (likely(crc32_alg == CRC32_SSE42_x64)) return crc32c_sse42_u64(data, init_val); +#endif +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u64_mimic(data, init_val); +#endif return crc32c_2words(data, init_val); } -- 1.9.3