From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 155F5CCE6 for ; Thu, 30 Apr 2015 17:05:53 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 30 Apr 2015 08:04:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,677,1422950400"; d="scan'208";a="487716032" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 30 Apr 2015 08:04:40 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t3UF4bQW029640; Thu, 30 Apr 2015 23:04:37 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t3UF4YPZ024105; Thu, 30 Apr 2015 23:04:36 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t3UF4YWM024101; Thu, 30 Apr 2015 23:04:34 +0800 From: Helin Zhang To: dev@dpdk.org Date: Thu, 30 Apr 2015 23:03:30 +0800 Message-Id: <1430406219-23901-25-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1430406219-23901-1-git-send-email-helin.zhang@intel.com> References: <1429518150-28098-1-git-send-email-helin.zhang@intel.com> <1430406219-23901-1-git-send-email-helin.zhang@intel.com> Cc: monica.kenguva@intel.com, steven.j.murray@intel.com, shannon.nelson@intel.com Subject: [dpdk-dev] [PATCH v2 24/33] i40e/base: get pf_id from HW rather than PCI function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Apr 2015 15:05:54 -0000 Getting the pf_id from the function number was a good place to start, but when the PF was setup in pass-thru mode, the PCI bus/device/function was virtualized and the number in the VM is different from the number in the bare metal. This caused HW configuration issues when the wrong pf_id was used to set up the HMC and other structures. The PF_FUNC_RID register has the real bus/device/function information as configured by the BIOS, so use that for a better number. Signed-off-by: Helin Zhang --- lib/librte_pmd_i40e/i40e/i40e_common.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/lib/librte_pmd_i40e/i40e/i40e_common.c b/lib/librte_pmd_i40e/i40e/i40e_common.c index 705b9dd..03980b9 100644 --- a/lib/librte_pmd_i40e/i40e/i40e_common.c +++ b/lib/librte_pmd_i40e/i40e/i40e_common.c @@ -592,7 +592,7 @@ enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) { enum i40e_status_code status = I40E_SUCCESS; - u32 reg; + u32 port, ari, func_rid; DEBUGFUNC("i40e_init_shared_code"); @@ -607,18 +607,17 @@ enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) hw->phy.get_link_info = true; - /* Determine port number */ - reg = rd32(hw, I40E_PFGEN_PORTNUM); - reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >> - I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT); - hw->port = (u8)reg; - - /* Determine the PF number based on the PCI fn */ - reg = rd32(hw, I40E_GLPCI_CAPSUP); - if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK) - hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func); + /* Determine port number and PF number*/ + port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) + >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; + hw->port = (u8)port; + ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> + I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; + func_rid = rd32(hw, I40E_PF_FUNC_RID); + if (ari) + hw->pf_id = (u8)(func_rid & 0xff); else - hw->pf_id = (u8)hw->bus.func; + hw->pf_id = (u8)(func_rid & 0x7); status = i40e_init_nvm(hw); return status; -- 1.8.1.4