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[50.53.82.155]) by mx.google.com with ESMTPSA id ki3sm3203006pdb.74.2015.05.07.16.25.36 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 May 2015 16:25:37 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Date: Thu, 7 May 2015 16:25:34 -0700 Message-Id: <1431041135-6289-4-git-send-email-stephen@networkplumber.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1431041135-6289-1-git-send-email-stephen@networkplumber.org> References: <1431041135-6289-1-git-send-email-stephen@networkplumber.org> X-Mailman-Approved-At: Fri, 08 May 2015 01:45:55 +0200 Subject: [dpdk-dev] [PATCH 3/4] bnx2x: new poll mode driver (part2) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 May 2015 23:25:43 -0000 From: Sergey Kreys Add driver for the Broadcom NetXtremeII 10 gigabit devices. Signed-off-by: Stephen Hemminger --- v3 - this is same as previous bcm driver just renamed v4 - split into two pieces for review. --- lib/librte_pmd_bnx2x/debug.c | 113 + lib/librte_pmd_bnx2x/ecore_fw_defs.h | 422 + lib/librte_pmd_bnx2x/ecore_hsi.h | 6348 +++++++++++++++ lib/librte_pmd_bnx2x/ecore_init.h | 841 ++ lib/librte_pmd_bnx2x/ecore_init_ops.h | 886 +++ lib/librte_pmd_bnx2x/ecore_mfw_req.h | 206 + lib/librte_pmd_bnx2x/ecore_reg.h | 3663 +++++++++ lib/librte_pmd_bnx2x/ecore_sp.c | 5455 +++++++++++++ lib/librte_pmd_bnx2x/ecore_sp.h | 1795 +++++ lib/librte_pmd_bnx2x/elink.c | 13378 ++++++++++++++++++++++++++++++++ lib/librte_pmd_bnx2x/elink.h | 609 ++ 11 files changed, 33716 insertions(+) create mode 100644 lib/librte_pmd_bnx2x/debug.c create mode 100644 lib/librte_pmd_bnx2x/ecore_fw_defs.h create mode 100644 lib/librte_pmd_bnx2x/ecore_hsi.h create mode 100644 lib/librte_pmd_bnx2x/ecore_init.h create mode 100644 lib/librte_pmd_bnx2x/ecore_init_ops.h create mode 100644 lib/librte_pmd_bnx2x/ecore_mfw_req.h create mode 100644 lib/librte_pmd_bnx2x/ecore_reg.h create mode 100644 lib/librte_pmd_bnx2x/ecore_sp.c create mode 100644 lib/librte_pmd_bnx2x/ecore_sp.h create mode 100644 lib/librte_pmd_bnx2x/elink.c create mode 100644 lib/librte_pmd_bnx2x/elink.h diff --git a/lib/librte_pmd_bnx2x/debug.c b/lib/librte_pmd_bnx2x/debug.c new file mode 100644 index 0000000..ba51f1a --- /dev/null +++ b/lib/librte_pmd_bnx2x/debug.c @@ -0,0 +1,113 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "bnx2x.h" + + +/* + * Debug versions of the 8/16/32 bit OS register read/write functions to + * capture/display values read/written from/to the controller. + */ +void +bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) +{ + PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val); + *((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val; +} + +void +bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) +{ + if ((offset % 2) != 0) { + PMD_DRV_LOG(DEBUG, "Unaligned 16-bit write to 0x%08lx", offset); + } + + PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%04x", offset, val); + *((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val; +} + +void +bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) +{ + if ((offset % 4) != 0) { + PMD_DRV_LOG(DEBUG, "Unaligned 32-bit write to 0x%08lx", offset); + } + + PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val); + *((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val; +} + +uint8_t +bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) +{ + uint8_t val; + + val = (uint8_t)(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))); + PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val); + + return (val); +} + +uint16_t +bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) +{ + uint16_t val; + + if ((offset % 2) != 0) { + PMD_DRV_LOG(DEBUG, "Unaligned 16-bit read from 0x%08lx", offset); + } + + val = (uint16_t)(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))); + PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val); + + return (val); +} + +uint32_t +bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) +{ + uint32_t val; + + if ((offset % 4) != 0) { + PMD_DRV_LOG(DEBUG, "Unaligned 32-bit read from 0x%08lx", offset); + return 0; + } + + val = (uint32_t)(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset))); + PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val); + + return (val); +} diff --git a/lib/librte_pmd_bnx2x/ecore_fw_defs.h b/lib/librte_pmd_bnx2x/ecore_fw_defs.h new file mode 100644 index 0000000..0e39e15 --- /dev/null +++ b/lib/librte_pmd_bnx2x/ecore_fw_defs.h @@ -0,0 +1,422 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ECORE_FW_DEFS_H +#define ECORE_FW_DEFS_H + + +#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base) +#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ + (IRO[147].base + ((assertListEntry) * IRO[147].m1)) +#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ + (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \ + IRO[153].m2)) +#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ + (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \ + IRO[154].m2)) +#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \ + (IRO[155].base + ((vfId) * IRO[155].m1)) +#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \ + (IRO[156].base + ((vfId) * IRO[156].m1)) +#define CSTORM_VF_TO_PF_OFFSET(funcId) \ + (IRO[150].base + ((funcId) * IRO[150].m1)) +#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ + (IRO[159].base + ((funcId) * IRO[159].m1)) +#define CSTORM_FUNC_EN_OFFSET(funcId) \ + (IRO[149].base + ((funcId) * IRO[149].m1)) +#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \ + (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2)) +#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \ + (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \ + * IRO[138].m2) + ((sbId) * IRO[138].m3)) +#define CSTORM_IGU_MODE_OFFSET (IRO[157].base) +#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ + (IRO[317].base + ((pfId) * IRO[317].m1)) +#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ + (IRO[318].base + ((pfId) * IRO[318].m1)) +#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ + (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2)) +#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ + (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2)) +#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ + (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2)) +#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ + (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2)) +#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ + (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2)) +#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ + (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) +#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ + (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2)) +#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ + (IRO[316].base + ((pfId) * IRO[316].m1)) +#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ + (IRO[308].base + ((pfId) * IRO[308].m1)) +#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ + (IRO[307].base + ((pfId) * IRO[307].m1)) +#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ + (IRO[306].base + ((pfId) * IRO[306].m1)) +#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ + (IRO[151].base + ((funcId) * IRO[151].m1)) +#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ + (IRO[142].base + ((pfId) * IRO[142].m1)) +#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \ + (IRO[143].base + ((pfId) * IRO[143].m1)) +#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ + (IRO[141].base + ((pfId) * IRO[141].m1)) +#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size) +#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ + (IRO[144].base + ((pfId) * IRO[144].m1)) +#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size) +#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \ + (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2)) +#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ + (IRO[133].base + ((sbId) * IRO[133].m1)) +#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \ + (IRO[134].base + ((sbId) * IRO[134].m1)) +#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \ + (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2)) +#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ + (IRO[132].base + ((sbId) * IRO[132].m1)) +#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size) +#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ + (IRO[137].base + ((sbId) * IRO[137].m1)) +#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size) +#define CSTORM_VF_TO_PF_OFFSET(funcId) \ + (IRO[150].base + ((funcId) * IRO[150].m1)) +#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base) +#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ + (IRO[203].base + ((pfId) * IRO[203].m1)) +#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) +#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ + (IRO[101].base + ((assertListEntry) * IRO[101].m1)) +#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ + (IRO[201].base + ((pfId) * IRO[201].m1)) +#define TSTORM_FUNC_EN_OFFSET(funcId) \ + (IRO[103].base + ((funcId) * IRO[103].m1)) +#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ + (IRO[272].base + ((pfId) * IRO[272].m1)) +#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ + (IRO[271].base + ((pfId) * IRO[271].m1)) +#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ + (IRO[270].base + ((pfId) * IRO[270].m1)) +#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ + (IRO[269].base + ((pfId) * IRO[269].m1)) +#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ + (IRO[268].base + ((pfId) * IRO[268].m1)) +#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ + (IRO[278].base + ((pfId) * IRO[278].m1)) +#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ + (IRO[264].base + ((pfId) * IRO[264].m1)) +#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ + (IRO[265].base + ((pfId) * IRO[265].m1)) +#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \ + (IRO[266].base + ((pfId) * IRO[266].m1)) +#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ + (IRO[267].base + ((pfId) * IRO[267].m1)) +#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ + (IRO[202].base + ((pfId) * IRO[202].m1)) +#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ + (IRO[105].base + ((funcId) * IRO[105].m1)) +#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ + (IRO[217].base + ((pfId) * IRO[217].m1)) +#define TSTORM_VF_TO_PF_OFFSET(funcId) \ + (IRO[104].base + ((funcId) * IRO[104].m1)) +#define USTORM_AGG_DATA_OFFSET (IRO[206].base) +#define USTORM_AGG_DATA_SIZE (IRO[206].size) +#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base) +#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ + (IRO[176].base + ((assertListEntry) * IRO[176].m1)) +#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \ + (IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * IRO[205].m2)) +#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ + (IRO[183].base + ((portId) * IRO[183].m1)) +#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ + (IRO[319].base + ((pfId) * IRO[319].m1)) +#define USTORM_FUNC_EN_OFFSET(funcId) \ + (IRO[178].base + ((funcId) * IRO[178].m1)) +#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ + (IRO[283].base + ((pfId) * IRO[283].m1)) +#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ + (IRO[284].base + ((pfId) * IRO[284].m1)) +#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ + (IRO[288].base + ((pfId) * IRO[288].m1)) +#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ + (IRO[285].base + ((pfId) * IRO[285].m1)) +#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ + (IRO[281].base + ((pfId) * IRO[281].m1)) +#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ + (IRO[280].base + ((pfId) * IRO[280].m1)) +#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ + (IRO[279].base + ((pfId) * IRO[279].m1)) +#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ + (IRO[282].base + ((pfId) * IRO[282].m1)) +#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ + (IRO[286].base + ((pfId) * IRO[286].m1)) +#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ + (IRO[287].base + ((pfId) * IRO[287].m1)) +#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ + (IRO[182].base + ((pfId) * IRO[182].m1)) +#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ + (IRO[180].base + ((funcId) * IRO[180].m1)) +#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ + (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \ + IRO[209].m2)) +#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ + (IRO[210].base + ((qzoneId) * IRO[210].m1)) +#define USTORM_TPA_BTR_OFFSET (IRO[207].base) +#define USTORM_TPA_BTR_SIZE (IRO[207].size) +#define USTORM_VF_TO_PF_OFFSET(funcId) \ + (IRO[179].base + ((funcId) * IRO[179].m1)) +#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base) +#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base) +#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base) +#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ + (IRO[50].base + ((assertListEntry) * IRO[50].m1)) +#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \ + (IRO[43].base + ((portId) * IRO[43].m1)) +#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \ + (IRO[45].base + ((pfId) * IRO[45].m1)) +#define XSTORM_FUNC_EN_OFFSET(funcId) \ + (IRO[47].base + ((funcId) * IRO[47].m1)) +#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ + (IRO[296].base + ((pfId) * IRO[296].m1)) +#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ + (IRO[299].base + ((pfId) * IRO[299].m1)) +#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ + (IRO[300].base + ((pfId) * IRO[300].m1)) +#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ + (IRO[301].base + ((pfId) * IRO[301].m1)) +#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ + (IRO[302].base + ((pfId) * IRO[302].m1)) +#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ + (IRO[303].base + ((pfId) * IRO[303].m1)) +#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ + (IRO[304].base + ((pfId) * IRO[304].m1)) +#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ + (IRO[305].base + ((pfId) * IRO[305].m1)) +#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ + (IRO[295].base + ((pfId) * IRO[295].m1)) +#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ + (IRO[294].base + ((pfId) * IRO[294].m1)) +#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ + (IRO[293].base + ((pfId) * IRO[293].m1)) +#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ + (IRO[298].base + ((pfId) * IRO[298].m1)) +#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ + (IRO[297].base + ((pfId) * IRO[297].m1)) +#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ + (IRO[292].base + ((pfId) * IRO[292].m1)) +#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ + (IRO[291].base + ((pfId) * IRO[291].m1)) +#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ + (IRO[290].base + ((pfId) * IRO[290].m1)) +#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ + (IRO[289].base + ((pfId) * IRO[289].m1)) +#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ + (IRO[44].base + ((pfId) * IRO[44].m1)) +#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ + (IRO[49].base + ((funcId) * IRO[49].m1)) +#define XSTORM_SPQ_DATA_OFFSET(funcId) \ + (IRO[32].base + ((funcId) * IRO[32].m1)) +#define XSTORM_SPQ_DATA_SIZE (IRO[32].size) +#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \ + (IRO[30].base + ((funcId) * IRO[30].m1)) +#define XSTORM_SPQ_PROD_OFFSET(funcId) \ + (IRO[31].base + ((funcId) * IRO[31].m1)) +#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ + (IRO[211].base + ((portId) * IRO[211].m1)) +#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ + (IRO[212].base + ((portId) * IRO[212].m1)) +#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ + (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \ + IRO[214].m2)) +#define XSTORM_VF_TO_PF_OFFSET(funcId) \ + (IRO[48].base + ((funcId) * IRO[48].m1)) +#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base) + + +/* Ethernet Ring parameters */ +#define X_ETH_LOCAL_RING_SIZE 13 +#define FIRST_BD_IN_PKT 0 +#define PARSE_BD_INDEX 1 +#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) + +/* Rx ring params */ +#define U_ETH_LOCAL_BD_RING_SIZE 8 +#define U_ETH_SGL_SIZE 8 + /* The fw will padd the buffer with this value, so the IP header \ + will be align to 4 Byte */ +#define IP_HEADER_ALIGNMENT_PADDING 2 + +#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) +#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) + +#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) +#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) + +#define U_ETH_UNDEFINED_Q 0xFF + +#define T_ETH_INDIRECTION_TABLE_SIZE 128 +#define T_ETH_RSS_KEY 10 +#define ETH_NUM_OF_RSS_ENGINES_E2 72 + +#define FILTER_RULES_COUNT 16 +#define MULTICAST_RULES_COUNT 16 +#define CLASSIFY_RULES_COUNT 16 + +/*The CRC32 seed, that is used for the hash(reduction) multicast address */ +#define ETH_CRC32_HASH_SEED 0x00000000 + +#define ETH_CRC32_HASH_BIT_SIZE (8) +#define ETH_CRC32_HASH_MASK EVAL((1< + * David Christensen + * Gary Zambrano + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ECORE_HSI_H +#define ECORE_HSI_H + +#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e + +struct license_key { + uint32_t reserved[6]; + + uint32_t max_iscsi_conn; +#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF +#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0 +#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 +#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16 + + uint32_t reserved_a; + + uint32_t max_fcoe_conn; +#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF +#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0 +#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 +#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16 + + uint32_t reserved_b[4]; +}; + +typedef struct license_key license_key_t; + + +/**************************************************************************** + * Shared HW configuration * + ****************************************************************************/ +#define PIN_CFG_NA 0x00000000 +#define PIN_CFG_GPIO0_P0 0x00000001 +#define PIN_CFG_GPIO1_P0 0x00000002 +#define PIN_CFG_GPIO2_P0 0x00000003 +#define PIN_CFG_GPIO3_P0 0x00000004 +#define PIN_CFG_GPIO0_P1 0x00000005 +#define PIN_CFG_GPIO1_P1 0x00000006 +#define PIN_CFG_GPIO2_P1 0x00000007 +#define PIN_CFG_GPIO3_P1 0x00000008 +#define PIN_CFG_EPIO0 0x00000009 +#define PIN_CFG_EPIO1 0x0000000a +#define PIN_CFG_EPIO2 0x0000000b +#define PIN_CFG_EPIO3 0x0000000c +#define PIN_CFG_EPIO4 0x0000000d +#define PIN_CFG_EPIO5 0x0000000e +#define PIN_CFG_EPIO6 0x0000000f +#define PIN_CFG_EPIO7 0x00000010 +#define PIN_CFG_EPIO8 0x00000011 +#define PIN_CFG_EPIO9 0x00000012 +#define PIN_CFG_EPIO10 0x00000013 +#define PIN_CFG_EPIO11 0x00000014 +#define PIN_CFG_EPIO12 0x00000015 +#define PIN_CFG_EPIO13 0x00000016 +#define PIN_CFG_EPIO14 0x00000017 +#define PIN_CFG_EPIO15 0x00000018 +#define PIN_CFG_EPIO16 0x00000019 +#define PIN_CFG_EPIO17 0x0000001a +#define PIN_CFG_EPIO18 0x0000001b +#define PIN_CFG_EPIO19 0x0000001c +#define PIN_CFG_EPIO20 0x0000001d +#define PIN_CFG_EPIO21 0x0000001e +#define PIN_CFG_EPIO22 0x0000001f +#define PIN_CFG_EPIO23 0x00000020 +#define PIN_CFG_EPIO24 0x00000021 +#define PIN_CFG_EPIO25 0x00000022 +#define PIN_CFG_EPIO26 0x00000023 +#define PIN_CFG_EPIO27 0x00000024 +#define PIN_CFG_EPIO28 0x00000025 +#define PIN_CFG_EPIO29 0x00000026 +#define PIN_CFG_EPIO30 0x00000027 +#define PIN_CFG_EPIO31 0x00000028 + +/* EPIO definition */ +#define EPIO_CFG_NA 0x00000000 +#define EPIO_CFG_EPIO0 0x00000001 +#define EPIO_CFG_EPIO1 0x00000002 +#define EPIO_CFG_EPIO2 0x00000003 +#define EPIO_CFG_EPIO3 0x00000004 +#define EPIO_CFG_EPIO4 0x00000005 +#define EPIO_CFG_EPIO5 0x00000006 +#define EPIO_CFG_EPIO6 0x00000007 +#define EPIO_CFG_EPIO7 0x00000008 +#define EPIO_CFG_EPIO8 0x00000009 +#define EPIO_CFG_EPIO9 0x0000000a +#define EPIO_CFG_EPIO10 0x0000000b +#define EPIO_CFG_EPIO11 0x0000000c +#define EPIO_CFG_EPIO12 0x0000000d +#define EPIO_CFG_EPIO13 0x0000000e +#define EPIO_CFG_EPIO14 0x0000000f +#define EPIO_CFG_EPIO15 0x00000010 +#define EPIO_CFG_EPIO16 0x00000011 +#define EPIO_CFG_EPIO17 0x00000012 +#define EPIO_CFG_EPIO18 0x00000013 +#define EPIO_CFG_EPIO19 0x00000014 +#define EPIO_CFG_EPIO20 0x00000015 +#define EPIO_CFG_EPIO21 0x00000016 +#define EPIO_CFG_EPIO22 0x00000017 +#define EPIO_CFG_EPIO23 0x00000018 +#define EPIO_CFG_EPIO24 0x00000019 +#define EPIO_CFG_EPIO25 0x0000001a +#define EPIO_CFG_EPIO26 0x0000001b +#define EPIO_CFG_EPIO27 0x0000001c +#define EPIO_CFG_EPIO28 0x0000001d +#define EPIO_CFG_EPIO29 0x0000001e +#define EPIO_CFG_EPIO30 0x0000001f +#define EPIO_CFG_EPIO31 0x00000020 + +struct mac_addr { + uint32_t upper; + uint32_t lower; +}; + + +struct shared_hw_cfg { /* NVRAM Offset */ + /* Up to 16 bytes of NULL-terminated string */ + uint8_t part_num[16]; /* 0x104 */ + + uint32_t config; /* 0x114 */ + #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 + #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 + #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 + #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 + + #define SHARED_HW_CFG_PORT_SWAP 0x00000004 + + #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 + + #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 + #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 + + #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 + #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 + /* Whatever MFW found in NVM + (if multiple found, priority order is: NC-SI, UMP, IPMI) */ + #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 + #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 + #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 + #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 + /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI + (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ + #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 + /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI + (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ + #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 + /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP + (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ + #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 + + /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For + backwards compatibility, value of 0 is disabling this feature. + That means that though 0 is a valid value, it cannot be + configured. */ + #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 + #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 + + #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 + #define SHARED_HW_CFG_LED_MODE_SHIFT 16 + #define SHARED_HW_CFG_LED_MAC1 0x00000000 + #define SHARED_HW_CFG_LED_PHY1 0x00010000 + #define SHARED_HW_CFG_LED_PHY2 0x00020000 + #define SHARED_HW_CFG_LED_PHY3 0x00030000 + #define SHARED_HW_CFG_LED_MAC2 0x00040000 + #define SHARED_HW_CFG_LED_PHY4 0x00050000 + #define SHARED_HW_CFG_LED_PHY5 0x00060000 + #define SHARED_HW_CFG_LED_PHY6 0x00070000 + #define SHARED_HW_CFG_LED_MAC3 0x00080000 + #define SHARED_HW_CFG_LED_PHY7 0x00090000 + #define SHARED_HW_CFG_LED_PHY9 0x000a0000 + #define SHARED_HW_CFG_LED_PHY11 0x000b0000 + #define SHARED_HW_CFG_LED_MAC4 0x000c0000 + #define SHARED_HW_CFG_LED_PHY8 0x000d0000 + #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 + #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 + + #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 + #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 + #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 + + #define SHARED_HW_CFG_ATC_MASK 0x80000000 + #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 + #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 + + uint32_t config2; /* 0x118 */ + + #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 + #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 + #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 + #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 + + #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 + #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 + #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 + + #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 + + + /* Output low when PERST is asserted */ + #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 + #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 + #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 + + #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 + #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 + #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 + #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 + #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 + #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 + + /* The fan failure mechanism is usually related to the PHY type + since the power consumption of the board is determined by the PHY. + Currently, fan is required for most designs with SFX7101, BNX2X8727 + and BNX2X8481. If a fan is not required for a board which uses one + of those PHYs, this field should be set to "Disabled". If a fan is + required for a different PHY type, this option should be set to + "Enabled". The fan failure indication is expected on SPIO5 */ + #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 + #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 + #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 + #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 + #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 + + /* ASPM Power Management support */ + #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 + #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 + #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 + #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 + #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 + #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 + + /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register + tl_control_0 (register 0x2800) */ + #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 + #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 + #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 + + + /* Set the MDC/MDIO access for the first external phy */ + #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 + + /* Set the MDC/MDIO access for the second external phy */ + #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 + #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 + + /* Max number of PF MSIX vectors */ + uint32_t config_3; /* 0x11C */ + #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F + #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 + + uint32_t ump_nc_si_config; /* 0x120 */ + #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 + #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 + #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 + #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 + #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 + #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 + + /* Reserved bits: 226-230 */ + + /* The output pin template BSC_SEL which selects the I2C for this + port in the I2C Mux */ + uint32_t board; /* 0x124 */ + #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F + #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 + + #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 + #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 + /* Use the PIN_CFG_XXX defines on top */ + #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 + #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 + + #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 + #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 + + #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 + #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 + + uint32_t wc_lane_config; /* 0x128 */ + #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF + #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 + #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b + #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 + #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 + #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 + #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b + #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 + #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF + #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 + #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 + #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 + + /* TX lane Polarity swap */ + #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 + #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 + #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 + #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 + /* TX lane Polarity swap */ + #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 + #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 + #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 + #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 + + /* Selects the port layout of the board */ + #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 + #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 + #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 + #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 + #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 + #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 + #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 + #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 +}; + + +/**************************************************************************** + * Port HW configuration * + ****************************************************************************/ +struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ + + uint32_t pci_id; + #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF + #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 + + #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 + #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 + + uint32_t pci_sub_id; + #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF + #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 + + #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 + #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 + + uint32_t power_dissipated; + #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF + #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 + #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 + #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 + #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 + #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 + #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 + #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 + + uint32_t power_consumed; + #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF + #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 + #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 + #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 + #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 + #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 + #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 + #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 + + uint32_t mac_upper; + uint32_t mac_lower; /* 0x140 */ + #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF + #define PORT_HW_CFG_UPPERMAC_SHIFT 0 + + + uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ + uint32_t iscsi_mac_lower; + + uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */ + uint32_t rdma_mac_lower; + + uint32_t serdes_config; + #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF + #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 + + #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 + #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 + + + /* Default values: 2P-64, 4P-32 */ + uint32_t reserved; + + uint32_t vf_config; /* 0x15C */ + #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 + #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 + + uint32_t mf_pci_id; /* 0x160 */ + #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF + #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 + + /* Controls the TX laser of the SFP+ module */ + uint32_t sfp_ctrl; /* 0x164 */ + #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF + #define PORT_HW_CFG_TX_LASER_SHIFT 0 + #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 + #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 + #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 + #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 + #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 + + /* Controls the fault module LED of the SFP+ */ + #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 + #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 + #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 + #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 + #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 + #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 + #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 + + /* The output pin TX_DIS that controls the TX laser of the SFP+ + module. Use the PIN_CFG_XXX defines on top */ + uint32_t e3_sfp_ctrl; /* 0x168 */ + #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF + #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 + + /* The output pin for SFPP_TYPE which turns on the Fault module LED */ + #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 + #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 + + /* The input pin MOD_ABS that indicates whether SFP+ module is + present or not. Use the PIN_CFG_XXX defines on top */ + #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 + #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 + + /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ + module. Use the PIN_CFG_XXX defines on top */ + #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 + #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 + + /* + * The input pin which signals module transmit fault. Use the + * PIN_CFG_XXX defines on top + */ + uint32_t e3_cmn_pin_cfg; /* 0x16C */ + #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF + #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 + + /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on + top */ + #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 + #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 + + /* + * The output pin which powers down the PHY. Use the PIN_CFG_XXX + * defines on top + */ + #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 + #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 + + /* The output pin values BSC_SEL which selects the I2C for this port + in the I2C Mux */ + #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 + #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 + + + /* + * The input pin I_FAULT which indicate over-current has occurred. + * Use the PIN_CFG_XXX defines on top + */ + uint32_t e3_cmn_pin_cfg1; /* 0x170 */ + #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF + #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 + + /* pause on host ring */ + uint32_t generic_features; /* 0x174 */ + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 + + /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 + * LOM recommended and tested value is 0xBEB2. Using a different + * value means using a value not tested by BRCM + */ + uint32_t sfi_tap_values; /* 0x178 */ + #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF + #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 + + /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested + * value is 0x2. LOM recommended and tested value is 0x2. Using a + * different value means using a value not tested by BRCM + */ + #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 + #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 + + uint32_t reserved0[5]; /* 0x17c */ + + uint32_t aeu_int_mask; /* 0x190 */ + + uint32_t media_type; /* 0x194 */ + #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF + #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 + + #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 + #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 + + #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 + #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 + + /* 4 times 16 bits for all 4 lanes. In case external PHY is present + (not direct mode), those values will not take effect on the 4 XGXS + lanes. For some external PHYs (such as 8706 and 8726) the values + will be used to configure the external PHY in those cases, not + all 4 values are needed. */ + uint16_t xgxs_config_rx[4]; /* 0x198 */ + uint16_t xgxs_config_tx[4]; /* 0x1A0 */ + + + /* For storing FCOE mac on shared memory */ + uint32_t fcoe_fip_mac_upper; + #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff + #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 + uint32_t fcoe_fip_mac_lower; + + uint32_t fcoe_wwn_port_name_upper; + uint32_t fcoe_wwn_port_name_lower; + + uint32_t fcoe_wwn_node_name_upper; + uint32_t fcoe_wwn_node_name_lower; + + /* wwpn for npiv enabled */ + uint32_t wwpn_for_npiv_config; /* 0x1C0 */ + #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 + #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 + #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 + #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 + + /* wwpn for npiv valid addresses */ + uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */ + #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF + #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 + + struct mac_addr wwpn_for_niv_macs[16]; + + /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ + uint32_t Reserved1[14]; + + uint32_t pf_allocation; /* 0x280 */ + /* number of vfs per PF, if 0 - sriov disabled */ + #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF + #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 + + /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), + 84833 only */ + uint32_t xgbt_phy_cfg; /* 0x284 */ + #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF + #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 + + uint32_t default_cfg; /* 0x288 */ + #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 + #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 + #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 + #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 + #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 + #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 + + #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C + #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 + #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 + #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 + #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 + #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c + + #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 + #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 + #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 + #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 + #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 + #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 + + #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 + #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 + #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 + #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 + #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 + #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 + + /* When KR link is required to be set to force which is not + KR-compliant, this parameter determine what is the trigger for it. + When GPIO is selected, low input will force the speed. Currently + default speed is 1G. In the future, it may be widen to select the + forced speed in with another parameter. Note when force-1G is + enabled, it override option 56: Link Speed option. */ + #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 + #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 + #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 + #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 + #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 + /* Enable to determine with which GPIO to reset the external phy */ + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 + #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 + + /* Enable BAM on KR */ + #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 + #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 + #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 + #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 + + /* Enable Common Mode Sense */ + #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 + #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 + #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 + #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 + + /* Determine the Serdes electrical interface */ + #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 + #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 + #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 + #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 + #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 + #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 + #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 + #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 + + /* SFP+ main TAP and post TAP volumes */ + #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 + #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 + #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 + #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 + #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 + #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 + #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 + #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 + + uint32_t speed_capability_mask2; /* 0x28C */ + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 + + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 + #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 + + + /* In the case where two media types (e.g. copper and fiber) are + present and electrically active at the same time, PHY Selection + will determine which of the two PHYs will be designated as the + Active PHY and used for a connection to the network. */ + uint32_t multi_phy_config; /* 0x290 */ + #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 + #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 + #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 + #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 + #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 + #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 + #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 + + /* When enabled, all second phy nvram parameters will be swapped + with the first phy parameters */ + #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 + #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 + #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 + #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 + + + /* Address of the second external phy */ + uint32_t external_phy_config2; /* 0x294 */ + #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF + #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 + + /* The second XGXS external PHY type */ + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8071 0x00000100 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8072 0x00000200 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8073 0x00000300 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8705 0x00000400 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8706 0x00000500 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8726 0x00000600 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8481 0x00000700 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727 0x00000900 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727_NOC 0x00000a00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84823 0x00000b00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54640 0x00000c00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84833 0x00000d00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE 0x00000e00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 + #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 + + + /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as + 8706, 8726 and 8727) not all 4 values are needed. */ + uint16_t xgxs_config2_rx[4]; /* 0x296 */ + uint16_t xgxs_config2_tx[4]; /* 0x2A0 */ + + uint32_t lane_config; + #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF + #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 + /* AN and forced */ + #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b + /* forced only */ + #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 + /* forced only */ + #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 + /* forced only */ + #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 + #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF + #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 + #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 + #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 + #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 + #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 + + /* Indicate whether to swap the external phy polarity */ + #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 + #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 + #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 + + + uint32_t external_phy_config; + #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF + #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 + + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8071 0x00000100 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8072 0x00000200 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073 0x00000300 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705 0x00000400 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706 0x00000500 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726 0x00000600 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481 0x00000700 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727 0x00000900 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC 0x00000a00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823 0x00000b00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54640 0x00000c00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833 0x00000d00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE 0x00000e00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 + #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 + + #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 + #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 + + #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 + #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 + #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 + #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BNX2X5482 0x01000000 + #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 + #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 + + uint32_t speed_capability_mask; + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 + #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 + + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 + #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 + + /* A place to hold the original MAC address as a backup */ + uint32_t backup_mac_upper; /* 0x2B4 */ + uint32_t backup_mac_lower; /* 0x2B8 */ + +}; + + +/**************************************************************************** + * Shared Feature configuration * + ****************************************************************************/ +struct shared_feat_cfg { /* NVRAM Offset */ + + uint32_t config; /* 0x450 */ + #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 + + /* Use NVRAM values instead of HW default values */ + #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ + 0x00000002 + #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ + 0x00000000 + #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ + 0x00000002 + + #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 + #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 + #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 + + #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 + #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 + + /* Override the OTP back to single function mode. When using GPIO, + high means only SF, 0 is according to CLP configuration */ + #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 + #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 + #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 + #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 + #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 + #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 + #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 + + /* Act as if the FCoE license is invalid */ + #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 + + /* Force FLR capability to all ports */ + #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 + + /* Act as if the iSCSI license is invalid */ + #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 + #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 + #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 + #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 + + /* The interval in seconds between sending LLDP packets. Set to zero + to disable the feature */ + #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 + #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 + + /* The assigned device type ID for LLDP usage */ + #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 + #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 + +}; + + +/**************************************************************************** + * Port Feature configuration * + ****************************************************************************/ +struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ + + uint32_t config; + #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F + #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 + #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 + #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 + #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 + #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 + #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 + #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 + #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 + #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 + #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 + #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 + #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a + #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b + #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c + #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d + #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e + #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f + #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 + #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 + #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 + #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 + #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 + #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 + #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 + #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 + #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 + #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 + #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 + #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 + #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 + #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 + #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 + #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 + #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 + #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 + + #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 + #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 + #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 + + #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 + #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 + #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 + #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 + + #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 + #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 + #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 + #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 + #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 + #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 + + #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 + #define PORT_FEATURE_EN_SIZE_SHIFT 24 + #define PORT_FEATURE_WOL_ENABLED 0x01000000 + #define PORT_FEATURE_MBA_ENABLED 0x02000000 + #define PORT_FEATURE_MFW_ENABLED 0x04000000 + + /* Advertise expansion ROM even if MBA is disabled */ + #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 + #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 + #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 + + /* Check the optic vendor via i2c against a list of approved modules + in a separate nvram image */ + #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 + #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 + #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ + 0x00000000 + #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ + 0x20000000 + #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 + #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 + + uint32_t wol_config; + /* Default is used when driver sets to "auto" mode */ + #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 + + uint32_t mba_config; + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 + #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 + + #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 + #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 + + #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 + #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 + #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 + #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 + + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 + #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 + #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 + #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 + #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 + #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 + #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 + #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 + #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 + #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 + #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 + #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 + #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 + #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 + #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 + #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 + #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 + #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 + #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 + #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 + #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 + + uint32_t Reserved0; /* 0x460 */ + + uint32_t mba_vlan_cfg; + #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF + #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 + #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 + + uint32_t Reserved1; + uint32_t smbus_config; + #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe + #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 + + uint32_t vf_config; + #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F + #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 + #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a + #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b + #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c + #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d + #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e + #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f + + uint32_t link_config; /* Used as HW defaults for the driver */ + + #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 + #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 + #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 + #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 + #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 + #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 + #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 + #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 + #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 + #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 + + #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 + #define PORT_FEATURE_LINK_SPEED_SHIFT 16 + #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 + #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 + #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 + #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 + #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 + #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 + #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 + #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 + #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 + + #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 + #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 + /* (forced) low speed switch (< 10G) */ + #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 + /* (forced) high speed switch (>= 10G) */ + #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 + #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 + #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 + + + /* The default for MCP link configuration, + uses the same defines as link_config */ + uint32_t mfw_wol_link_cfg; + + /* The default for the driver of the second external phy, + uses the same defines as link_config */ + uint32_t link_config2; /* 0x47C */ + + /* The default for MCP of the second external phy, + uses the same defines as link_config */ + uint32_t mfw_wol_link_cfg2; /* 0x480 */ + + + /* EEE power saving mode */ + uint32_t eee_power_mode; /* 0x484 */ + #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF + #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 + #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 + #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 + #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 + #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 + + + uint32_t Reserved2[16]; /* 0x488 */ +}; + +/**************************************************************************** + * Device Information * + ****************************************************************************/ +struct shm_dev_info { /* size */ + + uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ + + struct shared_hw_cfg shared_hw_config; /* 40 */ + + struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ + + struct shared_feat_cfg shared_feature_config; /* 4 */ + + struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ + +}; + +struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ + + /* Threshold in celcius to start using the fan */ + uint32_t temperature_monitor1; /* 0x4000 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 + + /* Threshold in celcius to shut down the board */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 + + /* EPIO of fan temperature status */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 + + /* EPIO of shut down temperature status */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 + + + /* EPIO of shut down temperature status */ + uint32_t temperature_monitor2; /* 0x4004 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 + + + /* MFW flavor to be used */ + uint32_t mfw_cfg; /* 0x4008 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF + #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 + + /* Should NIC data query remain enabled upon last drv unload */ + #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 + #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 + #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 + + /* Hide DCBX feature in CCM/BACS menus */ + #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 + #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 + #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 + + uint32_t smbus_config; /* 0x400C */ + #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF + #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 + + /* Switching regulator loop gain */ + uint32_t board_cfg; /* 0x4010 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e + #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f + + /* whether shadow swim feature is supported */ + #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 + #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 + #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 + + /* whether to show/hide SRIOV menu in CCM */ + #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 + #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 + #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 + + /* Threshold in celcius for max continuous operation */ + uint32_t temperature_report; /* 0x4014 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 + + /* Threshold in celcius for sensor caution */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 + #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 + + /* wwn node prefix to be used (unless value is 0) */ + uint32_t wwn_prefix; /* 0x4018 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 + + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 + + /* wwn port prefix to be used (unless value is 0) */ + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 + + /* wwn port prefix to be used (unless value is 0) */ + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 + + /* General debug nvm cfg */ + uint32_t dbg_cfg_flags; /* 0x401C */ + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 + + /* Debug signet rx threshold */ + uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 + #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 + + /* Enable IFFE feature */ + uint32_t iffe_features; /* 0x4024 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 + #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 + + /* Allowable port enablement (bitmask for ports 3-1) */ + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 + + /* Allow iSCSI offload override */ + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 + + /* Allow FCoE offload override */ + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 + + /* Tie to adaptor */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 + #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 + + /* Currently enabled port(s) (bitmask for ports 3-1) */ + uint32_t current_iffe_mask; /* 0x4028 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 + + /* Current iSCSI offload */ + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 + + /* Current FCoE offload */ + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 + + /* FW set this pin to "0" (assert) these signal if either of its MAC + * or PHY specific threshold values is exceeded. + * Values are standard GPIO/EPIO pins. + */ + uint32_t threshold_pin; /* 0x402C */ + #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF + #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 + #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 + #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 + + /* MAC die temperature threshold in Celsius. */ + uint32_t mac_threshold_val; /* 0x4030 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF + #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 + #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 + #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 + + /* PHY die temperature threshold in Celsius. */ + uint32_t phy_threshold_val; /* 0x4034 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF + #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 + #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 + #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 + + /* External pins to communicate with host. + * Values are standard GPIO/EPIO pins. + */ + uint32_t host_pin; /* 0x4038 */ + #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF + #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 + #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 + #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 + #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 + #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 + #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 + #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 +}; + + +#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) + #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." +#endif + +#define FUNC_0 0 +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 +#define E1H_FUNC_MAX 8 +#define E2_FUNC_MAX 4 /* per path */ + +#define VN_0 0 +#define VN_1 1 +#define VN_2 2 +#define VN_3 3 +#define E1VN_MAX 1 +#define E1HVN_MAX 4 + +#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ +/* This value (in milliseconds) determines the frequency of the driver + * issuing the PULSE message code. The firmware monitors this periodic + * pulse to determine when to switch to an OS-absent mode. */ +#define DRV_PULSE_PERIOD_MS 250 + +/* This value (in milliseconds) determines how long the driver should + * wait for an acknowledgement from the firmware before timing out. Once + * the firmware has timed out, the driver will assume there is no firmware + * running and there won't be any firmware-driver synchronization during a + * driver reset. */ +#define FW_ACK_TIME_OUT_MS 5000 + +#define FW_ACK_POLL_TIME_MS 1 + +#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) + +#define MFW_TRACE_SIGNATURE 0x54524342 + +/**************************************************************************** + * Driver <-> FW Mailbox * + ****************************************************************************/ +struct drv_port_mb { + + uint32_t link_status; + /* Driver should update this field on any link change event */ + + #define LINK_STATUS_NONE (0<<0) + #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 + #define LINK_STATUS_LINK_UP 0x00000001 + #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E + #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) + #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) + + #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 + #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 + + #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 + #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 + #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 + + #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 + #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 + #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 + #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 + #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 + #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 + #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 + + #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 + #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 + + #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 + #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 + + #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 + #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) + #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) + #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) + #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) + + #define LINK_STATUS_SERDES_LINK 0x00100000 + + #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 + #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 + #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 + #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 + + #define LINK_STATUS_PFC_ENABLED 0x20000000 + + #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 + #define LINK_STATUS_SFP_TX_FAULT 0x80000000 + + uint32_t port_stx; + + uint32_t stat_nig_timer; + + /* MCP firmware does not use this field */ + uint32_t ext_phy_fw_version; + +}; + + +struct drv_func_mb { + + uint32_t drv_mb_header; + #define DRV_MSG_CODE_MASK 0xffff0000 + #define DRV_MSG_CODE_LOAD_REQ 0x10000000 + #define DRV_MSG_CODE_LOAD_DONE 0x11000000 + #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 + #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 + #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 + #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 + #define DRV_MSG_CODE_DCC_OK 0x30000000 + #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 + #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 + #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 + #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 + #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 + #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 + #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 + #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 + + /* + * The optic module verification command requires bootcode + * v5.0.6 or later, te specific optic module verification command + * requires bootcode v5.2.12 or later + */ + #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 + #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 + #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 + #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 + #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 + #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 + #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 + #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 + #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 + #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 + + #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 + #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 + #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 + + #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 + + #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 + #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 + #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 + #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 + #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 + + #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 + #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 + + #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 + + #define DRV_MSG_CODE_RMMOD 0xdb000000 + #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f + + #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 + #define REQ_BC_VER_4_SET_MF_BW 0x00060202 + #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 + + #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 + + #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 + #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 + + #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 + #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 + #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 + #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 + + #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 + #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 + + #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff + + uint32_t drv_mb_param; + #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 + #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 + + #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 + #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 + + #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a + #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 + + #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 + + uint32_t fw_mb_header; + #define FW_MSG_CODE_MASK 0xffff0000 + #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 + #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 + #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 + /* Load common chip is supported from bc 6.0.0 */ + #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 + #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 + + #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 + #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 + #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 + #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 + #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 + #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 + #define FW_MSG_CODE_DCC_DONE 0x30100000 + #define FW_MSG_CODE_LLDP_DONE 0x40100000 + #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 + #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 + #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 + #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 + #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 + #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 + #define FW_MSG_CODE_NO_KEY 0x80f00000 + #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 + #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 + #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 + #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 + #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 + #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 + #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 + #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 + #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 + #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 + #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 + + #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 + #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 + #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 + #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 + #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 + + #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 + #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 + + #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 + + #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 + + #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 + #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 + + #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 + + #define FW_MSG_CODE_FLR_ACK 0x02000000 + #define FW_MSG_CODE_FLR_NACK 0x02100000 + + #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 + #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 + #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 + #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 + + #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 + #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 + + #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff + + uint32_t fw_mb_param; + + #define FW_PARAM_INVALID_IMG 0xffffffff + + uint32_t drv_pulse_mb; + #define DRV_PULSE_SEQ_MASK 0x00007fff + #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 + /* + * The system time is in the format of + * (year-2001)*12*32 + month*32 + day. + */ + #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 + /* + * Indicate to the firmware not to go into the + * OS-absent when it is not getting driver pulse. + * This is used for debugging as well for PXE(MBA). + */ + + uint32_t mcp_pulse_mb; + #define MCP_PULSE_SEQ_MASK 0x00007fff + #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 + /* Indicates to the driver not to assert due to lack + * of MCP response */ + #define MCP_EVENT_MASK 0xffff0000 + #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 + + uint32_t iscsi_boot_signature; + uint32_t iscsi_boot_block_offset; + + uint32_t drv_status; + #define DRV_STATUS_PMF 0x00000001 + #define DRV_STATUS_VF_DISABLED 0x00000002 + #define DRV_STATUS_SET_MF_BW 0x00000004 + #define DRV_STATUS_LINK_EVENT 0x00000008 + + #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 + #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 + #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 + #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 + #define DRV_STATUS_DCC_RESERVED1 0x00000800 + #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 + #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 + + #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 + #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 + #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 + #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 + #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 + #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 + #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 + + #define DRV_STATUS_DRV_INFO_REQ 0x04000000 + + #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 + + uint32_t virt_mac_upper; + #define VIRT_MAC_SIGN_MASK 0xffff0000 + #define VIRT_MAC_SIGNATURE 0x564d0000 + uint32_t virt_mac_lower; + +}; + + +/**************************************************************************** + * Management firmware state * + ****************************************************************************/ +/* Allocate 440 bytes for management firmware */ +#define MGMTFW_STATE_WORD_SIZE 110 + +struct mgmtfw_state { + uint32_t opaque[MGMTFW_STATE_WORD_SIZE]; +}; + + +/**************************************************************************** + * Multi-Function configuration * + ****************************************************************************/ +struct shared_mf_cfg { + + uint32_t clp_mb; + #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 + /* set by CLP */ + #define SHARED_MF_CLP_EXIT 0x00000001 + /* set by MCP */ + #define SHARED_MF_CLP_EXIT_DONE 0x00010000 + +}; + +struct port_mf_cfg { + + uint32_t dynamic_cfg; /* device control channel */ + #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff + #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 + #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK + + uint32_t reserved[1]; + +}; + +struct func_mf_cfg { + + uint32_t config; + /* E/R/I/D */ + /* function 0 of each port cannot be hidden */ + #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 + + #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 + #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 + #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 + #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 + #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 + #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ + FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA + + #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 + #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 + + #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 + #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 + #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 + #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 + + /* PRI */ + /* 0 - low priority, 3 - high priority */ + #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 + #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 + #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 + + /* MINBW, MAXBW */ + /* value range - 0..100, increments in 100Mbps */ + #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 + #define FUNC_MF_CFG_MIN_BW_SHIFT 16 + #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 + #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 + #define FUNC_MF_CFG_MAX_BW_SHIFT 24 + #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 + + uint32_t mac_upper; /* MAC */ + #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff + #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 + #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK + uint32_t mac_lower; + #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff + + uint32_t e1hov_tag; /* VNI */ + #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff + #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 + #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK + + /* afex default VLAN ID - 12 bits */ + #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 + #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 + + uint32_t afex_config; + #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff + #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 + #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 + #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 + #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 + #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 + #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 + + uint32_t pf_allocation; + /* number of vfs in function, if 0 - sriov disabled */ + #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF + #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 +}; + +enum mf_cfg_afex_vlan_mode { + FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, + FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, + FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE +}; + +/* This structure is not applicable and should not be accessed on 57711 */ +struct func_ext_cfg { + uint32_t func_cfg; + #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F + #define MACP_FUNC_CFG_FLAGS_SHIFT 0 + #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 + #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 + #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 + #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 + #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 + + uint32_t iscsi_mac_addr_upper; + uint32_t iscsi_mac_addr_lower; + + uint32_t fcoe_mac_addr_upper; + uint32_t fcoe_mac_addr_lower; + + uint32_t fcoe_wwn_port_name_upper; + uint32_t fcoe_wwn_port_name_lower; + + uint32_t fcoe_wwn_node_name_upper; + uint32_t fcoe_wwn_node_name_lower; + + uint32_t preserve_data; + #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) + #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) + #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) + #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) + #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) + #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) +}; + +struct mf_cfg { + + struct shared_mf_cfg shared_mf_config; /* 0x4 */ + struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; + /* 0x10*2=0x20 */ + /* for all chips, there are 8 mf functions */ + struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ + /* + * Extended configuration per function - this array does not exist and + * should not be accessed on 57711 + */ + struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ +}; /* 0x224 */ + +/**************************************************************************** + * Shared Memory Region * + ****************************************************************************/ +struct shmem_region { /* SharedMem Offset (size) */ + + uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ + #define SHR_MEM_FORMAT_REV_MASK 0xff000000 + #define SHR_MEM_FORMAT_REV_ID ('A'<<24) + /* validity bits */ + #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 + #define SHR_MEM_VALIDITY_MB 0x00200000 + #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 + #define SHR_MEM_VALIDITY_RESERVED 0x00000007 + /* One licensing bit should be set */ + #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 + #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 + #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 + #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 + /* Active MFW */ + #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 + #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 + #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 + #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 + #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 + #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 + + struct shm_dev_info dev_info; /* 0x8 (0x438) */ + + license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ + + /* FW information (for internal FW use) */ + uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */ + struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ + + struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ + + +#ifdef BMAPI + /* This is a variable length array */ + /* the number of function depends on the chip type */ + struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ +#else + /* the number of function depends on the chip type */ + struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ +#endif /* BMAPI */ + +}; /* 57711 = 0x7E4 | 57712 = 0x734 */ + +/**************************************************************************** + * Shared Memory 2 Region * + ****************************************************************************/ +/* The fw_flr_ack is actually built in the following way: */ +/* 8 bit: PF ack */ +/* 64 bit: VF ack */ +/* 8 bit: ios_dis_ack */ +/* In order to maintain endianity in the mailbox hsi, we want to keep using */ +/* uint32_t. The fw must have the VF right after the PF since this is how it */ +/* access arrays(it expects always the VF to reside after the PF, and that */ +/* makes the calculation much easier for it. ) */ +/* In order to answer both limitations, and keep the struct small, the code */ +/* will abuse the structure defined here to achieve the actual partition */ +/* above */ +/****************************************************************************/ +struct fw_flr_ack { + uint32_t pf_ack; + uint32_t vf_ack[1]; + uint32_t iov_dis_ack; +}; + +struct fw_flr_mb { + uint32_t aggint; + uint32_t opgen_addr; + struct fw_flr_ack ack; +}; + +struct eee_remote_vals { + uint32_t tx_tw; + uint32_t rx_tw; +}; + +/**** SUPPORT FOR SHMEM ARRRAYS *** + * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to + * define arrays with storage types smaller then unsigned dwords. + * The macros below add generic support for SHMEM arrays with numeric elements + * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword + * array with individual bit-filed elements accessed using shifts and masks. + * + */ + +/* eb is the bitwidth of a single element */ +#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) +#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) + +/* the bit-position macro allows the used to flip the order of the arrays + * elements on a per byte or word boundary. + * + * example: an array with 8 entries each 4 bit wide. This array will fit into + * a single dword. The diagrmas below show the array order of the nibbles. + * + * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: + * + * | | | | + * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | + * | | | | + * + * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: + * + * | | | | + * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | + * | | | | + * + * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: + * + * | | | | + * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | + * | | | | + */ +#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ + ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ + (((i)%((fb)/(eb))) * (eb))) + +#define SHMEM_ARRAY_GET(a, i, eb, fb) \ + ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ + SHMEM_ARRAY_MASK(eb)) + +#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ +do { \ + a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ + SHMEM_ARRAY_BITPOS(i, eb, fb)); \ + a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ + SHMEM_ARRAY_BITPOS(i, eb, fb)); \ +} while (0) + + +/****START OF DCBX STRUCTURES DECLARATIONS****/ +#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 +#define DCBX_PRI_PG_BITWIDTH 4 +#define DCBX_PRI_PG_FBITS 8 +#define DCBX_PRI_PG_GET(a, i) \ + SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) +#define DCBX_PRI_PG_SET(a, i, val) \ + SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) +#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 +#define DCBX_BW_PG_BITWIDTH 8 +#define DCBX_PG_BW_GET(a, i) \ + SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) +#define DCBX_PG_BW_SET(a, i, val) \ + SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) +#define DCBX_STRICT_PRI_PG 15 +#define DCBX_MAX_APP_PROTOCOL 16 +#define DCBX_MAX_APP_LOCAL 32 +#define FCOE_APP_IDX 0 +#define ISCSI_APP_IDX 1 +#define PREDEFINED_APP_IDX_MAX 2 + + +/* Big/Little endian have the same representation. */ +struct dcbx_ets_feature { + /* + * For Admin MIB - is this feature supported by the + * driver | For Local MIB - should this feature be enabled. + */ + uint32_t enabled; + uint32_t pg_bw_tbl[2]; + uint32_t pri_pg_tbl[1]; +}; + +/* Driver structure in LE */ +struct dcbx_pfc_feature { +#ifdef __BIG_ENDIAN + uint8_t pri_en_bitmap; + #define DCBX_PFC_PRI_0 0x01 + #define DCBX_PFC_PRI_1 0x02 + #define DCBX_PFC_PRI_2 0x04 + #define DCBX_PFC_PRI_3 0x08 + #define DCBX_PFC_PRI_4 0x10 + #define DCBX_PFC_PRI_5 0x20 + #define DCBX_PFC_PRI_6 0x40 + #define DCBX_PFC_PRI_7 0x80 + uint8_t pfc_caps; + uint8_t reserved; + uint8_t enabled; +#elif defined(__LITTLE_ENDIAN) + uint8_t enabled; + uint8_t reserved; + uint8_t pfc_caps; + uint8_t pri_en_bitmap; + #define DCBX_PFC_PRI_0 0x01 + #define DCBX_PFC_PRI_1 0x02 + #define DCBX_PFC_PRI_2 0x04 + #define DCBX_PFC_PRI_3 0x08 + #define DCBX_PFC_PRI_4 0x10 + #define DCBX_PFC_PRI_5 0x20 + #define DCBX_PFC_PRI_6 0x40 + #define DCBX_PFC_PRI_7 0x80 +#endif +}; + +struct dcbx_app_priority_entry { +#ifdef __BIG_ENDIAN + uint16_t app_id; + uint8_t pri_bitmap; + uint8_t appBitfield; + #define DCBX_APP_ENTRY_VALID 0x01 + #define DCBX_APP_ENTRY_SF_MASK 0x30 + #define DCBX_APP_ENTRY_SF_SHIFT 4 + #define DCBX_APP_SF_ETH_TYPE 0x10 + #define DCBX_APP_SF_PORT 0x20 +#elif defined(__LITTLE_ENDIAN) + uint8_t appBitfield; + #define DCBX_APP_ENTRY_VALID 0x01 + #define DCBX_APP_ENTRY_SF_MASK 0x30 + #define DCBX_APP_ENTRY_SF_SHIFT 4 + #define DCBX_APP_SF_ETH_TYPE 0x10 + #define DCBX_APP_SF_PORT 0x20 + uint8_t pri_bitmap; + uint16_t app_id; +#endif +}; + + +/* FW structure in BE */ +struct dcbx_app_priority_feature { +#ifdef __BIG_ENDIAN + uint8_t reserved; + uint8_t default_pri; + uint8_t tc_supported; + uint8_t enabled; +#elif defined(__LITTLE_ENDIAN) + uint8_t enabled; + uint8_t tc_supported; + uint8_t default_pri; + uint8_t reserved; +#endif + struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; +}; + +/* FW structure in BE */ +struct dcbx_features { + /* PG feature */ + struct dcbx_ets_feature ets; + /* PFC feature */ + struct dcbx_pfc_feature pfc; + /* APP feature */ + struct dcbx_app_priority_feature app; +}; + +/* LLDP protocol parameters */ +/* FW structure in BE */ +struct lldp_params { +#ifdef __BIG_ENDIAN + uint8_t msg_fast_tx_interval; + uint8_t msg_tx_hold; + uint8_t msg_tx_interval; + uint8_t admin_status; + #define LLDP_TX_ONLY 0x01 + #define LLDP_RX_ONLY 0x02 + #define LLDP_TX_RX 0x03 + #define LLDP_DISABLED 0x04 + uint8_t reserved1; + uint8_t tx_fast; + uint8_t tx_crd_max; + uint8_t tx_crd; +#elif defined(__LITTLE_ENDIAN) + uint8_t admin_status; + #define LLDP_TX_ONLY 0x01 + #define LLDP_RX_ONLY 0x02 + #define LLDP_TX_RX 0x03 + #define LLDP_DISABLED 0x04 + uint8_t msg_tx_interval; + uint8_t msg_tx_hold; + uint8_t msg_fast_tx_interval; + uint8_t tx_crd; + uint8_t tx_crd_max; + uint8_t tx_fast; + uint8_t reserved1; +#endif + #define REM_CHASSIS_ID_STAT_LEN 4 + #define REM_PORT_ID_STAT_LEN 4 + /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ + uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; + /* Holds remote Port ID TLV header, subtype and 9B of payload. */ + uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]; +}; + +struct lldp_dcbx_stat { + #define LOCAL_CHASSIS_ID_STAT_LEN 2 + #define LOCAL_PORT_ID_STAT_LEN 2 + /* Holds local Chassis ID 8B payload of constant subtype 4. */ + uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; + /* Holds local Port ID 8B payload of constant subtype 3. */ + uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]; + /* Number of DCBX frames transmitted. */ + uint32_t num_tx_dcbx_pkts; + /* Number of DCBX frames received. */ + uint32_t num_rx_dcbx_pkts; +}; + +/* ADMIN MIB - DCBX local machine default configuration. */ +struct lldp_admin_mib { + uint32_t ver_cfg_flags; + #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 + #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 + #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 + #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 + #define DCBX_ETS_RECO_VALID 0x00000010 + #define DCBX_ETS_WILLING 0x00000020 + #define DCBX_PFC_WILLING 0x00000040 + #define DCBX_APP_WILLING 0x00000080 + #define DCBX_VERSION_CEE 0x00000100 + #define DCBX_VERSION_IEEE 0x00000200 + #define DCBX_DCBX_ENABLED 0x00000400 + #define DCBX_CEE_VERSION_MASK 0x0000f000 + #define DCBX_CEE_VERSION_SHIFT 12 + #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 + #define DCBX_CEE_MAX_VERSION_SHIFT 16 + struct dcbx_features features; +}; + +/* REMOTE MIB - remote machine DCBX configuration. */ +struct lldp_remote_mib { + uint32_t prefix_seq_num; + uint32_t flags; + #define DCBX_ETS_TLV_RX 0x00000001 + #define DCBX_PFC_TLV_RX 0x00000002 + #define DCBX_APP_TLV_RX 0x00000004 + #define DCBX_ETS_RX_ERROR 0x00000010 + #define DCBX_PFC_RX_ERROR 0x00000020 + #define DCBX_APP_RX_ERROR 0x00000040 + #define DCBX_ETS_REM_WILLING 0x00000100 + #define DCBX_PFC_REM_WILLING 0x00000200 + #define DCBX_APP_REM_WILLING 0x00000400 + #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 + #define DCBX_REMOTE_MIB_VALID 0x00002000 + struct dcbx_features features; + uint32_t suffix_seq_num; +}; + +/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ +struct lldp_local_mib { + uint32_t prefix_seq_num; + /* Indicates if there is mismatch with negotiation results. */ + uint32_t error; + #define DCBX_LOCAL_ETS_ERROR 0x00000001 + #define DCBX_LOCAL_PFC_ERROR 0x00000002 + #define DCBX_LOCAL_APP_ERROR 0x00000004 + #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 + #define DCBX_LOCAL_APP_MISMATCH 0x00000020 + #define DCBX_REMOTE_MIB_ERROR 0x00000040 + #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 + #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 + #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 + struct dcbx_features features; + uint32_t suffix_seq_num; +}; + +struct lldp_local_mib_ext { + uint32_t prefix_seq_num; + /* APP TLV extension - 16 more entries for negotiation results*/ + struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; + uint32_t suffix_seq_num; +}; +/***END OF DCBX STRUCTURES DECLARATIONS***/ + +/***********************************************************/ +/* Elink section */ +/***********************************************************/ +#define SHMEM_LINK_CONFIG_SIZE 2 +struct shmem_lfa { + uint32_t req_duplex; + #define REQ_DUPLEX_PHY0_MASK 0x0000ffff + #define REQ_DUPLEX_PHY0_SHIFT 0 + #define REQ_DUPLEX_PHY1_MASK 0xffff0000 + #define REQ_DUPLEX_PHY1_SHIFT 16 + uint32_t req_flow_ctrl; + #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff + #define REQ_FLOW_CTRL_PHY0_SHIFT 0 + #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 + #define REQ_FLOW_CTRL_PHY1_SHIFT 16 + uint32_t req_line_speed; /* Also determine AutoNeg */ + #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff + #define REQ_LINE_SPD_PHY0_SHIFT 0 + #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 + #define REQ_LINE_SPD_PHY1_SHIFT 16 + uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; + uint32_t additional_config; + #define REQ_FC_AUTO_ADV_MASK 0x0000ffff + #define REQ_FC_AUTO_ADV0_SHIFT 0 + #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 + uint32_t lfa_sts; + #define LFA_LINK_FLAP_REASON_OFFSET 0 + #define LFA_LINK_FLAP_REASON_MASK 0x000000ff + #define LFA_LINK_DOWN 0x1 + #define LFA_LOOPBACK_ENABLED 0x2 + #define LFA_DUPLEX_MISMATCH 0x3 + #define LFA_MFW_IS_TOO_OLD 0x4 + #define LFA_LINK_SPEED_MISMATCH 0x5 + #define LFA_FLOW_CTRL_MISMATCH 0x6 + #define LFA_SPEED_CAP_MISMATCH 0x7 + #define LFA_DCC_LFA_DISABLED 0x8 + #define LFA_EEE_MISMATCH 0x9 + + #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 + #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 + + #define LINK_FLAP_COUNT_OFFSET 16 + #define LINK_FLAP_COUNT_MASK 0x00ff0000 + + #define LFA_FLAGS_MASK 0xff000000 + #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) + +}; + +struct shmem2_region { + + uint32_t size; /* 0x0000 */ + + uint32_t dcc_support; /* 0x0004 */ + #define SHMEM_DCC_SUPPORT_NONE 0x00000000 + #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 + #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 + #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 + #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 + #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 + + uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ + /* + * For backwards compatibility, if the mf_cfg_addr does not exist + * (the size filed is smaller than 0xc) the mf_cfg resides at the + * end of struct shmem_region + */ + uint32_t mf_cfg_addr; /* 0x0010 */ + #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 + + struct fw_flr_mb flr_mb; /* 0x0014 */ + uint32_t dcbx_lldp_params_offset; /* 0x0028 */ + #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 + uint32_t dcbx_neg_res_offset; /* 0x002c */ + #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 + uint32_t dcbx_remote_mib_offset; /* 0x0030 */ + #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 + /* + * The other shmemX_base_addr holds the other path's shmem address + * required for example in case of common phy init, or for path1 to know + * the address of mcp debug trace which is located in offset from shmem + * of path0 + */ + uint32_t other_shmem_base_addr; /* 0x0034 */ + uint32_t other_shmem2_base_addr; /* 0x0038 */ + /* + * mcp_vf_disabled is set by the MCP to indicate the driver about VFs + * which were disabled/flred + */ + uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ + + /* + * drv_ack_vf_disabled is set by the PF driver to ack handled disabled + * VFs + */ + uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ + + uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ + #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 + + /* + * edebug_driver_if field is used to transfer messages between edebug + * app to the driver through shmem2. + * + * message format: + * bits 0-2 - function number / instance of driver to perform request + * bits 3-5 - op code / is_ack? + * bits 6-63 - data + */ + uint32_t edebug_driver_if[2]; /* 0x0068 */ + #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 + #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 + #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 + + uint32_t nvm_retain_bitmap_addr; /* 0x0070 */ + + /* afex support of that driver */ + uint32_t afex_driver_support; /* 0x0074 */ + #define SHMEM_AFEX_VERSION_MASK 0x100f + #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 + #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 + + /* driver receives addr in scratchpad to which it should respond */ + uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]; + + /* + * generic params from MCP to driver (value depends on the msg sent + * to driver + */ + uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ + uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ + + uint32_t swim_base_addr; /* 0x0108 */ + uint32_t swim_funcs; + uint32_t swim_main_cb; + + /* + * bitmap notifying which VIF profiles stored in nvram are enabled by + * switch + */ + uint32_t afex_profiles_enabled[2]; + + /* generic flags controlled by the driver */ + uint32_t drv_flags; + #define DRV_FLAGS_DCB_CONFIGURED 0x0 + #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 + #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 + + #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ + (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ + (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) + /* Port offset*/ + #define DRV_FLAGS_P0_OFFSET 0 + #define DRV_FLAGS_P1_OFFSET 16 + #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ + DRV_FLAGS_P0_OFFSET : \ + DRV_FLAGS_P1_OFFSET) + + #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ + DRV_FLAGS_GET_PORT_OFFSET(_port)) + + #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ + (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) + + /* pointer to extended dev_info shared data copied from nvm image */ + uint32_t extended_dev_info_shared_addr; + uint32_t ncsi_oem_data_addr; + + uint32_t sensor_data_addr; + uint32_t buffer_block_addr; + uint32_t sensor_data_req_update_interval; + uint32_t temperature_in_half_celsius; + uint32_t glob_struct_in_host; + + uint32_t dcbx_neg_res_ext_offset; + #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 + + uint32_t drv_capabilities_flag[E2_FUNC_MAX]; + #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 + #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 + #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 + #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 + + uint32_t extended_dev_info_shared_cfg_size; + + uint32_t dcbx_en[PORT_MAX]; + + /* The offset points to the multi threaded meta structure */ + uint32_t multi_thread_data_offset; + + /* address of DMAable host address holding values from the drivers */ + uint32_t drv_info_host_addr_lo; + uint32_t drv_info_host_addr_hi; + + /* general values written by the MFW (such as current version) */ + uint32_t drv_info_control; + #define DRV_INFO_CONTROL_VER_MASK 0x000000ff + #define DRV_INFO_CONTROL_VER_SHIFT 0 + #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 + #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 + uint32_t ibft_host_addr; /* initialized by option ROM */ + + struct eee_remote_vals eee_remote_vals[PORT_MAX]; + uint32_t pf_allocation[E2_FUNC_MAX]; + #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ + #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 + + /* the status of EEE auto-negotiation + * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. + * bits 19:16 the supported modes for EEE. + * bits 23:20 the speeds advertised for EEE. + * bits 27:24 the speeds the Link partner advertised for EEE. + * The supported/adv. modes in bits 27:19 originate from the + * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). + * bit 28 when 1'b1 EEE was requested. + * bit 29 when 1'b1 tx lpi was requested. + * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff + * 30:29 are 2'b11. + * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as + * value. When 1'b1 those bits contains a value times 16 microseconds. + */ + uint32_t eee_status[PORT_MAX]; + #define SHMEM_EEE_TIMER_MASK 0x0000ffff + #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 + #define SHMEM_EEE_SUPPORTED_SHIFT 16 + #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 + #define SHMEM_EEE_100M_ADV (1<<0) + #define SHMEM_EEE_1G_ADV (1<<1) + #define SHMEM_EEE_10G_ADV (1<<2) + #define SHMEM_EEE_ADV_STATUS_SHIFT 20 + #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 + #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 + #define SHMEM_EEE_REQUESTED_BIT 0x10000000 + #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 + #define SHMEM_EEE_ACTIVE_BIT 0x40000000 + #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 + + uint32_t sizeof_port_stats; + + /* Link Flap Avoidance */ + uint32_t lfa_host_addr[PORT_MAX]; + + /* External PHY temperature in deg C. */ + uint32_t extphy_temps_in_celsius; + #define EXTPHY1_TEMP_MASK 0x0000ffff + #define EXTPHY1_TEMP_SHIFT 0 + + uint32_t ocdata_info_addr; /* Offset 0x148 */ + uint32_t drv_func_info_addr; /* Offset 0x14C */ + uint32_t drv_func_info_size; /* Offset 0x150 */ + uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */ + #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) +}; + + +struct emac_stats { + uint32_t rx_stat_ifhcinoctets; + uint32_t rx_stat_ifhcinbadoctets; + uint32_t rx_stat_etherstatsfragments; + uint32_t rx_stat_ifhcinucastpkts; + uint32_t rx_stat_ifhcinmulticastpkts; + uint32_t rx_stat_ifhcinbroadcastpkts; + uint32_t rx_stat_dot3statsfcserrors; + uint32_t rx_stat_dot3statsalignmenterrors; + uint32_t rx_stat_dot3statscarriersenseerrors; + uint32_t rx_stat_xonpauseframesreceived; + uint32_t rx_stat_xoffpauseframesreceived; + uint32_t rx_stat_maccontrolframesreceived; + uint32_t rx_stat_xoffstateentered; + uint32_t rx_stat_dot3statsframestoolong; + uint32_t rx_stat_etherstatsjabbers; + uint32_t rx_stat_etherstatsundersizepkts; + uint32_t rx_stat_etherstatspkts64octets; + uint32_t rx_stat_etherstatspkts65octetsto127octets; + uint32_t rx_stat_etherstatspkts128octetsto255octets; + uint32_t rx_stat_etherstatspkts256octetsto511octets; + uint32_t rx_stat_etherstatspkts512octetsto1023octets; + uint32_t rx_stat_etherstatspkts1024octetsto1522octets; + uint32_t rx_stat_etherstatspktsover1522octets; + + uint32_t rx_stat_falsecarriererrors; + + uint32_t tx_stat_ifhcoutoctets; + uint32_t tx_stat_ifhcoutbadoctets; + uint32_t tx_stat_etherstatscollisions; + uint32_t tx_stat_outxonsent; + uint32_t tx_stat_outxoffsent; + uint32_t tx_stat_flowcontroldone; + uint32_t tx_stat_dot3statssinglecollisionframes; + uint32_t tx_stat_dot3statsmultiplecollisionframes; + uint32_t tx_stat_dot3statsdeferredtransmissions; + uint32_t tx_stat_dot3statsexcessivecollisions; + uint32_t tx_stat_dot3statslatecollisions; + uint32_t tx_stat_ifhcoutucastpkts; + uint32_t tx_stat_ifhcoutmulticastpkts; + uint32_t tx_stat_ifhcoutbroadcastpkts; + uint32_t tx_stat_etherstatspkts64octets; + uint32_t tx_stat_etherstatspkts65octetsto127octets; + uint32_t tx_stat_etherstatspkts128octetsto255octets; + uint32_t tx_stat_etherstatspkts256octetsto511octets; + uint32_t tx_stat_etherstatspkts512octetsto1023octets; + uint32_t tx_stat_etherstatspkts1024octetsto1522octets; + uint32_t tx_stat_etherstatspktsover1522octets; + uint32_t tx_stat_dot3statsinternalmactransmiterrors; +}; + + +struct bmac1_stats { + uint32_t tx_stat_gtpkt_lo; + uint32_t tx_stat_gtpkt_hi; + uint32_t tx_stat_gtxpf_lo; + uint32_t tx_stat_gtxpf_hi; + uint32_t tx_stat_gtfcs_lo; + uint32_t tx_stat_gtfcs_hi; + uint32_t tx_stat_gtmca_lo; + uint32_t tx_stat_gtmca_hi; + uint32_t tx_stat_gtbca_lo; + uint32_t tx_stat_gtbca_hi; + uint32_t tx_stat_gtfrg_lo; + uint32_t tx_stat_gtfrg_hi; + uint32_t tx_stat_gtovr_lo; + uint32_t tx_stat_gtovr_hi; + uint32_t tx_stat_gt64_lo; + uint32_t tx_stat_gt64_hi; + uint32_t tx_stat_gt127_lo; + uint32_t tx_stat_gt127_hi; + uint32_t tx_stat_gt255_lo; + uint32_t tx_stat_gt255_hi; + uint32_t tx_stat_gt511_lo; + uint32_t tx_stat_gt511_hi; + uint32_t tx_stat_gt1023_lo; + uint32_t tx_stat_gt1023_hi; + uint32_t tx_stat_gt1518_lo; + uint32_t tx_stat_gt1518_hi; + uint32_t tx_stat_gt2047_lo; + uint32_t tx_stat_gt2047_hi; + uint32_t tx_stat_gt4095_lo; + uint32_t tx_stat_gt4095_hi; + uint32_t tx_stat_gt9216_lo; + uint32_t tx_stat_gt9216_hi; + uint32_t tx_stat_gt16383_lo; + uint32_t tx_stat_gt16383_hi; + uint32_t tx_stat_gtmax_lo; + uint32_t tx_stat_gtmax_hi; + uint32_t tx_stat_gtufl_lo; + uint32_t tx_stat_gtufl_hi; + uint32_t tx_stat_gterr_lo; + uint32_t tx_stat_gterr_hi; + uint32_t tx_stat_gtbyt_lo; + uint32_t tx_stat_gtbyt_hi; + + uint32_t rx_stat_gr64_lo; + uint32_t rx_stat_gr64_hi; + uint32_t rx_stat_gr127_lo; + uint32_t rx_stat_gr127_hi; + uint32_t rx_stat_gr255_lo; + uint32_t rx_stat_gr255_hi; + uint32_t rx_stat_gr511_lo; + uint32_t rx_stat_gr511_hi; + uint32_t rx_stat_gr1023_lo; + uint32_t rx_stat_gr1023_hi; + uint32_t rx_stat_gr1518_lo; + uint32_t rx_stat_gr1518_hi; + uint32_t rx_stat_gr2047_lo; + uint32_t rx_stat_gr2047_hi; + uint32_t rx_stat_gr4095_lo; + uint32_t rx_stat_gr4095_hi; + uint32_t rx_stat_gr9216_lo; + uint32_t rx_stat_gr9216_hi; + uint32_t rx_stat_gr16383_lo; + uint32_t rx_stat_gr16383_hi; + uint32_t rx_stat_grmax_lo; + uint32_t rx_stat_grmax_hi; + uint32_t rx_stat_grpkt_lo; + uint32_t rx_stat_grpkt_hi; + uint32_t rx_stat_grfcs_lo; + uint32_t rx_stat_grfcs_hi; + uint32_t rx_stat_grmca_lo; + uint32_t rx_stat_grmca_hi; + uint32_t rx_stat_grbca_lo; + uint32_t rx_stat_grbca_hi; + uint32_t rx_stat_grxcf_lo; + uint32_t rx_stat_grxcf_hi; + uint32_t rx_stat_grxpf_lo; + uint32_t rx_stat_grxpf_hi; + uint32_t rx_stat_grxuo_lo; + uint32_t rx_stat_grxuo_hi; + uint32_t rx_stat_grjbr_lo; + uint32_t rx_stat_grjbr_hi; + uint32_t rx_stat_grovr_lo; + uint32_t rx_stat_grovr_hi; + uint32_t rx_stat_grflr_lo; + uint32_t rx_stat_grflr_hi; + uint32_t rx_stat_grmeg_lo; + uint32_t rx_stat_grmeg_hi; + uint32_t rx_stat_grmeb_lo; + uint32_t rx_stat_grmeb_hi; + uint32_t rx_stat_grbyt_lo; + uint32_t rx_stat_grbyt_hi; + uint32_t rx_stat_grund_lo; + uint32_t rx_stat_grund_hi; + uint32_t rx_stat_grfrg_lo; + uint32_t rx_stat_grfrg_hi; + uint32_t rx_stat_grerb_lo; + uint32_t rx_stat_grerb_hi; + uint32_t rx_stat_grfre_lo; + uint32_t rx_stat_grfre_hi; + uint32_t rx_stat_gripj_lo; + uint32_t rx_stat_gripj_hi; +}; + +struct bmac2_stats { + uint32_t tx_stat_gtpk_lo; /* gtpok */ + uint32_t tx_stat_gtpk_hi; /* gtpok */ + uint32_t tx_stat_gtxpf_lo; /* gtpf */ + uint32_t tx_stat_gtxpf_hi; /* gtpf */ + uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */ + uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */ + uint32_t tx_stat_gtfcs_lo; + uint32_t tx_stat_gtfcs_hi; + uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */ + uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */ + uint32_t tx_stat_gtmca_lo; + uint32_t tx_stat_gtmca_hi; + uint32_t tx_stat_gtbca_lo; + uint32_t tx_stat_gtbca_hi; + uint32_t tx_stat_gtovr_lo; + uint32_t tx_stat_gtovr_hi; + uint32_t tx_stat_gtfrg_lo; + uint32_t tx_stat_gtfrg_hi; + uint32_t tx_stat_gtpkt1_lo; /* gtpkt */ + uint32_t tx_stat_gtpkt1_hi; /* gtpkt */ + uint32_t tx_stat_gt64_lo; + uint32_t tx_stat_gt64_hi; + uint32_t tx_stat_gt127_lo; + uint32_t tx_stat_gt127_hi; + uint32_t tx_stat_gt255_lo; + uint32_t tx_stat_gt255_hi; + uint32_t tx_stat_gt511_lo; + uint32_t tx_stat_gt511_hi; + uint32_t tx_stat_gt1023_lo; + uint32_t tx_stat_gt1023_hi; + uint32_t tx_stat_gt1518_lo; + uint32_t tx_stat_gt1518_hi; + uint32_t tx_stat_gt2047_lo; + uint32_t tx_stat_gt2047_hi; + uint32_t tx_stat_gt4095_lo; + uint32_t tx_stat_gt4095_hi; + uint32_t tx_stat_gt9216_lo; + uint32_t tx_stat_gt9216_hi; + uint32_t tx_stat_gt16383_lo; + uint32_t tx_stat_gt16383_hi; + uint32_t tx_stat_gtmax_lo; + uint32_t tx_stat_gtmax_hi; + uint32_t tx_stat_gtufl_lo; + uint32_t tx_stat_gtufl_hi; + uint32_t tx_stat_gterr_lo; + uint32_t tx_stat_gterr_hi; + uint32_t tx_stat_gtbyt_lo; + uint32_t tx_stat_gtbyt_hi; + + uint32_t rx_stat_gr64_lo; + uint32_t rx_stat_gr64_hi; + uint32_t rx_stat_gr127_lo; + uint32_t rx_stat_gr127_hi; + uint32_t rx_stat_gr255_lo; + uint32_t rx_stat_gr255_hi; + uint32_t rx_stat_gr511_lo; + uint32_t rx_stat_gr511_hi; + uint32_t rx_stat_gr1023_lo; + uint32_t rx_stat_gr1023_hi; + uint32_t rx_stat_gr1518_lo; + uint32_t rx_stat_gr1518_hi; + uint32_t rx_stat_gr2047_lo; + uint32_t rx_stat_gr2047_hi; + uint32_t rx_stat_gr4095_lo; + uint32_t rx_stat_gr4095_hi; + uint32_t rx_stat_gr9216_lo; + uint32_t rx_stat_gr9216_hi; + uint32_t rx_stat_gr16383_lo; + uint32_t rx_stat_gr16383_hi; + uint32_t rx_stat_grmax_lo; + uint32_t rx_stat_grmax_hi; + uint32_t rx_stat_grpkt_lo; + uint32_t rx_stat_grpkt_hi; + uint32_t rx_stat_grfcs_lo; + uint32_t rx_stat_grfcs_hi; + uint32_t rx_stat_gruca_lo; + uint32_t rx_stat_gruca_hi; + uint32_t rx_stat_grmca_lo; + uint32_t rx_stat_grmca_hi; + uint32_t rx_stat_grbca_lo; + uint32_t rx_stat_grbca_hi; + uint32_t rx_stat_grxpf_lo; /* grpf */ + uint32_t rx_stat_grxpf_hi; /* grpf */ + uint32_t rx_stat_grpp_lo; + uint32_t rx_stat_grpp_hi; + uint32_t rx_stat_grxuo_lo; /* gruo */ + uint32_t rx_stat_grxuo_hi; /* gruo */ + uint32_t rx_stat_grjbr_lo; + uint32_t rx_stat_grjbr_hi; + uint32_t rx_stat_grovr_lo; + uint32_t rx_stat_grovr_hi; + uint32_t rx_stat_grxcf_lo; /* grcf */ + uint32_t rx_stat_grxcf_hi; /* grcf */ + uint32_t rx_stat_grflr_lo; + uint32_t rx_stat_grflr_hi; + uint32_t rx_stat_grpok_lo; + uint32_t rx_stat_grpok_hi; + uint32_t rx_stat_grmeg_lo; + uint32_t rx_stat_grmeg_hi; + uint32_t rx_stat_grmeb_lo; + uint32_t rx_stat_grmeb_hi; + uint32_t rx_stat_grbyt_lo; + uint32_t rx_stat_grbyt_hi; + uint32_t rx_stat_grund_lo; + uint32_t rx_stat_grund_hi; + uint32_t rx_stat_grfrg_lo; + uint32_t rx_stat_grfrg_hi; + uint32_t rx_stat_grerb_lo; /* grerrbyt */ + uint32_t rx_stat_grerb_hi; /* grerrbyt */ + uint32_t rx_stat_grfre_lo; /* grfrerr */ + uint32_t rx_stat_grfre_hi; /* grfrerr */ + uint32_t rx_stat_gripj_lo; + uint32_t rx_stat_gripj_hi; +}; + +struct mstat_stats { + struct { + /* OTE MSTAT on E3 has a bug where this register's contents are + * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp + */ + uint32_t tx_gtxpok_lo; + uint32_t tx_gtxpok_hi; + uint32_t tx_gtxpf_lo; + uint32_t tx_gtxpf_hi; + uint32_t tx_gtxpp_lo; + uint32_t tx_gtxpp_hi; + uint32_t tx_gtfcs_lo; + uint32_t tx_gtfcs_hi; + uint32_t tx_gtuca_lo; + uint32_t tx_gtuca_hi; + uint32_t tx_gtmca_lo; + uint32_t tx_gtmca_hi; + uint32_t tx_gtgca_lo; + uint32_t tx_gtgca_hi; + uint32_t tx_gtpkt_lo; + uint32_t tx_gtpkt_hi; + uint32_t tx_gt64_lo; + uint32_t tx_gt64_hi; + uint32_t tx_gt127_lo; + uint32_t tx_gt127_hi; + uint32_t tx_gt255_lo; + uint32_t tx_gt255_hi; + uint32_t tx_gt511_lo; + uint32_t tx_gt511_hi; + uint32_t tx_gt1023_lo; + uint32_t tx_gt1023_hi; + uint32_t tx_gt1518_lo; + uint32_t tx_gt1518_hi; + uint32_t tx_gt2047_lo; + uint32_t tx_gt2047_hi; + uint32_t tx_gt4095_lo; + uint32_t tx_gt4095_hi; + uint32_t tx_gt9216_lo; + uint32_t tx_gt9216_hi; + uint32_t tx_gt16383_lo; + uint32_t tx_gt16383_hi; + uint32_t tx_gtufl_lo; + uint32_t tx_gtufl_hi; + uint32_t tx_gterr_lo; + uint32_t tx_gterr_hi; + uint32_t tx_gtbyt_lo; + uint32_t tx_gtbyt_hi; + uint32_t tx_collisions_lo; + uint32_t tx_collisions_hi; + uint32_t tx_singlecollision_lo; + uint32_t tx_singlecollision_hi; + uint32_t tx_multiplecollisions_lo; + uint32_t tx_multiplecollisions_hi; + uint32_t tx_deferred_lo; + uint32_t tx_deferred_hi; + uint32_t tx_excessivecollisions_lo; + uint32_t tx_excessivecollisions_hi; + uint32_t tx_latecollisions_lo; + uint32_t tx_latecollisions_hi; + } stats_tx; + + struct { + uint32_t rx_gr64_lo; + uint32_t rx_gr64_hi; + uint32_t rx_gr127_lo; + uint32_t rx_gr127_hi; + uint32_t rx_gr255_lo; + uint32_t rx_gr255_hi; + uint32_t rx_gr511_lo; + uint32_t rx_gr511_hi; + uint32_t rx_gr1023_lo; + uint32_t rx_gr1023_hi; + uint32_t rx_gr1518_lo; + uint32_t rx_gr1518_hi; + uint32_t rx_gr2047_lo; + uint32_t rx_gr2047_hi; + uint32_t rx_gr4095_lo; + uint32_t rx_gr4095_hi; + uint32_t rx_gr9216_lo; + uint32_t rx_gr9216_hi; + uint32_t rx_gr16383_lo; + uint32_t rx_gr16383_hi; + uint32_t rx_grpkt_lo; + uint32_t rx_grpkt_hi; + uint32_t rx_grfcs_lo; + uint32_t rx_grfcs_hi; + uint32_t rx_gruca_lo; + uint32_t rx_gruca_hi; + uint32_t rx_grmca_lo; + uint32_t rx_grmca_hi; + uint32_t rx_grbca_lo; + uint32_t rx_grbca_hi; + uint32_t rx_grxpf_lo; + uint32_t rx_grxpf_hi; + uint32_t rx_grxpp_lo; + uint32_t rx_grxpp_hi; + uint32_t rx_grxuo_lo; + uint32_t rx_grxuo_hi; + uint32_t rx_grovr_lo; + uint32_t rx_grovr_hi; + uint32_t rx_grxcf_lo; + uint32_t rx_grxcf_hi; + uint32_t rx_grflr_lo; + uint32_t rx_grflr_hi; + uint32_t rx_grpok_lo; + uint32_t rx_grpok_hi; + uint32_t rx_grbyt_lo; + uint32_t rx_grbyt_hi; + uint32_t rx_grund_lo; + uint32_t rx_grund_hi; + uint32_t rx_grfrg_lo; + uint32_t rx_grfrg_hi; + uint32_t rx_grerb_lo; + uint32_t rx_grerb_hi; + uint32_t rx_grfre_lo; + uint32_t rx_grfre_hi; + + uint32_t rx_alignmenterrors_lo; + uint32_t rx_alignmenterrors_hi; + uint32_t rx_falsecarrier_lo; + uint32_t rx_falsecarrier_hi; + uint32_t rx_llfcmsgcnt_lo; + uint32_t rx_llfcmsgcnt_hi; + } stats_rx; +}; + +union mac_stats { + struct emac_stats emac_stats; + struct bmac1_stats bmac1_stats; + struct bmac2_stats bmac2_stats; + struct mstat_stats mstat_stats; +}; + + +struct mac_stx { + /* in_bad_octets */ + uint32_t rx_stat_ifhcinbadoctets_hi; + uint32_t rx_stat_ifhcinbadoctets_lo; + + /* out_bad_octets */ + uint32_t tx_stat_ifhcoutbadoctets_hi; + uint32_t tx_stat_ifhcoutbadoctets_lo; + + /* crc_receive_errors */ + uint32_t rx_stat_dot3statsfcserrors_hi; + uint32_t rx_stat_dot3statsfcserrors_lo; + /* alignment_errors */ + uint32_t rx_stat_dot3statsalignmenterrors_hi; + uint32_t rx_stat_dot3statsalignmenterrors_lo; + /* carrier_sense_errors */ + uint32_t rx_stat_dot3statscarriersenseerrors_hi; + uint32_t rx_stat_dot3statscarriersenseerrors_lo; + /* false_carrier_detections */ + uint32_t rx_stat_falsecarriererrors_hi; + uint32_t rx_stat_falsecarriererrors_lo; + + /* runt_packets_received */ + uint32_t rx_stat_etherstatsundersizepkts_hi; + uint32_t rx_stat_etherstatsundersizepkts_lo; + /* jabber_packets_received */ + uint32_t rx_stat_dot3statsframestoolong_hi; + uint32_t rx_stat_dot3statsframestoolong_lo; + + /* error_runt_packets_received */ + uint32_t rx_stat_etherstatsfragments_hi; + uint32_t rx_stat_etherstatsfragments_lo; + /* error_jabber_packets_received */ + uint32_t rx_stat_etherstatsjabbers_hi; + uint32_t rx_stat_etherstatsjabbers_lo; + + /* control_frames_received */ + uint32_t rx_stat_maccontrolframesreceived_hi; + uint32_t rx_stat_maccontrolframesreceived_lo; + uint32_t rx_stat_mac_xpf_hi; + uint32_t rx_stat_mac_xpf_lo; + uint32_t rx_stat_mac_xcf_hi; + uint32_t rx_stat_mac_xcf_lo; + + /* xoff_state_entered */ + uint32_t rx_stat_xoffstateentered_hi; + uint32_t rx_stat_xoffstateentered_lo; + /* pause_xon_frames_received */ + uint32_t rx_stat_xonpauseframesreceived_hi; + uint32_t rx_stat_xonpauseframesreceived_lo; + /* pause_xoff_frames_received */ + uint32_t rx_stat_xoffpauseframesreceived_hi; + uint32_t rx_stat_xoffpauseframesreceived_lo; + /* pause_xon_frames_transmitted */ + uint32_t tx_stat_outxonsent_hi; + uint32_t tx_stat_outxonsent_lo; + /* pause_xoff_frames_transmitted */ + uint32_t tx_stat_outxoffsent_hi; + uint32_t tx_stat_outxoffsent_lo; + /* flow_control_done */ + uint32_t tx_stat_flowcontroldone_hi; + uint32_t tx_stat_flowcontroldone_lo; + + /* ether_stats_collisions */ + uint32_t tx_stat_etherstatscollisions_hi; + uint32_t tx_stat_etherstatscollisions_lo; + /* single_collision_transmit_frames */ + uint32_t tx_stat_dot3statssinglecollisionframes_hi; + uint32_t tx_stat_dot3statssinglecollisionframes_lo; + /* multiple_collision_transmit_frames */ + uint32_t tx_stat_dot3statsmultiplecollisionframes_hi; + uint32_t tx_stat_dot3statsmultiplecollisionframes_lo; + /* deferred_transmissions */ + uint32_t tx_stat_dot3statsdeferredtransmissions_hi; + uint32_t tx_stat_dot3statsdeferredtransmissions_lo; + /* excessive_collision_frames */ + uint32_t tx_stat_dot3statsexcessivecollisions_hi; + uint32_t tx_stat_dot3statsexcessivecollisions_lo; + /* late_collision_frames */ + uint32_t tx_stat_dot3statslatecollisions_hi; + uint32_t tx_stat_dot3statslatecollisions_lo; + + /* frames_transmitted_64_bytes */ + uint32_t tx_stat_etherstatspkts64octets_hi; + uint32_t tx_stat_etherstatspkts64octets_lo; + /* frames_transmitted_65_127_bytes */ + uint32_t tx_stat_etherstatspkts65octetsto127octets_hi; + uint32_t tx_stat_etherstatspkts65octetsto127octets_lo; + /* frames_transmitted_128_255_bytes */ + uint32_t tx_stat_etherstatspkts128octetsto255octets_hi; + uint32_t tx_stat_etherstatspkts128octetsto255octets_lo; + /* frames_transmitted_256_511_bytes */ + uint32_t tx_stat_etherstatspkts256octetsto511octets_hi; + uint32_t tx_stat_etherstatspkts256octetsto511octets_lo; + /* frames_transmitted_512_1023_bytes */ + uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi; + uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo; + /* frames_transmitted_1024_1522_bytes */ + uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi; + uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo; + /* frames_transmitted_1523_9022_bytes */ + uint32_t tx_stat_etherstatspktsover1522octets_hi; + uint32_t tx_stat_etherstatspktsover1522octets_lo; + uint32_t tx_stat_mac_2047_hi; + uint32_t tx_stat_mac_2047_lo; + uint32_t tx_stat_mac_4095_hi; + uint32_t tx_stat_mac_4095_lo; + uint32_t tx_stat_mac_9216_hi; + uint32_t tx_stat_mac_9216_lo; + uint32_t tx_stat_mac_16383_hi; + uint32_t tx_stat_mac_16383_lo; + + /* internal_mac_transmit_errors */ + uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi; + uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo; + + /* if_out_discards */ + uint32_t tx_stat_mac_ufl_hi; + uint32_t tx_stat_mac_ufl_lo; +}; + + +#define MAC_STX_IDX_MAX 2 + +struct host_port_stats { + uint32_t host_port_stats_counter; + + struct mac_stx mac_stx[MAC_STX_IDX_MAX]; + + uint32_t brb_drop_hi; + uint32_t brb_drop_lo; + + uint32_t not_used; /* obsolete as of MFW 7.2.1 */ + + uint32_t pfc_frames_tx_hi; + uint32_t pfc_frames_tx_lo; + uint32_t pfc_frames_rx_hi; + uint32_t pfc_frames_rx_lo; + + uint32_t eee_lpi_count_hi; + uint32_t eee_lpi_count_lo; +}; + + +struct host_func_stats { + uint32_t host_func_stats_start; + + uint32_t total_bytes_received_hi; + uint32_t total_bytes_received_lo; + + uint32_t total_bytes_transmitted_hi; + uint32_t total_bytes_transmitted_lo; + + uint32_t total_unicast_packets_received_hi; + uint32_t total_unicast_packets_received_lo; + + uint32_t total_multicast_packets_received_hi; + uint32_t total_multicast_packets_received_lo; + + uint32_t total_broadcast_packets_received_hi; + uint32_t total_broadcast_packets_received_lo; + + uint32_t total_unicast_packets_transmitted_hi; + uint32_t total_unicast_packets_transmitted_lo; + + uint32_t total_multicast_packets_transmitted_hi; + uint32_t total_multicast_packets_transmitted_lo; + + uint32_t total_broadcast_packets_transmitted_hi; + uint32_t total_broadcast_packets_transmitted_lo; + + uint32_t valid_bytes_received_hi; + uint32_t valid_bytes_received_lo; + + uint32_t host_func_stats_end; +}; + +/* VIC definitions */ +#define VICSTATST_UIF_INDEX 2 + +/* + * stats collected for afex. + * NOTE: structure is exactly as expected to be received by the switch. + * order must remain exactly as is unless protocol changes ! + */ +struct afex_stats { + uint32_t tx_unicast_frames_hi; + uint32_t tx_unicast_frames_lo; + uint32_t tx_unicast_bytes_hi; + uint32_t tx_unicast_bytes_lo; + uint32_t tx_multicast_frames_hi; + uint32_t tx_multicast_frames_lo; + uint32_t tx_multicast_bytes_hi; + uint32_t tx_multicast_bytes_lo; + uint32_t tx_broadcast_frames_hi; + uint32_t tx_broadcast_frames_lo; + uint32_t tx_broadcast_bytes_hi; + uint32_t tx_broadcast_bytes_lo; + uint32_t tx_frames_discarded_hi; + uint32_t tx_frames_discarded_lo; + uint32_t tx_frames_dropped_hi; + uint32_t tx_frames_dropped_lo; + + uint32_t rx_unicast_frames_hi; + uint32_t rx_unicast_frames_lo; + uint32_t rx_unicast_bytes_hi; + uint32_t rx_unicast_bytes_lo; + uint32_t rx_multicast_frames_hi; + uint32_t rx_multicast_frames_lo; + uint32_t rx_multicast_bytes_hi; + uint32_t rx_multicast_bytes_lo; + uint32_t rx_broadcast_frames_hi; + uint32_t rx_broadcast_frames_lo; + uint32_t rx_broadcast_bytes_hi; + uint32_t rx_broadcast_bytes_lo; + uint32_t rx_frames_discarded_hi; + uint32_t rx_frames_discarded_lo; + uint32_t rx_frames_dropped_hi; + uint32_t rx_frames_dropped_lo; +}; + +/* To maintain backward compatibility between FW and drivers, new elements */ +/* should be added to the end of the structure. */ + +/* Per Port Statistics */ +struct port_info { + uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */ + uint32_t enabled; /* 0 =Disabled, 1= Enabled */ + uint32_t link_speed; /* multiplier of 100Mb */ + uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */ + uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/ + uint32_t flex10; /* Flex10 mode enabled. non zero = yes */ + uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */ + uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI. + This is flagged by Consumer as an error. */ + uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */ + uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */ + uint32_t rx_mcast_lo; /* RX Multicast Packets */ + uint32_t rx_mcast_hi; /* RX Multicast Packets */ + uint32_t rx_bcast_lo; /* RX Broadcast Packets */ + uint32_t rx_bcast_hi; /* RX Broadcast Packets */ + uint32_t tx_uncast_lo; /* TX Unicast Packets */ + uint32_t tx_uncast_hi; /* TX Unicast Packets */ + uint32_t tx_mcast_lo; /* TX Multicast Packets */ + uint32_t tx_mcast_hi; /* TX Multicast Packets */ + uint32_t tx_bcast_lo; /* TX Broadcast Packets */ + uint32_t tx_bcast_hi; /* TX Broadcast Packets */ + uint32_t tx_errors; /* TX Errors */ + uint32_t tx_discards; /* TX Discards */ + uint32_t rx_frames_lo; /* RX Frames received */ + uint32_t rx_frames_hi; /* RX Frames received */ + uint32_t rx_bytes_lo; /* RX Bytes received */ + uint32_t rx_bytes_hi; /* RX Bytes received */ + uint32_t tx_frames_lo; /* TX Frames sent */ + uint32_t tx_frames_hi; /* TX Frames sent */ + uint32_t tx_bytes_lo; /* TX Bytes sent */ + uint32_t tx_bytes_hi; /* TX Bytes sent */ + uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled. + 1:1 bit for link good, + 2:1 Set if link changed between last poll. */ + uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */ + uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */ + uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */ + uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */ +}; + + +#define BNX2X_5710_FW_MAJOR_VERSION 7 +#define BNX2X_5710_FW_MINOR_VERSION 2 +#define BNX2X_5710_FW_REVISION_VERSION 51 +#define BNX2X_5710_FW_ENGINEERING_VERSION 0 +#define BNX2X_5710_FW_COMPILE_FLAGS 1 + + +/* + * attention bits $$KEEP_ENDIANNESS$$ + */ +struct atten_sp_status_block +{ + uint32_t attn_bits /* 16 bit of attention signal lines */; + uint32_t attn_bits_ack /* 16 bit of attention signal ack */; + uint8_t status_block_id /* status block id */; + uint8_t reserved0 /* resreved for padding */; + uint16_t attn_bits_index /* attention bits running index */; + uint32_t reserved1 /* resreved for padding */; +}; + + +/* + * The eth aggregative context of Cstorm + */ +struct cstorm_eth_ag_context +{ + uint32_t __reserved0[10]; +}; + + +/* + * dmae command structure + */ +struct dmae_command +{ + uint32_t opcode; +#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */ +#define DMAE_COMMAND_SRC_SHIFT 0 +#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ +#define DMAE_COMMAND_DST_SHIFT 1 +#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */ +#define DMAE_COMMAND_C_DST_SHIFT 3 +#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */ +#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 +#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */ +#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 +#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */ +#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 +#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ +#define DMAE_COMMAND_ENDIANITY_SHIFT 9 +#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */ +#define DMAE_COMMAND_PORT_SHIFT 11 +#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */ +#define DMAE_COMMAND_CRC_RESET_SHIFT 12 +#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */ +#define DMAE_COMMAND_SRC_RESET_SHIFT 13 +#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */ +#define DMAE_COMMAND_DST_RESET_SHIFT 14 +#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ +#define DMAE_COMMAND_E1HVN_SHIFT 15 +#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */ +#define DMAE_COMMAND_DST_VN_SHIFT 17 +#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */ +#define DMAE_COMMAND_C_FUNC_SHIFT 19 +#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */ +#define DMAE_COMMAND_ERR_POLICY_SHIFT 20 +#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */ +#define DMAE_COMMAND_RESERVED0_SHIFT 22 + uint32_t src_addr_lo /* source address low/grc address */; + uint32_t src_addr_hi /* source address hi */; + uint32_t dst_addr_lo /* dest address low/grc address */; + uint32_t dst_addr_hi /* dest address hi */; +#if defined(__BIG_ENDIAN) + uint16_t opcode_iov; +#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ +#define DMAE_COMMAND_SRC_VFID_SHIFT 0 +#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ +#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 +#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ +#define DMAE_COMMAND_RESERVED1_SHIFT 7 +#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ +#define DMAE_COMMAND_DST_VFID_SHIFT 8 +#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ +#define DMAE_COMMAND_DST_VFPF_SHIFT 14 +#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ +#define DMAE_COMMAND_RESERVED2_SHIFT 15 + uint16_t len /* copy length */; +#elif defined(__LITTLE_ENDIAN) + uint16_t len /* copy length */; + uint16_t opcode_iov; +#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ +#define DMAE_COMMAND_SRC_VFID_SHIFT 0 +#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ +#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 +#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ +#define DMAE_COMMAND_RESERVED1_SHIFT 7 +#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ +#define DMAE_COMMAND_DST_VFID_SHIFT 8 +#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ +#define DMAE_COMMAND_DST_VFPF_SHIFT 14 +#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ +#define DMAE_COMMAND_RESERVED2_SHIFT 15 +#endif + uint32_t comp_addr_lo /* completion address low/grc address */; + uint32_t comp_addr_hi /* completion address hi */; + uint32_t comp_val /* value to write to completion address */; + uint32_t crc32 /* crc32 result */; + uint32_t crc32_c /* crc32_c result */; +#if defined(__BIG_ENDIAN) + uint16_t crc16_c /* crc16_c result */; + uint16_t crc16 /* crc16 result */; +#elif defined(__LITTLE_ENDIAN) + uint16_t crc16 /* crc16 result */; + uint16_t crc16_c /* crc16_c result */; +#endif +#if defined(__BIG_ENDIAN) + uint16_t reserved3; + uint16_t crc_t10 /* crc_t10 result */; +#elif defined(__LITTLE_ENDIAN) + uint16_t crc_t10 /* crc_t10 result */; + uint16_t reserved3; +#endif +#if defined(__BIG_ENDIAN) + uint16_t xsum8 /* checksum8 result */; + uint16_t xsum16 /* checksum16 result */; +#elif defined(__LITTLE_ENDIAN) + uint16_t xsum16 /* checksum16 result */; + uint16_t xsum8 /* checksum8 result */; +#endif +}; + + +/* + * common data for all protocols + */ +struct doorbell_hdr +{ + uint8_t header; +#define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */ +#define DOORBELL_HDR_RX_SHIFT 0 +#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */ +#define DOORBELL_HDR_DB_TYPE_SHIFT 1 +#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */ +#define DOORBELL_HDR_DPM_SIZE_SHIFT 2 +#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */ +#define DOORBELL_HDR_CONN_TYPE_SHIFT 4 +}; + +/* + * Ethernet doorbell + */ +struct eth_tx_doorbell +{ +#if defined(__BIG_ENDIAN) + uint16_t npackets /* number of data bytes that were added in the doorbell */; + uint8_t params; +#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ +#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 +#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ +#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 +#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ +#define ETH_TX_DOORBELL_SPARE_SHIFT 7 + struct doorbell_hdr hdr; +#elif defined(__LITTLE_ENDIAN) + struct doorbell_hdr hdr; + uint8_t params; +#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ +#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 +#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ +#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 +#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ +#define ETH_TX_DOORBELL_SPARE_SHIFT 7 + uint16_t npackets /* number of data bytes that were added in the doorbell */; +#endif +}; + + +/* + * 3 lines. status block $$KEEP_ENDIANNESS$$ + */ +struct hc_status_block_e1x +{ + uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */; + uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; + uint32_t rsrv[11]; +}; + +/* + * host status block + */ +struct host_hc_status_block_e1x +{ + struct hc_status_block_e1x sb /* fast path indices */; +}; + + +/* + * 3 lines. status block $$KEEP_ENDIANNESS$$ + */ +struct hc_status_block_e2 +{ + uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */; + uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; + uint32_t reserved[11]; +}; + +/* + * host status block + */ +struct host_hc_status_block_e2 +{ + struct hc_status_block_e2 sb /* fast path indices */; +}; + + +/* + * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$ + */ +struct hc_sp_status_block +{ + uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */; + uint16_t running_index /* Status Block running index */; + uint16_t rsrv; + uint32_t rsrv1; +}; + +/* + * host status block + */ +struct host_sp_status_block +{ + struct atten_sp_status_block atten_status_block /* attention bits section */; + struct hc_sp_status_block sp_sb /* slow path indices */; +}; + + +/* + * IGU driver acknowledgment register + */ +union igu_ack_register +{ + struct { +#if defined(__BIG_ENDIAN) + uint16_t sb_id_and_flags; +#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ +#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 +#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ +#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 +#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ +#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 +#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ +#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 +#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ +#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 + uint16_t status_block_index /* status block index acknowledgement */; +#elif defined(__LITTLE_ENDIAN) + uint16_t status_block_index /* status block index acknowledgement */; + uint16_t sb_id_and_flags; +#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ +#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 +#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ +#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 +#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ +#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 +#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ +#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 +#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ +#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 +#endif + } sb; + uint32_t raw_data; +}; + + +/* + * IGU driver acknowledgement register + */ +struct igu_backward_compatible +{ + uint32_t sb_id_and_flags; +#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */ +#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 +#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */ +#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 +#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ +#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 +#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */ +#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 +#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ +#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 +#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */ +#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 + uint32_t reserved_2; +}; + + +/* + * IGU driver acknowledgement register + */ +struct igu_regular +{ + uint32_t sb_id_and_flags; +#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_SB_INDEX_SHIFT 0 +#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_RESERVED0_SHIFT 20 +#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */ +#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 +#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_BUPDATE_SHIFT 24 +#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */ +#define IGU_REGULAR_ENABLE_INT_SHIFT 25 +#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_RESERVED_1_SHIFT 27 +#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 +#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 +#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_BCLEANUP_SHIFT 31 + uint32_t reserved_2; +}; + +/* + * IGU driver acknowledgement register + */ +union igu_consprod_reg +{ + struct igu_regular regular; + struct igu_backward_compatible backward_compatible; +}; + + +/* + * Igu control commands + */ +enum igu_ctrl_cmd +{ + IGU_CTRL_CMD_TYPE_RD, + IGU_CTRL_CMD_TYPE_WR, + MAX_IGU_CTRL_CMD}; + + +/* + * Control register for the IGU command register + */ +struct igu_ctrl_reg +{ + uint32_t ctrl_data; +#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */ +#define IGU_CTRL_REG_ADDRESS_SHIFT 0 +#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */ +#define IGU_CTRL_REG_FID_SHIFT 12 +#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */ +#define IGU_CTRL_REG_RESERVED_SHIFT 19 +#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */ +#define IGU_CTRL_REG_TYPE_SHIFT 20 +#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */ +#define IGU_CTRL_REG_UNUSED_SHIFT 21 +}; + + +/* + * Igu interrupt command + */ +enum igu_int_cmd +{ + IGU_INT_ENABLE, + IGU_INT_DISABLE, + IGU_INT_NOP, + IGU_INT_NOP2, + MAX_IGU_INT_CMD}; + + +/* + * Igu segments + */ +enum igu_seg_access +{ + IGU_SEG_ACCESS_NORM, + IGU_SEG_ACCESS_DEF, + IGU_SEG_ACCESS_ATTN, + MAX_IGU_SEG_ACCESS}; + + +/* + * Parser parsing flags field + */ +struct parsing_flags +{ + uint16_t flags; +#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */ +#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 +#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */ +#define PARSING_FLAGS_VLAN_SHIFT 1 +#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */ +#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 +#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */ +#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 +#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */ +#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 +#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */ +#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 +#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */ +#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 +#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */ +#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 +#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */ +#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 +#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */ +#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 +#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */ +#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 +#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */ +#define PARSING_FLAGS_LLC_SNAP_SHIFT 13 +#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */ +#define PARSING_FLAGS_RESERVED0_SHIFT 14 +}; + + +/* + * Parsing flags for TCP ACK type + */ +enum prs_flags_ack_type +{ + PRS_FLAG_PUREACK_PIGGY, + PRS_FLAG_PUREACK_PURE, + MAX_PRS_FLAGS_ACK_TYPE}; + + +/* + * Parsing flags for Ethernet address type + */ +enum prs_flags_eth_addr_type +{ + PRS_FLAG_ETHTYPE_NON_UNICAST, + PRS_FLAG_ETHTYPE_UNICAST, + MAX_PRS_FLAGS_ETH_ADDR_TYPE}; + + +/* + * Parsing flags for over-ethernet protocol + */ +enum prs_flags_over_eth +{ + PRS_FLAG_OVERETH_UNKNOWN, + PRS_FLAG_OVERETH_IPV4, + PRS_FLAG_OVERETH_IPV6, + PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, + MAX_PRS_FLAGS_OVER_ETH}; + + +/* + * Parsing flags for over-IP protocol + */ +enum prs_flags_over_ip +{ + PRS_FLAG_OVERIP_UNKNOWN, + PRS_FLAG_OVERIP_TCP, + PRS_FLAG_OVERIP_UDP, + MAX_PRS_FLAGS_OVER_IP}; + + +/* + * SDM operation gen command (generate aggregative interrupt) + */ +struct sdm_op_gen +{ + uint32_t command; +#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */ +#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 +#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */ +#define SDM_OP_GEN_COMP_TYPE_SHIFT 5 +#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */ +#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 +#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */ +#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 +#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */ +#define SDM_OP_GEN_RESERVED_SHIFT 17 +}; + + +/* + * Timers connection context + */ +struct timers_block_context +{ + uint32_t __reserved_0 /* data of client 0 of the timers block*/; + uint32_t __reserved_1 /* data of client 1 of the timers block*/; + uint32_t __reserved_2 /* data of client 2 of the timers block*/; + uint32_t flags; +#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */ +#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 +#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */ +#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 +#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */ +#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 +}; + + +/* + * The eth aggregative context of Tstorm + */ +struct tstorm_eth_ag_context +{ + uint32_t __reserved0[14]; +}; + + +/* + * The eth aggregative context of Ustorm + */ +struct ustorm_eth_ag_context +{ + uint32_t __reserved0; +#if defined(__BIG_ENDIAN) + uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; + uint8_t __reserved2; + uint16_t __reserved1; +#elif defined(__LITTLE_ENDIAN) + uint16_t __reserved1; + uint8_t __reserved2; + uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; +#endif + uint32_t __reserved3[6]; +}; + + +/* + * The eth aggregative context of Xstorm + */ +struct xstorm_eth_ag_context +{ + uint32_t reserved0; +#if defined(__BIG_ENDIAN) + uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; + uint8_t reserved2; + uint16_t reserved1; +#elif defined(__LITTLE_ENDIAN) + uint16_t reserved1; + uint8_t reserved2; + uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; +#endif + uint32_t reserved3[30]; +}; + + +/* + * doorbell message sent to the chip + */ +struct doorbell +{ +#if defined(__BIG_ENDIAN) + uint16_t zero_fill2 /* driver must zero this field! */; + uint8_t zero_fill1 /* driver must zero this field! */; + struct doorbell_hdr header; +#elif defined(__LITTLE_ENDIAN) + struct doorbell_hdr header; + uint8_t zero_fill1 /* driver must zero this field! */; + uint16_t zero_fill2 /* driver must zero this field! */; +#endif +}; + + +/* + * doorbell message sent to the chip + */ +struct doorbell_set_prod +{ +#if defined(__BIG_ENDIAN) + uint16_t prod /* Producer index to be set */; + uint8_t zero_fill1 /* driver must zero this field! */; + struct doorbell_hdr header; +#elif defined(__LITTLE_ENDIAN) + struct doorbell_hdr header; + uint8_t zero_fill1 /* driver must zero this field! */; + uint16_t prod /* Producer index to be set */; +#endif +}; + + +struct regpair +{ + uint32_t lo /* low word for reg-pair */; + uint32_t hi /* high word for reg-pair */; +}; + + +struct regpair_native +{ + uint32_t lo /* low word for reg-pair */; + uint32_t hi /* high word for reg-pair */; +}; + + +/* + * Classify rule opcodes in E2/E3 + */ +enum classify_rule +{ + CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */, + CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */, + CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */, + MAX_CLASSIFY_RULE}; + + +/* + * Classify rule types in E2/E3 + */ +enum classify_rule_action_type +{ + CLASSIFY_RULE_REMOVE, + CLASSIFY_RULE_ADD, + MAX_CLASSIFY_RULE_ACTION_TYPE}; + + +/* + * client init ramrod data $$KEEP_ENDIANNESS$$ + */ +struct client_init_general_data +{ + uint8_t client_id /* client_id */; + uint8_t statistics_counter_id /* statistics counter id */; + uint8_t statistics_en_flg /* statistics en flg */; + uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */; + uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; + uint8_t sp_client_id /* the slow path rings client Id. */; + uint16_t mtu /* Host MTU from client config */; + uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */; + uint8_t func_id /* PCI function ID (0-71) */; + uint8_t cos /* The connection cos, if applicable */; + uint8_t traffic_type; + uint32_t reserved0; +}; + + +/* + * client init rx data $$KEEP_ENDIANNESS$$ + */ +struct client_init_rx_data +{ + uint8_t tpa_en; +#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */ +#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 +#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */ +#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 +#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */ +#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 +#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */ +#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 + uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */; + uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */; + uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */; + uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */; + uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; + uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */; + uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */; + uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */; + uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */; + uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */; + uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */; + uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */; + uint8_t status_block_id /* rx status block id */; + uint8_t rx_sb_index_number /* status block indices */; + uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; + uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; + uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; + uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */; + uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; + uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */; + uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */; + struct regpair bd_page_base /* BD page base address at the host */; + struct regpair sge_page_base /* SGE page base address at the host */; + struct regpair cqe_page_base /* Completion queue base address */; + uint8_t is_leading_rss; + uint8_t is_approx_mcast; + uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; + uint16_t state; +#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */ +#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 +#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */ +#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 +#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */ +#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 +#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */ +#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 +#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */ +#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 +#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */ +#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 +#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */ +#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 +#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */ +#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 + uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */; + uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */; + uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */; + uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */; + uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; + uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; + uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */; + uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; + uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; + uint32_t reserved6[2]; +}; + +/* + * client init tx data $$KEEP_ENDIANNESS$$ + */ +struct client_init_tx_data +{ + uint8_t enforce_security_flg /* if set, security checks will be made for this connection */; + uint8_t tx_status_block_id /* the number of status block to update */; + uint8_t tx_sb_index_number /* the index to use inside the status block */; + uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */; + uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */; + uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */; + uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; + struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */; + uint16_t state; +#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */ +#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 +#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */ +#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 +#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */ +#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 +#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */ +#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 +#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */ +#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 + uint8_t default_vlan_flg /* is default vlan valid for this client. */; + uint8_t force_default_pri_flg /* if set, force default priority */; + uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */; + uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */; + uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */; + uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */; +}; + +/* + * client init ramrod data $$KEEP_ENDIANNESS$$ + */ +struct client_init_ramrod_data +{ + struct client_init_general_data general /* client init general data */; + struct client_init_rx_data rx /* client init rx data */; + struct client_init_tx_data tx /* client init tx data */; +}; + + +/* + * client update ramrod data $$KEEP_ENDIANNESS$$ + */ +struct client_update_ramrod_data +{ + uint8_t client_id /* the client to update */; + uint8_t func_id /* PCI function ID this client belongs to (0-71) */; + uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */; + uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */; + uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */; + uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */; + uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */; + uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */; + uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; + uint8_t activate_change_flg /* If set, activate_flg will be checked */; + uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; + uint8_t default_vlan_enable_flg; + uint8_t default_vlan_change_flg; + uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; + uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; + uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; + uint8_t silent_vlan_change_flg; + uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */; + uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */; + uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */; + uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */; + uint32_t reserved1; + uint32_t echo /* echo value to be sent to driver on event ring */; +}; + + +/* + * The eth storm context of Cstorm + */ +struct cstorm_eth_st_context +{ + uint32_t __reserved0[4]; +}; + + +struct double_regpair +{ + uint32_t regpair0_lo /* low word for reg-pair0 */; + uint32_t regpair0_hi /* high word for reg-pair0 */; + uint32_t regpair1_lo /* low word for reg-pair1 */; + uint32_t regpair1_hi /* high word for reg-pair1 */; +}; + + +/* + * Ethernet address typesm used in ethernet tx BDs + */ +enum eth_addr_type +{ + UNKNOWN_ADDRESS, + UNICAST_ADDRESS, + MULTICAST_ADDRESS, + BROADCAST_ADDRESS, + MAX_ETH_ADDR_TYPE}; + + +/* + * $$KEEP_ENDIANNESS$$ + */ +struct eth_classify_cmd_header +{ + uint8_t cmd_general_data; +#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ +#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 +#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ +#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 +#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */ +#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 +#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */ +#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 +#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */ +#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 + uint8_t func_id /* the function id */; + uint8_t client_id; + uint8_t reserved1; +}; + + +/* + * header for eth classification config ramrod $$KEEP_ENDIANNESS$$ + */ +struct eth_classify_header +{ + uint8_t rule_cnt /* number of rules in classification config ramrod */; + uint8_t reserved0; + uint16_t reserved1; + uint32_t echo /* echo value to be sent to driver on event ring */; +}; + + +/* + * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$ + */ +struct eth_classify_mac_cmd +{ + struct eth_classify_cmd_header header; + uint16_t reserved0; + uint16_t inner_mac; + uint16_t mac_lsb; + uint16_t mac_mid; + uint16_t mac_msb; + uint16_t reserved1; +}; + + +/* + * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$ + */ +struct eth_classify_pair_cmd +{ + struct eth_classify_cmd_header header; + uint16_t reserved0; + uint16_t inner_mac; + uint16_t mac_lsb; + uint16_t mac_mid; + uint16_t mac_msb; + uint16_t vlan; +}; + + +/* + * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$ + */ +struct eth_classify_vlan_cmd +{ + struct eth_classify_cmd_header header; + uint32_t reserved0; + uint32_t reserved1; + uint16_t reserved2; + uint16_t vlan; +}; + +/* + * union for eth classification rule $$KEEP_ENDIANNESS$$ + */ +union eth_classify_rule_cmd +{ + struct eth_classify_mac_cmd mac; + struct eth_classify_vlan_cmd vlan; + struct eth_classify_pair_cmd pair; +}; + +/* + * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ + */ +struct eth_classify_rules_ramrod_data +{ + struct eth_classify_header header; + union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; +}; + + +/* + * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$ + */ +struct eth_common_ramrod_data +{ + uint32_t client_id /* id of this client. (5 bits are used) */; + uint32_t reserved1; +}; + + +/* + * The eth storm context of Ustorm + */ +struct ustorm_eth_st_context +{ + uint32_t reserved0[52]; +}; + +/* + * The eth storm context of Tstorm + */ +struct tstorm_eth_st_context +{ + uint32_t __reserved0[28]; +}; + +/* + * The eth storm context of Xstorm + */ +struct xstorm_eth_st_context +{ + uint32_t reserved0[60]; +}; + +/* + * Ethernet connection context + */ +struct eth_context +{ + struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */; + struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */; + struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */; + struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */; + struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */; + struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */; + struct timers_block_context timers_context /* Timers block context */; + struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */; + struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */; +}; + + +/* + * union for sgl and raw data. + */ +union eth_sgl_or_raw_data +{ + uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */; + uint32_t raw_data[4] /* raw data from Tstorm to the driver. */; +}; + +/* + * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$ + */ +struct eth_end_agg_rx_cqe +{ + uint8_t type_error_flags; +#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ +#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 +#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ +#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 +#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */ +#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 + uint8_t reserved1; + uint8_t queue_index /* The aggregation queue index of this packet */; + uint8_t reserved2; + uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */; + uint16_t num_of_coalesced_segs /* Num of coalesced segments. */; + uint16_t pkt_len /* Packet length */; + uint8_t pure_ack_count /* Number of pure acks coalesced. */; + uint8_t reserved3; + uint16_t reserved4; + union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; + uint32_t reserved5[8]; +}; + + +/* + * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$ + */ +struct eth_fast_path_rx_cqe +{ + uint8_t type_error_flags; +#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ +#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 +#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ +#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 +#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */ +#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 +#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */ +#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 +#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */ +#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 +#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */ +#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 + uint8_t status_flags; +#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */ +#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 +#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */ +#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 +#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */ +#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 +#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */ +#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 +#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */ +#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 +#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */ +#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 + uint8_t queue_index /* The aggregation queue index of this packet */; + uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */; + uint32_t rss_hash_result /* RSS toeplitz hash result */; + uint16_t vlan_tag /* Ethernet VLAN tag field */; + uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */; + uint16_t len_on_bd /* Number of bytes placed on the BD */; + struct parsing_flags pars_flags; + union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; + uint32_t reserved1[8]; +}; + + +/* + * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$ + */ +struct eth_filter_rules_cmd +{ + uint8_t cmd_general_data; +#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ +#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 +#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ +#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 +#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */ +#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 + uint8_t func_id /* the function id */; + uint8_t client_id /* the client id */; + uint8_t reserved1; + uint16_t state; +#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */ +#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 +#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */ +#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 +#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */ +#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 +#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */ +#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 +#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */ +#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 +#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */ +#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 +#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */ +#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 +#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */ +#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 + uint16_t reserved3; + struct regpair reserved4; +}; + + +/* + * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$ + */ +struct eth_filter_rules_ramrod_data +{ + struct eth_classify_header header; + struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; +}; + + +/* + * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ + */ +struct eth_general_rules_ramrod_data +{ + struct eth_classify_header header; + union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; +}; + + +/* + * The data for Halt ramrod + */ +struct eth_halt_ramrod_data +{ + uint32_t client_id /* id of this client. (5 bits are used) */; + uint32_t reserved0; +}; + + +/* + * destination and source mac address. + */ +struct eth_mac_addresses +{ +#if defined(__BIG_ENDIAN) + uint16_t dst_mid /* destination mac address 16 middle bits */; + uint16_t dst_lo /* destination mac address 16 low bits */; +#elif defined(__LITTLE_ENDIAN) + uint16_t dst_lo /* destination mac address 16 low bits */; + uint16_t dst_mid /* destination mac address 16 middle bits */; +#endif +#if defined(__BIG_ENDIAN) + uint16_t src_lo /* source mac address 16 low bits */; + uint16_t dst_hi /* destination mac address 16 high bits */; +#elif defined(__LITTLE_ENDIAN) + uint16_t dst_hi /* destination mac address 16 high bits */; + uint16_t src_lo /* source mac address 16 low bits */; +#endif +#if defined(__BIG_ENDIAN) + uint16_t src_hi /* source mac address 16 high bits */; + uint16_t src_mid /* source mac address 16 middle bits */; +#elif defined(__LITTLE_ENDIAN) + uint16_t src_mid /* source mac address 16 middle bits */; + uint16_t src_hi /* source mac address 16 high bits */; +#endif +}; + + +/* + * tunneling related data. + */ +struct eth_tunnel_data +{ +#if defined(__BIG_ENDIAN) + uint16_t dst_mid /* destination mac address 16 middle bits */; + uint16_t dst_lo /* destination mac address 16 low bits */; +#elif defined(__LITTLE_ENDIAN) + uint16_t dst_lo /* destination mac address 16 low bits */; + uint16_t dst_mid /* destination mac address 16 middle bits */; +#endif +#if defined(__BIG_ENDIAN) + uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; + uint16_t dst_hi /* destination mac address 16 high bits */; +#elif defined(__LITTLE_ENDIAN) + uint16_t dst_hi /* destination mac address 16 high bits */; + uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; +#endif +#if defined(__BIG_ENDIAN) + uint8_t flags; +#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ +#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 +#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ +#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 + uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; + uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; +#elif defined(__LITTLE_ENDIAN) + uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; + uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; + uint8_t flags; +#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ +#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 +#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ +#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 +#endif +}; + +/* + * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). + */ +union eth_mac_addr_or_tunnel_data +{ + struct eth_mac_addresses mac_addr /* destination and source mac addresses. */; + struct eth_tunnel_data tunnel_data /* tunneling related data. */; +}; + + +/* + * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$ + */ +struct eth_multicast_rules_cmd +{ + uint8_t cmd_general_data; +#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ +#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 +#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ +#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 +#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */ +#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 +#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */ +#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 + uint8_t func_id /* the function id */; + uint8_t bin_id /* the bin to add this function to (0-255) */; + uint8_t engine_id /* the approximate multicast engine id */; + uint32_t reserved2; + struct regpair reserved3; +}; + + +/* + * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$ + */ +struct eth_multicast_rules_ramrod_data +{ + struct eth_classify_header header; + struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; +}; + + +/* + * Place holder for ramrods protocol specific data + */ +struct ramrod_data +{ + uint32_t data_lo; + uint32_t data_hi; +}; + +/* + * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) + */ +union eth_ramrod_data +{ + struct ramrod_data general; +}; + + +/* + * RSS toeplitz hash type, as reported in CQE + */ +enum eth_rss_hash_type +{ + DEFAULT_HASH_TYPE, + IPV4_HASH_TYPE, + TCP_IPV4_HASH_TYPE, + IPV6_HASH_TYPE, + TCP_IPV6_HASH_TYPE, + VLAN_PRI_HASH_TYPE, + E1HOV_PRI_HASH_TYPE, + DSCP_HASH_TYPE, + MAX_ETH_RSS_HASH_TYPE}; + + +/* + * Ethernet RSS mode + */ +enum eth_rss_mode +{ + ETH_RSS_MODE_DISABLED, + ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */, + ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, + ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */, + ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */, + ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */, + MAX_ETH_RSS_MODE}; + + +/* + * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$ + */ +struct eth_rss_update_ramrod_data +{ + uint8_t rss_engine_id; + uint8_t capabilities; +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */ +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */ +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */ +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */ +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */ +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */ +#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 +#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */ +#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 +#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */ +#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 + uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; + uint8_t rss_mode /* The RSS mode for this function */; + uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; + uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; + uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */; + uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */; + uint32_t echo; + uint32_t reserved3; +}; + + +/* + * The eth Rx Buffer Descriptor + */ +struct eth_rx_bd +{ + uint32_t addr_lo /* Single continuous buffer low pointer */; + uint32_t addr_hi /* Single continuous buffer high pointer */; +}; + + +/* + * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$ + */ +struct common_ramrod_eth_rx_cqe +{ + uint8_t ramrod_type; +#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */ +#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 +#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */ +#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 +#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */ +#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 + uint8_t conn_type /* only 3 bits are used */; + uint16_t reserved1 /* protocol specific data */; + uint32_t conn_and_cmd_data; +#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ +#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 +#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */ +#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 + struct ramrod_data protocol_data /* protocol specific data */; + uint32_t echo; + uint32_t reserved2[11]; +}; + +/* + * Rx Last CQE in page (in ETH) + */ +struct eth_rx_cqe_next_page +{ + uint32_t addr_lo /* Next page low pointer */; + uint32_t addr_hi /* Next page high pointer */; + uint32_t reserved[14]; +}; + +/* + * union for all eth rx cqe types (fix their sizes) + */ +union eth_rx_cqe +{ + struct eth_fast_path_rx_cqe fast_path_cqe; + struct common_ramrod_eth_rx_cqe ramrod_cqe; + struct eth_rx_cqe_next_page next_page_cqe; + struct eth_end_agg_rx_cqe end_agg_cqe; +}; + + +/* + * Values for RX ETH CQE type field + */ +enum eth_rx_cqe_type +{ + RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */, + RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */, + RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */, + RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */, + MAX_ETH_RX_CQE_TYPE}; + + +/* + * Type of SGL/Raw field in ETH RX fast path CQE + */ +enum eth_rx_fp_sel +{ + ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */, + ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */, + MAX_ETH_RX_FP_SEL}; + + +/* + * The eth Rx SGE Descriptor + */ +struct eth_rx_sge +{ + uint32_t addr_lo /* Single continuous buffer low pointer */; + uint32_t addr_hi /* Single continuous buffer high pointer */; +}; + + +/* + * common data for all protocols $$KEEP_ENDIANNESS$$ + */ +struct spe_hdr +{ + uint32_t conn_and_cmd_data; +#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ +#define SPE_HDR_CID_SHIFT 0 +#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */ +#define SPE_HDR_CMD_ID_SHIFT 24 + uint16_t type; +#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */ +#define SPE_HDR_CONN_TYPE_SHIFT 0 +#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */ +#define SPE_HDR_FUNCTION_ID_SHIFT 8 + uint16_t reserved1; +}; + +/* + * specific data for ethernet slow path element + */ +union eth_specific_data +{ + uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; + struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */; + struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */; + struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */; + struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */; + struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */; + struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */; + struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */; + struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */; +}; + +/* + * Ethernet slow path element + */ +struct eth_spe +{ + struct spe_hdr hdr /* common data for all protocols */; + union eth_specific_data data /* data specific to ethernet protocol */; +}; + + +/* + * Ethernet command ID for slow path elements + */ +enum eth_spqe_cmd_id +{ + RAMROD_CMD_ID_ETH_UNUSED, + RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */, + RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */, + RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */, + RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */, + RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */, + RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */, + RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */, + RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */, + RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, + RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, + RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, + RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */, + RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */, + MAX_ETH_SPQE_CMD_ID}; + + +/* + * eth tpa update command + */ +enum eth_tpa_update_command +{ + TPA_UPDATE_NONE_COMMAND /* nop command */, + TPA_UPDATE_ENABLE_COMMAND /* enable command */, + TPA_UPDATE_DISABLE_COMMAND /* disable command */, + MAX_ETH_TPA_UPDATE_COMMAND}; + + +/* + * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header + */ +enum eth_tunnel_lso_inc_ip_id +{ + EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */, + INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */, + MAX_ETH_TUNNEL_LSO_INC_IP_ID}; + + +/* + * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD. + */ +enum eth_tunnel_non_lso_csum_location +{ + CSUM_ON_PKT /* checksum is on the packet. */, + CSUM_ON_BD /* checksum is on the BD. */, + MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION}; + + +/* + * Tx regular BD structure $$KEEP_ENDIANNESS$$ + */ +struct eth_tx_bd +{ + uint32_t addr_lo /* Single continuous buffer low pointer */; + uint32_t addr_hi /* Single continuous buffer high pointer */; + uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */; + uint16_t nbytes /* Size of the data represented by the BD */; + uint8_t reserved[4] /* keeps same size as other eth tx bd types */; +}; + + +/* + * structure for easy accessibility to assembler + */ +struct eth_tx_bd_flags +{ + uint8_t as_bitfield; +#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */ +#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 +#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */ +#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 +#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */ +#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 +#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */ +#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 +#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */ +#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 +#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */ +#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 +#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */ +#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 +}; + +/* + * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$ + */ +struct eth_tx_start_bd +{ + uint64_t addr; + uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */; + uint16_t nbytes /* Size of the data represented by the BD */; + uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */; + struct eth_tx_bd_flags bd_flags; + uint8_t general_data; +#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */ +#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 +#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */ +#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 +#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */ +#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 +#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */ +#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 +}; + +/* + * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$ + */ +struct eth_tx_parse_bd_e1x +{ + uint16_t global_data; +#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */ +#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 +#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */ +#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 +#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */ +#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 +#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */ +#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 +#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ +#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 +#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */ +#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 + uint8_t tcp_flags; +#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ +#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 +#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ +#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 +#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ +#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 +#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ +#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 +#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ +#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 +#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ +#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 +#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ +#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 +#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ +#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 + uint8_t ip_hlen_w /* IP header length in WORDs */; + uint16_t total_hlen_w /* IP+TCP+ETH */; + uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */; + uint16_t lso_mss /* for LSO mode */; + uint16_t ip_id /* for LSO mode */; + uint32_t tcp_send_seq /* for LSO mode */; +}; + +/* + * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$ + */ +struct eth_tx_parse_bd_e2 +{ + union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */; + uint32_t parsing_data; +#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */ +#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 +#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */ +#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 +#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */ +#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 +#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */ +#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 +#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */ +#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 +}; + +/* + * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$ + */ +struct eth_tx_parse_2nd_bd +{ + uint16_t global_data; +#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */ +#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 +#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */ +#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 +#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */ +#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 +#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ +#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 +#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */ +#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 +#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */ +#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 +#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */ +#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 + uint16_t reserved2; + uint8_t tcp_flags; +#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ +#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 +#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ +#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 +#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ +#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 +#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ +#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 +#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ +#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 +#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ +#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 +#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ +#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 +#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ +#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 + uint8_t reserved3; + uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */; + uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */; + uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */; + uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */; + uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */; +}; + +/* + * The last BD in the BD memory will hold a pointer to the next BD memory + */ +struct eth_tx_next_bd +{ + uint32_t addr_lo /* Single continuous buffer low pointer */; + uint32_t addr_hi /* Single continuous buffer high pointer */; + uint8_t reserved[8] /* keeps same size as other eth tx bd types */; +}; + +/* + * union for 4 Bd types + */ +union eth_tx_bd_types +{ + struct eth_tx_start_bd start_bd /* the first bd in a packets */; + struct eth_tx_bd reg_bd /* the common bd */; + struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */; + struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */; + struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */; + struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */; +}; + +/* + * array of 13 bds as appears in the eth xstorm context + */ +struct eth_tx_bds_array +{ + union eth_tx_bd_types bds[13]; +}; + + +/* + * VLAN mode on TX BDs + */ +enum eth_tx_vlan_type +{ + X_ETH_NO_VLAN, + X_ETH_OUTBAND_VLAN, + X_ETH_INBAND_VLAN, + X_ETH_FW_ADDED_VLAN /* Driver should not use this! */, + MAX_ETH_TX_VLAN_TYPE}; + + +/* + * Ethernet VLAN filtering mode in E1x + */ +enum eth_vlan_filter_mode +{ + ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */, + ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */, + ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */, + MAX_ETH_VLAN_FILTER_MODE}; + + +/* + * MAC filtering configuration command header $$KEEP_ENDIANNESS$$ + */ +struct mac_configuration_hdr +{ + uint8_t length /* number of entries valid in this command (6 bits) */; + uint8_t offset /* offset of the first entry in the list */; + uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */; + uint32_t echo /* echo value to be sent to driver on event ring */; +}; + +/* + * MAC address in list for ramrod $$KEEP_ENDIANNESS$$ + */ +struct mac_configuration_entry +{ + uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; + uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */; + uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; + uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */; + uint8_t pf_id /* The pf id, for multi function mode */; + uint8_t flags; +#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */ +#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 +#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */ +#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 +#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */ +#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 +#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */ +#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 +#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */ +#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 +#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */ +#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 + uint16_t reserved0; + uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */; +}; + +/* + * MAC filtering configuration command + */ +struct mac_configuration_cmd +{ + struct mac_configuration_hdr hdr /* header */; + struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */; +}; + + +/* + * Set-MAC command type (in E1x) + */ +enum set_mac_action_type +{ + T_ETH_MAC_COMMAND_INVALIDATE, + T_ETH_MAC_COMMAND_SET, + MAX_SET_MAC_ACTION_TYPE}; + + +/* + * Ethernet TPA Modes + */ +enum tpa_mode +{ + TPA_LRO /* LRO mode TPA */, + TPA_GRO /* GRO mode TPA */, + MAX_TPA_MODE}; + + +/* + * tpa update ramrod data $$KEEP_ENDIANNESS$$ + */ +struct tpa_update_ramrod_data +{ + uint8_t update_ipv4 /* none, enable or disable */; + uint8_t update_ipv6 /* none, enable or disable */; + uint8_t client_id /* client init flow control data */; + uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; + uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; + uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */; + uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; + uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */; + uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; + uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; + uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */; + uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */; + uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; + uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; +}; + + +/* + * approximate-match multicast filtering for E1H per function in Tstorm + */ +struct tstorm_eth_approximate_match_multicast_filtering +{ + uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */; +}; + + +/* + * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$ + */ +struct tstorm_eth_function_common_config +{ + uint16_t config_flags; +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */ +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */ +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */ +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */ +#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 +#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */ +#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 + uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; + uint8_t reserved1; + uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */; +}; + + +/* + * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$ + */ +struct tstorm_eth_mac_filter_config +{ + uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */; + uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */; + uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */; + uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */; + uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */; + uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */; + uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */; +}; + + +/* + * tx only queue init ramrod data $$KEEP_ENDIANNESS$$ + */ +struct tx_queue_init_ramrod_data +{ + struct client_init_general_data general /* client init general data */; + struct client_init_tx_data tx /* client init tx data */; +}; + + +/* + * Three RX producers for ETH + */ +union ustorm_eth_rx_producers +{ + struct { +#if defined(__BIG_ENDIAN) + uint16_t bd_prod /* Producer of the RX BD ring */; + uint16_t cqe_prod /* Producer of the RX CQE ring */; +#elif defined(__LITTLE_ENDIAN) + uint16_t cqe_prod /* Producer of the RX CQE ring */; + uint16_t bd_prod /* Producer of the RX BD ring */; +#endif +#if defined(__BIG_ENDIAN) + uint16_t reserved; + uint16_t sge_prod /* Producer of the RX SGE ring */; +#elif defined(__LITTLE_ENDIAN) + uint16_t sge_prod /* Producer of the RX SGE ring */; + uint16_t reserved; +#endif + } prod; + uint32_t raw_data[2]; +}; + + +/* + * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$ + */ +struct afex_vif_list_ramrod_data +{ + uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */; + uint8_t func_bit_map /* the function bit map to set */; + uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */; + uint8_t func_to_clear /* the func id to clear in case of clear func mode */; + uint8_t echo; + uint16_t reserved1; +}; + + +/* + * cfc delete event data $$KEEP_ENDIANNESS$$ + */ +struct cfc_del_event_data +{ + uint32_t cid /* cid of deleted connection */; + uint32_t reserved0; + uint32_t reserved1; +}; + + +/* + * per-port SAFC demo variables + */ +struct cmng_flags_per_port +{ + uint32_t cmng_enables; +#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */ +#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 +#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */ +#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 +#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */ +#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 +#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */ +#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 +#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */ +#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 + uint32_t __reserved1; +}; + + +/* + * per-port rate shaping variables + */ +struct rate_shaping_vars_per_port +{ + uint32_t rs_periodic_timeout /* timeout of periodic timer */; + uint32_t rs_threshold /* threshold, below which we start to stop queues */; +}; + +/* + * per-port fairness variables + */ +struct fairness_vars_per_port +{ + uint32_t upper_bound /* Quota for a protocol/vnic */; + uint32_t fair_threshold /* almost-empty threshold */; + uint32_t fairness_timeout /* timeout of fairness timer */; + uint32_t reserved0; +}; + +/* + * per-port SAFC variables + */ +struct safc_struct_per_port +{ +#if defined(__BIG_ENDIAN) + uint16_t __reserved1; + uint8_t __reserved0; + uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; +#elif defined(__LITTLE_ENDIAN) + uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; + uint8_t __reserved0; + uint16_t __reserved1; +#endif + uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */; + uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */; +}; + +/* + * Per-port congestion management variables + */ +struct cmng_struct_per_port +{ + struct rate_shaping_vars_per_port rs_vars; + struct fairness_vars_per_port fair_vars; + struct safc_struct_per_port safc_vars; + struct cmng_flags_per_port flags; +}; + +/* + * a single rate shaping counter. can be used as protocol or vnic counter + */ +struct rate_shaping_counter +{ + uint32_t quota /* Quota for a protocol/vnic */; +#if defined(__BIG_ENDIAN) + uint16_t __reserved0; + uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; +#elif defined(__LITTLE_ENDIAN) + uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; + uint16_t __reserved0; +#endif +}; + +/* + * per-vnic rate shaping variables + */ +struct rate_shaping_vars_per_vn +{ + struct rate_shaping_counter vn_counter /* per-vnic counter */; +}; + +/* + * per-vnic fairness variables + */ +struct fairness_vars_per_vn +{ + uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */; + uint32_t vn_credit_delta /* used for incrementing the credit */; + uint32_t __reserved0; +}; + +/* + * cmng port init state + */ +struct cmng_vnic +{ + struct rate_shaping_vars_per_vn vnic_max_rate[4]; + struct fairness_vars_per_vn vnic_min_rate[4]; +}; + +/* + * cmng port init state + */ +struct cmng_init +{ + struct cmng_struct_per_port port; + struct cmng_vnic vnic; +}; + + +/* + * driver parameters for congestion management init, all rates are in Mbps + */ +struct cmng_init_input +{ + uint32_t port_rate; + uint16_t vnic_min_rate[4] /* rates are in Mbps */; + uint16_t vnic_max_rate[4] /* rates are in Mbps */; + uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */; + uint16_t cos_to_pause_mask[MAX_COS_NUMBER]; + struct cmng_flags_per_port flags; +}; + + +/* + * Protocol-common command ID for slow path elements + */ +enum common_spqe_cmd_id +{ + RAMROD_CMD_ID_COMMON_UNUSED, + RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */, + RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */, + RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */, + RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */, + RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, + RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */, + RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, + RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, + RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */, + RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, + MAX_COMMON_SPQE_CMD_ID}; + + +/* + * Per-protocol connection types + */ +enum connection_type +{ + ETH_CONNECTION_TYPE /* Ethernet */, + TOE_CONNECTION_TYPE /* TOE */, + RDMA_CONNECTION_TYPE /* RDMA */, + ISCSI_CONNECTION_TYPE /* iSCSI */, + FCOE_CONNECTION_TYPE /* FCoE */, + RESERVED_CONNECTION_TYPE_0, + RESERVED_CONNECTION_TYPE_1, + RESERVED_CONNECTION_TYPE_2, + NONE_CONNECTION_TYPE /* General- used for common slow path */, + MAX_CONNECTION_TYPE}; + + +/* + * Cos modes + */ +enum cos_mode +{ + OVERRIDE_COS /* Firmware deduce cos according to DCB */, + STATIC_COS /* Firmware has constant queues per CoS */, + FW_WRR /* Firmware keep fairness between different CoSes */, + MAX_COS_MODE}; + + +/* + * Dynamic HC counters set by the driver + */ +struct hc_dynamic_drv_counter +{ + uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */; +}; + +/* + * zone A per-queue data + */ +struct cstorm_queue_zone_data +{ + struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */; + struct regpair reserved[2]; +}; + + +/* + * Vf-PF channel data in cstorm ram (non-triggered zone) + */ +struct vf_pf_channel_zone_data +{ + uint32_t msg_addr_lo /* the message address on VF memory */; + uint32_t msg_addr_hi /* the message address on VF memory */; +}; + +/* + * zone for VF non-triggered data + */ +struct non_trigger_vf_zone +{ + struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */; +}; + +/* + * Vf-PF channel trigger zone in cstorm ram + */ +struct vf_pf_channel_zone_trigger +{ + uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */; +}; + +/* + * zone that triggers the in-bound interrupt + */ +struct trigger_vf_zone +{ +#if defined(__BIG_ENDIAN) + uint16_t reserved1; + uint8_t reserved0; + struct vf_pf_channel_zone_trigger vf_pf_channel; +#elif defined(__LITTLE_ENDIAN) + struct vf_pf_channel_zone_trigger vf_pf_channel; + uint8_t reserved0; + uint16_t reserved1; +#endif + uint32_t reserved2; +}; + +/* + * zone B per-VF data + */ +struct cstorm_vf_zone_data +{ + struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */; + struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */; +}; + + +/* + * Dynamic host coalescing init parameters, per state machine + */ +struct dynamic_hc_sm_config +{ + uint32_t threshold[3] /* thresholds of number of outstanding bytes */; + uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */; + uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */; + uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */; + uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */; + uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */; +}; + +/* + * Dynamic host coalescing init parameters + */ +struct dynamic_hc_config +{ + struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */; +}; + + +struct e2_integ_data +{ +#if defined(__BIG_ENDIAN) + uint8_t flags; +#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ +#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 +#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ +#define E2_INTEG_DATA_LB_TX_SHIFT 1 +#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ +#define E2_INTEG_DATA_COS_TX_SHIFT 2 +#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ +#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 +#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ +#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 +#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ +#define E2_INTEG_DATA_RESERVED_SHIFT 5 + uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; + uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; + uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; +#elif defined(__LITTLE_ENDIAN) + uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; + uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; + uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; + uint8_t flags; +#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ +#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 +#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ +#define E2_INTEG_DATA_LB_TX_SHIFT 1 +#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ +#define E2_INTEG_DATA_COS_TX_SHIFT 2 +#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ +#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 +#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ +#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 +#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ +#define E2_INTEG_DATA_RESERVED_SHIFT 5 +#endif +#if defined(__BIG_ENDIAN) + uint16_t reserved3; + uint8_t reserved2; + uint8_t ramEn /* context area reserved for reading enable bit from ram */; +#elif defined(__LITTLE_ENDIAN) + uint8_t ramEn /* context area reserved for reading enable bit from ram */; + uint8_t reserved2; + uint16_t reserved3; +#endif +}; + + +/* + * set mac event data $$KEEP_ENDIANNESS$$ + */ +struct eth_event_data +{ + uint32_t echo /* set mac echo data to return to driver */; + uint32_t reserved0; + uint32_t reserved1; +}; + + +/* + * pf-vf event data $$KEEP_ENDIANNESS$$ + */ +struct vf_pf_event_data +{ + uint8_t vf_id /* VF ID (0-63) */; + uint8_t reserved0; + uint16_t reserved1; + uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */; + uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */; +}; + +/* + * VF FLR event data $$KEEP_ENDIANNESS$$ + */ +struct vf_flr_event_data +{ + uint8_t vf_id /* VF ID (0-63) */; + uint8_t reserved0; + uint16_t reserved1; + uint32_t reserved2; + uint32_t reserved3; +}; + +/* + * malicious VF event data $$KEEP_ENDIANNESS$$ + */ +struct malicious_vf_event_data +{ + uint8_t vf_id /* VF ID (0-63) */; + uint8_t err_id /* reason for malicious notification */; + uint16_t reserved1; + uint32_t reserved2; + uint32_t reserved3; +}; + +/* + * vif list event data $$KEEP_ENDIANNESS$$ + */ +struct vif_list_event_data +{ + uint8_t func_bit_map /* bit map of pf indice */; + uint8_t echo; + uint16_t reserved0; + uint32_t reserved1; + uint32_t reserved2; +}; + +/* + * function update event data $$KEEP_ENDIANNESS$$ + */ +struct function_update_event_data +{ + uint8_t echo; + uint8_t reserved; + uint16_t reserved0; + uint32_t reserved1; + uint32_t reserved2; +}; + +/* + * union for all event ring message types + */ +union event_data +{ + struct vf_pf_event_data vf_pf_event /* vf-pf event data */; + struct eth_event_data eth_event /* set mac event data */; + struct cfc_del_event_data cfc_del_event /* cfc delete event data */; + struct vf_flr_event_data vf_flr_event /* vf flr event data */; + struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */; + struct vif_list_event_data vif_list_event /* vif list event data */; + struct function_update_event_data function_update_event /* function update event data */; +}; + + +/* + * per PF event ring data + */ +struct event_ring_data +{ + struct regpair_native base_addr /* ring base address */; +#if defined(__BIG_ENDIAN) + uint8_t index_id /* index ID within the status block */; + uint8_t sb_id /* status block ID */; + uint16_t producer /* event ring producer */; +#elif defined(__LITTLE_ENDIAN) + uint16_t producer /* event ring producer */; + uint8_t sb_id /* status block ID */; + uint8_t index_id /* index ID within the status block */; +#endif + uint32_t reserved0; +}; + + +/* + * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$ + */ +struct event_ring_msg +{ + uint8_t opcode; + uint8_t error /* error on the mesasage */; + uint16_t reserved1; + union event_data data /* message data (96 bits data) */; +}; + +/* + * event ring next page element (128 bits) + */ +struct event_ring_next +{ + struct regpair addr /* Address of the next page of the ring */; + uint32_t reserved[2]; +}; + +/* + * union for event ring element types (each element is 128 bits) + */ +union event_ring_elem +{ + struct event_ring_msg message /* event ring message */; + struct event_ring_next next_page /* event ring next page */; +}; + + +/* + * Common event ring opcodes + */ +enum event_ring_opcode +{ + EVENT_RING_OPCODE_VF_PF_CHANNEL, + EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */, + EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */, + EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */, + EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, + EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */, + EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, + EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, + EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */, + EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */, + EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */, + EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */, + EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */, + EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */, + EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */, + EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */, + EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, + EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, + EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, + MAX_EVENT_RING_OPCODE}; + + +/* + * Modes for fairness algorithm + */ +enum fairness_mode +{ + FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */, + FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */, + MAX_FAIRNESS_MODE}; + + +/* + * Priority and cos $$KEEP_ENDIANNESS$$ + */ +struct priority_cos +{ + uint8_t priority /* Priority */; + uint8_t cos /* Cos */; + uint16_t reserved1; +}; + +/* + * The data for flow control configuration $$KEEP_ENDIANNESS$$ + */ +struct flow_control_configuration +{ + struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */; + uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */; + uint8_t dcb_version /* DCB version Increase by one on each DCB update */; + uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */; + uint8_t reserved1; + uint32_t reserved2; +}; + + +/* + * $$KEEP_ENDIANNESS$$ + */ +struct function_start_data +{ + uint8_t function_mode /* the function mode */; + uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independant function mode. (E2/E3 Only) */; + uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */; + uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; + uint8_t path_id; + uint8_t network_cos_mode /* The cos mode for network traffic. */; + uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */; + uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; + uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; + uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; + uint16_t reserved1[2]; +}; + + +/* + * $$KEEP_ENDIANNESS$$ + */ +struct function_update_data +{ + uint8_t vif_id_change_flg /* If set, vif_id will be checked */; + uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */; + uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */; + uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */; + uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; + uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */; + uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */; + uint8_t network_cos_mode /* The cos mode for network traffic. */; + uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */; + uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */; + uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */; + uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */; + uint8_t echo; + uint8_t reserved1; + uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */; + uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; + uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; + uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; + uint32_t reserved3; +}; + + +/* + * FW version stored in the Xstorm RAM + */ +struct fw_version +{ +#if defined(__BIG_ENDIAN) + uint8_t engineering /* firmware current engineering version */; + uint8_t revision /* firmware current revision version */; + uint8_t minor /* firmware current minor version */; + uint8_t major /* firmware current major version */; +#elif defined(__LITTLE_ENDIAN) + uint8_t major /* firmware current major version */; + uint8_t minor /* firmware current minor version */; + uint8_t revision /* firmware current revision version */; + uint8_t engineering /* firmware current engineering version */; +#endif + uint32_t flags; +#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ +#define FW_VERSION_OPTIMIZED_SHIFT 0 +#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */ +#define FW_VERSION_BIG_ENDIEN_SHIFT 1 +#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 1 - E1H */ +#define FW_VERSION_CHIP_VERSION_SHIFT 2 +#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */ +#define __FW_VERSION_RESERVED_SHIFT 4 +}; + + +/* + * GRE RSS Mode + */ +enum gre_rss_mode +{ + GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */, + GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */, + NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */, + MAX_GRE_RSS_MODE}; + + +/* + * GRE Tunnel Mode + */ +enum gre_tunnel_type +{ + NO_GRE_TUNNEL, + NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */, + L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */, + IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */, + MAX_GRE_TUNNEL_TYPE}; + + +/* + * Dynamic Host-Coalescing - Driver(host) counters + */ +struct hc_dynamic_sb_drv_counters +{ + uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */; +}; + + +/* + * 2 bytes. configuration/state parameters for a single protocol index + */ +struct hc_index_data +{ +#if defined(__BIG_ENDIAN) + uint8_t flags; +#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ +#define HC_INDEX_DATA_SM_ID_SHIFT 0 +#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ +#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 +#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ +#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 +#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ +#define HC_INDEX_DATA_RESERVE_SHIFT 3 + uint8_t timeout /* the timeout values for this index. Units are 4 usec */; +#elif defined(__LITTLE_ENDIAN) + uint8_t timeout /* the timeout values for this index. Units are 4 usec */; + uint8_t flags; +#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ +#define HC_INDEX_DATA_SM_ID_SHIFT 0 +#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ +#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 +#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ +#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 +#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ +#define HC_INDEX_DATA_RESERVE_SHIFT 3 +#endif +}; + + +/* + * HC state-machine + */ +struct hc_status_block_sm +{ +#if defined(__BIG_ENDIAN) + uint8_t igu_seg_id; + uint8_t igu_sb_id /* sb_id within the IGU */; + uint8_t timer_value /* Determines the time_to_expire */; + uint8_t __flags; +#elif defined(__LITTLE_ENDIAN) + uint8_t __flags; + uint8_t timer_value /* Determines the time_to_expire */; + uint8_t igu_sb_id /* sb_id within the IGU */; + uint8_t igu_seg_id; +#endif + uint32_t time_to_expire /* The time in which it expects to wake up */; +}; + +/* + * hold PCI identification variables- used in various places in firmware + */ +struct pci_entity +{ +#if defined(__BIG_ENDIAN) + uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; + uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; + uint8_t vnic_id /* Virtual NIC ID (0-3) */; + uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; +#elif defined(__LITTLE_ENDIAN) + uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; + uint8_t vnic_id /* Virtual NIC ID (0-3) */; + uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; + uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; +#endif +}; + +/* + * The fast-path status block meta-data, common to all chips + */ +struct hc_sb_data +{ + struct regpair_native host_sb_addr /* Host status block address */; + struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */; + struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; +#if defined(__BIG_ENDIAN) + uint8_t rsrv0; + uint8_t state; + uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; + uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; +#elif defined(__LITTLE_ENDIAN) + uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; + uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; + uint8_t state; + uint8_t rsrv0; +#endif + struct regpair_native rsrv1[2]; +}; + + +/* + * Segment types for host coaslescing + */ +enum hc_segment +{ + HC_REGULAR_SEGMENT, + HC_DEFAULT_SEGMENT, + MAX_HC_SEGMENT}; + + +/* + * The fast-path status block meta-data + */ +struct hc_sp_status_block_data +{ + struct regpair_native host_sb_addr /* Host status block address */; +#if defined(__BIG_ENDIAN) + uint8_t rsrv1; + uint8_t state; + uint8_t igu_seg_id /* segment id of the IGU */; + uint8_t igu_sb_id /* sb_id within the IGU */; +#elif defined(__LITTLE_ENDIAN) + uint8_t igu_sb_id /* sb_id within the IGU */; + uint8_t igu_seg_id /* segment id of the IGU */; + uint8_t state; + uint8_t rsrv1; +#endif + struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; +}; + + +/* + * The fast-path status block meta-data + */ +struct hc_status_block_data_e1x +{ + struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */; + struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; +}; + + +/* + * The fast-path status block meta-data + */ +struct hc_status_block_data_e2 +{ + struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */; + struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; +}; + + +/* + * IGU block operartion modes (in Everest2) + */ +enum igu_mode +{ + HC_IGU_BC_MODE /* Backward compatible mode */, + HC_IGU_NBC_MODE /* Non-backward compatible mode */, + MAX_IGU_MODE}; + + +/* + * IP versions + */ +enum ip_ver +{ + IP_V4, + IP_V6, + MAX_IP_VER}; + + +/* + * Malicious VF error ID + */ +enum malicious_vf_error_id +{ + VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, + ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */, + ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */, + ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */, + ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */, + ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */, + ETH_TOO_MANY_BDS /* Tx packet has too many BDs */, + ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */, + ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */, + ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */, + ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */, + ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */, + ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */, + ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */, + MAX_MALICIOUS_VF_ERROR_ID}; + + +/* + * Multi-function modes + */ +enum mf_mode +{ + SINGLE_FUNCTION, + MULTI_FUNCTION_SD /* Switch dependent (vlan based) */, + MULTI_FUNCTION_SI /* Switch independent (mac based) */, + MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */, + MAX_MF_MODE}; + + +/* + * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$ + */ +struct tstorm_per_pf_stats +{ + struct regpair rcv_error_bytes /* number of bytes received with errors */; +}; + +/* + * $$KEEP_ENDIANNESS$$ + */ +struct per_pf_stats +{ + struct tstorm_per_pf_stats tstorm_pf_statistics; +}; + + +/* + * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$ + */ +struct tstorm_per_port_stats +{ + uint32_t mac_discard /* number of packets with mac errors */; + uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */; + uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */; + uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */; + uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */; + uint32_t reserved; +}; + +/* + * $$KEEP_ENDIANNESS$$ + */ +struct per_port_stats +{ + struct tstorm_per_port_stats tstorm_port_statistics; +}; + + +/* + * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$ + */ +struct tstorm_per_queue_stats +{ + struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */; + uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */; + uint32_t checksum_discard /* number of total packets received with checksum error */; + struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */; + uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */; + uint32_t pkts_too_big_discard /* number of too long packets received */; + struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */; + uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */; + uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */; + uint16_t no_buff_discard; + uint16_t reserved0; + uint32_t reserved1; +}; + +/* + * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$ + */ +struct ustorm_per_queue_stats +{ + struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */; + struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */; + struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */; + uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; + uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; + uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; + uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */; + struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */; + uint32_t coalesced_events /* the number of aggregations */; + uint32_t coalesced_aborts /* the number of exception which avoid aggregation */; +}; + +/* + * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$ + */ +struct xstorm_per_queue_stats +{ + struct regpair ucast_bytes_sent /* number of total bytes sent without errors */; + struct regpair mcast_bytes_sent /* number of total bytes sent without errors */; + struct regpair bcast_bytes_sent /* number of total bytes sent without errors */; + uint32_t ucast_pkts_sent /* number of total packets sent without errors */; + uint32_t mcast_pkts_sent /* number of total packets sent without errors */; + uint32_t bcast_pkts_sent /* number of total packets sent without errors */; + uint32_t error_drop_pkts /* number of total packets drooped due to errors */; +}; + +/* + * $$KEEP_ENDIANNESS$$ + */ +struct per_queue_stats +{ + struct tstorm_per_queue_stats tstorm_queue_statistics; + struct ustorm_per_queue_stats ustorm_queue_statistics; + struct xstorm_per_queue_stats xstorm_queue_statistics; +}; + + +/* + * FW version stored in first line of pram $$KEEP_ENDIANNESS$$ + */ +struct pram_fw_version +{ + uint8_t major /* firmware current major version */; + uint8_t minor /* firmware current minor version */; + uint8_t revision /* firmware current revision version */; + uint8_t engineering /* firmware current engineering version */; + uint8_t flags; +#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ +#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 +#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */ +#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 +#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */ +#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 +#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */ +#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 +#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */ +#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 +}; + + +/* + * Ethernet slow path element + */ +union protocol_common_specific_data +{ + uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; + struct regpair phy_address /* SPE physical address */; + struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */; + struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */; +}; + +/* + * The send queue element + */ +struct protocol_common_spe +{ + struct spe_hdr hdr /* SPE header */; + union protocol_common_specific_data data /* data specific to common protocol */; +}; + + +/* + * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$ + */ +struct set_timesync_ramrod_data +{ + uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */; + uint8_t offset_cmd /* Timesync Offset Command */; + uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */; + uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */; + uint32_t drift_adjust_period /* Drift Adjust Period (in us) */; + struct regpair offset_delta /* Timesync Offset Delta (in ns) */; +}; + + +/* + * The send queue element + */ +struct slow_path_element +{ + struct spe_hdr hdr /* common data for all protocols */; + struct regpair protocol_data /* additional data specific to the protocol */; +}; + + +/* + * Protocol-common statistics counter $$KEEP_ENDIANNESS$$ + */ +struct stats_counter +{ + uint16_t xstats_counter /* xstorm statistics counter */; + uint16_t reserved0; + uint32_t reserved1; + uint16_t tstats_counter /* tstorm statistics counter */; + uint16_t reserved2; + uint32_t reserved3; + uint16_t ustats_counter /* ustorm statistics counter */; + uint16_t reserved4; + uint32_t reserved5; + uint16_t cstats_counter /* ustorm statistics counter */; + uint16_t reserved6; + uint32_t reserved7; +}; + + +/* + * $$KEEP_ENDIANNESS$$ + */ +struct stats_query_entry +{ + uint8_t kind; + uint8_t index /* queue index */; + uint16_t funcID /* the func the statistic will send to */; + uint32_t reserved; + struct regpair address /* pxp address */; +}; + +/* + * statistic command $$KEEP_ENDIANNESS$$ + */ +struct stats_query_cmd_group +{ + struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; +}; + + +/* + * statistic command header $$KEEP_ENDIANNESS$$ + */ +struct stats_query_header +{ + uint8_t cmd_num /* command number */; + uint8_t reserved0; + uint16_t drv_stats_counter; + uint32_t reserved1; + struct regpair stats_counters_addrs /* stats counter */; +}; + + +/* + * Types of statistcis query entry + */ +enum stats_query_type +{ + STATS_TYPE_QUEUE, + STATS_TYPE_PORT, + STATS_TYPE_PF, + STATS_TYPE_TOE, + STATS_TYPE_FCOE, + MAX_STATS_QUERY_TYPE}; + + +/* + * Indicate of the function status block state + */ +enum status_block_state +{ + SB_DISABLED, + SB_ENABLED, + SB_CLEANED, + MAX_STATUS_BLOCK_STATE}; + + +/* + * Storm IDs (including attentions for IGU related enums) + */ +enum storm_id +{ + USTORM_ID, + CSTORM_ID, + XSTORM_ID, + TSTORM_ID, + ATTENTION_ID, + MAX_STORM_ID}; + + +/* + * Taffic types used in ETS and flow control algorithms + */ +enum traffic_type +{ + LLFC_TRAFFIC_TYPE_NW /* Networking */, + LLFC_TRAFFIC_TYPE_FCOE /* FCoE */, + LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */, + MAX_TRAFFIC_TYPE}; + + +/* + * zone A per-queue data + */ +struct tstorm_queue_zone_data +{ + struct regpair reserved[4]; +}; + + +/* + * zone B per-VF data + */ +struct tstorm_vf_zone_data +{ + struct regpair reserved; +}; + + +/* + * Add or Subtract Value for Set Timesync Ramrod + */ +enum ts_add_sub_value +{ + TS_SUB_VALUE /* Subtract Value */, + TS_ADD_VALUE /* Add Value */, + MAX_TS_ADD_SUB_VALUE}; + + +/* + * Drift-Adjust Commands for Set Timesync Ramrod + */ +enum ts_drift_adjust_cmd +{ + TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */, + TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */, + TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */, + MAX_TS_DRIFT_ADJUST_CMD}; + + +/* + * Offset Commands for Set Timesync Ramrod + */ +enum ts_offset_cmd +{ + TS_OFFSET_KEEP /* Keep Offset at current values */, + TS_OFFSET_INC /* Increase Offset by Offset Delta */, + TS_OFFSET_DEC /* Decrease Offset by Offset Delta */, + MAX_TS_OFFSET_CMD}; + + +/* + * zone A per-queue data + */ +struct ustorm_queue_zone_data +{ + union ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */; + struct regpair reserved[3]; +}; + + +/* + * zone B per-VF data + */ +struct ustorm_vf_zone_data +{ + struct regpair reserved; +}; + + +/* + * data per VF-PF channel + */ +struct vf_pf_channel_data +{ +#if defined(__BIG_ENDIAN) + uint16_t reserved0; + uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; + uint8_t state /* channel state (ready / waiting for ack) */; +#elif defined(__LITTLE_ENDIAN) + uint8_t state /* channel state (ready / waiting for ack) */; + uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; + uint16_t reserved0; +#endif + uint32_t reserved1; +}; + + +/* + * State of VF-PF channel + */ +enum vf_pf_channel_state +{ + VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */, + VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */, + MAX_VF_PF_CHANNEL_STATE}; + + +/* + * vif_list_rule_kind + */ +enum vif_list_rule_kind +{ + VIF_LIST_RULE_SET, + VIF_LIST_RULE_GET, + VIF_LIST_RULE_CLEAR_ALL, + VIF_LIST_RULE_CLEAR_FUNC, + MAX_VIF_LIST_RULE_KIND}; + + +/* + * zone A per-queue data + */ +struct xstorm_queue_zone_data +{ + struct regpair reserved[4]; +}; + + +/* + * zone B per-VF data + */ +struct xstorm_vf_zone_data +{ + struct regpair reserved; +}; + + +#endif /* ECORE_HSI_H */ diff --git a/lib/librte_pmd_bnx2x/ecore_init.h b/lib/librte_pmd_bnx2x/ecore_init.h new file mode 100644 index 0000000..f5414c9 --- /dev/null +++ b/lib/librte_pmd_bnx2x/ecore_init.h @@ -0,0 +1,841 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ECORE_INIT_H +#define ECORE_INIT_H + +/* Init operation types and structures */ +enum { + OP_RD = 0x1, /* read a single register */ + OP_WR, /* write a single register */ + OP_SW, /* copy a string to the device */ + OP_ZR, /* clear memory */ + OP_ZP, /* unzip then copy with DMAE */ + OP_WR_64, /* write 64 bit pattern */ + OP_WB, /* copy a string using DMAE */ + OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */ + OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */ + OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */ + OP_IF_PHASE, + OP_RT, + OP_DELAY, + OP_VERIFY, + OP_MAX +}; + +enum { + STAGE_START, + STAGE_END, +}; + +/* Returns the index of start or end of a specific block stage in ops array*/ +#define BLOCK_OPS_IDX(block, stage, end) \ + (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end)) + + +/* structs for the various opcodes */ +struct raw_op { + uint32_t op:8; + uint32_t offset:24; + uint32_t raw_data; +}; + +struct op_read { + uint32_t op:8; + uint32_t offset:24; + uint32_t val; +}; + +struct op_write { + uint32_t op:8; + uint32_t offset:24; + uint32_t val; +}; + +struct op_arr_write { + uint32_t op:8; + uint32_t offset:24; +#ifdef __BIG_ENDIAN + uint16_t data_len; + uint16_t data_off; +#else /* __LITTLE_ENDIAN */ + uint16_t data_off; + uint16_t data_len; +#endif +}; + +struct op_zero { + uint32_t op:8; + uint32_t offset:24; + uint32_t len; +}; + +struct op_if_mode { + uint32_t op:8; + uint32_t cmd_offset:24; + uint32_t mode_bit_map; +}; + +struct op_if_phase { + uint32_t op:8; + uint32_t cmd_offset:24; + uint32_t phase_bit_map; +}; + +struct op_delay { + uint32_t op:8; + uint32_t reserved:24; + uint32_t delay; +}; + +union init_op { + struct op_read read; + struct op_write write; + struct op_arr_write arr_wr; + struct op_zero zero; + struct raw_op raw; + struct op_if_mode if_mode; + struct op_if_phase if_phase; + struct op_delay delay; +}; + + +/* Init Phases */ +enum { + PHASE_COMMON, + PHASE_PORT0, + PHASE_PORT1, + PHASE_PF0, + PHASE_PF1, + PHASE_PF2, + PHASE_PF3, + PHASE_PF4, + PHASE_PF5, + PHASE_PF6, + PHASE_PF7, + NUM_OF_INIT_PHASES +}; + +/* Init Modes */ +enum { + MODE_ASIC = 0x00000001, + MODE_FPGA = 0x00000002, + MODE_EMUL = 0x00000004, + MODE_E2 = 0x00000008, + MODE_E3 = 0x00000010, + MODE_PORT2 = 0x00000020, + MODE_PORT4 = 0x00000040, + MODE_SF = 0x00000080, + MODE_MF = 0x00000100, + MODE_MF_SD = 0x00000200, + MODE_MF_SI = 0x00000400, + MODE_MF_AFEX = 0x00000800, + MODE_E3_A0 = 0x00001000, + MODE_E3_B0 = 0x00002000, + MODE_COS3 = 0x00004000, + MODE_COS6 = 0x00008000, + MODE_LITTLE_ENDIAN = 0x00010000, + MODE_BIG_ENDIAN = 0x00020000, +}; + +/* Init Blocks */ +enum { + BLOCK_ATC, + BLOCK_BRB1, + BLOCK_CCM, + BLOCK_CDU, + BLOCK_CFC, + BLOCK_CSDM, + BLOCK_CSEM, + BLOCK_DBG, + BLOCK_DMAE, + BLOCK_DORQ, + BLOCK_HC, + BLOCK_IGU, + BLOCK_MISC, + BLOCK_NIG, + BLOCK_PBF, + BLOCK_PGLUE_B, + BLOCK_PRS, + BLOCK_PXP2, + BLOCK_PXP, + BLOCK_QM, + BLOCK_SRC, + BLOCK_TCM, + BLOCK_TM, + BLOCK_TSDM, + BLOCK_TSEM, + BLOCK_UCM, + BLOCK_UPB, + BLOCK_USDM, + BLOCK_USEM, + BLOCK_XCM, + BLOCK_XPB, + BLOCK_XSDM, + BLOCK_XSEM, + BLOCK_MISC_AEU, + NUM_OF_INIT_BLOCKS +}; + + + + + + + + +/* Vnics per mode */ +#define ECORE_PORT2_MODE_NUM_VNICS 4 + + +/* QM queue numbers */ +#define ECORE_ETH_Q 0 +#define ECORE_TOE_Q 3 +#define ECORE_TOE_ACK_Q 6 +#define ECORE_ISCSI_Q 9 +#define ECORE_ISCSI_ACK_Q 11 +#define ECORE_FCOE_Q 10 + +/* Vnics per mode */ +#define ECORE_PORT4_MODE_NUM_VNICS 2 + +/* COS offset for port1 in E3 B0 4port mode */ +#define ECORE_E3B0_PORT1_COS_OFFSET 3 + +/* QM Register addresses */ +#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\ + (QM_REG_QVOQIDX_0 + 4 * (pf_q_num)) +#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\ + (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5))) +#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\ + (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4)) + +/* extracts the QM queue number for the specified port and vnic */ +#define ECORE_PF_Q_NUM(q_num, port, vnic)\ + ((((port) << 1) | (vnic)) * 16 + (q_num)) + + +/* Maps the specified queue to the specified COS */ +static inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint32_t new_cos) +{ + /* find current COS mapping */ + uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4); + + /* check if queue->COS mapping has changed */ + if (curr_cos != new_cos) { + uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS; + uint32_t reg_addr, reg_bit_map, vnic; + + /* update parameters for 4port mode */ + if (INIT_MODE_FLAGS(sc) & MODE_PORT4) { + num_vnics = ECORE_PORT4_MODE_NUM_VNICS; + if (PORT_ID(sc)) { + curr_cos += ECORE_E3B0_PORT1_COS_OFFSET; + new_cos += ECORE_E3B0_PORT1_COS_OFFSET; + } + } + + /* change queue mapping for each VNIC */ + for (vnic = 0; vnic < num_vnics; vnic++) { + uint32_t pf_q_num = + ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic); + uint32_t q_bit_map = 1 << (pf_q_num & 0x1f); + + /* overwrite queue->VOQ mapping */ + REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos); + + /* clear queue bit from current COS bit map */ + reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); + reg_bit_map = REG_RD(sc, reg_addr); + REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map)); + + /* set queue bit in new COS bit map */ + reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num); + reg_bit_map = REG_RD(sc, reg_addr); + REG_WR(sc, reg_addr, reg_bit_map | q_bit_map); + + /* set/clear queue bit in command-queue bit map + (E2/E3A0 only, valid COS values are 0/1) */ + if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) { + reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num); + reg_bit_map = REG_RD(sc, reg_addr); + q_bit_map = 1 << (2 * (pf_q_num & 0xf)); + reg_bit_map = new_cos ? + (reg_bit_map | q_bit_map) : + (reg_bit_map & (~q_bit_map)); + REG_WR(sc, reg_addr, reg_bit_map); + } + } + } +} + +/* Configures the QM according to the specified per-traffic-type COSes */ +static inline void ecore_dcb_config_qm(struct bnx2x_softc *sc, enum cos_mode mode, + struct priority_cos *traffic_cos) +{ + ecore_map_q_cos(sc, ECORE_FCOE_Q, + traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos); + ecore_map_q_cos(sc, ECORE_ISCSI_Q, + traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos); + ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q, + traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos); + if (mode != STATIC_COS) { + /* required only in OVERRIDE_COS mode */ + ecore_map_q_cos(sc, ECORE_ETH_Q, + traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); + ecore_map_q_cos(sc, ECORE_TOE_Q, + traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); + ecore_map_q_cos(sc, ECORE_TOE_ACK_Q, + traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); + } +} + + +/* + * congestion managment port init api description + * the api works as follows: + * the driver should pass the cmng_init_input struct, the port_init function + * will prepare the required internal ram structure which will be passed back + * to the driver (cmng_init) that will write it into the internal ram. + * + * IMPORTANT REMARKS: + * 1. the cmng_init struct does not represent the contiguous internal ram + * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET + * offset in order to write the port sub struct and the + * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other + * words - don't use memcpy!). + * 2. although the cmng_init struct is filled for the maximal vnic number + * possible, the driver should only write the valid vnics into the internal + * ram according to the appropriate port mode. + */ +#define BITS_TO_BYTES(x) ((x)/8) + +/* CMNG constants, as derived from system spec calculations */ + +/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */ +#define DEF_MIN_RATE 100 + +/* resolution of the rate shaping timer - 400 usec */ +#define RS_PERIODIC_TIMEOUT_USEC 400 + +/* + * number of bytes in single QM arbitration cycle - + * coefficient for calculating the fairness timer + */ +#define QM_ARB_BYTES 160000 + +/* resolution of Min algorithm 1:100 */ +#define MIN_RES 100 + +/* + * how many bytes above threshold for + * the minimal credit of Min algorithm + */ +#define MIN_ABOVE_THRESH 32768 + +/* + * Fairness algorithm integration time coefficient - + * for calculating the actual Tfair + */ +#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) + +/* Memory of fairness algorithm - 2 cycles */ +#define FAIR_MEM 2 +#define SAFC_TIMEOUT_USEC 52 + +#define SDM_TICKS 4 + + +static inline void ecore_init_max(const struct cmng_init_input *input_data, + uint32_t r_param, struct cmng_init *ram_data) +{ + uint32_t vnic; + struct cmng_vnic *vdata = &ram_data->vnic; + struct cmng_struct_per_port *pdata = &ram_data->port; + /* + * rate shaping per-port variables + * 100 micro seconds in SDM ticks = 25 + * since each tick is 4 microSeconds + */ + + pdata->rs_vars.rs_periodic_timeout = + RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS; + + /* this is the threshold below which no timer arming will occur. + * 1.25 coefficient is for the threshold to be a little bigger + * then the real time to compensate for timer in-accuracy + */ + pdata->rs_vars.rs_threshold = + (5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4; + + /* rate shaping per-vnic variables */ + for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { + /* global vnic counter */ + vdata->vnic_max_rate[vnic].vn_counter.rate = + input_data->vnic_max_rate[vnic]; + /* + * maximal Mbps for this vnic + * the quota in each timer period - number of bytes + * transmitted in this period + */ + vdata->vnic_max_rate[vnic].vn_counter.quota = + RS_PERIODIC_TIMEOUT_USEC * + (uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8; + } + +} + +static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate, + struct rate_shaping_vars_per_vn *ram_data) +{ + /* global vnic counter */ + ram_data->vn_counter.rate = vnic_max_rate; + + /* + * maximal Mbps for this vnic + * the quota in each timer period - number of bytes + * transmitted in this period + */ + ram_data->vn_counter.quota = + RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8; +} + +static inline void ecore_init_min(const struct cmng_init_input *input_data, + uint32_t r_param, struct cmng_init *ram_data) +{ + uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair; + struct cmng_vnic *vdata = &ram_data->vnic; + struct cmng_struct_per_port *pdata = &ram_data->port; + + /* this is the resolution of the fairness timer */ + fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; + + /* + * fairness per-port variables + * for 10G it is 1000usec. for 1G it is 10000usec. + */ + tFair = T_FAIR_COEF / input_data->port_rate; + + /* this is the threshold below which we won't arm the timer anymore */ + pdata->fair_vars.fair_threshold = QM_ARB_BYTES; + + /* + * we multiply by 1e3/8 to get bytes/msec. We don't want the credits + * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution) + */ + pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM; + + /* since each tick is 4 microSeconds */ + pdata->fair_vars.fairness_timeout = + fair_periodic_timeout_usec / SDM_TICKS; + + /* calculate sum of weights */ + vnicWeightSum = 0; + + for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) + vnicWeightSum += input_data->vnic_min_rate[vnic]; + + /* global vnic counter */ + if (vnicWeightSum > 0) { + /* fairness per-vnic variables */ + for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { + /* + * this is the credit for each period of the fairness + * algorithm - number of bytes in T_FAIR (this vnic + * share of the port rate) + */ + vdata->vnic_min_rate[vnic].vn_credit_delta = + ((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 * + (T_FAIR_COEF / (8 * 100 * vnicWeightSum))); + if (vdata->vnic_min_rate[vnic].vn_credit_delta < + pdata->fair_vars.fair_threshold + + MIN_ABOVE_THRESH) { + vdata->vnic_min_rate[vnic].vn_credit_delta = + pdata->fair_vars.fair_threshold + + MIN_ABOVE_THRESH; + } + } + } +} + +static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data, + struct cmng_init *ram_data) +{ + uint32_t vnic, cos; + uint32_t cosWeightSum = 0; + struct cmng_vnic *vdata = &ram_data->vnic; + struct cmng_struct_per_port *pdata = &ram_data->port; + + for (cos = 0; cos < MAX_COS_NUMBER; cos++) + cosWeightSum += input_data->cos_min_rate[cos]; + + if (cosWeightSum > 0) { + + for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { + /* + * Since cos and vnic shouldn't work together the rate + * to divide between the coses is the port rate. + */ + uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta; + for (cos = 0; cos < MAX_COS_NUMBER; cos++) { + /* + * this is the credit for each period of + * the fairness algorithm - number of bytes + * in T_FAIR (this cos share of the vnic rate) + */ + ccd[cos] = + ((uint32_t)input_data->cos_min_rate[cos] * 100 * + (T_FAIR_COEF / (8 * 100 * cosWeightSum))); + if (ccd[cos] < pdata->fair_vars.fair_threshold + + MIN_ABOVE_THRESH) { + ccd[cos] = + pdata->fair_vars.fair_threshold + + MIN_ABOVE_THRESH; + } + } + } + } +} + +static inline void ecore_init_safc(struct cmng_init *ram_data) +{ + /* in microSeconds */ + ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC; +} + +/* Congestion management port init */ +static inline void ecore_init_cmng(const struct cmng_init_input *input_data, + struct cmng_init *ram_data) +{ + uint32_t r_param; + ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init)); + + ram_data->port.flags = input_data->flags; + + /* + * number of bytes transmitted in a rate of 10Gbps + * in one usec = 1.25KB. + */ + r_param = BITS_TO_BYTES(input_data->port_rate); + ecore_init_max(input_data, r_param, ram_data); + ecore_init_min(input_data, r_param, ram_data); + ecore_init_fw_wrr(input_data, ram_data); + ecore_init_safc(ram_data); +} + + + + +/* Returns the index of start or end of a specific block stage in ops array*/ +#define BLOCK_OPS_IDX(block, stage, end) \ + (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end)) + + +#define INITOP_SET 0 /* set the HW directly */ +#define INITOP_CLEAR 1 /* clear the HW directly */ +#define INITOP_INIT 2 /* set the init-value array */ + +/**************************************************************************** +* ILT management +****************************************************************************/ +struct ilt_line { + ecore_dma_addr_t page_mapping; + void *page; + uint32_t size; +}; + +struct ilt_client_info { + uint32_t page_size; + uint16_t start; + uint16_t end; + uint16_t client_num; + uint16_t flags; +#define ILT_CLIENT_SKIP_INIT 0x1 +#define ILT_CLIENT_SKIP_MEM 0x2 +}; + +struct ecore_ilt { + uint32_t start_line; + struct ilt_line *lines; + struct ilt_client_info clients[4]; +#define ILT_CLIENT_CDU 0 +#define ILT_CLIENT_QM 1 +#define ILT_CLIENT_SRC 2 +#define ILT_CLIENT_TM 3 +}; + +/**************************************************************************** +* SRC configuration +****************************************************************************/ +struct src_ent { + uint8_t opaque[56]; + uint64_t next; +}; + +/**************************************************************************** +* Parity configuration +****************************************************************************/ +#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \ +{ \ + block##_REG_##block##_PRTY_MASK, \ + block##_REG_##block##_PRTY_STS_CLR, \ + en_mask, {m1h, m2, m3}, #block \ +} + +#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \ +{ \ + block##_REG_##block##_PRTY_MASK_0, \ + block##_REG_##block##_PRTY_STS_CLR_0, \ + en_mask, {m1h, m2, m3}, #block"_0" \ +} + +#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \ +{ \ + block##_REG_##block##_PRTY_MASK_1, \ + block##_REG_##block##_PRTY_STS_CLR_1, \ + en_mask, {m1h, m2, m3}, #block"_1" \ +} + +static const struct { + uint32_t mask_addr; + uint32_t sts_clr_addr; + uint32_t en_mask; /* Mask to enable parity attentions */ + struct { + uint32_t e1h; /* 57711 */ + uint32_t e2; /* 57712 */ + uint32_t e3; /* 578xx */ + } reg_mask; /* Register mask (all valid bits) */ + char name[8]; /* Block's longest name is 7 characters long + * (name + suffix) + */ +} ecore_blocks_parity_data[] = { + /* bit 19 masked */ + /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */ + /* bit 5,18,20-31 */ + /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */ + /* bit 5 */ + /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */ + /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */ + /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */ + + /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't + * want to handle "system kill" flow at the moment. + */ + BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff, + 0x7ffffff), + BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff), + BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7ff, 0x1ffffff), + BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0), + BLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0), + BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0xffffffff, 0xffffffff), + BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0xff, 0xffff), + BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff), + BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1), + BLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff), + BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f), + BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3), + BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3), + {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, + GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf, + {0xf, 0xf, 0xf}, "UPB"}, + {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, + GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0, + {0xf, 0xf, 0xf}, "XPB"}, + BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7), + BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f), + BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f), + BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1), + BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf), + BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf), + BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff), + BLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff), + BLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f), + BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff), + BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff), + BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff), + BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff), + BLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), + BLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), + BLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), + BLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff), + BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff), + BLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f), + BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff), + BLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f), + BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff), + BLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f), + BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff), + BLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f), +}; + + +/* [28] MCP Latched rom_parity + * [29] MCP Latched ump_rx_parity + * [30] MCP Latched ump_tx_parity + * [31] MCP Latched scpad_parity + */ +#define MISC_AEU_ENABLE_MCP_PRTY_BITS \ + (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) + +/* Below registers control the MCP parity attention output. When + * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are + * enabled, when cleared - disabled. + */ +static const uint32_t mcp_attn_ctl_regs[] = { + MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, + MISC_REG_AEU_ENABLE4_NIG_0, + MISC_REG_AEU_ENABLE4_PXP_0, + MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, + MISC_REG_AEU_ENABLE4_NIG_1, + MISC_REG_AEU_ENABLE4_PXP_1 +}; + +static inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable) +{ + uint32_t i; + uint32_t reg_val; + + for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) { + reg_val = REG_RD(sc, mcp_attn_ctl_regs[i]); + + if (enable) + reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; + else + reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; + + REG_WR(sc, mcp_attn_ctl_regs[i], reg_val); + } +} + +static inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx) +{ + if (CHIP_IS_E1H(sc)) + return ecore_blocks_parity_data[idx].reg_mask.e1h; + else if (CHIP_IS_E2(sc)) + return ecore_blocks_parity_data[idx].reg_mask.e2; + else /* CHIP_IS_E3 */ + return ecore_blocks_parity_data[idx].reg_mask.e3; +} + +static inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc) +{ + uint32_t i; + + for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { + uint32_t dis_mask = ecore_parity_reg_mask(sc, i); + + if (dis_mask) { + REG_WR(sc, ecore_blocks_parity_data[i].mask_addr, + dis_mask); + ECORE_MSG("Setting parity mask " + "for %s to\t\t0x%x", + ecore_blocks_parity_data[i].name, dis_mask); + } + } + + /* Disable MCP parity attentions */ + ecore_set_mcp_parity(sc, FALSE); +} + +/** + * Clear the parity error status registers. + */ +static inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc) +{ + uint32_t i; + uint32_t reg_val, mcp_aeu_bits = + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY | + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY; + + /* Clear SEM_FAST parities */ + REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); + REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); + REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); + REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); + + for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { + uint32_t reg_mask = ecore_parity_reg_mask(sc, i); + + if (reg_mask) { + reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. + sts_clr_addr); + if (reg_val & reg_mask) + ECORE_MSG(sc, + "Parity errors in %s: 0x%x", + ecore_blocks_parity_data[i].name, + reg_val & reg_mask); + } + } + + /* Check if there were parity attentions in MCP */ + reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); + if (reg_val & mcp_aeu_bits) + ECORE_MSG("Parity error in MCP: 0x%x", + reg_val & mcp_aeu_bits); + + /* Clear parity attentions in MCP: + * [7] clears Latched rom_parity + * [8] clears Latched ump_rx_parity + * [9] clears Latched ump_tx_parity + * [10] clears Latched scpad_parity (both ports) + */ + REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); +} + +static inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc) +{ + uint32_t i; + + for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { + uint32_t reg_mask = ecore_parity_reg_mask(sc, i); + + if (reg_mask) + REG_WR(sc, ecore_blocks_parity_data[i].mask_addr, + ecore_blocks_parity_data[i].en_mask & reg_mask); + } + + /* Enable MCP parity attentions */ + ecore_set_mcp_parity(sc, TRUE); +} + + +#endif /* ECORE_INIT_H */ diff --git a/lib/librte_pmd_bnx2x/ecore_init_ops.h b/lib/librte_pmd_bnx2x/ecore_init_ops.h new file mode 100644 index 0000000..f750766 --- /dev/null +++ b/lib/librte_pmd_bnx2x/ecore_init_ops.h @@ -0,0 +1,886 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ECORE_INIT_OPS_H +#define ECORE_INIT_OPS_H + +static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t *zbuf, int len); +static void ecore_write_dmae_phys_len(struct bnx2x_softc *sc, + ecore_dma_addr_t phys_addr, uint32_t addr, + uint32_t len); + +static void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr, + const uint32_t *data, uint32_t len) +{ + uint32_t i; + + for (i = 0; i < len; i++) + REG_WR(sc, addr + i*4, data[i]); +} + +static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len) +{ + if (DMAE_READY(sc)) + ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len); + + else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len); +} + +static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, + uint32_t len) +{ + uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4)); + uint32_t buf_len32 = buf_len/4; + uint32_t i; + + ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len); + + for (i = 0; i < len; i += buf_len32) { + uint32_t cur_len = min(buf_len32, len - i); + + ecore_write_big_buf(sc, addr + i*4, cur_len); + } +} + +static void ecore_write_big_buf_wb(struct bnx2x_softc *sc, uint32_t addr, uint32_t len) +{ + if (DMAE_READY(sc)) + ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len); + + else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len); +} + +static void ecore_init_wr_64(struct bnx2x_softc *sc, uint32_t addr, + const uint32_t *data, uint32_t len64) +{ + uint32_t buf_len32 = FW_BUF_SIZE/4; + uint32_t len = len64*2; + uint64_t data64 = 0; + uint32_t i; + + /* 64 bit value is in a blob: first low DWORD, then high DWORD */ + data64 = HILO_U64((*(data + 1)), (*data)); + + len64 = min((uint32_t)(FW_BUF_SIZE/8), len64); + for (i = 0; i < len64; i++) { + uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i; + + *pdata = data64; + } + + for (i = 0; i < len; i += buf_len32) { + uint32_t cur_len = min(buf_len32, len - i); + + ecore_write_big_buf_wb(sc, addr + i*4, cur_len); + } +} + +/********************************************************* + There are different blobs for each PRAM section. + In addition, each blob write operation is divided into a few operations + in order to decrease the amount of phys. contiguous buffer needed. + Thus, when we select a blob the address may be with some offset + from the beginning of PRAM section. + The same holds for the INT_TABLE sections. +**********************************************************/ +#define IF_IS_INT_TABLE_ADDR(base, addr) \ + if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) + +#define IF_IS_PRAM_ADDR(base, addr) \ + if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) + +static const uint8_t *ecore_sel_blob(struct bnx2x_softc *sc, uint32_t addr, + const uint8_t *data) +{ + IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) + data = INIT_TSEM_INT_TABLE_DATA(sc); + else + IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) + data = INIT_CSEM_INT_TABLE_DATA(sc); + else + IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) + data = INIT_USEM_INT_TABLE_DATA(sc); + else + IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) + data = INIT_XSEM_INT_TABLE_DATA(sc); + else + IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) + data = INIT_TSEM_PRAM_DATA(sc); + else + IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) + data = INIT_CSEM_PRAM_DATA(sc); + else + IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) + data = INIT_USEM_PRAM_DATA(sc); + else + IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) + data = INIT_XSEM_PRAM_DATA(sc); + + return data; +} + +static void ecore_init_wr_wb(struct bnx2x_softc *sc, uint32_t addr, + const uint32_t *data, uint32_t len) +{ + if (DMAE_READY(sc)) + VIRT_WR_DMAE_LEN(sc, data, addr, len, 0); + + else ecore_init_str_wr(sc, addr, data, len); +} + +static void ecore_wr_64(struct bnx2x_softc *sc, uint32_t reg, uint32_t val_lo, + uint32_t val_hi) +{ + uint32_t wb_write[2]; + + wb_write[0] = val_lo; + wb_write[1] = val_hi; + REG_WR_DMAE_LEN(sc, reg, wb_write, 2); +} + +static void ecore_init_wr_zp(struct bnx2x_softc *sc, uint32_t addr, uint32_t len, + uint32_t blob_off) +{ + const uint8_t *data = NULL; + int rc; + uint32_t i; + + data = ecore_sel_blob(sc, addr, data) + blob_off*4; + + rc = ecore_gunzip(sc, data, len); + if (rc) + return; + + /* gunzip_outlen is in dwords */ + len = GUNZIP_OUTLEN(sc); + for (i = 0; i < len; i++) + ((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t) + ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]); + + ecore_write_big_buf_wb(sc, addr, len); +} + +static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t stage) +{ + uint16_t op_start = + INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage, + STAGE_START)]; + uint16_t op_end = + INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage, + STAGE_END)]; + const union init_op *op; + uint32_t op_idx, op_type, addr, len; + const uint32_t *data, *data_base; + + /* If empty block */ + if (op_start == op_end) + return; + + data_base = INIT_DATA(sc); + + for (op_idx = op_start; op_idx < op_end; op_idx++) { + + op = (const union init_op *)&(INIT_OPS(sc)[op_idx]); + /* Get generic data */ + op_type = op->raw.op; + addr = op->raw.offset; + /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and + * OP_WR64 (we assume that op_arr_write and op_write have the + * same structure). + */ + len = op->arr_wr.data_len; + data = data_base + op->arr_wr.data_off; + + switch (op_type) { + case OP_RD: + REG_RD(sc, addr); + break; + case OP_WR: + REG_WR(sc, addr, op->write.val); + break; + case OP_SW: + ecore_init_str_wr(sc, addr, data, len); + break; + case OP_WB: + ecore_init_wr_wb(sc, addr, data, len); + break; + case OP_ZR: + case OP_WB_ZR: + ecore_init_fill(sc, addr, 0, op->zero.len); + break; + case OP_ZP: + ecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off); + break; + case OP_WR_64: + ecore_init_wr_64(sc, addr, data, len); + break; + case OP_IF_MODE_AND: + /* if any of the flags doesn't match, skip the + * conditional block. + */ + if ((INIT_MODE_FLAGS(sc) & + op->if_mode.mode_bit_map) != + op->if_mode.mode_bit_map) + op_idx += op->if_mode.cmd_offset; + break; + case OP_IF_MODE_OR: + /* if all the flags don't match, skip the conditional + * block. + */ + if ((INIT_MODE_FLAGS(sc) & + op->if_mode.mode_bit_map) == 0) + op_idx += op->if_mode.cmd_offset; + break; + /* the following opcodes are unused at the moment. */ + case OP_IF_PHASE: + case OP_RT: + case OP_DELAY: + case OP_VERIFY: + default: + /* Should never get here! */ + + break; + } + } +} + + +/**************************************************************************** +* PXP Arbiter +****************************************************************************/ +/* + * This code configures the PCI read/write arbiter + * which implements a weighted round robin + * between the virtual queues in the chip. + * + * The values were derived for each PCI max payload and max request size. + * since max payload and max request size are only known at run time, + * this is done as a separate init stage. + */ + +#define NUM_WR_Q 13 +#define NUM_RD_Q 29 +#define MAX_RD_ORD 3 +#define MAX_WR_ORD 2 + +/* configuration for one arbiter queue */ +struct arb_line { + int l; + int add; + int ubound; +}; + +/* derived configuration for each read queue for each max request size */ +static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { +/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, + { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} }, + { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} }, + { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} }, + { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, +/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, +/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, + { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} } +}; + +/* derived configuration for each write queue for each max request size */ +static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { +/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} }, + { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} }, + { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, + { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, + { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, + { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, + { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} }, + { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, + { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, +/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} }, + { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} }, + { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} }, + { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} } +}; + +/* register addresses for read queues */ +static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { +/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, + PXP2_REG_RQ_BW_RD_UBOUND0}, + {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, + PXP2_REG_PSWRQ_BW_UB1}, + {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, + PXP2_REG_PSWRQ_BW_UB2}, + {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, + PXP2_REG_PSWRQ_BW_UB3}, + {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, + PXP2_REG_RQ_BW_RD_UBOUND4}, + {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, + PXP2_REG_RQ_BW_RD_UBOUND5}, + {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, + PXP2_REG_PSWRQ_BW_UB6}, + {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, + PXP2_REG_PSWRQ_BW_UB7}, + {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, + PXP2_REG_PSWRQ_BW_UB8}, +/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, + PXP2_REG_PSWRQ_BW_UB9}, + {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, + PXP2_REG_PSWRQ_BW_UB10}, + {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, + PXP2_REG_PSWRQ_BW_UB11}, + {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, + PXP2_REG_RQ_BW_RD_UBOUND12}, + {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, + PXP2_REG_RQ_BW_RD_UBOUND13}, + {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, + PXP2_REG_RQ_BW_RD_UBOUND14}, + {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, + PXP2_REG_RQ_BW_RD_UBOUND15}, + {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, + PXP2_REG_RQ_BW_RD_UBOUND16}, + {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, + PXP2_REG_RQ_BW_RD_UBOUND17}, + {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, + PXP2_REG_RQ_BW_RD_UBOUND18}, +/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, + PXP2_REG_RQ_BW_RD_UBOUND19}, + {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, + PXP2_REG_RQ_BW_RD_UBOUND20}, + {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, + PXP2_REG_RQ_BW_RD_UBOUND22}, + {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, + PXP2_REG_RQ_BW_RD_UBOUND23}, + {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, + PXP2_REG_RQ_BW_RD_UBOUND24}, + {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, + PXP2_REG_RQ_BW_RD_UBOUND25}, + {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, + PXP2_REG_RQ_BW_RD_UBOUND26}, + {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, + PXP2_REG_RQ_BW_RD_UBOUND27}, + {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, + PXP2_REG_PSWRQ_BW_UB28} +}; + +/* register addresses for write queues */ +static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { +/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, + PXP2_REG_PSWRQ_BW_UB1}, + {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, + PXP2_REG_PSWRQ_BW_UB2}, + {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, + PXP2_REG_PSWRQ_BW_UB3}, + {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, + PXP2_REG_PSWRQ_BW_UB6}, + {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, + PXP2_REG_PSWRQ_BW_UB7}, + {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, + PXP2_REG_PSWRQ_BW_UB8}, + {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, + PXP2_REG_PSWRQ_BW_UB9}, + {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, + PXP2_REG_PSWRQ_BW_UB10}, + {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, + PXP2_REG_PSWRQ_BW_UB11}, +/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, + PXP2_REG_PSWRQ_BW_UB28}, + {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, + PXP2_REG_RQ_BW_WR_UBOUND29}, + {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, + PXP2_REG_RQ_BW_WR_UBOUND30} +}; + +static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order, + int w_order) +{ + uint32_t val, i; + + if (r_order > MAX_RD_ORD) { + ECORE_MSG("read order of %d order adjusted to %d", + r_order, MAX_RD_ORD); + r_order = MAX_RD_ORD; + } + if (w_order > MAX_WR_ORD) { + ECORE_MSG("write order of %d order adjusted to %d", + w_order, MAX_WR_ORD); + w_order = MAX_WR_ORD; + } + if (CHIP_REV_IS_FPGA(sc)) { + ECORE_MSG("write order adjusted to 1 for FPGA"); + w_order = 0; + } + ECORE_MSG("read order %d write order %d", r_order, w_order); + + for (i = 0; i < NUM_RD_Q-1; i++) { + REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l); + REG_WR(sc, read_arb_addr[i].add, + read_arb_data[i][r_order].add); + REG_WR(sc, read_arb_addr[i].ubound, + read_arb_data[i][r_order].ubound); + } + + for (i = 0; i < NUM_WR_Q-1; i++) { + if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || + (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { + + REG_WR(sc, write_arb_addr[i].l, + write_arb_data[i][w_order].l); + + REG_WR(sc, write_arb_addr[i].add, + write_arb_data[i][w_order].add); + + REG_WR(sc, write_arb_addr[i].ubound, + write_arb_data[i][w_order].ubound); + } else { + + val = REG_RD(sc, write_arb_addr[i].l); + REG_WR(sc, write_arb_addr[i].l, + val | (write_arb_data[i][w_order].l << 10)); + + val = REG_RD(sc, write_arb_addr[i].add); + REG_WR(sc, write_arb_addr[i].add, + val | (write_arb_data[i][w_order].add << 10)); + + val = REG_RD(sc, write_arb_addr[i].ubound); + REG_WR(sc, write_arb_addr[i].ubound, + val | (write_arb_data[i][w_order].ubound << 7)); + } + } + + val = write_arb_data[NUM_WR_Q-1][w_order].add; + val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; + val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; + REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val); + + val = read_arb_data[NUM_RD_Q-1][r_order].add; + val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; + val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; + REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val); + + REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order); + REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order); + REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order); + REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order); + + if (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD)) + REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00); + + if (CHIP_IS_E3(sc)) + REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); + else if (CHIP_IS_E2(sc)) + REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); + else + REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); + + /* MPS w_order optimal TH presently TH + * 128 0 0 2 + * 256 1 1 3 + * >=512 2 2 3 + */ + /* DMAE is special */ + if (!CHIP_IS_E1H(sc)) { + /* E2 can use optimal TH */ + val = w_order; + REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val); + } else { + val = ((w_order == 0) ? 2 : 3); + REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2); + } + + REG_WR(sc, PXP2_REG_WR_HC_MPS, val); + REG_WR(sc, PXP2_REG_WR_USDM_MPS, val); + REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val); + REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val); + REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val); + REG_WR(sc, PXP2_REG_WR_QM_MPS, val); + REG_WR(sc, PXP2_REG_WR_TM_MPS, val); + REG_WR(sc, PXP2_REG_WR_SRC_MPS, val); + REG_WR(sc, PXP2_REG_WR_DBG_MPS, val); + REG_WR(sc, PXP2_REG_WR_CDU_MPS, val); + + /* Validate number of tags suppoted by device */ +#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980 + val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST); + val &= 0xFF; + if (val <= 0x20) + REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20); +} + +/**************************************************************************** +* ILT management +****************************************************************************/ +/* + * This codes hides the low level HW interaction for ILT management and + * configuration. The API consists of a shadow ILT table which is set by the + * driver and a set of routines to use it to configure the HW. + * + */ + +/* ILT HW init operations */ + +/* ILT memory management operations */ +#define ILT_MEMOP_ALLOC 0 +#define ILT_MEMOP_FREE 1 + +/* the phys address is shifted right 12 bits and has an added + * 1=valid bit added to the 53rd bit + * then since this is a wide register(TM) + * we split it into two 32 bit writes + */ +#define ILT_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) +#define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) +#define ILT_RANGE(f, l) (((l) << 10) | f) + +static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc, + struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i) +{ +#define ECORE_ILT_NAMESIZE 10 + char str[ECORE_ILT_NAMESIZE]; + + if (memop == ILT_MEMOP_FREE) { + ECORE_ILT_FREE(line->page, line->page_mapping, line->size); + return 0; + } + snprintf(str, ECORE_ILT_NAMESIZE, "ILT_%d_%d", cli_num, i); + ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str); + if (!line->page) + return -1; + line->size = size; + return 0; +} + + +static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num, + uint8_t memop) +{ + int i, rc = 0; + struct ecore_ilt *ilt = SC_ILT(sc); + struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; + + if (!ilt || !ilt->lines) + return -1; + + if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM)) + return 0; + + for (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) { + rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i], + ilt_cli->page_size, memop, cli_num, i); + } + return rc; +} + +static inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc *sc, uint8_t memop) +{ + int rc = 0; + + if (CONFIGURE_NIC_MODE(sc)) + rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop); + if (!rc) + rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop); + + return rc; +} + +static int ecore_ilt_mem_op(struct bnx2x_softc *sc, uint8_t memop) +{ + int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop); + if (!rc) + rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop); + if (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc)) + rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop); + + return rc; +} + +static void ecore_ilt_line_wr(struct bnx2x_softc *sc, int abs_idx, + ecore_dma_addr_t page_mapping) +{ + uint32_t reg; + + reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8; + + ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping)); +} + +static void ecore_ilt_line_init_op(struct bnx2x_softc *sc, + struct ecore_ilt *ilt, int idx, uint8_t initop) +{ + ecore_dma_addr_t null_mapping; + int abs_idx = ilt->start_line + idx; + + switch (initop) { + case INITOP_INIT: + /* set in the init-value array */ + case INITOP_SET: + ecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping); + break; + case INITOP_CLEAR: + null_mapping = 0; + ecore_ilt_line_wr(sc, abs_idx, null_mapping); + break; + } +} + +static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc, + struct ilt_client_info *ilt_cli, + uint32_t ilt_start) +{ + uint32_t start_reg = 0; + uint32_t end_reg = 0; + + /* The boundary is either SET or INIT, + CLEAR => SET and for now SET ~~ INIT */ + + /* find the appropriate regs */ + switch (ilt_cli->client_num) { + case ILT_CLIENT_CDU: + start_reg = PXP2_REG_RQ_CDU_FIRST_ILT; + end_reg = PXP2_REG_RQ_CDU_LAST_ILT; + break; + case ILT_CLIENT_QM: + start_reg = PXP2_REG_RQ_QM_FIRST_ILT; + end_reg = PXP2_REG_RQ_QM_LAST_ILT; + break; + case ILT_CLIENT_SRC: + start_reg = PXP2_REG_RQ_SRC_FIRST_ILT; + end_reg = PXP2_REG_RQ_SRC_LAST_ILT; + break; + case ILT_CLIENT_TM: + start_reg = PXP2_REG_RQ_TM_FIRST_ILT; + end_reg = PXP2_REG_RQ_TM_LAST_ILT; + break; + } + REG_WR(sc, start_reg, (ilt_start + ilt_cli->start)); + REG_WR(sc, end_reg, (ilt_start + ilt_cli->end)); +} + +static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc, + struct ecore_ilt *ilt, + struct ilt_client_info *ilt_cli, + uint8_t initop) +{ + int i; + + if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) + return; + + for (i = ilt_cli->start; i <= ilt_cli->end; i++) + ecore_ilt_line_init_op(sc, ilt, i, initop); + + /* init/clear the ILT boundries */ + ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line); +} + +static void ecore_ilt_client_init_op(struct bnx2x_softc *sc, + struct ilt_client_info *ilt_cli, uint8_t initop) +{ + struct ecore_ilt *ilt = SC_ILT(sc); + + ecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop); +} + +static void ecore_ilt_client_id_init_op(struct bnx2x_softc *sc, + int cli_num, uint8_t initop) +{ + struct ecore_ilt *ilt = SC_ILT(sc); + struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; + + ecore_ilt_client_init_op(sc, ilt_cli, initop); +} + +static inline void ecore_ilt_init_op_cnic(struct bnx2x_softc *sc, uint8_t initop) +{ + if (CONFIGURE_NIC_MODE(sc)) + ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop); + ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop); +} + +static void ecore_ilt_init_op(struct bnx2x_softc *sc, uint8_t initop) +{ + ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop); + ecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop); + if (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc)) + ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop); +} + +static void ecore_ilt_init_client_psz(struct bnx2x_softc *sc, int cli_num, + uint32_t psz_reg, uint8_t initop) +{ + struct ecore_ilt *ilt = SC_ILT(sc); + struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; + + if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) + return; + + switch (initop) { + case INITOP_INIT: + /* set in the init-value array */ + case INITOP_SET: + REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12)); + break; + case INITOP_CLEAR: + break; + } +} + +/* + * called during init common stage, ilt clients should be initialized + * prioir to calling this function + */ +static void ecore_ilt_init_page_size(struct bnx2x_softc *sc, uint8_t initop) +{ + ecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU, + PXP2_REG_RQ_CDU_P_SIZE, initop); + ecore_ilt_init_client_psz(sc, ILT_CLIENT_QM, + PXP2_REG_RQ_QM_P_SIZE, initop); + ecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC, + PXP2_REG_RQ_SRC_P_SIZE, initop); + ecore_ilt_init_client_psz(sc, ILT_CLIENT_TM, + PXP2_REG_RQ_TM_P_SIZE, initop); +} + +/**************************************************************************** +* QM initializations +****************************************************************************/ +#define QM_QUEUES_PER_FUNC 16 +#define QM_INIT_MIN_CID_COUNT 31 +#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT) + +/* called during init port stage */ +static void ecore_qm_init_cid_count(struct bnx2x_softc *sc, int qm_cid_count, + uint8_t initop) +{ + int port = SC_PORT(sc); + + if (QM_INIT(qm_cid_count)) { + switch (initop) { + case INITOP_INIT: + /* set in the init-value array */ + case INITOP_SET: + REG_WR(sc, QM_REG_CONNNUM_0 + port*4, + qm_cid_count/16 - 1); + break; + case INITOP_CLEAR: + break; + } + } +} + +static void ecore_qm_set_ptr_table(struct bnx2x_softc *sc, int qm_cid_count, + uint32_t base_reg, uint32_t reg) +{ + int i; + uint32_t wb_data[2] = {0, 0}; + for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) { + REG_WR(sc, base_reg + i*4, + qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC)); + ecore_init_wr_wb(sc, reg + i*8, + wb_data, 2); + } +} + +/* called during init common stage */ +static void ecore_qm_init_ptr_table(struct bnx2x_softc *sc, int qm_cid_count, + uint8_t initop) +{ + if (!QM_INIT(qm_cid_count)) + return; + + switch (initop) { + case INITOP_INIT: + /* set in the init-value array */ + case INITOP_SET: + ecore_qm_set_ptr_table(sc, qm_cid_count, + QM_REG_BASEADDR, QM_REG_PTRTBL); + if (CHIP_IS_E1H(sc)) + ecore_qm_set_ptr_table(sc, qm_cid_count, + QM_REG_BASEADDR_EXT_A, + QM_REG_PTRTBL_EXT_A); + break; + case INITOP_CLEAR: + break; + } +} + +/**************************************************************************** +* SRC initializations +****************************************************************************/ +#ifdef ECORE_L5 +/* called during init func stage */ +static void ecore_src_init_t2(struct bnx2x_softc *sc, struct src_ent *t2, + ecore_dma_addr_t t2_mapping, int src_cid_count) +{ + int i; + int port = SC_PORT(sc); + + /* Initialize T2 */ + for (i = 0; i < src_cid_count-1; i++) + t2[i].next = (uint64_t)(t2_mapping + + (i+1)*sizeof(struct src_ent)); + + /* tell the searcher where the T2 table is */ + REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count); + + ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16, + U64_LO(t2_mapping), U64_HI(t2_mapping)); + + ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16, + U64_LO((uint64_t)t2_mapping + + (src_cid_count-1) * sizeof(struct src_ent)), + U64_HI((uint64_t)t2_mapping + + (src_cid_count-1) * sizeof(struct src_ent))); +} +#endif +#endif /* ECORE_INIT_OPS_H */ diff --git a/lib/librte_pmd_bnx2x/ecore_mfw_req.h b/lib/librte_pmd_bnx2x/ecore_mfw_req.h new file mode 100644 index 0000000..39a2848 --- /dev/null +++ b/lib/librte_pmd_bnx2x/ecore_mfw_req.h @@ -0,0 +1,206 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ECORE_MFW_REQ_H +#define ECORE_MFW_REQ_H + + + +#define PORT_0 0 +#define PORT_1 1 +#define PORT_MAX 2 +#define NVM_PATH_MAX 2 + +/* FCoE capabilities required from the driver */ +struct fcoe_capabilities { + uint32_t capability1; + /* Maximum number of I/Os per connection */ + #define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff + #define FCOE_IOS_PER_CONNECTION_SHIFT 0 + /* Maximum number of Logins per port */ + #define FCOE_LOGINS_PER_PORT_MASK 0xffff0000 + #define FCOE_LOGINS_PER_PORT_SHIFT 16 + + uint32_t capability2; + /* Maximum number of exchanges */ + #define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff + #define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0 + /* Maximum NPIV WWN per port */ + #define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000 + #define FCOE_NPIV_WWN_PER_PORT_SHIFT 16 + + uint32_t capability3; + /* Maximum number of targets supported */ + #define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff + #define FCOE_TARGETS_SUPPORTED_SHIFT 0 + /* Maximum number of outstanding commands across all connections */ + #define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000 + #define FCOE_OUTSTANDING_COMMANDS_SHIFT 16 + + uint32_t capability4; + #define FCOE_CAPABILITY4_STATEFUL 0x00000001 + #define FCOE_CAPABILITY4_STATELESS 0x00000002 + #define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID 0x00000004 +}; + +struct glob_ncsi_oem_data +{ + uint32_t driver_version; + uint32_t unused[3]; + struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX]; +}; + +/* current drv_info version */ +#define DRV_INFO_CUR_VER 2 + +/* drv_info op codes supported */ +enum drv_info_opcode { + ETH_STATS_OPCODE, + FCOE_STATS_OPCODE, + ISCSI_STATS_OPCODE +}; + +#define ETH_STAT_INFO_VERSION_LEN 12 +/* Per PCI Function Ethernet Statistics required from the driver */ +struct eth_stats_info { + /* Function's Driver Version. padded to 12 */ + char version[ETH_STAT_INFO_VERSION_LEN]; + /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */ + uint8_t mac_local[8]; + uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */ + uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */ + uint32_t mtu_size; /* MTU Size. Note : Negotiated MTU */ + uint32_t feature_flags; /* Feature_Flags. */ +#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01 +#define FEATURE_ETH_LSO_MASK 0x02 +#define FEATURE_ETH_BOOTMODE_MASK 0x1C +#define FEATURE_ETH_BOOTMODE_SHIFT 2 +#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2) +#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2) +#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2) +#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2) +#define FEATURE_ETH_TOE_MASK 0x20 + uint32_t lso_max_size; /* LSO MaxOffloadSize. */ + uint32_t lso_min_seg_cnt; /* LSO MinSegmentCount. */ + /* Num Offloaded Connections TCP_IPv4. */ + uint32_t ipv4_ofld_cnt; + /* Num Offloaded Connections TCP_IPv6. */ + uint32_t ipv6_ofld_cnt; + uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */ + uint32_t txq_size; /* TX Descriptors Queue Size */ + uint32_t rxq_size; /* RX Descriptors Queue Size */ + /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */ + uint32_t txq_avg_depth; + /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */ + uint32_t rxq_avg_depth; + /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/ + uint32_t iov_offload; + /* Number of NetQueue/VMQ Config'd. */ + uint32_t netq_cnt; + uint32_t vf_cnt; /* Num VF assigned to this PF. */ +}; + +/* Per PCI Function FCOE Statistics required from the driver */ +struct fcoe_stats_info { + uint8_t version[12]; /* Function's Driver Version. */ + uint8_t mac_local[8]; /* Locally Admin Addr. */ + uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */ + uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */ + /* QoS Priority (per 802.1p). 0-7255 */ + uint32_t qos_priority; + uint32_t txq_size; /* FCoE TX Descriptors Queue Size. */ + uint32_t rxq_size; /* FCoE RX Descriptors Queue Size. */ + /* FCoE TX Descriptor Queue Avg Depth. */ + uint32_t txq_avg_depth; + /* FCoE RX Descriptors Queue Avg Depth. */ + uint32_t rxq_avg_depth; + uint32_t rx_frames_lo; /* FCoE RX Frames received. */ + uint32_t rx_frames_hi; /* FCoE RX Frames received. */ + uint32_t rx_bytes_lo; /* FCoE RX Bytes received. */ + uint32_t rx_bytes_hi; /* FCoE RX Bytes received. */ + uint32_t tx_frames_lo; /* FCoE TX Frames sent. */ + uint32_t tx_frames_hi; /* FCoE TX Frames sent. */ + uint32_t tx_bytes_lo; /* FCoE TX Bytes sent. */ + uint32_t tx_bytes_hi; /* FCoE TX Bytes sent. */ + uint32_t rx_fcs_errors; /* number of receive packets with FCS errors */ + uint32_t rx_fc_crc_errors; /* number of FC frames with CRC errors*/ + uint32_t fip_login_failures; /* number of FCoE/FIP Login failures */ +}; + +/* Per PCI Function iSCSI Statistics required from the driver*/ +struct iscsi_stats_info { + uint8_t version[12]; /* Function's Driver Version. */ + uint8_t mac_local[8]; /* Locally Admin iSCSI MAC Addr. */ + uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */ + /* QoS Priority (per 802.1p). 0-7255 */ + uint32_t qos_priority; + + uint8_t initiator_name[64]; /* iSCSI Boot Initiator Node name. */ + + uint8_t ww_port_name[64]; /* iSCSI World wide port name */ + + uint8_t boot_target_name[64];/* iSCSI Boot Target Name. */ + + uint8_t boot_target_ip[16]; /* iSCSI Boot Target IP. */ + uint32_t boot_target_portal; /* iSCSI Boot Target Portal. */ + uint8_t boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */ + uint32_t max_frame_size; /* Max Frame Size. bytes */ + uint32_t txq_size; /* PDU TX Descriptors Queue Size. */ + uint32_t rxq_size; /* PDU RX Descriptors Queue Size. */ + + uint32_t txq_avg_depth; /*PDU TX Descriptor Queue Avg Depth. */ + uint32_t rxq_avg_depth; /*PDU RX Descriptors Queue Avg Depth. */ + uint32_t rx_pdus_lo; /* iSCSI PDUs received. */ + uint32_t rx_pdus_hi; /* iSCSI PDUs received. */ + + uint32_t rx_bytes_lo; /* iSCSI RX Bytes received. */ + uint32_t rx_bytes_hi; /* iSCSI RX Bytes received. */ + uint32_t tx_pdus_lo; /* iSCSI PDUs sent. */ + uint32_t tx_pdus_hi; /* iSCSI PDUs sent. */ + + uint32_t tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */ + uint32_t tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */ + uint32_t pcp_prior_map_tbl; /*C-PCP to S-PCP Priority MapTable. + 9 nibbles, the position of each nibble + represents the C-PCP value, the value + of the nibble = S-PCP value.*/ +}; + +union drv_info_to_mcp { + struct eth_stats_info ether_stat; + struct fcoe_stats_info fcoe_stat; + struct iscsi_stats_info iscsi_stat; +}; + + +#endif /* ECORE_MFW_REQ_H */ diff --git a/lib/librte_pmd_bnx2x/ecore_reg.h b/lib/librte_pmd_bnx2x/ecore_reg.h new file mode 100644 index 0000000..3f980f8 --- /dev/null +++ b/lib/librte_pmd_bnx2x/ecore_reg.h @@ -0,0 +1,3663 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ECORE_REG_H +#define ECORE_REG_H + + +#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \ + (0x1<<0) +#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \ + (0x1<<2) +#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \ + (0x1<<5) +#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \ + (0x1<<3) +#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \ + (0x1<<4) +#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \ + (0x1<<1) +#define ATC_REG_ATC_INIT_DONE \ + 0x1100bcUL +#define ATC_REG_ATC_INT_STS_CLR \ + 0x1101c0UL +#define ATC_REG_ATC_PRTY_MASK \ + 0x1101d8UL +#define ATC_REG_ATC_PRTY_STS_CLR \ + 0x1101d0UL +#define BRB1_REG_BRB1_INT_MASK \ + 0x60128UL +#define BRB1_REG_BRB1_PRTY_MASK \ + 0x60138UL +#define BRB1_REG_BRB1_PRTY_STS_CLR \ + 0x60130UL +#define BRB1_REG_MAC_GUARANTIED_0 \ + 0x601e8UL +#define BRB1_REG_MAC_GUARANTIED_1 \ + 0x60240UL +#define BRB1_REG_NUM_OF_FULL_BLOCKS \ + 0x60090UL +#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \ + 0x60078UL +#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \ + 0x60068UL +#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \ + 0x60094UL +#define CCM_REG_CCM_INT_MASK \ + 0xd01e4UL +#define CCM_REG_CCM_PRTY_MASK \ + 0xd01f4UL +#define CCM_REG_CCM_PRTY_STS_CLR \ + 0xd01ecUL +#define CDU_REG_CDU_GLOBAL_PARAMS \ + 0x101020UL +#define CDU_REG_CDU_INT_MASK \ + 0x10103cUL +#define CDU_REG_CDU_PRTY_MASK \ + 0x10104cUL +#define CDU_REG_CDU_PRTY_STS_CLR \ + 0x101044UL +#define CFC_REG_AC_INIT_DONE \ + 0x104078UL +#define CFC_REG_CAM_INIT_DONE \ + 0x10407cUL +#define CFC_REG_CFC_INT_MASK \ + 0x104108UL +#define CFC_REG_CFC_INT_STS_CLR \ + 0x104100UL +#define CFC_REG_CFC_PRTY_MASK \ + 0x104118UL +#define CFC_REG_CFC_PRTY_STS_CLR \ + 0x104110UL +#define CFC_REG_DEBUG0 \ + 0x104050UL +#define CFC_REG_INIT_REG \ + 0x10404cUL +#define CFC_REG_LL_INIT_DONE \ + 0x104074UL +#define CFC_REG_NUM_LCIDS_INSIDE_PF \ + 0x104120UL +#define CFC_REG_STRONG_ENABLE_PF \ + 0x104128UL +#define CFC_REG_WEAK_ENABLE_PF \ + 0x104124UL +#define CSDM_REG_CSDM_INT_MASK_0 \ + 0xc229cUL +#define CSDM_REG_CSDM_INT_MASK_1 \ + 0xc22acUL +#define CSDM_REG_CSDM_PRTY_MASK \ + 0xc22bcUL +#define CSDM_REG_CSDM_PRTY_STS_CLR \ + 0xc22b4UL +#define CSEM_REG_CSEM_INT_MASK_0 \ + 0x200110UL +#define CSEM_REG_CSEM_INT_MASK_1 \ + 0x200120UL +#define CSEM_REG_CSEM_PRTY_MASK_0 \ + 0x200130UL +#define CSEM_REG_CSEM_PRTY_MASK_1 \ + 0x200140UL +#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \ + 0x200128UL +#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \ + 0x200138UL +#define CSEM_REG_FAST_MEMORY \ + 0x220000UL +#define CSEM_REG_INT_TABLE \ + 0x200400UL +#define CSEM_REG_PASSIVE_BUFFER \ + 0x202000UL +#define CSEM_REG_PRAM \ + 0x240000UL +#define CSEM_REG_VFPF_ERR_NUM \ + 0x200380UL +#define DBG_REG_DBG_PRTY_MASK \ + 0xc0a8UL +#define DBG_REG_DBG_PRTY_STS_CLR \ + 0xc0a0UL +#define DMAE_REG_BACKWARD_COMP_EN \ + 0x10207cUL +#define DMAE_REG_CMD_MEM \ + 0x102400UL +#define DMAE_REG_DMAE_INT_MASK \ + 0x102054UL +#define DMAE_REG_DMAE_PRTY_MASK \ + 0x102064UL +#define DMAE_REG_DMAE_PRTY_STS_CLR \ + 0x10205cUL +#define DMAE_REG_GO_C0 \ + 0x102080UL +#define DMAE_REG_GO_C1 \ + 0x102084UL +#define DMAE_REG_GO_C10 \ + 0x102088UL +#define DMAE_REG_GO_C11 \ + 0x10208cUL +#define DMAE_REG_GO_C12 \ + 0x102090UL +#define DMAE_REG_GO_C13 \ + 0x102094UL +#define DMAE_REG_GO_C14 \ + 0x102098UL +#define DMAE_REG_GO_C15 \ + 0x10209cUL +#define DMAE_REG_GO_C2 \ + 0x1020a0UL +#define DMAE_REG_GO_C3 \ + 0x1020a4UL +#define DMAE_REG_GO_C4 \ + 0x1020a8UL +#define DMAE_REG_GO_C5 \ + 0x1020acUL +#define DMAE_REG_GO_C6 \ + 0x1020b0UL +#define DMAE_REG_GO_C7 \ + 0x1020b4UL +#define DMAE_REG_GO_C8 \ + 0x1020b8UL +#define DMAE_REG_GO_C9 \ + 0x1020bcUL +#define DORQ_REG_DORQ_INT_MASK \ + 0x170180UL +#define DORQ_REG_DORQ_INT_STS_CLR \ + 0x170178UL +#define DORQ_REG_DORQ_PRTY_MASK \ + 0x170190UL +#define DORQ_REG_DORQ_PRTY_STS_CLR \ + 0x170188UL +#define DORQ_REG_DPM_CID_OFST \ + 0x170030UL +#define DORQ_REG_MAX_RVFID_SIZE \ + 0x1701ecUL +#define DORQ_REG_NORM_CID_OFST \ + 0x17002cUL +#define DORQ_REG_PF_USAGE_CNT \ + 0x1701d0UL +#define DORQ_REG_VF_NORM_CID_BASE \ + 0x1701a0UL +#define DORQ_REG_VF_NORM_CID_OFST \ + 0x1701f4UL +#define DORQ_REG_VF_NORM_CID_WND_SIZE \ + 0x1701a4UL +#define DORQ_REG_VF_NORM_MAX_CID_COUNT \ + 0x1701e4UL +#define DORQ_REG_VF_NORM_VF_BASE \ + 0x1701a8UL +#define DORQ_REG_VF_TYPE_MASK_0 \ + 0x170218UL +#define DORQ_REG_VF_TYPE_MAX_MCID_0 \ + 0x1702d8UL +#define DORQ_REG_VF_TYPE_MIN_MCID_0 \ + 0x170298UL +#define DORQ_REG_VF_TYPE_VALUE_0 \ + 0x170258UL +#define DORQ_REG_VF_USAGE_CNT \ + 0x170320UL +#define DORQ_REG_VF_USAGE_CT_LIMIT \ + 0x170340UL +#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \ + (0x1<<4) +#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \ + (0x1<<0) +#define HC_CONFIG_0_REG_INT_LINE_EN_0 \ + (0x1<<3) +#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \ + (0x1<<7) +#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \ + (0x1<<2) +#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \ + (0x1<<1) +#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \ + (0x1<<0) +#define HC_REG_ATTN_MSG0_ADDR_L \ + 0x108018UL +#define HC_REG_ATTN_MSG1_ADDR_L \ + 0x108020UL +#define HC_REG_COMMAND_REG \ + 0x108180UL +#define HC_REG_CONFIG_0 \ + 0x108000UL +#define HC_REG_CONFIG_1 \ + 0x108004UL +#define HC_REG_HC_PRTY_MASK \ + 0x1080a0UL +#define HC_REG_HC_PRTY_STS_CLR \ + 0x108098UL +#define HC_REG_INT_MASK \ + 0x108108UL +#define HC_REG_LEADING_EDGE_0 \ + 0x108040UL +#define HC_REG_MAIN_MEMORY \ + 0x108800UL +#define HC_REG_MAIN_MEMORY_SIZE \ + 152 +#define HC_REG_TRAILING_EDGE_0 \ + 0x108044UL +#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \ + (0x1<<1) +#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \ + (0x1<<0) +#define IGU_REG_ATTENTION_ACK_BITS \ + 0x130108UL +#define IGU_REG_ATTN_MSG_ADDR_H \ + 0x13011cUL +#define IGU_REG_ATTN_MSG_ADDR_L \ + 0x130120UL +#define IGU_REG_BLOCK_CONFIGURATION \ + 0x130000UL +#define IGU_REG_COMMAND_REG_32LSB_DATA \ + 0x130124UL +#define IGU_REG_COMMAND_REG_CTRL \ + 0x13012cUL +#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \ + 0x130200UL +#define IGU_REG_IGU_PRTY_MASK \ + 0x1300a8UL +#define IGU_REG_IGU_PRTY_STS_CLR \ + 0x1300a0UL +#define IGU_REG_LEADING_EDGE_LATCH \ + 0x130134UL +#define IGU_REG_MAPPING_MEMORY \ + 0x131000UL +#define IGU_REG_MAPPING_MEMORY_SIZE \ + 136 +#define IGU_REG_PBA_STATUS_LSB \ + 0x130138UL +#define IGU_REG_PBA_STATUS_MSB \ + 0x13013cUL +#define IGU_REG_PCI_PF_MSIX_EN \ + 0x130144UL +#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \ + 0x130148UL +#define IGU_REG_PCI_PF_MSI_EN \ + 0x130140UL +#define IGU_REG_PENDING_BITS_STATUS \ + 0x130300UL +#define IGU_REG_PF_CONFIGURATION \ + 0x130154UL +#define IGU_REG_PROD_CONS_MEMORY \ + 0x132000UL +#define IGU_REG_RESET_MEMORIES \ + 0x130158UL +#define IGU_REG_SB_INT_BEFORE_MASK_LSB \ + 0x13015cUL +#define IGU_REG_SB_INT_BEFORE_MASK_MSB \ + 0x130160UL +#define IGU_REG_SB_MASK_LSB \ + 0x130164UL +#define IGU_REG_SB_MASK_MSB \ + 0x130168UL +#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \ + 0x130800UL +#define IGU_REG_TRAILING_EDGE_LATCH \ + 0x130104UL +#define IGU_REG_VF_CONFIGURATION \ + 0x130170UL +#define MCP_REG_MCPR_ACCESS_LOCK \ + 0x8009c +#define MCP_REG_MCPR_GP_INPUTS \ + 0x800c0 +#define MCP_REG_MCPR_GP_OENABLE \ + 0x800c8 +#define MCP_REG_MCPR_GP_OUTPUTS \ + 0x800c4 +#define MCP_REG_MCPR_IMC_COMMAND \ + 0x85900 +#define MCP_REG_MCPR_IMC_DATAREG0 \ + 0x85920 +#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \ + 0x85904 +#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \ + 0x86424 +#define MCP_REG_MCPR_NVM_ADDR \ + 0x8640c +#define MCP_REG_MCPR_NVM_CFG4 \ + 0x8642c +#define MCP_REG_MCPR_NVM_COMMAND \ + 0x86400 +#define MCP_REG_MCPR_NVM_READ \ + 0x86410 +#define MCP_REG_MCPR_NVM_SW_ARB \ + 0x86420 +#define MCP_REG_MCPR_NVM_WRITE \ + 0x86408 +#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \ + (0x1<<1) +#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \ + (0x1<<0) +#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \ + 0xa42cUL +#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \ + 0xa438UL +#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \ + 0xa444UL +#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \ + 0xa450UL +#define MISC_REG_AEU_AFTER_INVERT_4_MCP \ + 0xa458UL +#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \ + 0xa700UL +#define MISC_REG_AEU_CLR_LATCH_SIGNAL \ + 0xa45cUL +#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \ + 0xa06cUL +#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \ + 0xa07cUL +#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \ + 0xa08cUL +#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \ + 0xa10cUL +#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \ + 0xa11cUL +#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \ + 0xa12cUL +#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \ + 0xa078UL +#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \ + 0xa118UL +#define MISC_REG_AEU_ENABLE4_NIG_0 \ + 0xa0f8UL +#define MISC_REG_AEU_ENABLE4_NIG_1 \ + 0xa198UL +#define MISC_REG_AEU_ENABLE4_PXP_0 \ + 0xa108UL +#define MISC_REG_AEU_ENABLE4_PXP_1 \ + 0xa1a8UL +#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \ + 0xa688UL +#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \ + 0xa6b0UL +#define MISC_REG_AEU_GENERAL_ATTN_0 \ + 0xa000UL +#define MISC_REG_AEU_GENERAL_ATTN_1 \ + 0xa004UL +#define MISC_REG_AEU_GENERAL_ATTN_10 \ + 0xa028UL +#define MISC_REG_AEU_GENERAL_ATTN_11 \ + 0xa02cUL +#define MISC_REG_AEU_GENERAL_ATTN_12 \ + 0xa030UL +#define MISC_REG_AEU_GENERAL_ATTN_2 \ + 0xa008UL +#define MISC_REG_AEU_GENERAL_ATTN_3 \ + 0xa00cUL +#define MISC_REG_AEU_GENERAL_ATTN_4 \ + 0xa010UL +#define MISC_REG_AEU_GENERAL_ATTN_5 \ + 0xa014UL +#define MISC_REG_AEU_GENERAL_ATTN_6 \ + 0xa018UL +#define MISC_REG_AEU_GENERAL_ATTN_7 \ + 0xa01cUL +#define MISC_REG_AEU_GENERAL_ATTN_8 \ + 0xa020UL +#define MISC_REG_AEU_GENERAL_ATTN_9 \ + 0xa024UL +#define MISC_REG_AEU_GENERAL_MASK \ + 0xa61cUL +#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \ + 0xa060UL +#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \ + 0xa064UL +#define MISC_REG_BOND_ID \ + 0xa400UL +#define MISC_REG_CHIP_NUM \ + 0xa408UL +#define MISC_REG_CHIP_REV \ + 0xa40cUL +#define MISC_REG_CHIP_TYPE \ + 0xac60UL +#define MISC_REG_CHIP_TYPE_57811_MASK \ + (1<<1) +#define MISC_REG_CPMU_LP_DR_ENABLE \ + 0xa858UL +#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \ + 0xa84cUL +#define MISC_REG_CPMU_LP_IDLE_THR_P0 \ + 0xa8a0UL +#define MISC_REG_CPMU_LP_MASK_ENT_P0 \ + 0xa880UL +#define MISC_REG_CPMU_LP_MASK_EXT_P0 \ + 0xa888UL +#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \ + 0xa8b8UL +#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \ + 0xa8bcUL +#define MISC_REG_DRIVER_CONTROL_1 \ + 0xa510UL +#define MISC_REG_DRIVER_CONTROL_7 \ + 0xa3c8UL +#define MISC_REG_FOUR_PORT_PATH_SWAP \ + 0xa75cUL +#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \ + 0xa738UL +#define MISC_REG_FOUR_PORT_PORT_SWAP \ + 0xa754UL +#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \ + 0xa734UL +#define MISC_REG_GENERIC_CR_0 \ + 0xa460UL +#define MISC_REG_GENERIC_CR_1 \ + 0xa464UL +#define MISC_REG_GENERIC_POR_1 \ + 0xa474UL +#define MISC_REG_GEN_PURP_HWG \ + 0xa9a0UL +#define MISC_REG_GPIO \ + 0xa490UL +#define MISC_REG_GPIO_EVENT_EN \ + 0xa2bcUL +#define MISC_REG_GPIO_INT \ + 0xa494UL +#define MISC_REG_GRC_RSV_ATTN \ + 0xa3c0UL +#define MISC_REG_GRC_TIMEOUT_ATTN \ + 0xa3c4UL +#define MISC_REG_LCPLL_E40_PWRDWN \ + 0xaa74UL +#define MISC_REG_LCPLL_E40_RESETB_ANA \ + 0xaa78UL +#define MISC_REG_LCPLL_E40_RESETB_DIG \ + 0xaa7cUL +#define MISC_REG_MISC_INT_MASK \ + 0xa388UL +#define MISC_REG_MISC_PRTY_MASK \ + 0xa398UL +#define MISC_REG_MISC_PRTY_STS_CLR \ + 0xa390UL +#define MISC_REG_PORT4MODE_EN \ + 0xa750UL +#define MISC_REG_PORT4MODE_EN_OVWR \ + 0xa720UL +#define MISC_REG_RESET_REG_1 \ + 0xa580UL +#define MISC_REG_RESET_REG_2 \ + 0xa590UL +#define MISC_REG_SHARED_MEM_ADDR \ + 0xa2b4UL +#define MISC_REG_SPIO \ + 0xa4fcUL +#define MISC_REG_SPIO_EVENT_EN \ + 0xa2b8UL +#define MISC_REG_SPIO_INT \ + 0xa500UL +#define MISC_REG_TWO_PORT_PATH_SWAP \ + 0xa758UL +#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \ + 0xa72cUL +#define MISC_REG_UNPREPARED \ + 0xa424UL +#define MISC_REG_WC0_CTRL_PHY_ADDR \ + 0xa9ccUL +#define MISC_REG_WC0_RESET \ + 0xac30UL +#define MISC_REG_XMAC_CORE_PORT_MODE \ + 0xa964UL +#define MISC_REG_XMAC_PHY_PORT_MODE \ + 0xa960UL +#define MSTAT_REG_RX_STAT_GR64_LO \ + 0x200UL +#define MSTAT_REG_TX_STAT_GTXPOK_LO \ + 0UL +#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \ + (0x1<<0) +#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \ + (0x1<<0) +#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \ + (0x1<<0) +#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \ + (0x1<<9) +#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \ + (0x1<<15) +#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \ + (0xf<<18) +#define NIG_REG_BMAC0_IN_EN \ + 0x100acUL +#define NIG_REG_BMAC0_OUT_EN \ + 0x100e0UL +#define NIG_REG_BMAC0_PAUSE_OUT_EN \ + 0x10110UL +#define NIG_REG_BMAC0_REGS_OUT_EN \ + 0x100e8UL +#define NIG_REG_BRB0_PAUSE_IN_EN \ + 0x100c4UL +#define NIG_REG_BRB1_PAUSE_IN_EN \ + 0x100c8UL +#define NIG_REG_DEBUG_PACKET_LB \ + 0x10800UL +#define NIG_REG_EGRESS_DRAIN0_MODE \ + 0x10060UL +#define NIG_REG_EGRESS_EMAC0_OUT_EN \ + 0x10120UL +#define NIG_REG_EGRESS_EMAC0_PORT \ + 0x10058UL +#define NIG_REG_EMAC0_IN_EN \ + 0x100a4UL +#define NIG_REG_EMAC0_PAUSE_OUT_EN \ + 0x10118UL +#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \ + 0x10494UL +#define NIG_REG_INGRESS_BMAC0_MEM \ + 0x10c00UL +#define NIG_REG_INGRESS_BMAC1_MEM \ + 0x11000UL +#define NIG_REG_INGRESS_EOP_LB_EMPTY \ + 0x104e0UL +#define NIG_REG_INGRESS_EOP_LB_FIFO \ + 0x104e4UL +#define NIG_REG_LATCH_BC_0 \ + 0x16210UL +#define NIG_REG_LATCH_STATUS_0 \ + 0x18000UL +#define NIG_REG_LED_10G_P0 \ + 0x10320UL +#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \ + 0x10318UL +#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \ + 0x10310UL +#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \ + 0x10308UL +#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \ + 0x102f8UL +#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \ + 0x10300UL +#define NIG_REG_LED_MODE_P0 \ + 0x102f0UL +#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \ + 0x16070UL +#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \ + 0x16074UL +#define NIG_REG_LLFC_ENABLE_0 \ + 0x16208UL +#define NIG_REG_LLFC_ENABLE_1 \ + 0x1620cUL +#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \ + 0x16058UL +#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \ + 0x1605cUL +#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \ + 0x16060UL +#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \ + 0x16064UL +#define NIG_REG_LLFC_OUT_EN_0 \ + 0x160c8UL +#define NIG_REG_LLFC_OUT_EN_1 \ + 0x160ccUL +#define NIG_REG_LLH0_BRB1_DRV_MASK \ + 0x10244UL +#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \ + 0x16048UL +#define NIG_REG_LLH0_BRB1_NOT_MCP \ + 0x1025cUL +#define NIG_REG_LLH0_CLS_TYPE \ + 0x16080UL +#define NIG_REG_LLH0_FUNC_EN \ + 0x160fcUL +#define NIG_REG_LLH0_FUNC_MEM \ + 0x16180UL +#define NIG_REG_LLH0_FUNC_MEM_ENABLE \ + 0x16140UL +#define NIG_REG_LLH0_FUNC_VLAN_ID \ + 0x16100UL +#define NIG_REG_LLH0_XCM_MASK \ + 0x10130UL +#define NIG_REG_LLH1_BRB1_NOT_MCP \ + 0x102dcUL +#define NIG_REG_LLH1_CLS_TYPE \ + 0x16084UL +#define NIG_REG_LLH1_FUNC_MEM \ + 0x161c0UL +#define NIG_REG_LLH1_FUNC_MEM_ENABLE \ + 0x16160UL +#define NIG_REG_LLH1_FUNC_MEM_SIZE \ + 16 +#define NIG_REG_LLH1_MF_MODE \ + 0x18614UL +#define NIG_REG_LLH1_XCM_MASK \ + 0x10134UL +#define NIG_REG_LLH_E1HOV_MODE \ + 0x160d8UL +#define NIG_REG_LLH_MF_MODE \ + 0x16024UL +#define NIG_REG_MASK_INTERRUPT_PORT0 \ + 0x10330UL +#define NIG_REG_MASK_INTERRUPT_PORT1 \ + 0x10334UL +#define NIG_REG_NIG_EMAC0_EN \ + 0x1003cUL +#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \ + 0x10044UL +#define NIG_REG_NIG_INT_STS_CLR_0 \ + 0x103b4UL +#define NIG_REG_NIG_PRTY_MASK \ + 0x103dcUL +#define NIG_REG_NIG_PRTY_MASK_0 \ + 0x183c8UL +#define NIG_REG_NIG_PRTY_MASK_1 \ + 0x183d8UL +#define NIG_REG_NIG_PRTY_STS_CLR \ + 0x103d4UL +#define NIG_REG_NIG_PRTY_STS_CLR_0 \ + 0x183c0UL +#define NIG_REG_NIG_PRTY_STS_CLR_1 \ + 0x183d0UL +#define NIG_REG_P0_HDRS_AFTER_BASIC \ + 0x18038UL +#define NIG_REG_P0_HWPFC_ENABLE \ + 0x18078UL +#define NIG_REG_P0_LLH_FUNC_MEM2 \ + 0x18480UL +#define NIG_REG_P0_MAC_IN_EN \ + 0x185acUL +#define NIG_REG_P0_MAC_OUT_EN \ + 0x185b0UL +#define NIG_REG_P0_MAC_PAUSE_OUT_EN \ + 0x185b4UL +#define NIG_REG_P0_PKT_PRIORITY_TO_COS \ + 0x18054UL +#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \ + 0x18058UL +#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \ + 0x1805cUL +#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \ + 0x186b0UL +#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \ + 0x186b4UL +#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \ + 0x186b8UL +#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \ + 0x186bcUL +#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \ + 0x180f0UL +#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \ + 0x18688UL +#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \ + 0x1868cUL +#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \ + 0x180e8UL +#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \ + 0x180ecUL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \ + 0x1810cUL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \ + 0x18110UL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \ + 0x18114UL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \ + 0x18118UL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \ + 0x1811cUL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \ + 0x186a0UL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \ + 0x186a4UL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \ + 0x186a8UL +#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \ + 0x186acUL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \ + 0x180f8UL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \ + 0x180fcUL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \ + 0x18100UL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \ + 0x18104UL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \ + 0x18108UL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \ + 0x18690UL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \ + 0x18694UL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \ + 0x18698UL +#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \ + 0x1869cUL +#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \ + 0x180f4UL +#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \ + 0x180e4UL +#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \ + 0x18680UL +#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \ + 0x18684UL +#define NIG_REG_P1_HDRS_AFTER_BASIC \ + 0x1818cUL +#define NIG_REG_P1_HWPFC_ENABLE \ + 0x181d0UL +#define NIG_REG_P1_LLH_FUNC_MEM2 \ + 0x184c0UL +#define NIG_REG_P1_MAC_IN_EN \ + 0x185c0UL +#define NIG_REG_P1_MAC_OUT_EN \ + 0x185c4UL +#define NIG_REG_P1_MAC_PAUSE_OUT_EN \ + 0x185c8UL +#define NIG_REG_P1_PKT_PRIORITY_TO_COS \ + 0x181a8UL +#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \ + 0x181acUL +#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \ + 0x181b0UL +#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \ + 0x186f8UL +#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \ + 0x186e8UL +#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \ + 0x186ecUL +#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \ + 0x18234UL +#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \ + 0x18238UL +#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \ + 0x18258UL +#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \ + 0x1825cUL +#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \ + 0x18260UL +#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \ + 0x18264UL +#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \ + 0x18268UL +#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \ + 0x186f4UL +#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \ + 0x18244UL +#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \ + 0x18248UL +#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \ + 0x1824cUL +#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \ + 0x18250UL +#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \ + 0x18254UL +#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \ + 0x186f0UL +#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \ + 0x18240UL +#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \ + 0x186e0UL +#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \ + 0x186e4UL +#define NIG_REG_PAUSE_ENABLE_0 \ + 0x160c0UL +#define NIG_REG_PAUSE_ENABLE_1 \ + 0x160c4UL +#define NIG_REG_PORT_SWAP \ + 0x10394UL +#define NIG_REG_PPP_ENABLE_0 \ + 0x160b0UL +#define NIG_REG_PPP_ENABLE_1 \ + 0x160b4UL +#define NIG_REG_PRS_REQ_IN_EN \ + 0x100b8UL +#define NIG_REG_SERDES0_CTRL_MD_DEVAD \ + 0x10370UL +#define NIG_REG_SERDES0_CTRL_MD_ST \ + 0x1036cUL +#define NIG_REG_SERDES0_CTRL_PHY_ADDR \ + 0x10374UL +#define NIG_REG_SERDES0_STATUS_LINK_STATUS \ + 0x10578UL +#define NIG_REG_STAT0_BRB_DISCARD \ + 0x105f0UL +#define NIG_REG_STAT0_BRB_TRUNCATE \ + 0x105f8UL +#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \ + 0x10750UL +#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \ + 0x10760UL +#define NIG_REG_STAT1_BRB_DISCARD \ + 0x10628UL +#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \ + 0x107a0UL +#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \ + 0x107b0UL +#define NIG_REG_STAT2_BRB_OCTET \ + 0x107e0UL +#define NIG_REG_STATUS_INTERRUPT_PORT0 \ + 0x10328UL +#define NIG_REG_STRAP_OVERRIDE \ + 0x10398UL +#define NIG_REG_XCM0_OUT_EN \ + 0x100f0UL +#define NIG_REG_XCM1_OUT_EN \ + 0x100f4UL +#define NIG_REG_XGXS0_CTRL_MD_DEVAD \ + 0x1033cUL +#define NIG_REG_XGXS0_CTRL_MD_ST \ + 0x10338UL +#define NIG_REG_XGXS0_CTRL_PHY_ADDR \ + 0x10340UL +#define NIG_REG_XGXS0_STATUS_LINK10G \ + 0x10680UL +#define NIG_REG_XGXS0_STATUS_LINK_STATUS \ + 0x10684UL +#define NIG_REG_XGXS_LANE_SEL_P0 \ + 0x102e8UL +#define NIG_REG_XGXS_SERDES0_MODE_SEL \ + 0x102e0UL +#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \ + (0x1<<0) +#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \ + (0x1<<9) +#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \ + (0x1<<15) +#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \ + (0xf<<18) +#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \ + 18 +#define PBF_REG_COS0_UPPER_BOUND \ + 0x15c05cUL +#define PBF_REG_COS0_UPPER_BOUND_P0 \ + 0x15c2ccUL +#define PBF_REG_COS0_UPPER_BOUND_P1 \ + 0x15c2e4UL +#define PBF_REG_COS0_WEIGHT \ + 0x15c054UL +#define PBF_REG_COS0_WEIGHT_P0 \ + 0x15c2a8UL +#define PBF_REG_COS0_WEIGHT_P1 \ + 0x15c2c0UL +#define PBF_REG_COS1_UPPER_BOUND \ + 0x15c060UL +#define PBF_REG_COS1_WEIGHT \ + 0x15c058UL +#define PBF_REG_COS1_WEIGHT_P0 \ + 0x15c2acUL +#define PBF_REG_COS1_WEIGHT_P1 \ + 0x15c2c4UL +#define PBF_REG_COS2_WEIGHT_P0 \ + 0x15c2b0UL +#define PBF_REG_COS2_WEIGHT_P1 \ + 0x15c2c8UL +#define PBF_REG_COS3_WEIGHT_P0 \ + 0x15c2b4UL +#define PBF_REG_COS4_WEIGHT_P0 \ + 0x15c2b8UL +#define PBF_REG_COS5_WEIGHT_P0 \ + 0x15c2bcUL +#define PBF_REG_CREDIT_LB_Q \ + 0x140338UL +#define PBF_REG_CREDIT_Q0 \ + 0x14033cUL +#define PBF_REG_CREDIT_Q1 \ + 0x140340UL +#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \ + 0x14005cUL +#define PBF_REG_DISABLE_PF \ + 0x1402e8UL +#define PBF_REG_DISABLE_VF \ + 0x1402ecUL +#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \ + 0x15c288UL +#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \ + 0x15c28cUL +#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \ + 0x15c278UL +#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \ + 0x15c27cUL +#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \ + 0x15c280UL +#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \ + 0x15c284UL +#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \ + 0x15c2a0UL +#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \ + 0x15c2a4UL +#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \ + 0x15c270UL +#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \ + 0x15c274UL +#define PBF_REG_ETS_ENABLED \ + 0x15c050UL +#define PBF_REG_HDRS_AFTER_BASIC \ + 0x15c0a8UL +#define PBF_REG_HDRS_AFTER_TAG_0 \ + 0x15c0b8UL +#define PBF_REG_HIGH_PRIORITY_COS_NUM \ + 0x15c04cUL +#define PBF_REG_INIT_CRD_LB_Q \ + 0x15c248UL +#define PBF_REG_INIT_CRD_Q0 \ + 0x15c230UL +#define PBF_REG_INIT_CRD_Q1 \ + 0x15c234UL +#define PBF_REG_INIT_P0 \ + 0x140004UL +#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \ + 0x140354UL +#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \ + 0x140358UL +#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \ + 0x14035cUL +#define PBF_REG_MUST_HAVE_HDRS \ + 0x15c0c4UL +#define PBF_REG_NUM_STRICT_ARB_SLOTS \ + 0x15c064UL +#define PBF_REG_P0_ARB_THRSH \ + 0x1400e4UL +#define PBF_REG_P0_CREDIT \ + 0x140200UL +#define PBF_REG_P0_INIT_CRD \ + 0x1400d0UL +#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \ + 0x140308UL +#define PBF_REG_P0_PAUSE_ENABLE \ + 0x140014UL +#define PBF_REG_P0_TQ_LINES_FREED_CNT \ + 0x1402f0UL +#define PBF_REG_P0_TQ_OCCUPANCY \ + 0x1402fcUL +#define PBF_REG_P1_CREDIT \ + 0x140208UL +#define PBF_REG_P1_INIT_CRD \ + 0x1400d4UL +#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \ + 0x14030cUL +#define PBF_REG_P1_TQ_LINES_FREED_CNT \ + 0x1402f4UL +#define PBF_REG_P1_TQ_OCCUPANCY \ + 0x140300UL +#define PBF_REG_P4_CREDIT \ + 0x140210UL +#define PBF_REG_P4_INIT_CRD \ + 0x1400e0UL +#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \ + 0x140310UL +#define PBF_REG_P4_TQ_LINES_FREED_CNT \ + 0x1402f8UL +#define PBF_REG_P4_TQ_OCCUPANCY \ + 0x140304UL +#define PBF_REG_PBF_INT_MASK \ + 0x1401d4UL +#define PBF_REG_PBF_PRTY_MASK \ + 0x1401e4UL +#define PBF_REG_PBF_PRTY_STS_CLR \ + 0x1401dcUL +#define PBF_REG_TAG_ETHERTYPE_0 \ + 0x15c090UL +#define PBF_REG_TAG_LEN_0 \ + 0x15c09cUL +#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \ + 0x14038cUL +#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \ + 0x140390UL +#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \ + 0x140394UL +#define PBF_REG_TQ_OCCUPANCY_LB_Q \ + 0x1403a8UL +#define PBF_REG_TQ_OCCUPANCY_Q0 \ + 0x1403acUL +#define PBF_REG_TQ_OCCUPANCY_Q1 \ + 0x1403b0UL +#define PB_REG_PB_INT_MASK \ + 0x28UL +#define PB_REG_PB_PRTY_MASK \ + 0x38UL +#define PB_REG_PB_PRTY_STS_CLR \ + 0x30UL +#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \ + (0x1<<0) +#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \ + (0x1<<8) +#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \ + (0x1<<1) +#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \ + (0x1<<6) +#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \ + (0x1<<7) +#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \ + (0x1<<4) +#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \ + (0x1<<3) +#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \ + (0x1<<5) +#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \ + (0x1<<2) +#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \ + 0x9418UL +#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ + 0x9478UL +#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \ + 0x947cUL +#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \ + 0x9480UL +#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \ + 0x9474UL +#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ + 0x942cUL +#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ + 0x9430UL +#define PGLUE_B_REG_INTERNAL_VFID_ENABLE \ + 0x9438UL +#define PGLUE_B_REG_PGLUE_B_INT_STS \ + 0x9298UL +#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \ + 0x929cUL +#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \ + 0x92b4UL +#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \ + 0x92acUL +#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \ + 0x9458UL +#define PGLUE_B_REG_TAGS_63_32 \ + 0x9244UL +#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \ + 0x9470UL +#define PRS_REG_A_PRSU_20 \ + 0x40134UL +#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \ + 0x4011cUL +#define PRS_REG_E1HOV_MODE \ + 0x401c8UL +#define PRS_REG_HDRS_AFTER_BASIC \ + 0x40238UL +#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \ + 0x40270UL +#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \ + 0x40290UL +#define PRS_REG_HDRS_AFTER_TAG_0 \ + 0x40248UL +#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \ + 0x40280UL +#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \ + 0x402a0UL +#define PRS_REG_MUST_HAVE_HDRS \ + 0x40254UL +#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \ + 0x4028cUL +#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \ + 0x402acUL +#define PRS_REG_NIC_MODE \ + 0x40138UL +#define PRS_REG_NUM_OF_PACKETS \ + 0x40124UL +#define PRS_REG_PRS_PRTY_MASK \ + 0x401a4UL +#define PRS_REG_PRS_PRTY_STS_CLR \ + 0x4019cUL +#define PRS_REG_TAG_ETHERTYPE_0 \ + 0x401d4UL +#define PRS_REG_TAG_LEN_0 \ + 0x4022cUL +#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \ + (0x1<<19) +#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \ + (0x1<<20) +#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \ + (0x1<<22) +#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \ + (0x1<<23) +#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \ + (0x1<<24) +#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \ + (0x1<<7) +#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \ + (0x1<<7) +#define PXP2_REG_PGL_ADDR_88_F0 \ + 0x120534UL +#define PXP2_REG_PGL_ADDR_88_F1 \ + 0x120544UL +#define PXP2_REG_PGL_ADDR_8C_F0 \ + 0x120538UL +#define PXP2_REG_PGL_ADDR_8C_F1 \ + 0x120548UL +#define PXP2_REG_PGL_ADDR_90_F0 \ + 0x12053cUL +#define PXP2_REG_PGL_ADDR_90_F1 \ + 0x12054cUL +#define PXP2_REG_PGL_ADDR_94_F0 \ + 0x120540UL +#define PXP2_REG_PGL_ADDR_94_F1 \ + 0x120550UL +#define PXP2_REG_PGL_EXP_ROM2 \ + 0x120808UL +#define PXP2_REG_PGL_PRETEND_FUNC_F0 \ + 0x120674UL +#define PXP2_REG_PGL_PRETEND_FUNC_F1 \ + 0x120678UL +#define PXP2_REG_PGL_TAGS_LIMIT \ + 0x1205a8UL +#define PXP2_REG_PSWRQ_BW_ADD1 \ + 0x1201c0UL +#define PXP2_REG_PSWRQ_BW_ADD10 \ + 0x1201e4UL +#define PXP2_REG_PSWRQ_BW_ADD11 \ + 0x1201e8UL +#define PXP2_REG_PSWRQ_BW_ADD2 \ + 0x1201c4UL +#define PXP2_REG_PSWRQ_BW_ADD28 \ + 0x120228UL +#define PXP2_REG_PSWRQ_BW_ADD3 \ + 0x1201c8UL +#define PXP2_REG_PSWRQ_BW_ADD6 \ + 0x1201d4UL +#define PXP2_REG_PSWRQ_BW_ADD7 \ + 0x1201d8UL +#define PXP2_REG_PSWRQ_BW_ADD8 \ + 0x1201dcUL +#define PXP2_REG_PSWRQ_BW_ADD9 \ + 0x1201e0UL +#define PXP2_REG_PSWRQ_BW_L1 \ + 0x1202b0UL +#define PXP2_REG_PSWRQ_BW_L10 \ + 0x1202d4UL +#define PXP2_REG_PSWRQ_BW_L11 \ + 0x1202d8UL +#define PXP2_REG_PSWRQ_BW_L2 \ + 0x1202b4UL +#define PXP2_REG_PSWRQ_BW_L28 \ + 0x120318UL +#define PXP2_REG_PSWRQ_BW_L3 \ + 0x1202b8UL +#define PXP2_REG_PSWRQ_BW_L6 \ + 0x1202c4UL +#define PXP2_REG_PSWRQ_BW_L7 \ + 0x1202c8UL +#define PXP2_REG_PSWRQ_BW_L8 \ + 0x1202ccUL +#define PXP2_REG_PSWRQ_BW_L9 \ + 0x1202d0UL +#define PXP2_REG_PSWRQ_BW_RD \ + 0x120324UL +#define PXP2_REG_PSWRQ_BW_UB1 \ + 0x120238UL +#define PXP2_REG_PSWRQ_BW_UB10 \ + 0x12025cUL +#define PXP2_REG_PSWRQ_BW_UB11 \ + 0x120260UL +#define PXP2_REG_PSWRQ_BW_UB2 \ + 0x12023cUL +#define PXP2_REG_PSWRQ_BW_UB28 \ + 0x1202a0UL +#define PXP2_REG_PSWRQ_BW_UB3 \ + 0x120240UL +#define PXP2_REG_PSWRQ_BW_UB6 \ + 0x12024cUL +#define PXP2_REG_PSWRQ_BW_UB7 \ + 0x120250UL +#define PXP2_REG_PSWRQ_BW_UB8 \ + 0x120254UL +#define PXP2_REG_PSWRQ_BW_UB9 \ + 0x120258UL +#define PXP2_REG_PSWRQ_BW_WR \ + 0x120328UL +#define PXP2_REG_PSWRQ_CDU0_L2P \ + 0x120000UL +#define PXP2_REG_PSWRQ_QM0_L2P \ + 0x120038UL +#define PXP2_REG_PSWRQ_SRC0_L2P \ + 0x120054UL +#define PXP2_REG_PSWRQ_TM0_L2P \ + 0x12001cUL +#define PXP2_REG_PXP2_INT_MASK_0 \ + 0x120578UL +#define PXP2_REG_PXP2_INT_MASK_1 \ + 0x120614UL +#define PXP2_REG_PXP2_INT_STS_0 \ + 0x12056cUL +#define PXP2_REG_PXP2_INT_STS_1 \ + 0x120608UL +#define PXP2_REG_PXP2_INT_STS_CLR_0 \ + 0x120570UL +#define PXP2_REG_PXP2_PRTY_MASK_0 \ + 0x120588UL +#define PXP2_REG_PXP2_PRTY_MASK_1 \ + 0x120598UL +#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \ + 0x120580UL +#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \ + 0x120590UL +#define PXP2_REG_RD_BLK_CNT \ + 0x120418UL +#define PXP2_REG_RD_CDURD_SWAP_MODE \ + 0x120404UL +#define PXP2_REG_RD_DISABLE_INPUTS \ + 0x120374UL +#define PXP2_REG_RD_INIT_DONE \ + 0x120370UL +#define PXP2_REG_RD_PBF_SWAP_MODE \ + 0x1203f4UL +#define PXP2_REG_RD_PORT_IS_IDLE_0 \ + 0x12041cUL +#define PXP2_REG_RD_PORT_IS_IDLE_1 \ + 0x120420UL +#define PXP2_REG_RD_QM_SWAP_MODE \ + 0x1203f8UL +#define PXP2_REG_RD_SRC_SWAP_MODE \ + 0x120400UL +#define PXP2_REG_RD_SR_CNT \ + 0x120414UL +#define PXP2_REG_RD_START_INIT \ + 0x12036cUL +#define PXP2_REG_RD_TM_SWAP_MODE \ + 0x1203fcUL +#define PXP2_REG_RQ_BW_RD_ADD0 \ + 0x1201bcUL +#define PXP2_REG_RQ_BW_RD_ADD12 \ + 0x1201ecUL +#define PXP2_REG_RQ_BW_RD_ADD13 \ + 0x1201f0UL +#define PXP2_REG_RQ_BW_RD_ADD14 \ + 0x1201f4UL +#define PXP2_REG_RQ_BW_RD_ADD15 \ + 0x1201f8UL +#define PXP2_REG_RQ_BW_RD_ADD16 \ + 0x1201fcUL +#define PXP2_REG_RQ_BW_RD_ADD17 \ + 0x120200UL +#define PXP2_REG_RQ_BW_RD_ADD18 \ + 0x120204UL +#define PXP2_REG_RQ_BW_RD_ADD19 \ + 0x120208UL +#define PXP2_REG_RQ_BW_RD_ADD20 \ + 0x12020cUL +#define PXP2_REG_RQ_BW_RD_ADD22 \ + 0x120210UL +#define PXP2_REG_RQ_BW_RD_ADD23 \ + 0x120214UL +#define PXP2_REG_RQ_BW_RD_ADD24 \ + 0x120218UL +#define PXP2_REG_RQ_BW_RD_ADD25 \ + 0x12021cUL +#define PXP2_REG_RQ_BW_RD_ADD26 \ + 0x120220UL +#define PXP2_REG_RQ_BW_RD_ADD27 \ + 0x120224UL +#define PXP2_REG_RQ_BW_RD_ADD4 \ + 0x1201ccUL +#define PXP2_REG_RQ_BW_RD_ADD5 \ + 0x1201d0UL +#define PXP2_REG_RQ_BW_RD_L0 \ + 0x1202acUL +#define PXP2_REG_RQ_BW_RD_L12 \ + 0x1202dcUL +#define PXP2_REG_RQ_BW_RD_L13 \ + 0x1202e0UL +#define PXP2_REG_RQ_BW_RD_L14 \ + 0x1202e4UL +#define PXP2_REG_RQ_BW_RD_L15 \ + 0x1202e8UL +#define PXP2_REG_RQ_BW_RD_L16 \ + 0x1202ecUL +#define PXP2_REG_RQ_BW_RD_L17 \ + 0x1202f0UL +#define PXP2_REG_RQ_BW_RD_L18 \ + 0x1202f4UL +#define PXP2_REG_RQ_BW_RD_L19 \ + 0x1202f8UL +#define PXP2_REG_RQ_BW_RD_L20 \ + 0x1202fcUL +#define PXP2_REG_RQ_BW_RD_L22 \ + 0x120300UL +#define PXP2_REG_RQ_BW_RD_L23 \ + 0x120304UL +#define PXP2_REG_RQ_BW_RD_L24 \ + 0x120308UL +#define PXP2_REG_RQ_BW_RD_L25 \ + 0x12030cUL +#define PXP2_REG_RQ_BW_RD_L26 \ + 0x120310UL +#define PXP2_REG_RQ_BW_RD_L27 \ + 0x120314UL +#define PXP2_REG_RQ_BW_RD_L4 \ + 0x1202bcUL +#define PXP2_REG_RQ_BW_RD_L5 \ + 0x1202c0UL +#define PXP2_REG_RQ_BW_RD_UBOUND0 \ + 0x120234UL +#define PXP2_REG_RQ_BW_RD_UBOUND12 \ + 0x120264UL +#define PXP2_REG_RQ_BW_RD_UBOUND13 \ + 0x120268UL +#define PXP2_REG_RQ_BW_RD_UBOUND14 \ + 0x12026cUL +#define PXP2_REG_RQ_BW_RD_UBOUND15 \ + 0x120270UL +#define PXP2_REG_RQ_BW_RD_UBOUND16 \ + 0x120274UL +#define PXP2_REG_RQ_BW_RD_UBOUND17 \ + 0x120278UL +#define PXP2_REG_RQ_BW_RD_UBOUND18 \ + 0x12027cUL +#define PXP2_REG_RQ_BW_RD_UBOUND19 \ + 0x120280UL +#define PXP2_REG_RQ_BW_RD_UBOUND20 \ + 0x120284UL +#define PXP2_REG_RQ_BW_RD_UBOUND22 \ + 0x120288UL +#define PXP2_REG_RQ_BW_RD_UBOUND23 \ + 0x12028cUL +#define PXP2_REG_RQ_BW_RD_UBOUND24 \ + 0x120290UL +#define PXP2_REG_RQ_BW_RD_UBOUND25 \ + 0x120294UL +#define PXP2_REG_RQ_BW_RD_UBOUND26 \ + 0x120298UL +#define PXP2_REG_RQ_BW_RD_UBOUND27 \ + 0x12029cUL +#define PXP2_REG_RQ_BW_RD_UBOUND4 \ + 0x120244UL +#define PXP2_REG_RQ_BW_RD_UBOUND5 \ + 0x120248UL +#define PXP2_REG_RQ_BW_WR_ADD29 \ + 0x12022cUL +#define PXP2_REG_RQ_BW_WR_ADD30 \ + 0x120230UL +#define PXP2_REG_RQ_BW_WR_L29 \ + 0x12031cUL +#define PXP2_REG_RQ_BW_WR_L30 \ + 0x120320UL +#define PXP2_REG_RQ_BW_WR_UBOUND29 \ + 0x1202a4UL +#define PXP2_REG_RQ_BW_WR_UBOUND30 \ + 0x1202a8UL +#define PXP2_REG_RQ_CDU_ENDIAN_M \ + 0x1201a0UL +#define PXP2_REG_RQ_CDU_FIRST_ILT \ + 0x12061cUL +#define PXP2_REG_RQ_CDU_LAST_ILT \ + 0x120620UL +#define PXP2_REG_RQ_CDU_P_SIZE \ + 0x120018UL +#define PXP2_REG_RQ_CFG_DONE \ + 0x1201b4UL +#define PXP2_REG_RQ_DBG_ENDIAN_M \ + 0x1201a4UL +#define PXP2_REG_RQ_DISABLE_INPUTS \ + 0x120330UL +#define PXP2_REG_RQ_DRAM_ALIGN \ + 0x1205b0UL +#define PXP2_REG_RQ_DRAM_ALIGN_RD \ + 0x12092cUL +#define PXP2_REG_RQ_DRAM_ALIGN_SEL \ + 0x120930UL +#define PXP2_REG_RQ_HC_ENDIAN_M \ + 0x1201a8UL +#define PXP2_REG_RQ_ONCHIP_AT \ + 0x122000UL +#define PXP2_REG_RQ_ONCHIP_AT_B0 \ + 0x128000UL +#define PXP2_REG_RQ_PDR_LIMIT \ + 0x12033cUL +#define PXP2_REG_RQ_QM_ENDIAN_M \ + 0x120194UL +#define PXP2_REG_RQ_QM_FIRST_ILT \ + 0x120634UL +#define PXP2_REG_RQ_QM_LAST_ILT \ + 0x120638UL +#define PXP2_REG_RQ_QM_P_SIZE \ + 0x120050UL +#define PXP2_REG_RQ_RBC_DONE \ + 0x1201b0UL +#define PXP2_REG_RQ_RD_MBS0 \ + 0x120160UL +#define PXP2_REG_RQ_RD_MBS1 \ + 0x120168UL +#define PXP2_REG_RQ_SRC_ENDIAN_M \ + 0x12019cUL +#define PXP2_REG_RQ_SRC_FIRST_ILT \ + 0x12063cUL +#define PXP2_REG_RQ_SRC_LAST_ILT \ + 0x120640UL +#define PXP2_REG_RQ_SRC_P_SIZE \ + 0x12006cUL +#define PXP2_REG_RQ_TM_ENDIAN_M \ + 0x120198UL +#define PXP2_REG_RQ_TM_FIRST_ILT \ + 0x120644UL +#define PXP2_REG_RQ_TM_LAST_ILT \ + 0x120648UL +#define PXP2_REG_RQ_TM_P_SIZE \ + 0x120034UL +#define PXP2_REG_RQ_WR_MBS0 \ + 0x12015cUL +#define PXP2_REG_RQ_WR_MBS1 \ + 0x120164UL +#define PXP2_REG_WR_CDU_MPS \ + 0x1205f0UL +#define PXP2_REG_WR_CSDM_MPS \ + 0x1205d0UL +#define PXP2_REG_WR_DBG_MPS \ + 0x1205e8UL +#define PXP2_REG_WR_DMAE_MPS \ + 0x1205ecUL +#define PXP2_REG_WR_HC_MPS \ + 0x1205c8UL +#define PXP2_REG_WR_QM_MPS \ + 0x1205dcUL +#define PXP2_REG_WR_SRC_MPS \ + 0x1205e4UL +#define PXP2_REG_WR_TM_MPS \ + 0x1205e0UL +#define PXP2_REG_WR_TSDM_MPS \ + 0x1205d4UL +#define PXP2_REG_WR_USDMDP_TH \ + 0x120348UL +#define PXP2_REG_WR_USDM_MPS \ + 0x1205ccUL +#define PXP2_REG_WR_XSDM_MPS \ + 0x1205d8UL +#define PXP_REG_HST_DISCARD_DOORBELLS \ + 0x1030a4UL +#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \ + 0x1030a8UL +#define PXP_REG_HST_ZONE_PERMISSION_TABLE \ + 0x103400UL +#define PXP_REG_PXP_INT_MASK_0 \ + 0x103074UL +#define PXP_REG_PXP_INT_MASK_1 \ + 0x103084UL +#define PXP_REG_PXP_INT_STS_CLR_0 \ + 0x10306cUL +#define PXP_REG_PXP_INT_STS_CLR_1 \ + 0x10307cUL +#define PXP_REG_PXP_PRTY_MASK \ + 0x103094UL +#define PXP_REG_PXP_PRTY_STS_CLR \ + 0x10308cUL +#define QM_REG_BASEADDR \ + 0x168900UL +#define QM_REG_BASEADDR_EXT_A \ + 0x16e100UL +#define QM_REG_BYTECRDCMDQ_0 \ + 0x16e6e8UL +#define QM_REG_CONNNUM_0 \ + 0x168020UL +#define QM_REG_PF_EN \ + 0x16e70cUL +#define QM_REG_PF_USG_CNT_0 \ + 0x16e040UL +#define QM_REG_PTRTBL \ + 0x168a00UL +#define QM_REG_PTRTBL_EXT_A \ + 0x16e200UL +#define QM_REG_QM_INT_MASK \ + 0x168444UL +#define QM_REG_QM_PRTY_MASK \ + 0x168454UL +#define QM_REG_QM_PRTY_STS_CLR \ + 0x16844cUL +#define QM_REG_QVOQIDX_0 \ + 0x1680f4UL +#define QM_REG_SOFT_RESET \ + 0x168428UL +#define QM_REG_VOQQMASK_0_LSB \ + 0x168240UL +#define SEM_FAST_REG_PARITY_RST \ + 0x18840UL +#define SRC_REG_COUNTFREE0 \ + 0x40500UL +#define SRC_REG_FIRSTFREE0 \ + 0x40510UL +#define SRC_REG_KEYSEARCH_0 \ + 0x40458UL +#define SRC_REG_KEYSEARCH_1 \ + 0x4045cUL +#define SRC_REG_KEYSEARCH_2 \ + 0x40460UL +#define SRC_REG_KEYSEARCH_3 \ + 0x40464UL +#define SRC_REG_KEYSEARCH_4 \ + 0x40468UL +#define SRC_REG_KEYSEARCH_5 \ + 0x4046cUL +#define SRC_REG_KEYSEARCH_6 \ + 0x40470UL +#define SRC_REG_KEYSEARCH_7 \ + 0x40474UL +#define SRC_REG_KEYSEARCH_8 \ + 0x40478UL +#define SRC_REG_KEYSEARCH_9 \ + 0x4047cUL +#define SRC_REG_LASTFREE0 \ + 0x40530UL +#define SRC_REG_NUMBER_HASH_BITS0 \ + 0x40400UL +#define SRC_REG_SOFT_RST \ + 0x4049cUL +#define SRC_REG_SRC_PRTY_MASK \ + 0x404c8UL +#define SRC_REG_SRC_PRTY_STS_CLR \ + 0x404c0UL +#define TCM_REG_PRS_IFEN \ + 0x50020UL +#define TCM_REG_TCM_INT_MASK \ + 0x501dcUL +#define TCM_REG_TCM_PRTY_MASK \ + 0x501ecUL +#define TCM_REG_TCM_PRTY_STS_CLR \ + 0x501e4UL +#define TM_REG_EN_LINEAR0_TIMER \ + 0x164014UL +#define TM_REG_LIN0_MAX_ACTIVE_CID \ + 0x164048UL +#define TM_REG_LIN0_NUM_SCANS \ + 0x1640a0UL +#define TM_REG_LIN0_SCAN_ON \ + 0x1640d0UL +#define TM_REG_LIN0_SCAN_TIME \ + 0x16403cUL +#define TM_REG_LIN0_VNIC_UC \ + 0x164128UL +#define TM_REG_TM_INT_MASK \ + 0x1640fcUL +#define TM_REG_TM_PRTY_MASK \ + 0x16410cUL +#define TM_REG_TM_PRTY_STS_CLR \ + 0x164104UL +#define TSDM_REG_ENABLE_IN1 \ + 0x42238UL +#define TSDM_REG_TSDM_INT_MASK_0 \ + 0x4229cUL +#define TSDM_REG_TSDM_INT_MASK_1 \ + 0x422acUL +#define TSDM_REG_TSDM_PRTY_MASK \ + 0x422bcUL +#define TSDM_REG_TSDM_PRTY_STS_CLR \ + 0x422b4UL +#define TSEM_REG_FAST_MEMORY \ + 0x1a0000UL +#define TSEM_REG_INT_TABLE \ + 0x180400UL +#define TSEM_REG_PASSIVE_BUFFER \ + 0x181000UL +#define TSEM_REG_PRAM \ + 0x1c0000UL +#define TSEM_REG_TSEM_INT_MASK_0 \ + 0x180100UL +#define TSEM_REG_TSEM_INT_MASK_1 \ + 0x180110UL +#define TSEM_REG_TSEM_PRTY_MASK_0 \ + 0x180120UL +#define TSEM_REG_TSEM_PRTY_MASK_1 \ + 0x180130UL +#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \ + 0x180118UL +#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \ + 0x180128UL +#define TSEM_REG_VFPF_ERR_NUM \ + 0x180380UL +#define UCM_REG_UCM_INT_MASK \ + 0xe01d4UL +#define UCM_REG_UCM_PRTY_MASK \ + 0xe01e4UL +#define UCM_REG_UCM_PRTY_STS_CLR \ + 0xe01dcUL +#define UMAC_COMMAND_CONFIG_REG_HD_ENA \ + (0x1<<10) +#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \ + (0x1<<28) +#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \ + (0x1<<15) +#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \ + (0x1<<24) +#define UMAC_COMMAND_CONFIG_REG_PAD_EN \ + (0x1<<5) +#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \ + (0x1<<8) +#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \ + (0x1<<4) +#define UMAC_COMMAND_CONFIG_REG_RX_ENA \ + (0x1<<1) +#define UMAC_COMMAND_CONFIG_REG_SW_RESET \ + (0x1<<13) +#define UMAC_COMMAND_CONFIG_REG_TX_ENA \ + (0x1<<0) +#define UMAC_REG_COMMAND_CONFIG \ + 0x8UL +#define UMAC_REG_EEE_WAKE_TIMER \ + 0x6cUL +#define UMAC_REG_MAC_ADDR0 \ + 0xcUL +#define UMAC_REG_MAC_ADDR1 \ + 0x10UL +#define UMAC_REG_MAXFR \ + 0x14UL +#define UMAC_REG_UMAC_EEE_CTRL \ + 0x64UL +#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \ + (0x1<<3) +#define USDM_REG_USDM_INT_MASK_0 \ + 0xc42a0UL +#define USDM_REG_USDM_INT_MASK_1 \ + 0xc42b0UL +#define USDM_REG_USDM_PRTY_MASK \ + 0xc42c0UL +#define USDM_REG_USDM_PRTY_STS_CLR \ + 0xc42b8UL +#define USEM_REG_FAST_MEMORY \ + 0x320000UL +#define USEM_REG_INT_TABLE \ + 0x300400UL +#define USEM_REG_PASSIVE_BUFFER \ + 0x302000UL +#define USEM_REG_PRAM \ + 0x340000UL +#define USEM_REG_USEM_INT_MASK_0 \ + 0x300110UL +#define USEM_REG_USEM_INT_MASK_1 \ + 0x300120UL +#define USEM_REG_USEM_PRTY_MASK_0 \ + 0x300130UL +#define USEM_REG_USEM_PRTY_MASK_1 \ + 0x300140UL +#define USEM_REG_USEM_PRTY_STS_CLR_0 \ + 0x300128UL +#define USEM_REG_USEM_PRTY_STS_CLR_1 \ + 0x300138UL +#define USEM_REG_VFPF_ERR_NUM \ + 0x300380UL +#define VFC_MEMORIES_RST_REG_CAM_RST \ + (0x1<<0) +#define VFC_MEMORIES_RST_REG_RAM_RST \ + (0x1<<1) +#define VFC_REG_MEMORIES_RST \ + 0x1943cUL +#define XCM_REG_XCM_INT_MASK \ + 0x202b4UL +#define XCM_REG_XCM_PRTY_MASK \ + 0x202c4UL +#define XCM_REG_XCM_PRTY_STS_CLR \ + 0x202bcUL +#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \ + (0x1<<0) +#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \ + (0x1<<1) +#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \ + (0x1<<2) +#define XMAC_CTRL_REG_RX_EN \ + (0x1<<1) +#define XMAC_CTRL_REG_SOFT_RESET \ + (0x1<<6) +#define XMAC_CTRL_REG_TX_EN \ + (0x1<<0) +#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \ + (0x1<<7) +#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \ + (0x1<<18) +#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \ + (0x1<<17) +#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \ + (0x1<<1) +#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \ + (0x1<<0) +#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \ + (0x1<<3) +#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \ + (0x1<<4) +#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \ + (0x1<<5) +#define XMAC_REG_CLEAR_RX_LSS_STATUS \ + 0x60UL +#define XMAC_REG_CTRL \ + 0UL +#define XMAC_REG_CTRL_SA_HI \ + 0x2cUL +#define XMAC_REG_CTRL_SA_LO \ + 0x28UL +#define XMAC_REG_EEE_CTRL \ + 0xd8UL +#define XMAC_REG_EEE_TIMERS_HI \ + 0xe4UL +#define XMAC_REG_PAUSE_CTRL \ + 0x68UL +#define XMAC_REG_PFC_CTRL \ + 0x70UL +#define XMAC_REG_PFC_CTRL_HI \ + 0x74UL +#define XMAC_REG_RX_LSS_CTRL \ + 0x50UL +#define XMAC_REG_RX_LSS_STATUS \ + 0x58UL +#define XMAC_REG_RX_MAX_SIZE \ + 0x40UL +#define XMAC_REG_TX_CTRL \ + 0x20UL +#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \ + (0x1<<0) +#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \ + (0x1<<1) +#define XSDM_REG_OPERATION_GEN \ + 0x1664c4UL +#define XSDM_REG_XSDM_INT_MASK_0 \ + 0x16629cUL +#define XSDM_REG_XSDM_INT_MASK_1 \ + 0x1662acUL +#define XSDM_REG_XSDM_PRTY_MASK \ + 0x1662bcUL +#define XSDM_REG_XSDM_PRTY_STS_CLR \ + 0x1662b4UL +#define XSEM_REG_FAST_MEMORY \ + 0x2a0000UL +#define XSEM_REG_INT_TABLE \ + 0x280400UL +#define XSEM_REG_PASSIVE_BUFFER \ + 0x282000UL +#define XSEM_REG_PRAM \ + 0x2c0000UL +#define XSEM_REG_VFPF_ERR_NUM \ + 0x280380UL +#define XSEM_REG_XSEM_INT_MASK_0 \ + 0x280110UL +#define XSEM_REG_XSEM_INT_MASK_1 \ + 0x280120UL +#define XSEM_REG_XSEM_PRTY_MASK_0 \ + 0x280130UL +#define XSEM_REG_XSEM_PRTY_MASK_1 \ + 0x280140UL +#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \ + 0x280128UL +#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \ + 0x280138UL +#define MCPR_ACCESS_LOCK_LOCK (1L<<31) +#define MCPR_IMC_COMMAND_ENABLE (1L<<31) +#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 +#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 +#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 +#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) +#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) +#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) +#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) +#define MCPR_NVM_COMMAND_DOIT (1L<<4) +#define MCPR_NVM_COMMAND_DONE (1L<<3) +#define MCPR_NVM_COMMAND_FIRST (1L<<7) +#define MCPR_NVM_COMMAND_LAST (1L<<8) +#define MCPR_NVM_COMMAND_WR (1L<<5) +#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) +#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) +#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) + + +#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) +#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) +#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) +#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) +#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) +#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) +#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) +#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) +#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) +#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) +#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) +#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) +#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) +#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) +#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) +#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) +#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) +#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) +#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) +#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) +#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) +#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) +#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) +#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) +#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) +#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) +#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) +#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) +#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) +#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) +#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) + + +#define EMAC_LED_1000MB_OVERRIDE (1L<<1) +#define EMAC_LED_100MB_OVERRIDE (1L<<2) +#define EMAC_LED_10MB_OVERRIDE (1L<<3) +#define EMAC_LED_OVERRIDE (1L<<0) +#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) +#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) +#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) +#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) +#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) +#define EMAC_MDIO_COMM_DATA (0xffffL<<0) +#define EMAC_MDIO_COMM_START_BUSY (1L<<29) +#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) +#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) +#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) +#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 +#define EMAC_MDIO_STATUS_10MB (1L<<1) +#define EMAC_MODE_25G_MODE (1L<<5) +#define EMAC_MODE_HALF_DUPLEX (1L<<1) +#define EMAC_MODE_PORT_GMII (2L<<2) +#define EMAC_MODE_PORT_MII (1L<<2) +#define EMAC_MODE_PORT_MII_10M (3L<<2) +#define EMAC_MODE_RESET (1L<<0) +#define EMAC_REG_EMAC_LED 0xc +#define EMAC_REG_EMAC_MAC_MATCH 0x10 +#define EMAC_REG_EMAC_MDIO_COMM 0xac +#define EMAC_REG_EMAC_MDIO_MODE 0xb4 +#define EMAC_REG_EMAC_MDIO_STATUS 0xb0 +#define EMAC_REG_EMAC_MODE 0x0 +#define EMAC_REG_EMAC_RX_MODE 0xc8 +#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c +#define EMAC_REG_EMAC_RX_STAT_AC 0x180 +#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 +#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 +#define EMAC_REG_EMAC_TX_MODE 0xbc +#define EMAC_REG_EMAC_TX_STAT_AC 0x280 +#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 +#define EMAC_REG_RX_PFC_MODE 0x320 +#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) +#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) +#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) +#define EMAC_REG_RX_PFC_PARAM 0x324 +#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 +#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 +#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 +#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) +#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 +#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) +#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c +#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) +#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 +#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) +#define EMAC_RX_MODE_FLOW_EN (1L<<2) +#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) +#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) +#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) +#define EMAC_RX_MODE_RESET (1L<<0) +#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) +#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) +#define EMAC_TX_MODE_FLOW_EN (1L<<4) +#define EMAC_TX_MODE_RESET (1L<<0) + + +#define MISC_REGISTERS_GPIO_0 0 +#define MISC_REGISTERS_GPIO_1 1 +#define MISC_REGISTERS_GPIO_2 2 +#define MISC_REGISTERS_GPIO_3 3 +#define MISC_REGISTERS_GPIO_CLR_POS 16 +#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) +#define MISC_REGISTERS_GPIO_FLOAT_POS 24 +#define MISC_REGISTERS_GPIO_HIGH 1 +#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 +#define MISC_REGISTERS_GPIO_INT_CLR_POS 24 +#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 +#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 +#define MISC_REGISTERS_GPIO_INT_SET_POS 16 +#define MISC_REGISTERS_GPIO_LOW 0 +#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 +#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 +#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 +#define MISC_REGISTERS_GPIO_SET_POS 8 +#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 +#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0) +#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \ + (0x1<<19) +#define MISC_REGISTERS_RESET_REG_1_RST_HC \ + (0x1<<29) +#define MISC_REGISTERS_RESET_REG_1_RST_PXP \ + (0x1<<26) +#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \ + (0x1<<27) +#define MISC_REGISTERS_RESET_REG_1_RST_QM \ + (0x1<<17) +#define MISC_REGISTERS_RESET_REG_1_SET 0x584 +#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 +#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \ + (0x1<<24) +#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \ + (0x1<<25) +#define MISC_REGISTERS_RESET_REG_2_PGLC \ + (0x1<<19) +#define MISC_REGISTERS_RESET_REG_2_RST_ATC \ + (0x1<<17) +#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) +#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) +#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) +#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \ + (0x1<<14) +#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) +#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \ + (0x1<<15) +#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) +#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) +#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) +#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) +#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) +#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \ + (0x1<<11) +#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \ + (0x1<<13) +#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \ + (0x1<<16) +#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) +#define MISC_REGISTERS_RESET_REG_2_SET 0x594 +#define MISC_REGISTERS_RESET_REG_2_UMAC0 \ + (0x1<<20) +#define MISC_REGISTERS_RESET_REG_2_UMAC1 \ + (0x1<<21) +#define MISC_REGISTERS_RESET_REG_2_XMAC \ + (0x1<<22) +#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \ + (0x1<<23) +#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) +#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) +#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 +#define MISC_SPIO_CLR_POS 16 +#define MISC_SPIO_FLOAT (0xffL<<24) +#define MISC_SPIO_FLOAT_POS 24 +#define MISC_SPIO_INPUT_HI_Z 2 +#define MISC_SPIO_INT_OLD_SET_POS 16 +#define MISC_SPIO_OUTPUT_HIGH 1 +#define MISC_SPIO_OUTPUT_LOW 0 +#define MISC_SPIO_SET_POS 8 +#define MISC_SPIO_SPIO4 0x10 +#define MISC_SPIO_SPIO5 0x20 +#define HW_LOCK_MAX_RESOURCE_VALUE 31 +#define HW_LOCK_RESOURCE_DRV_FLAGS 10 +#define HW_LOCK_RESOURCE_GPIO 1 +#define HW_LOCK_RESOURCE_NVRAM 12 +#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 +#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 +#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 +#define HW_LOCK_RESOURCE_RECOVERY_REG 11 +#define HW_LOCK_RESOURCE_RESET 5 +#define HW_LOCK_RESOURCE_SPIO 2 + + +#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) +#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) +#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19) +#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) +#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) +#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) +#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) +#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) +#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) +#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) +#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) +#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) +#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) +#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) +#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) +#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) +#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) +#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) +#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) +#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) +#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) +#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) +#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31) +#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) +#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) +#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) +#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) +#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) +#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) +#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31) +#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) +#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) +#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) +#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) +#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) +#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) +#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) +#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) +#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) +#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) +#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) +#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) +#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) +#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) +#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) +#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) +#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) +#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) +#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) +#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) +#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) +#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) +#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) +#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) +#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) +#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) +#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) +#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) +#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) +#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) +#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) +#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) +#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) +#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) +#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) +#define HW_PRTY_ASSERT_SET_0 \ +(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) +#define HW_PRTY_ASSERT_SET_1 \ +(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) +#define HW_PRTY_ASSERT_SET_2 \ +(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) +#define HW_PRTY_ASSERT_SET_3 \ +(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ + AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) +#define HW_PRTY_ASSERT_SET_4 \ +(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\ + AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) +#define HW_INTERRUT_ASSERT_SET_0 \ +(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) +#define HW_INTERRUT_ASSERT_SET_1 \ +(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) +#define HW_INTERRUT_ASSERT_SET_2 \ +(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ + AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) + + +#define RESERVED_GENERAL_ATTENTION_BIT_0 0 + +#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 +#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 + +#define RESERVED_GENERAL_ATTENTION_BIT_6 6 +#define RESERVED_GENERAL_ATTENTION_BIT_7 7 +#define RESERVED_GENERAL_ATTENTION_BIT_8 8 +#define RESERVED_GENERAL_ATTENTION_BIT_9 9 +#define RESERVED_GENERAL_ATTENTION_BIT_10 10 +#define RESERVED_GENERAL_ATTENTION_BIT_11 11 +#define RESERVED_GENERAL_ATTENTION_BIT_12 12 +#define RESERVED_GENERAL_ATTENTION_BIT_13 13 +#define RESERVED_GENERAL_ATTENTION_BIT_14 14 +#define RESERVED_GENERAL_ATTENTION_BIT_15 15 +#define RESERVED_GENERAL_ATTENTION_BIT_16 16 +#define RESERVED_GENERAL_ATTENTION_BIT_17 17 +#define RESERVED_GENERAL_ATTENTION_BIT_18 18 +#define RESERVED_GENERAL_ATTENTION_BIT_19 19 +#define RESERVED_GENERAL_ATTENTION_BIT_20 20 +#define RESERVED_GENERAL_ATTENTION_BIT_21 21 + +/* storm asserts attention bits */ +#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 +#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 +#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 +#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 + +/* mcp error attention bit */ +#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 + +/*E1H NIG status sync attention mapped to group 4-7*/ +#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 +#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 +#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 +#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 +#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 +#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 +#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 +#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 + + /* Used For Error Recovery: changing this will require more \ + changes in code that assume + * error recovery uses general attn bit20 ! */ +#define ERROR_RECOVERY_ATTENTION_BIT \ + RESERVED_GENERAL_ATTENTION_BIT_20 +#define RESERVED_ATTENTION_BIT \ + RESERVED_GENERAL_ATTENTION_BIT_21 + +#define LATCHED_ATTN_RBCR 23 +#define LATCHED_ATTN_RBCT 24 +#define LATCHED_ATTN_RBCN 25 +#define LATCHED_ATTN_RBCU 26 +#define LATCHED_ATTN_RBCP 27 +#define LATCHED_ATTN_TIMEOUT_GRC 28 +#define LATCHED_ATTN_RSVD_GRC 29 +#define LATCHED_ATTN_ROM_PARITY_MCP 30 +#define LATCHED_ATTN_UM_RX_PARITY_MCP 31 +#define LATCHED_ATTN_UM_TX_PARITY_MCP 32 +#define LATCHED_ATTN_SCPAD_PARITY_MCP 33 + +#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) +#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32)) + + +/* + * This file defines GRC base address for every block. + * This file is included by chipsim, asm microcode and cpp microcode. + * These values are used in Design.xml on regBase attribute + * Use the base with the generated offsets of specific registers. + */ + +#define GRCBASE_PXPCS 0x000000 +#define GRCBASE_PCICONFIG 0x002000 +#define GRCBASE_PCIREG 0x002400 +#define GRCBASE_EMAC0 0x008000 +#define GRCBASE_EMAC1 0x008400 +#define GRCBASE_DBU 0x008800 +#define GRCBASE_PGLUE_B 0x009000 +#define GRCBASE_MISC 0x00A000 +#define GRCBASE_DBG 0x00C000 +#define GRCBASE_NIG 0x010000 +#define GRCBASE_XCM 0x020000 +#define GRCBASE_PRS 0x040000 +#define GRCBASE_SRCH 0x040400 +#define GRCBASE_TSDM 0x042000 +#define GRCBASE_TCM 0x050000 +#define GRCBASE_BRB1 0x060000 +#define GRCBASE_MCP 0x080000 +#define GRCBASE_UPB 0x0C1000 +#define GRCBASE_CSDM 0x0C2000 +#define GRCBASE_USDM 0x0C4000 +#define GRCBASE_CCM 0x0D0000 +#define GRCBASE_UCM 0x0E0000 +#define GRCBASE_CDU 0x101000 +#define GRCBASE_DMAE 0x102000 +#define GRCBASE_PXP 0x103000 +#define GRCBASE_CFC 0x104000 +#define GRCBASE_HC 0x108000 +#define GRCBASE_ATC 0x110000 +#define GRCBASE_PXP2 0x120000 +#define GRCBASE_IGU 0x130000 +#define GRCBASE_PBF 0x140000 +#define GRCBASE_UMAC0 0x160000 +#define GRCBASE_UMAC1 0x160400 +#define GRCBASE_XPB 0x161000 +#define GRCBASE_MSTAT0 0x162000 +#define GRCBASE_MSTAT1 0x162800 +#define GRCBASE_XMAC0 0x163000 +#define GRCBASE_XMAC1 0x163800 +#define GRCBASE_TIMERS 0x164000 +#define GRCBASE_XSDM 0x166000 +#define GRCBASE_QM 0x168000 +#define GRCBASE_QM_4PORT 0x168000 +#define GRCBASE_DQ 0x170000 +#define GRCBASE_TSEM 0x180000 +#define GRCBASE_CSEM 0x200000 +#define GRCBASE_XSEM 0x280000 +#define GRCBASE_XSEM_4PORT 0x280000 +#define GRCBASE_USEM 0x300000 +#define GRCBASE_MCP_A 0x380000 +#define GRCBASE_MISC_AEU GRCBASE_MISC +#define GRCBASE_Tstorm GRCBASE_TSEM +#define GRCBASE_Cstorm GRCBASE_CSEM +#define GRCBASE_Xstorm GRCBASE_XSEM +#define GRCBASE_Ustorm GRCBASE_USEM + + +/* offset of configuration space in the pci core register */ +#define PCICFG_OFFSET 0x2000 +#define PCICFG_VENDOR_ID_OFFSET 0x00 +#define PCICFG_DEVICE_ID_OFFSET 0x02 +#define PCICFG_COMMAND_OFFSET 0x04 +#define PCICFG_COMMAND_IO_SPACE (1<<0) +#define PCICFG_COMMAND_MEM_SPACE (1<<1) +#define PCICFG_COMMAND_BUS_MASTER (1<<2) +#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) +#define PCICFG_COMMAND_MWI_CYCLES (1<<4) +#define PCICFG_COMMAND_VGA_SNOOP (1<<5) +#define PCICFG_COMMAND_PERR_ENA (1<<6) +#define PCICFG_COMMAND_STEPPING (1<<7) +#define PCICFG_COMMAND_SERR_ENA (1<<8) +#define PCICFG_COMMAND_FAST_B2B (1<<9) +#define PCICFG_COMMAND_INT_DISABLE (1<<10) +#define PCICFG_COMMAND_RESERVED (0x1f<<11) +#define PCICFG_STATUS_OFFSET 0x06 +#define PCICFG_REVISION_ID_OFFSET 0x08 +#define PCICFG_REVESION_ID_MASK 0xff +#define PCICFG_REVESION_ID_ERROR_VAL 0xff +#define PCICFG_CACHE_LINE_SIZE 0x0c +#define PCICFG_LATENCY_TIMER 0x0d +#define PCICFG_HEADER_TYPE 0x0e +#define PCICFG_HEADER_TYPE_NORMAL 0 +#define PCICFG_HEADER_TYPE_BRIDGE 1 +#define PCICFG_HEADER_TYPE_CARDBUS 2 +#define PCICFG_BAR_1_LOW 0x10 +#define PCICFG_BAR_1_HIGH 0x14 +#define PCICFG_BAR_2_LOW 0x18 +#define PCICFG_BAR_2_HIGH 0x1c +#define PCICFG_BAR_3_LOW 0x20 +#define PCICFG_BAR_3_HIGH 0x24 +#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c +#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e +#define PCICFG_INT_LINE 0x3c +#define PCICFG_INT_PIN 0x3d +#define PCICFG_PM_CAPABILITY 0x48 +#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) +#define PCICFG_PM_CAPABILITY_CLOCK (1<<19) +#define PCICFG_PM_CAPABILITY_RESERVED (1<<20) +#define PCICFG_PM_CAPABILITY_DSI (1<<21) +#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) +#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) +#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) +#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) +#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) +#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) +#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) +#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) +#define PCICFG_PM_CSR_OFFSET 0x4c +#define PCICFG_PM_CSR_STATE (0x3<<0) +#define PCICFG_PM_CSR_PME_ENABLE (1<<8) +#define PCICFG_PM_CSR_PME_STATUS (1<<15) +#define PCICFG_VPD_FLAG_ADDR_OFFSET 0x50 +#define PCICFG_VPD_DATA_OFFSET 0x54 +#define PCICFG_MSI_CAP_ID_OFFSET 0x58 +#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) +#define PCICFG_MSI_CONTROL_MCAP (0x7<<17) +#define PCICFG_MSI_CONTROL_MENA (0x7<<20) +#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) +#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) +#define PCICFG_MSI_ADDR_LOW_OFFSET 0x5c +#define PCICFG_MSI_ADDR_HIGH_OFFSET 0x60 +#define PCICFG_MSI_DATA_OFFSET 0x64 +#define PCICFG_GRC_ADDRESS 0x78 +#define PCICFG_GRC_DATA 0x80 +#define PCICFG_ME_REGISTER 0x98 +#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 +#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) +#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) +#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) +#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) + +#define PCICFG_DEVICE_CONTROL 0xb4 +#define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) +#define PCICFG_DEVICE_STATUS 0xb6 +#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) +#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) +#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) +#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) +#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) +#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) +#define PCICFG_LINK_CONTROL 0xbc + + +/* config_2 offset */ +#define GRC_CONFIG_2_SIZE_REG 0x408 +#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) +#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) +#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) +#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) +#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) +#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) +#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) +#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) +#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) +#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) +#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) + +/* config_3 offset */ +#define GRC_CONFIG_3_SIZE_REG 0x40c +#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) +#define PCI_CONFIG_3_FORCE_PME (1L<<24) +#define PCI_CONFIG_3_PME_STATUS (1L<<25) +#define PCI_CONFIG_3_PME_ENABLE (1L<<26) +#define PCI_CONFIG_3_PM_STATE (0x3L<<27) +#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) +#define PCI_CONFIG_3_PCI_POWER (1L<<31) + +#define GRC_REG_DEVICE_CONTROL 0x4d8 +#define PCIE_SRIOV_DISABLE_IN_PROGRESS \ + (1 << 29) /*When VF Enable is cleared(after it was previously set), + this register will read a value of 1, indicating that all the + VFs that belong to this PF should be flushed. + Software should clear this bit within 1 second of VF Enable + being set by writing a 1 to it, so that VFs are visible to the system again. + WC */ +#define PCIE_FLR_IN_PROGRESS \ + (1 << 27) /*When FLR is initiated, this register will read a \ + value of 1 indicating that the + Function is in FLR state. Func can be brought out of FLR state either by + writing 1 to this register (at least 50 ms after FLR was initiated), + or it can also be cleared automatically after 55 ms if auto_clear bit + in private reg space is set. This bit also exists in VF register space + WC */ + +#define GRC_BAR2_CONFIG 0x4e0 +#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) +#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) +#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) + +#define GRC_BAR3_CONFIG 0x4f4 +#define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) +#define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) +#define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) +#define PCI_CONFIG_2_BAR3_64ENA (1L<<4) + +#define PCI_PM_DATA_A 0x410 +#define PCI_PM_DATA_B 0x414 +#define PCI_ID_VAL1 0x434 +#define PCI_ID_VAL2 0x438 +#define PCI_ID_VAL3 0x43c +#define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) + + +#define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 +#define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf + +#define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C +#define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \ + 0x3F /*This field resides in VF only and does not exist in PF. + This register controls the read value of the MSIX_CONTROL[10:0] register + in the VF configuration space. A value of "00000000011" indicates + a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ + define in version.v */ + +#define GRC_CONFIG_REG_PF_INIT_VF 0x624 +#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \ + 0xf /*First VF_NUM for PF is encoded in this register. + The number of VFs assigned to a PF is assumed to be a multiple of 8. + Software should program these bits based on Total Number of VFs \ + programmed for each PF. + Since registers from 0x000-0x7ff are spilt across functions, each PF will have + the same location for the same 4 bits*/ + +#define PXPCS_TL_CONTROL_5 0x814 +#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ +#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ +#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ +#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ +#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ +#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ +#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ +#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ +#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ +#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ +#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ +#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ +#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ + + +#define PXPCS_TL_FUNC345_STAT 0x854 +#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \ + (1 << 28) /* Unsupported Request Error Status in function4, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \ + (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \ + (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \ + (1 << 25) /* Receiver Overflow Status Status in function 4, if \ + set, generate pcie_err_attn output when this error is seen.. WC \ + */ +#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \ + (1 << 24) /* Unexpected Completion Status Status in function 4, \ + if set, generate pcie_err_attn output when this error is seen. WC \ + */ +#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \ + (1 << 23) /* Receive UR Statusin function 4. If set, generate \ + pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \ + (1 << 22) /* Completer Timeout Status Status in function 4, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \ + (1 << 21) /* Flow Control Protocol Error Status Status in \ + function 4, if set, generate pcie_err_attn output when this error \ + is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \ + (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \ + (1 << 18) /* Unsupported Request Error Status in function3, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \ + (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \ + (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \ + (1 << 15) /* Receiver Overflow Status Status in function 3, if \ + set, generate pcie_err_attn output when this error is seen.. WC \ + */ +#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \ + (1 << 14) /* Unexpected Completion Status Status in function 3, \ + if set, generate pcie_err_attn output when this error is seen. WC \ + */ +#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \ + (1 << 13) /* Receive UR Statusin function 3. If set, generate \ + pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \ + (1 << 12) /* Completer Timeout Status Status in function 3, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \ + (1 << 11) /* Flow Control Protocol Error Status Status in \ + function 3, if set, generate pcie_err_attn output when this error \ + is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \ + (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \ + (1 << 8) /* Unsupported Request Error Status for Function 2, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \ + (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \ + (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \ + (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ + set, generate pcie_err_attn output when this error is seen.. WC \ + */ +#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \ + (1 << 4) /* Unexpected Completion Status Status for Function 2, \ + if set, generate pcie_err_attn output when this error is seen. WC \ + */ +#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \ + (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ + pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \ + (1 << 2) /* Completer Timeout Status Status for Function 2, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \ + (1 << 1) /* Flow Control Protocol Error Status Status for \ + Function 2, if set, generate pcie_err_attn output when this error \ + is seen. WC */ +#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \ + (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ + + +#define PXPCS_TL_FUNC678_STAT 0x85C +#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \ + (1 << 28) /* Unsupported Request Error Status in function7, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \ + (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \ + (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \ + (1 << 25) /* Receiver Overflow Status Status in function 7, if \ + set, generate pcie_err_attn output when this error is seen.. WC \ + */ +#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \ + (1 << 24) /* Unexpected Completion Status Status in function 7, \ + if set, generate pcie_err_attn output when this error is seen. WC \ + */ +#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \ + (1 << 23) /* Receive UR Statusin function 7. If set, generate \ + pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \ + (1 << 22) /* Completer Timeout Status Status in function 7, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \ + (1 << 21) /* Flow Control Protocol Error Status Status in \ + function 7, if set, generate pcie_err_attn output when this error \ + is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \ + (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \ + (1 << 18) /* Unsupported Request Error Status in function6, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \ + (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \ + (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \ + (1 << 15) /* Receiver Overflow Status Status in function 6, if \ + set, generate pcie_err_attn output when this error is seen.. WC \ + */ +#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \ + (1 << 14) /* Unexpected Completion Status Status in function 6, \ + if set, generate pcie_err_attn output when this error is seen. WC \ + */ +#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \ + (1 << 13) /* Receive UR Statusin function 6. If set, generate \ + pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \ + (1 << 12) /* Completer Timeout Status Status in function 6, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \ + (1 << 11) /* Flow Control Protocol Error Status Status in \ + function 6, if set, generate pcie_err_attn output when this error \ + is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \ + (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \ + (1 << 8) /* Unsupported Request Error Status for Function 5, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \ + (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \ + (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \ + (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ + set, generate pcie_err_attn output when this error is seen.. WC \ + */ +#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \ + (1 << 4) /* Unexpected Completion Status Status for Function 5, \ + if set, generate pcie_err_attn output when this error is seen. WC \ + */ +#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \ + (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ + pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \ + (1 << 2) /* Completer Timeout Status Status for Function 5, if \ + set, generate pcie_err_attn output when this error is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \ + (1 << 1) /* Flow Control Protocol Error Status Status for \ + Function 5, if set, generate pcie_err_attn output when this error \ + is seen. WC */ +#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \ + (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ + generate pcie_err_attn output when this error is seen.. WC */ + + +#define BAR_USTRORM_INTMEM 0x400000 +#define BAR_CSTRORM_INTMEM 0x410000 +#define BAR_XSTRORM_INTMEM 0x420000 +#define BAR_TSTRORM_INTMEM 0x430000 + +/* for accessing the IGU in case of status block ACK */ +#define BAR_IGU_INTMEM 0x440000 + +#define BAR_DOORBELL_OFFSET 0x800000 + +#define BAR_ME_REGISTER 0x450000 +#define ME_REG_PF_NUM_SHIFT 0 +#define ME_REG_PF_NUM \ + (7L<> ME_REG_VF_NUM_SHIFT) +#define ME_REG_VF_ERR (0x1<<3) +#define ME_REG_ABS_PF_NUM_SHIFT 16 +#define ME_REG_ABS_PF_NUM \ + (7L< + * David Christensen + * Gary Zambrano + * + * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "bnx2x.h" +#include "ecore_init.h" + +/**** Exe Queue interfaces ****/ + +/** + * ecore_exe_queue_init - init the Exe Queue object + * + * @o: pointer to the object + * @exe_len: length + * @owner: pointer to the owner + * @validate: validate function pointer + * @optimize: optimize function pointer + * @exec: execute function pointer + * @get: get function pointer + */ +static void +ecore_exe_queue_init(struct bnx2x_softc *sc __rte_unused, + struct ecore_exe_queue_obj *o, + int exe_len, + union ecore_qable_obj *owner, + exe_q_validate validate, + exe_q_remove remove, + exe_q_optimize optimize, exe_q_execute exec, exe_q_get get) +{ + ECORE_MEMSET(o, 0, sizeof(*o)); + + ECORE_LIST_INIT(&o->exe_queue); + ECORE_LIST_INIT(&o->pending_comp); + + ECORE_SPIN_LOCK_INIT(&o->lock, sc); + + o->exe_chunk_len = exe_len; + o->owner = owner; + + /* Owner specific callbacks */ + o->validate = validate; + o->remove = remove; + o->optimize = optimize; + o->execute = exec; + o->get = get; + + ECORE_MSG("Setup the execution queue with the chunk length of %d", + exe_len); +} + +static void ecore_exe_queue_free_elem(struct bnx2x_softc *sc __rte_unused, + struct ecore_exeq_elem *elem) +{ + ECORE_MSG("Deleting an exe_queue element"); + ECORE_FREE(sc, elem, sizeof(*elem)); +} + +static inline int ecore_exe_queue_length(struct ecore_exe_queue_obj *o) +{ + struct ecore_exeq_elem *elem; + int cnt = 0; + + ECORE_SPIN_LOCK_BH(&o->lock); + + ECORE_LIST_FOR_EACH_ENTRY(elem, &o->exe_queue, link, + struct ecore_exeq_elem) cnt++; + + ECORE_SPIN_UNLOCK_BH(&o->lock); + + return cnt; +} + +/** + * ecore_exe_queue_add - add a new element to the execution queue + * + * @sc: driver handle + * @o: queue + * @cmd: new command to add + * @restore: true - do not optimize the command + * + * If the element is optimized or is illegal, frees it. + */ +static int ecore_exe_queue_add(struct bnx2x_softc *sc, + struct ecore_exe_queue_obj *o, + struct ecore_exeq_elem *elem, int restore) +{ + int rc; + + ECORE_SPIN_LOCK_BH(&o->lock); + + if (!restore) { + /* Try to cancel this element queue */ + rc = o->optimize(sc, o->owner, elem); + if (rc) + goto free_and_exit; + + /* Check if this request is ok */ + rc = o->validate(sc, o->owner, elem); + if (rc) { + ECORE_MSG("Preamble failed: %d", rc); + goto free_and_exit; + } + } + + /* If so, add it to the execution queue */ + ECORE_LIST_PUSH_TAIL(&elem->link, &o->exe_queue); + + ECORE_SPIN_UNLOCK_BH(&o->lock); + + return ECORE_SUCCESS; + +free_and_exit: + ecore_exe_queue_free_elem(sc, elem); + + ECORE_SPIN_UNLOCK_BH(&o->lock); + + return rc; +} + +static void __ecore_exe_queue_reset_pending(struct bnx2x_softc *sc, struct ecore_exe_queue_obj + *o) +{ + struct ecore_exeq_elem *elem; + + while (!ECORE_LIST_IS_EMPTY(&o->pending_comp)) { + elem = ECORE_LIST_FIRST_ENTRY(&o->pending_comp, + struct ecore_exeq_elem, link); + + ECORE_LIST_REMOVE_ENTRY(&elem->link, &o->pending_comp); + ecore_exe_queue_free_elem(sc, elem); + } +} + +static inline void ecore_exe_queue_reset_pending(struct bnx2x_softc *sc, + struct ecore_exe_queue_obj *o) +{ + ECORE_SPIN_LOCK_BH(&o->lock); + + __ecore_exe_queue_reset_pending(sc, o); + + ECORE_SPIN_UNLOCK_BH(&o->lock); +} + +/** + * ecore_exe_queue_step - execute one execution chunk atomically + * + * @sc: driver handle + * @o: queue + * @ramrod_flags: flags + * + * (Should be called while holding the exe_queue->lock). + */ +static int ecore_exe_queue_step(struct bnx2x_softc *sc, + struct ecore_exe_queue_obj *o, + unsigned long *ramrod_flags) +{ + struct ecore_exeq_elem *elem, spacer; + int cur_len = 0, rc; + + ECORE_MEMSET(&spacer, 0, sizeof(spacer)); + + /* Next step should not be performed until the current is finished, + * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to + * properly clear object internals without sending any command to the FW + * which also implies there won't be any completion to clear the + * 'pending' list. + */ + if (!ECORE_LIST_IS_EMPTY(&o->pending_comp)) { + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { + ECORE_MSG + ("RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list"); + __ecore_exe_queue_reset_pending(sc, o); + } else { + return ECORE_PENDING; + } + } + + /* Run through the pending commands list and create a next + * execution chunk. + */ + while (!ECORE_LIST_IS_EMPTY(&o->exe_queue)) { + elem = ECORE_LIST_FIRST_ENTRY(&o->exe_queue, + struct ecore_exeq_elem, link); + ECORE_DBG_BREAK_IF(!elem->cmd_len); + + if (cur_len + elem->cmd_len <= o->exe_chunk_len) { + cur_len += elem->cmd_len; + /* Prevent from both lists being empty when moving an + * element. This will allow the call of + * ecore_exe_queue_empty() without locking. + */ + ECORE_LIST_PUSH_TAIL(&spacer.link, &o->pending_comp); + mb(); + ECORE_LIST_REMOVE_ENTRY(&elem->link, &o->exe_queue); + ECORE_LIST_PUSH_TAIL(&elem->link, &o->pending_comp); + ECORE_LIST_REMOVE_ENTRY(&spacer.link, &o->pending_comp); + } else + break; + } + + /* Sanity check */ + if (!cur_len) + return ECORE_SUCCESS; + + rc = o->execute(sc, o->owner, &o->pending_comp, ramrod_flags); + if (rc < 0) + /* In case of an error return the commands back to the queue + * and reset the pending_comp. + */ + ECORE_LIST_SPLICE_INIT(&o->pending_comp, &o->exe_queue); + else if (!rc) + /* If zero is returned, means there are no outstanding pending + * completions and we may dismiss the pending list. + */ + __ecore_exe_queue_reset_pending(sc, o); + + return rc; +} + +static inline int ecore_exe_queue_empty(struct ecore_exe_queue_obj *o) +{ + int empty = ECORE_LIST_IS_EMPTY(&o->exe_queue); + + /* Don't reorder!!! */ + mb(); + + return empty && ECORE_LIST_IS_EMPTY(&o->pending_comp); +} + +static struct ecore_exeq_elem *ecore_exe_queue_alloc_elem(struct + bnx2x_softc *sc + __rte_unused) +{ + ECORE_MSG("Allocating a new exe_queue element"); + return ECORE_ZALLOC(sizeof(struct ecore_exeq_elem), GFP_ATOMIC, sc); +} + +/************************ raw_obj functions ***********************************/ +static int ecore_raw_check_pending(struct ecore_raw_obj *o) +{ + /* + * !! converts the value returned by ECORE_TEST_BIT such that it + * is guaranteed not to be truncated regardless of int definition. + * + * Note we cannot simply define the function's return value type + * to match the type returned by ECORE_TEST_BIT, as it varies by + * platform/implementation. + */ + + return ! !ECORE_TEST_BIT(o->state, o->pstate); +} + +static void ecore_raw_clear_pending(struct ecore_raw_obj *o) +{ + ECORE_SMP_MB_BEFORE_CLEAR_BIT(); + ECORE_CLEAR_BIT(o->state, o->pstate); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); +} + +static void ecore_raw_set_pending(struct ecore_raw_obj *o) +{ + ECORE_SMP_MB_BEFORE_CLEAR_BIT(); + ECORE_SET_BIT(o->state, o->pstate); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); +} + +/** + * ecore_state_wait - wait until the given bit(state) is cleared + * + * @sc: device handle + * @state: state which is to be cleared + * @state_p: state buffer + * + */ +static int ecore_state_wait(struct bnx2x_softc *sc, int state, + unsigned long *pstate) +{ + /* can take a while if any port is running */ + int cnt = 5000; + + if (CHIP_REV_IS_EMUL(sc)) + cnt *= 20; + + ECORE_MSG("waiting for state to become %d", state); + + ECORE_MIGHT_SLEEP(); + while (cnt--) { + bnx2x_intr_legacy(sc, 1); + if (!ECORE_TEST_BIT(state, pstate)) { +#ifdef ECORE_STOP_ON_ERROR + ECORE_MSG("exit (cnt %d)", 5000 - cnt); +#endif + return ECORE_SUCCESS; + } + + ECORE_WAIT(sc, delay_us); + + if (sc->panic) + return ECORE_IO; + } + + /* timeout! */ + PMD_DRV_LOG(ERR, "timeout waiting for state %d", state); +#ifdef ECORE_STOP_ON_ERROR + ecore_panic(); +#endif + + return ECORE_TIMEOUT; +} + +static int ecore_raw_wait(struct bnx2x_softc *sc, struct ecore_raw_obj *raw) +{ + return ecore_state_wait(sc, raw->state, raw->pstate); +} + +/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ +/* credit handling callbacks */ +static int ecore_get_cam_offset_mac(struct ecore_vlan_mac_obj *o, int *offset) +{ + struct ecore_credit_pool_obj *mp = o->macs_pool; + + ECORE_DBG_BREAK_IF(!mp); + + return mp->get_entry(mp, offset); +} + +static int ecore_get_credit_mac(struct ecore_vlan_mac_obj *o) +{ + struct ecore_credit_pool_obj *mp = o->macs_pool; + + ECORE_DBG_BREAK_IF(!mp); + + return mp->get(mp, 1); +} + +static int ecore_put_cam_offset_mac(struct ecore_vlan_mac_obj *o, int offset) +{ + struct ecore_credit_pool_obj *mp = o->macs_pool; + + return mp->put_entry(mp, offset); +} + +static int ecore_put_credit_mac(struct ecore_vlan_mac_obj *o) +{ + struct ecore_credit_pool_obj *mp = o->macs_pool; + + return mp->put(mp, 1); +} + +/** + * __ecore_vlan_mac_h_write_trylock - try getting the writer lock on vlan mac + * head list. + * + * @sc: device handle + * @o: vlan_mac object + * + * @details: Non-blocking implementation; should be called under execution + * queue lock. + */ +static int __ecore_vlan_mac_h_write_trylock(struct bnx2x_softc *sc __rte_unused, + struct ecore_vlan_mac_obj *o) +{ + if (o->head_reader) { + ECORE_MSG("vlan_mac_lock writer - There are readers; Busy"); + return ECORE_BUSY; + } + + ECORE_MSG("vlan_mac_lock writer - Taken"); + return ECORE_SUCCESS; +} + +/** + * __ecore_vlan_mac_h_exec_pending - execute step instead of a previous step + * which wasn't able to run due to a taken lock on vlan mac head list. + * + * @sc: device handle + * @o: vlan_mac object + * + * @details Should be called under execution queue lock; notice it might release + * and reclaim it during its run. + */ +static void __ecore_vlan_mac_h_exec_pending(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o) +{ + int rc; + unsigned long ramrod_flags = o->saved_ramrod_flags; + + ECORE_MSG("vlan_mac_lock execute pending command with ramrod flags %lu", + ramrod_flags); + o->head_exe_request = FALSE; + o->saved_ramrod_flags = 0; + rc = ecore_exe_queue_step(sc, &o->exe_queue, &ramrod_flags); + if (rc != ECORE_SUCCESS) { + PMD_DRV_LOG(ERR, + "execution of pending commands failed with rc %d", + rc); +#ifdef ECORE_STOP_ON_ERROR + ecore_panic(); +#endif + } +} + +/** + * __ecore_vlan_mac_h_pend - Pend an execution step which couldn't have been + * called due to vlan mac head list lock being taken. + * + * @sc: device handle + * @o: vlan_mac object + * @ramrod_flags: ramrod flags of missed execution + * + * @details Should be called under execution queue lock. + */ +static void __ecore_vlan_mac_h_pend(struct bnx2x_softc *sc __rte_unused, + struct ecore_vlan_mac_obj *o, + unsigned long ramrod_flags) +{ + o->head_exe_request = TRUE; + o->saved_ramrod_flags = ramrod_flags; + ECORE_MSG("Placing pending execution with ramrod flags %lu", + ramrod_flags); +} + +/** + * __ecore_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock + * + * @sc: device handle + * @o: vlan_mac object + * + * @details Should be called under execution queue lock. Notice if a pending + * execution exists, it would perform it - possibly releasing and + * reclaiming the execution queue lock. + */ +static void __ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o) +{ + /* It's possible a new pending execution was added since this writer + * executed. If so, execute again. [Ad infinitum] + */ + while (o->head_exe_request) { + ECORE_MSG + ("vlan_mac_lock - writer release encountered a pending request"); + __ecore_vlan_mac_h_exec_pending(sc, o); + } +} + +/** + * ecore_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock + * + * @sc: device handle + * @o: vlan_mac object + * + * @details Notice if a pending execution exists, it would perform it - + * possibly releasing and reclaiming the execution queue lock. + */ +void ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o) +{ + ECORE_SPIN_LOCK_BH(&o->exe_queue.lock); + __ecore_vlan_mac_h_write_unlock(sc, o); + ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock); +} + +/** + * __ecore_vlan_mac_h_read_lock - lock the vlan mac head list reader lock + * + * @sc: device handle + * @o: vlan_mac object + * + * @details Should be called under the execution queue lock. May sleep. May + * release and reclaim execution queue lock during its run. + */ +static int __ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc __rte_unused, + struct ecore_vlan_mac_obj *o) +{ + /* If we got here, we're holding lock --> no WRITER exists */ + o->head_reader++; + ECORE_MSG("vlan_mac_lock - locked reader - number %d", o->head_reader); + + return ECORE_SUCCESS; +} + +/** + * ecore_vlan_mac_h_read_lock - lock the vlan mac head list reader lock + * + * @sc: device handle + * @o: vlan_mac object + * + * @details May sleep. Claims and releases execution queue lock during its run. + */ +static int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o) +{ + int rc; + + ECORE_SPIN_LOCK_BH(&o->exe_queue.lock); + rc = __ecore_vlan_mac_h_read_lock(sc, o); + ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock); + + return rc; +} + +/** + * __ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock + * + * @sc: device handle + * @o: vlan_mac object + * + * @details Should be called under execution queue lock. Notice if a pending + * execution exists, it would be performed if this was the last + * reader. possibly releasing and reclaiming the execution queue lock. + */ +static void __ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o) +{ + if (!o->head_reader) { + PMD_DRV_LOG(ERR, + "Need to release vlan mac reader lock, but lock isn't taken"); +#ifdef ECORE_STOP_ON_ERROR + ecore_panic(); +#endif + } else { + o->head_reader--; + PMD_DRV_LOG(INFO, + "vlan_mac_lock - decreased readers to %d", + o->head_reader); + } + + /* It's possible a new pending execution was added, and that this reader + * was last - if so we need to execute the command. + */ + if (!o->head_reader && o->head_exe_request) { + PMD_DRV_LOG(INFO, + "vlan_mac_lock - reader release encountered a pending request"); + + /* Writer release will do the trick */ + __ecore_vlan_mac_h_write_unlock(sc, o); + } +} + +/** + * ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock + * + * @sc: device handle + * @o: vlan_mac object + * + * @details Notice if a pending execution exists, it would be performed if this + * was the last reader. Claims and releases the execution queue lock + * during its run. + */ +void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o) +{ + ECORE_SPIN_LOCK_BH(&o->exe_queue.lock); + __ecore_vlan_mac_h_read_unlock(sc, o); + ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock); +} + +/** + * ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock + * + * @sc: device handle + * @o: vlan_mac object + * @n: number of elements to get + * @base: base address for element placement + * @stride: stride between elements (in bytes) + */ +static int ecore_get_n_elements(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, int n, + uint8_t * base, uint8_t stride, uint8_t size) +{ + struct ecore_vlan_mac_registry_elem *pos; + uint8_t *next = base; + int counter = 0, read_lock; + + ECORE_MSG("get_n_elements - taking vlan_mac_lock (reader)"); + read_lock = ecore_vlan_mac_h_read_lock(sc, o); + if (read_lock != ECORE_SUCCESS) + PMD_DRV_LOG(ERR, + "get_n_elements failed to get vlan mac reader lock; Access without lock"); + + /* traverse list */ + ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link, + struct ecore_vlan_mac_registry_elem) { + if (counter < n) { + ECORE_MEMCPY(next, &pos->u, size); + counter++; + ECORE_MSG + ("copied element number %d to address %p element was:", + counter, next); + next += stride + size; + } + } + + if (read_lock == ECORE_SUCCESS) { + ECORE_MSG("get_n_elements - releasing vlan_mac_lock (reader)"); + ecore_vlan_mac_h_read_unlock(sc, o); + } + + return counter * ETH_ALEN; +} + +/* check_add() callbacks */ +static int ecore_check_mac_add(struct bnx2x_softc *sc __rte_unused, + struct ecore_vlan_mac_obj *o, + union ecore_classification_ramrod_data *data) +{ + struct ecore_vlan_mac_registry_elem *pos; + + ECORE_MSG("Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for ADD command", + data->mac.mac[0], data->mac.mac[1], data->mac.mac[2], + data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]); + + if (!ECORE_IS_VALID_ETHER_ADDR(data->mac.mac)) + return ECORE_INVAL; + + /* Check if a requested MAC already exists */ + ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link, + struct ecore_vlan_mac_registry_elem) + if (!ECORE_MEMCMP(data->mac.mac, pos->u.mac.mac, ETH_ALEN) && + (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) + return ECORE_EXISTS; + + return ECORE_SUCCESS; +} + +/* check_del() callbacks */ +static struct ecore_vlan_mac_registry_elem *ecore_check_mac_del(struct bnx2x_softc + *sc + __rte_unused, + struct + ecore_vlan_mac_obj + *o, union + ecore_classification_ramrod_data + *data) +{ + struct ecore_vlan_mac_registry_elem *pos; + + ECORE_MSG("Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for DEL command", + data->mac.mac[0], data->mac.mac[1], data->mac.mac[2], + data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]); + + ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link, + struct ecore_vlan_mac_registry_elem) + if ((!ECORE_MEMCMP(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) && + (data->mac.is_inner_mac == pos->u.mac.is_inner_mac)) + return pos; + + return NULL; +} + +/* check_move() callback */ +static int ecore_check_move(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *src_o, + struct ecore_vlan_mac_obj *dst_o, + union ecore_classification_ramrod_data *data) +{ + struct ecore_vlan_mac_registry_elem *pos; + int rc; + + /* Check if we can delete the requested configuration from the first + * object. + */ + pos = src_o->check_del(sc, src_o, data); + + /* check if configuration can be added */ + rc = dst_o->check_add(sc, dst_o, data); + + /* If this classification can not be added (is already set) + * or can't be deleted - return an error. + */ + if (rc || !pos) + return FALSE; + + return TRUE; +} + +static int ecore_check_move_always_err(__rte_unused struct bnx2x_softc *sc, + __rte_unused struct ecore_vlan_mac_obj + *src_o, __rte_unused struct ecore_vlan_mac_obj + *dst_o, __rte_unused union + ecore_classification_ramrod_data *data) +{ + return FALSE; +} + +static uint8_t ecore_vlan_mac_get_rx_tx_flag(struct ecore_vlan_mac_obj + *o) +{ + struct ecore_raw_obj *raw = &o->raw; + uint8_t rx_tx_flag = 0; + + if ((raw->obj_type == ECORE_OBJ_TYPE_TX) || + (raw->obj_type == ECORE_OBJ_TYPE_RX_TX)) + rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD; + + if ((raw->obj_type == ECORE_OBJ_TYPE_RX) || + (raw->obj_type == ECORE_OBJ_TYPE_RX_TX)) + rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD; + + return rx_tx_flag; +} + +static void ecore_set_mac_in_nig(struct bnx2x_softc *sc, + int add, unsigned char *dev_addr, int index) +{ + uint32_t wb_data[2]; + uint32_t reg_offset = ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM : + NIG_REG_LLH0_FUNC_MEM; + + if (!ECORE_IS_MF_SI_MODE(sc) && !IS_MF_AFEX(sc)) + return; + + if (index > ECORE_LLH_CAM_MAX_PF_LINE) + return; + + ECORE_MSG("Going to %s LLH configuration at entry %d", + (add ? "ADD" : "DELETE"), index); + + if (add) { + /* LLH_FUNC_MEM is a uint64_t WB register */ + reg_offset += 8 * index; + + wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) | + (dev_addr[4] << 8) | dev_addr[5]); + wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]); + + ECORE_REG_WR_DMAE_LEN(sc, reg_offset, wb_data, 2); + } + + REG_WR(sc, (ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : + NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4 * index, add); +} + +/** + * ecore_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod + * + * @sc: device handle + * @o: queue for which we want to configure this rule + * @add: if TRUE the command is an ADD command, DEL otherwise + * @opcode: CLASSIFY_RULE_OPCODE_XXX + * @hdr: pointer to a header to setup + * + */ +static void ecore_vlan_mac_set_cmd_hdr_e2(struct ecore_vlan_mac_obj *o, + int add, int opcode, + struct eth_classify_cmd_header + *hdr) +{ + struct ecore_raw_obj *raw = &o->raw; + + hdr->client_id = raw->cl_id; + hdr->func_id = raw->func_id; + + /* Rx or/and Tx (internal switching) configuration ? */ + hdr->cmd_general_data |= ecore_vlan_mac_get_rx_tx_flag(o); + + if (add) + hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD; + + hdr->cmd_general_data |= + (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT); +} + +/** + * ecore_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header + * + * @cid: connection id + * @type: ECORE_FILTER_XXX_PENDING + * @hdr: pointer to header to setup + * @rule_cnt: + * + * currently we always configure one rule and echo field to contain a CID and an + * opcode type. + */ +static void ecore_vlan_mac_set_rdata_hdr_e2(uint32_t cid, int type, struct eth_classify_header + *hdr, int rule_cnt) +{ + hdr->echo = ECORE_CPU_TO_LE32((cid & ECORE_SWCID_MASK) | + (type << ECORE_SWCID_SHIFT)); + hdr->rule_cnt = (uint8_t) rule_cnt; +} + +/* hw_config() callbacks */ +static void ecore_set_one_mac_e2(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + struct ecore_exeq_elem *elem, int rule_idx, + __rte_unused int cam_offset) +{ + struct ecore_raw_obj *raw = &o->raw; + struct eth_classify_rules_ramrod_data *data = + (struct eth_classify_rules_ramrod_data *)(raw->rdata); + int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd; + union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx]; + int add = (cmd == ECORE_VLAN_MAC_ADD) ? TRUE : FALSE; + unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags; + uint8_t *mac = elem->cmd_data.vlan_mac.u.mac.mac; + + /* Set LLH CAM entry: currently only iSCSI and ETH macs are + * relevant. In addition, current implementation is tuned for a + * single ETH MAC. + * + * When multiple unicast ETH MACs PF configuration in switch + * independent mode is required (NetQ, multiple netdev MACs, + * etc.), consider better utilisation of 8 per function MAC + * entries in the LLH register. There is also + * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the + * total number of CAM entries to 16. + * + * Currently we won't configure NIG for MACs other than a primary ETH + * MAC and iSCSI L2 MAC. + * + * If this MAC is moving from one Queue to another, no need to change + * NIG configuration. + */ + if (cmd != ECORE_VLAN_MAC_MOVE) { + if (ECORE_TEST_BIT(ECORE_ISCSI_ETH_MAC, vlan_mac_flags)) + ecore_set_mac_in_nig(sc, add, mac, + ECORE_LLH_CAM_ISCSI_ETH_LINE); + else if (ECORE_TEST_BIT(ECORE_ETH_MAC, vlan_mac_flags)) + ecore_set_mac_in_nig(sc, add, mac, + ECORE_LLH_CAM_ETH_LINE); + } + + /* Reset the ramrod data buffer for the first rule */ + if (rule_idx == 0) + ECORE_MEMSET(data, 0, sizeof(*data)); + + /* Setup a command header */ + ecore_vlan_mac_set_cmd_hdr_e2(o, add, CLASSIFY_RULE_OPCODE_MAC, + &rule_entry->mac.header); + + ECORE_MSG("About to %s MAC %02x:%02x:%02x:%02x:%02x:%02x for Queue %d", + (add ? "add" : "delete"), mac[0], mac[1], mac[2], mac[3], + mac[4], mac[5], raw->cl_id); + + /* Set a MAC itself */ + ecore_set_fw_mac_addr(&rule_entry->mac.mac_msb, + &rule_entry->mac.mac_mid, + &rule_entry->mac.mac_lsb, mac); + rule_entry->mac.inner_mac = elem->cmd_data.vlan_mac.u.mac.is_inner_mac; + + /* MOVE: Add a rule that will add this MAC to the target Queue */ + if (cmd == ECORE_VLAN_MAC_MOVE) { + rule_entry++; + rule_cnt++; + + /* Setup ramrod data */ + ecore_vlan_mac_set_cmd_hdr_e2(elem->cmd_data. + vlan_mac.target_obj, TRUE, + CLASSIFY_RULE_OPCODE_MAC, + &rule_entry->mac.header); + + /* Set a MAC itself */ + ecore_set_fw_mac_addr(&rule_entry->mac.mac_msb, + &rule_entry->mac.mac_mid, + &rule_entry->mac.mac_lsb, mac); + rule_entry->mac.inner_mac = + elem->cmd_data.vlan_mac.u.mac.is_inner_mac; + } + + /* Set the ramrod data header */ + ecore_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header, + rule_cnt); +} + +/** + * ecore_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod + * + * @sc: device handle + * @o: queue + * @type: + * @cam_offset: offset in cam memory + * @hdr: pointer to a header to setup + * + * E1H + */ +static void ecore_vlan_mac_set_rdata_hdr_e1x(struct ecore_vlan_mac_obj + *o, int type, int cam_offset, struct mac_configuration_hdr + *hdr) +{ + struct ecore_raw_obj *r = &o->raw; + + hdr->length = 1; + hdr->offset = (uint8_t) cam_offset; + hdr->client_id = ECORE_CPU_TO_LE16(0xff); + hdr->echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) | + (type << ECORE_SWCID_SHIFT)); +} + +static void ecore_vlan_mac_set_cfg_entry_e1x(struct ecore_vlan_mac_obj + *o, int add, int opcode, + uint8_t * mac, + uint16_t vlan_id, struct + mac_configuration_entry + *cfg_entry) +{ + struct ecore_raw_obj *r = &o->raw; + uint32_t cl_bit_vec = (1 << r->cl_id); + + cfg_entry->clients_bit_vector = ECORE_CPU_TO_LE32(cl_bit_vec); + cfg_entry->pf_id = r->func_id; + cfg_entry->vlan_id = ECORE_CPU_TO_LE16(vlan_id); + + if (add) { + ECORE_SET_FLAG(cfg_entry->flags, + MAC_CONFIGURATION_ENTRY_ACTION_TYPE, + T_ETH_MAC_COMMAND_SET); + ECORE_SET_FLAG(cfg_entry->flags, + MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, + opcode); + + /* Set a MAC in a ramrod data */ + ecore_set_fw_mac_addr(&cfg_entry->msb_mac_addr, + &cfg_entry->middle_mac_addr, + &cfg_entry->lsb_mac_addr, mac); + } else + ECORE_SET_FLAG(cfg_entry->flags, + MAC_CONFIGURATION_ENTRY_ACTION_TYPE, + T_ETH_MAC_COMMAND_INVALIDATE); +} + +static void ecore_vlan_mac_set_rdata_e1x(struct bnx2x_softc *sc + __rte_unused, + struct ecore_vlan_mac_obj *o, + int type, int cam_offset, + int add, uint8_t * mac, + uint16_t vlan_id, int opcode, + struct mac_configuration_cmd + *config) +{ + struct mac_configuration_entry *cfg_entry = &config->config_table[0]; + + ecore_vlan_mac_set_rdata_hdr_e1x(o, type, cam_offset, &config->hdr); + ecore_vlan_mac_set_cfg_entry_e1x(o, add, opcode, mac, vlan_id, + cfg_entry); + + ECORE_MSG("%s MAC %02x:%02x:%02x:%02x:%02x:%02x CLID %d CAM offset %d", + (add ? "setting" : "clearing"), + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], + o->raw.cl_id, cam_offset); +} + +/** + * ecore_set_one_mac_e1x - fill a single MAC rule ramrod data + * + * @sc: device handle + * @o: ecore_vlan_mac_obj + * @elem: ecore_exeq_elem + * @rule_idx: rule_idx + * @cam_offset: cam_offset + */ +static void ecore_set_one_mac_e1x(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + struct ecore_exeq_elem *elem, + __rte_unused int rule_idx, int cam_offset) +{ + struct ecore_raw_obj *raw = &o->raw; + struct mac_configuration_cmd *config = + (struct mac_configuration_cmd *)(raw->rdata); + /* 57711 do not support MOVE command, + * so it's either ADD or DEL + */ + int add = (elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ? + TRUE : FALSE; + + /* Reset the ramrod data buffer */ + ECORE_MEMSET(config, 0, sizeof(*config)); + + ecore_vlan_mac_set_rdata_e1x(sc, o, raw->state, + cam_offset, add, + elem->cmd_data.vlan_mac.u.mac.mac, 0, + ETH_VLAN_FILTER_ANY_VLAN, config); +} + +/** + * ecore_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element + * + * @sc: device handle + * @p: command parameters + * @ppos: pointer to the cookie + * + * reconfigure next MAC/VLAN/VLAN-MAC element from the + * previously configured elements list. + * + * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken + * into an account + * + * pointer to the cookie - that should be given back in the next call to make + * function handle the next element. If *ppos is set to NULL it will restart the + * iterator. If returned *ppos == NULL this means that the last element has been + * handled. + * + */ +static int ecore_vlan_mac_restore(struct bnx2x_softc *sc, + struct ecore_vlan_mac_ramrod_params *p, + struct ecore_vlan_mac_registry_elem **ppos) +{ + struct ecore_vlan_mac_registry_elem *pos; + struct ecore_vlan_mac_obj *o = p->vlan_mac_obj; + + /* If list is empty - there is nothing to do here */ + if (ECORE_LIST_IS_EMPTY(&o->head)) { + *ppos = NULL; + return 0; + } + + /* make a step... */ + if (*ppos == NULL) + *ppos = ECORE_LIST_FIRST_ENTRY(&o->head, struct + ecore_vlan_mac_registry_elem, + link); + else + *ppos = ECORE_LIST_NEXT(*ppos, link, + struct ecore_vlan_mac_registry_elem); + + pos = *ppos; + + /* If it's the last step - return NULL */ + if (ECORE_LIST_IS_LAST(&pos->link, &o->head)) + *ppos = NULL; + + /* Prepare a 'user_req' */ + ECORE_MEMCPY(&p->user_req.u, &pos->u, sizeof(pos->u)); + + /* Set the command */ + p->user_req.cmd = ECORE_VLAN_MAC_ADD; + + /* Set vlan_mac_flags */ + p->user_req.vlan_mac_flags = pos->vlan_mac_flags; + + /* Set a restore bit */ + ECORE_SET_BIT_NA(RAMROD_RESTORE, &p->ramrod_flags); + + return ecore_config_vlan_mac(sc, p); +} + +/* ecore_exeq_get_mac/ecore_exeq_get_vlan/ecore_exeq_get_vlan_mac return a + * pointer to an element with a specific criteria and NULL if such an element + * hasn't been found. + */ +static struct ecore_exeq_elem *ecore_exeq_get_mac(struct ecore_exe_queue_obj *o, + struct ecore_exeq_elem *elem) +{ + struct ecore_exeq_elem *pos; + struct ecore_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac; + + /* Check pending for execution commands */ + ECORE_LIST_FOR_EACH_ENTRY(pos, &o->exe_queue, link, + struct ecore_exeq_elem) + if (!ECORE_MEMCMP(&pos->cmd_data.vlan_mac.u.mac, data, + sizeof(*data)) && + (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd)) + return pos; + + return NULL; +} + +/** + * ecore_validate_vlan_mac_add - check if an ADD command can be executed + * + * @sc: device handle + * @qo: ecore_qable_obj + * @elem: ecore_exeq_elem + * + * Checks that the requested configuration can be added. If yes and if + * requested, consume CAM credit. + * + * The 'validate' is run after the 'optimize'. + * + */ +static int ecore_validate_vlan_mac_add(struct bnx2x_softc *sc, + union ecore_qable_obj *qo, + struct ecore_exeq_elem *elem) +{ + struct ecore_vlan_mac_obj *o = &qo->vlan_mac; + struct ecore_exe_queue_obj *exeq = &o->exe_queue; + int rc; + + /* Check the registry */ + rc = o->check_add(sc, o, &elem->cmd_data.vlan_mac.u); + if (rc) { + ECORE_MSG + ("ADD command is not allowed considering current registry state."); + return rc; + } + + /* Check if there is a pending ADD command for this + * MAC/VLAN/VLAN-MAC. Return an error if there is. + */ + if (exeq->get(exeq, elem)) { + ECORE_MSG("There is a pending ADD command already"); + return ECORE_EXISTS; + } + + /* Consume the credit if not requested not to */ + if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT, + &elem->cmd_data.vlan_mac.vlan_mac_flags) || + o->get_credit(o))) + return ECORE_INVAL; + + return ECORE_SUCCESS; +} + +/** + * ecore_validate_vlan_mac_del - check if the DEL command can be executed + * + * @sc: device handle + * @qo: quable object to check + * @elem: element that needs to be deleted + * + * Checks that the requested configuration can be deleted. If yes and if + * requested, returns a CAM credit. + * + * The 'validate' is run after the 'optimize'. + */ +static int ecore_validate_vlan_mac_del(struct bnx2x_softc *sc, + union ecore_qable_obj *qo, + struct ecore_exeq_elem *elem) +{ + struct ecore_vlan_mac_obj *o = &qo->vlan_mac; + struct ecore_vlan_mac_registry_elem *pos; + struct ecore_exe_queue_obj *exeq = &o->exe_queue; + struct ecore_exeq_elem query_elem; + + /* If this classification can not be deleted (doesn't exist) + * - return a ECORE_EXIST. + */ + pos = o->check_del(sc, o, &elem->cmd_data.vlan_mac.u); + if (!pos) { + ECORE_MSG + ("DEL command is not allowed considering current registry state"); + return ECORE_EXISTS; + } + + /* Check if there are pending DEL or MOVE commands for this + * MAC/VLAN/VLAN-MAC. Return an error if so. + */ + ECORE_MEMCPY(&query_elem, elem, sizeof(query_elem)); + + /* Check for MOVE commands */ + query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_MOVE; + if (exeq->get(exeq, &query_elem)) { + PMD_DRV_LOG(ERR, "There is a pending MOVE command already"); + return ECORE_INVAL; + } + + /* Check for DEL commands */ + if (exeq->get(exeq, elem)) { + ECORE_MSG("There is a pending DEL command already"); + return ECORE_EXISTS; + } + + /* Return the credit to the credit pool if not requested not to */ + if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT, + &elem->cmd_data.vlan_mac.vlan_mac_flags) || + o->put_credit(o))) { + PMD_DRV_LOG(ERR, "Failed to return a credit"); + return ECORE_INVAL; + } + + return ECORE_SUCCESS; +} + +/** + * ecore_validate_vlan_mac_move - check if the MOVE command can be executed + * + * @sc: device handle + * @qo: quable object to check (source) + * @elem: element that needs to be moved + * + * Checks that the requested configuration can be moved. If yes and if + * requested, returns a CAM credit. + * + * The 'validate' is run after the 'optimize'. + */ +static int ecore_validate_vlan_mac_move(struct bnx2x_softc *sc, + union ecore_qable_obj *qo, + struct ecore_exeq_elem *elem) +{ + struct ecore_vlan_mac_obj *src_o = &qo->vlan_mac; + struct ecore_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj; + struct ecore_exeq_elem query_elem; + struct ecore_exe_queue_obj *src_exeq = &src_o->exe_queue; + struct ecore_exe_queue_obj *dest_exeq = &dest_o->exe_queue; + + /* Check if we can perform this operation based on the current registry + * state. + */ + if (!src_o->check_move(sc, src_o, dest_o, &elem->cmd_data.vlan_mac.u)) { + ECORE_MSG + ("MOVE command is not allowed considering current registry state"); + return ECORE_INVAL; + } + + /* Check if there is an already pending DEL or MOVE command for the + * source object or ADD command for a destination object. Return an + * error if so. + */ + ECORE_MEMCPY(&query_elem, elem, sizeof(query_elem)); + + /* Check DEL on source */ + query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_DEL; + if (src_exeq->get(src_exeq, &query_elem)) { + PMD_DRV_LOG(ERR, + "There is a pending DEL command on the source queue already"); + return ECORE_INVAL; + } + + /* Check MOVE on source */ + if (src_exeq->get(src_exeq, elem)) { + ECORE_MSG("There is a pending MOVE command already"); + return ECORE_EXISTS; + } + + /* Check ADD on destination */ + query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_ADD; + if (dest_exeq->get(dest_exeq, &query_elem)) { + PMD_DRV_LOG(ERR, + "There is a pending ADD command on the destination queue already"); + return ECORE_INVAL; + } + + /* Consume the credit if not requested not to */ + if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT_DEST, + &elem->cmd_data.vlan_mac.vlan_mac_flags) || + dest_o->get_credit(dest_o))) + return ECORE_INVAL; + + if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT, + &elem->cmd_data.vlan_mac.vlan_mac_flags) || + src_o->put_credit(src_o))) { + /* return the credit taken from dest... */ + dest_o->put_credit(dest_o); + return ECORE_INVAL; + } + + return ECORE_SUCCESS; +} + +static int ecore_validate_vlan_mac(struct bnx2x_softc *sc, + union ecore_qable_obj *qo, + struct ecore_exeq_elem *elem) +{ + switch (elem->cmd_data.vlan_mac.cmd) { + case ECORE_VLAN_MAC_ADD: + return ecore_validate_vlan_mac_add(sc, qo, elem); + case ECORE_VLAN_MAC_DEL: + return ecore_validate_vlan_mac_del(sc, qo, elem); + case ECORE_VLAN_MAC_MOVE: + return ecore_validate_vlan_mac_move(sc, qo, elem); + default: + return ECORE_INVAL; + } +} + +static int ecore_remove_vlan_mac(__rte_unused struct bnx2x_softc *sc, + union ecore_qable_obj *qo, + struct ecore_exeq_elem *elem) +{ + int rc = 0; + + /* If consumption wasn't required, nothing to do */ + if (ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT, + &elem->cmd_data.vlan_mac.vlan_mac_flags)) + return ECORE_SUCCESS; + + switch (elem->cmd_data.vlan_mac.cmd) { + case ECORE_VLAN_MAC_ADD: + case ECORE_VLAN_MAC_MOVE: + rc = qo->vlan_mac.put_credit(&qo->vlan_mac); + break; + case ECORE_VLAN_MAC_DEL: + rc = qo->vlan_mac.get_credit(&qo->vlan_mac); + break; + default: + return ECORE_INVAL; + } + + if (rc != TRUE) + return ECORE_INVAL; + + return ECORE_SUCCESS; +} + +/** + * ecore_wait_vlan_mac - passively wait for 5 seconds until all work completes. + * + * @sc: device handle + * @o: ecore_vlan_mac_obj + * + */ +static int ecore_wait_vlan_mac(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o) +{ + int cnt = 5000, rc; + struct ecore_exe_queue_obj *exeq = &o->exe_queue; + struct ecore_raw_obj *raw = &o->raw; + + while (cnt--) { + /* Wait for the current command to complete */ + rc = raw->wait_comp(sc, raw); + if (rc) + return rc; + + /* Wait until there are no pending commands */ + if (!ecore_exe_queue_empty(exeq)) + ECORE_WAIT(sc, 1000); + else + return ECORE_SUCCESS; + } + + return ECORE_TIMEOUT; +} + +static int __ecore_vlan_mac_execute_step(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + unsigned long *ramrod_flags) +{ + int rc = ECORE_SUCCESS; + + ECORE_SPIN_LOCK_BH(&o->exe_queue.lock); + + ECORE_MSG("vlan_mac_execute_step - trying to take writer lock"); + rc = __ecore_vlan_mac_h_write_trylock(sc, o); + + if (rc != ECORE_SUCCESS) { + __ecore_vlan_mac_h_pend(sc, o, *ramrod_flags); + + /** Calling function should not diffrentiate between this case + * and the case in which there is already a pending ramrod + */ + rc = ECORE_PENDING; + } else { + rc = ecore_exe_queue_step(sc, &o->exe_queue, ramrod_flags); + } + ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock); + + return rc; +} + +/** + * ecore_complete_vlan_mac - complete one VLAN-MAC ramrod + * + * @sc: device handle + * @o: ecore_vlan_mac_obj + * @cqe: + * @cont: if TRUE schedule next execution chunk + * + */ +static int ecore_complete_vlan_mac(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + union event_ring_elem *cqe, + unsigned long *ramrod_flags) +{ + struct ecore_raw_obj *r = &o->raw; + int rc; + + /* Reset pending list */ + ecore_exe_queue_reset_pending(sc, &o->exe_queue); + + /* Clear pending */ + r->clear_pending(r); + + /* If ramrod failed this is most likely a SW bug */ + if (cqe->message.error) + return ECORE_INVAL; + + /* Run the next bulk of pending commands if requested */ + if (ECORE_TEST_BIT(RAMROD_CONT, ramrod_flags)) { + rc = __ecore_vlan_mac_execute_step(sc, o, ramrod_flags); + if (rc < 0) + return rc; + } + + /* If there is more work to do return PENDING */ + if (!ecore_exe_queue_empty(&o->exe_queue)) + return ECORE_PENDING; + + return ECORE_SUCCESS; +} + +/** + * ecore_optimize_vlan_mac - optimize ADD and DEL commands. + * + * @sc: device handle + * @o: ecore_qable_obj + * @elem: ecore_exeq_elem + */ +static int ecore_optimize_vlan_mac(struct bnx2x_softc *sc, + union ecore_qable_obj *qo, + struct ecore_exeq_elem *elem) +{ + struct ecore_exeq_elem query, *pos; + struct ecore_vlan_mac_obj *o = &qo->vlan_mac; + struct ecore_exe_queue_obj *exeq = &o->exe_queue; + + ECORE_MEMCPY(&query, elem, sizeof(query)); + + switch (elem->cmd_data.vlan_mac.cmd) { + case ECORE_VLAN_MAC_ADD: + query.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_DEL; + break; + case ECORE_VLAN_MAC_DEL: + query.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_ADD; + break; + default: + /* Don't handle anything other than ADD or DEL */ + return 0; + } + + /* If we found the appropriate element - delete it */ + pos = exeq->get(exeq, &query); + if (pos) { + + /* Return the credit of the optimized command */ + if (!ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT, + &pos->cmd_data.vlan_mac.vlan_mac_flags)) { + if ((query.cmd_data.vlan_mac.cmd == + ECORE_VLAN_MAC_ADD) && !o->put_credit(o)) { + PMD_DRV_LOG(ERR, + "Failed to return the credit for the optimized ADD command"); + return ECORE_INVAL; + } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */ + PMD_DRV_LOG(ERR, + "Failed to recover the credit from the optimized DEL command"); + return ECORE_INVAL; + } + } + + ECORE_MSG("Optimizing %s command", + (elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ? + "ADD" : "DEL"); + + ECORE_LIST_REMOVE_ENTRY(&pos->link, &exeq->exe_queue); + ecore_exe_queue_free_elem(sc, pos); + return 1; + } + + return 0; +} + +/** + * ecore_vlan_mac_get_registry_elem - prepare a registry element + * + * @sc: device handle + * @o: + * @elem: + * @restore: + * @re: + * + * prepare a registry element according to the current command request. + */ +static int ecore_vlan_mac_get_registry_elem(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + struct ecore_exeq_elem *elem, + int restore, struct + ecore_vlan_mac_registry_elem + **re) +{ + enum ecore_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd; + struct ecore_vlan_mac_registry_elem *reg_elem; + + /* Allocate a new registry element if needed. */ + if (!restore && + ((cmd == ECORE_VLAN_MAC_ADD) || (cmd == ECORE_VLAN_MAC_MOVE))) { + reg_elem = ECORE_ZALLOC(sizeof(*reg_elem), GFP_ATOMIC, sc); + if (!reg_elem) + return ECORE_NOMEM; + + /* Get a new CAM offset */ + if (!o->get_cam_offset(o, ®_elem->cam_offset)) { + /* This shall never happen, because we have checked the + * CAM availability in the 'validate'. + */ + ECORE_DBG_BREAK_IF(1); + ECORE_FREE(sc, reg_elem, sizeof(*reg_elem)); + return ECORE_INVAL; + } + + ECORE_MSG("Got cam offset %d", reg_elem->cam_offset); + + /* Set a VLAN-MAC data */ + ECORE_MEMCPY(®_elem->u, &elem->cmd_data.vlan_mac.u, + sizeof(reg_elem->u)); + + /* Copy the flags (needed for DEL and RESTORE flows) */ + reg_elem->vlan_mac_flags = + elem->cmd_data.vlan_mac.vlan_mac_flags; + } else /* DEL, RESTORE */ + reg_elem = o->check_del(sc, o, &elem->cmd_data.vlan_mac.u); + + *re = reg_elem; + return ECORE_SUCCESS; +} + +/** + * ecore_execute_vlan_mac - execute vlan mac command + * + * @sc: device handle + * @qo: + * @exe_chunk: + * @ramrod_flags: + * + * go and send a ramrod! + */ +static int ecore_execute_vlan_mac(struct bnx2x_softc *sc, + union ecore_qable_obj *qo, + ecore_list_t * exe_chunk, + unsigned long *ramrod_flags) +{ + struct ecore_exeq_elem *elem; + struct ecore_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj; + struct ecore_raw_obj *r = &o->raw; + int rc, idx = 0; + int restore = ECORE_TEST_BIT(RAMROD_RESTORE, ramrod_flags); + int drv_only = ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags); + struct ecore_vlan_mac_registry_elem *reg_elem; + enum ecore_vlan_mac_cmd cmd; + + /* If DRIVER_ONLY execution is requested, cleanup a registry + * and exit. Otherwise send a ramrod to FW. + */ + if (!drv_only) { + + /* Set pending */ + r->set_pending(r); + + /* Fill the ramrod data */ + ECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link, + struct ecore_exeq_elem) { + cmd = elem->cmd_data.vlan_mac.cmd; + /* We will add to the target object in MOVE command, so + * change the object for a CAM search. + */ + if (cmd == ECORE_VLAN_MAC_MOVE) + cam_obj = elem->cmd_data.vlan_mac.target_obj; + else + cam_obj = o; + + rc = ecore_vlan_mac_get_registry_elem(sc, cam_obj, + elem, restore, + ®_elem); + if (rc) + goto error_exit; + + ECORE_DBG_BREAK_IF(!reg_elem); + + /* Push a new entry into the registry */ + if (!restore && + ((cmd == ECORE_VLAN_MAC_ADD) || + (cmd == ECORE_VLAN_MAC_MOVE))) + ECORE_LIST_PUSH_HEAD(®_elem->link, + &cam_obj->head); + + /* Configure a single command in a ramrod data buffer */ + o->set_one_rule(sc, o, elem, idx, reg_elem->cam_offset); + + /* MOVE command consumes 2 entries in the ramrod data */ + if (cmd == ECORE_VLAN_MAC_MOVE) + idx += 2; + else + idx++; + } + + /* + * No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + rc = ecore_sp_post(sc, o->ramrod_cmd, r->cid, + r->rdata_mapping, ETH_CONNECTION_TYPE); + if (rc) + goto error_exit; + } + + /* Now, when we are done with the ramrod - clean up the registry */ + ECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link, struct ecore_exeq_elem) { + cmd = elem->cmd_data.vlan_mac.cmd; + if ((cmd == ECORE_VLAN_MAC_DEL) || (cmd == ECORE_VLAN_MAC_MOVE)) { + reg_elem = o->check_del(sc, o, + &elem->cmd_data.vlan_mac.u); + + ECORE_DBG_BREAK_IF(!reg_elem); + + o->put_cam_offset(o, reg_elem->cam_offset); + ECORE_LIST_REMOVE_ENTRY(®_elem->link, &o->head); + ECORE_FREE(sc, reg_elem, sizeof(*reg_elem)); + } + } + + if (!drv_only) + return ECORE_PENDING; + else + return ECORE_SUCCESS; + +error_exit: + r->clear_pending(r); + + /* Cleanup a registry in case of a failure */ + ECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link, struct ecore_exeq_elem) { + cmd = elem->cmd_data.vlan_mac.cmd; + + if (cmd == ECORE_VLAN_MAC_MOVE) + cam_obj = elem->cmd_data.vlan_mac.target_obj; + else + cam_obj = o; + + /* Delete all newly added above entries */ + if (!restore && + ((cmd == ECORE_VLAN_MAC_ADD) || + (cmd == ECORE_VLAN_MAC_MOVE))) { + reg_elem = o->check_del(sc, cam_obj, + &elem->cmd_data.vlan_mac.u); + if (reg_elem) { + ECORE_LIST_REMOVE_ENTRY(®_elem->link, + &cam_obj->head); + ECORE_FREE(sc, reg_elem, sizeof(*reg_elem)); + } + } + } + + return rc; +} + +static int ecore_vlan_mac_push_new_cmd(struct bnx2x_softc *sc, struct + ecore_vlan_mac_ramrod_params *p) +{ + struct ecore_exeq_elem *elem; + struct ecore_vlan_mac_obj *o = p->vlan_mac_obj; + int restore = ECORE_TEST_BIT(RAMROD_RESTORE, &p->ramrod_flags); + + /* Allocate the execution queue element */ + elem = ecore_exe_queue_alloc_elem(sc); + if (!elem) + return ECORE_NOMEM; + + /* Set the command 'length' */ + switch (p->user_req.cmd) { + case ECORE_VLAN_MAC_MOVE: + elem->cmd_len = 2; + break; + default: + elem->cmd_len = 1; + } + + /* Fill the object specific info */ + ECORE_MEMCPY(&elem->cmd_data.vlan_mac, &p->user_req, + sizeof(p->user_req)); + + /* Try to add a new command to the pending list */ + return ecore_exe_queue_add(sc, &o->exe_queue, elem, restore); +} + +/** + * ecore_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules. + * + * @sc: device handle + * @p: + * + */ +int ecore_config_vlan_mac(struct bnx2x_softc *sc, + struct ecore_vlan_mac_ramrod_params *p) +{ + int rc = ECORE_SUCCESS; + struct ecore_vlan_mac_obj *o = p->vlan_mac_obj; + unsigned long *ramrod_flags = &p->ramrod_flags; + int cont = ECORE_TEST_BIT(RAMROD_CONT, ramrod_flags); + struct ecore_raw_obj *raw = &o->raw; + + /* + * Add new elements to the execution list for commands that require it. + */ + if (!cont) { + rc = ecore_vlan_mac_push_new_cmd(sc, p); + if (rc) + return rc; + } + + /* If nothing will be executed further in this iteration we want to + * return PENDING if there are pending commands + */ + if (!ecore_exe_queue_empty(&o->exe_queue)) + rc = ECORE_PENDING; + + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { + ECORE_MSG + ("RAMROD_DRV_CLR_ONLY requested: clearing a pending bit."); + raw->clear_pending(raw); + } + + /* Execute commands if required */ + if (cont || ECORE_TEST_BIT(RAMROD_EXEC, ramrod_flags) || + ECORE_TEST_BIT(RAMROD_COMP_WAIT, ramrod_flags)) { + rc = __ecore_vlan_mac_execute_step(sc, p->vlan_mac_obj, + &p->ramrod_flags); + if (rc < 0) + return rc; + } + + /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set + * then user want to wait until the last command is done. + */ + if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) { + /* Wait maximum for the current exe_queue length iterations plus + * one (for the current pending command). + */ + int max_iterations = ecore_exe_queue_length(&o->exe_queue) + 1; + + while (!ecore_exe_queue_empty(&o->exe_queue) && + max_iterations--) { + + /* Wait for the current command to complete */ + rc = raw->wait_comp(sc, raw); + if (rc) + return rc; + + /* Make a next step */ + rc = __ecore_vlan_mac_execute_step(sc, + p->vlan_mac_obj, + &p->ramrod_flags); + if (rc < 0) + return rc; + } + + return ECORE_SUCCESS; + } + + return rc; +} + +/** + * ecore_vlan_mac_del_all - delete elements with given vlan_mac_flags spec + * + * @sc: device handle + * @o: + * @vlan_mac_flags: + * @ramrod_flags: execution flags to be used for this deletion + * + * if the last operation has completed successfully and there are no + * more elements left, positive value if the last operation has completed + * successfully and there are more previously configured elements, negative + * value is current operation has failed. + */ +static int ecore_vlan_mac_del_all(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + unsigned long *vlan_mac_flags, + unsigned long *ramrod_flags) +{ + struct ecore_vlan_mac_registry_elem *pos = NULL; + int rc = 0, read_lock; + struct ecore_vlan_mac_ramrod_params p; + struct ecore_exe_queue_obj *exeq = &o->exe_queue; + struct ecore_exeq_elem *exeq_pos, *exeq_pos_n; + + /* Clear pending commands first */ + + ECORE_SPIN_LOCK_BH(&exeq->lock); + + ECORE_LIST_FOR_EACH_ENTRY_SAFE(exeq_pos, exeq_pos_n, + &exeq->exe_queue, link, + struct ecore_exeq_elem) { + if (exeq_pos->cmd_data.vlan_mac.vlan_mac_flags == + *vlan_mac_flags) { + rc = exeq->remove(sc, exeq->owner, exeq_pos); + if (rc) { + PMD_DRV_LOG(ERR, "Failed to remove command"); + ECORE_SPIN_UNLOCK_BH(&exeq->lock); + return rc; + } + ECORE_LIST_REMOVE_ENTRY(&exeq_pos->link, + &exeq->exe_queue); + ecore_exe_queue_free_elem(sc, exeq_pos); + } + } + + ECORE_SPIN_UNLOCK_BH(&exeq->lock); + + /* Prepare a command request */ + ECORE_MEMSET(&p, 0, sizeof(p)); + p.vlan_mac_obj = o; + p.ramrod_flags = *ramrod_flags; + p.user_req.cmd = ECORE_VLAN_MAC_DEL; + + /* Add all but the last VLAN-MAC to the execution queue without actually + * execution anything. + */ + ECORE_CLEAR_BIT_NA(RAMROD_COMP_WAIT, &p.ramrod_flags); + ECORE_CLEAR_BIT_NA(RAMROD_EXEC, &p.ramrod_flags); + ECORE_CLEAR_BIT_NA(RAMROD_CONT, &p.ramrod_flags); + + ECORE_MSG("vlan_mac_del_all -- taking vlan_mac_lock (reader)"); + read_lock = ecore_vlan_mac_h_read_lock(sc, o); + if (read_lock != ECORE_SUCCESS) + return read_lock; + + ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link, + struct ecore_vlan_mac_registry_elem) { + if (pos->vlan_mac_flags == *vlan_mac_flags) { + p.user_req.vlan_mac_flags = pos->vlan_mac_flags; + ECORE_MEMCPY(&p.user_req.u, &pos->u, sizeof(pos->u)); + rc = ecore_config_vlan_mac(sc, &p); + if (rc < 0) { + PMD_DRV_LOG(ERR, + "Failed to add a new DEL command"); + ecore_vlan_mac_h_read_unlock(sc, o); + return rc; + } + } + } + + ECORE_MSG("vlan_mac_del_all -- releasing vlan_mac_lock (reader)"); + ecore_vlan_mac_h_read_unlock(sc, o); + + p.ramrod_flags = *ramrod_flags; + ECORE_SET_BIT_NA(RAMROD_CONT, &p.ramrod_flags); + + return ecore_config_vlan_mac(sc, &p); +} + +static void ecore_init_raw_obj(struct ecore_raw_obj *raw, uint8_t cl_id, + uint32_t cid, uint8_t func_id, + void *rdata, + ecore_dma_addr_t rdata_mapping, int state, + unsigned long *pstate, ecore_obj_type type) +{ + raw->func_id = func_id; + raw->cid = cid; + raw->cl_id = cl_id; + raw->rdata = rdata; + raw->rdata_mapping = rdata_mapping; + raw->state = state; + raw->pstate = pstate; + raw->obj_type = type; + raw->check_pending = ecore_raw_check_pending; + raw->clear_pending = ecore_raw_clear_pending; + raw->set_pending = ecore_raw_set_pending; + raw->wait_comp = ecore_raw_wait; +} + +static void ecore_init_vlan_mac_common(struct ecore_vlan_mac_obj *o, + uint8_t cl_id, uint32_t cid, + uint8_t func_id, void *rdata, + ecore_dma_addr_t rdata_mapping, + int state, unsigned long *pstate, + ecore_obj_type type, + struct ecore_credit_pool_obj + *macs_pool, struct ecore_credit_pool_obj + *vlans_pool) +{ + ECORE_LIST_INIT(&o->head); + o->head_reader = 0; + o->head_exe_request = FALSE; + o->saved_ramrod_flags = 0; + + o->macs_pool = macs_pool; + o->vlans_pool = vlans_pool; + + o->delete_all = ecore_vlan_mac_del_all; + o->restore = ecore_vlan_mac_restore; + o->complete = ecore_complete_vlan_mac; + o->wait = ecore_wait_vlan_mac; + + ecore_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping, + state, pstate, type); +} + +void ecore_init_mac_obj(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *mac_obj, + uint8_t cl_id, uint32_t cid, uint8_t func_id, + void *rdata, ecore_dma_addr_t rdata_mapping, int state, + unsigned long *pstate, ecore_obj_type type, + struct ecore_credit_pool_obj *macs_pool) +{ + union ecore_qable_obj *qable_obj = (union ecore_qable_obj *)mac_obj; + + ecore_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata, + rdata_mapping, state, pstate, type, + macs_pool, NULL); + + /* CAM credit pool handling */ + mac_obj->get_credit = ecore_get_credit_mac; + mac_obj->put_credit = ecore_put_credit_mac; + mac_obj->get_cam_offset = ecore_get_cam_offset_mac; + mac_obj->put_cam_offset = ecore_put_cam_offset_mac; + + if (CHIP_IS_E1x(sc)) { + mac_obj->set_one_rule = ecore_set_one_mac_e1x; + mac_obj->check_del = ecore_check_mac_del; + mac_obj->check_add = ecore_check_mac_add; + mac_obj->check_move = ecore_check_move_always_err; + mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC; + + /* Exe Queue */ + ecore_exe_queue_init(sc, + &mac_obj->exe_queue, 1, qable_obj, + ecore_validate_vlan_mac, + ecore_remove_vlan_mac, + ecore_optimize_vlan_mac, + ecore_execute_vlan_mac, + ecore_exeq_get_mac); + } else { + mac_obj->set_one_rule = ecore_set_one_mac_e2; + mac_obj->check_del = ecore_check_mac_del; + mac_obj->check_add = ecore_check_mac_add; + mac_obj->check_move = ecore_check_move; + mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES; + mac_obj->get_n_elements = ecore_get_n_elements; + + /* Exe Queue */ + ecore_exe_queue_init(sc, + &mac_obj->exe_queue, CLASSIFY_RULES_COUNT, + qable_obj, ecore_validate_vlan_mac, + ecore_remove_vlan_mac, + ecore_optimize_vlan_mac, + ecore_execute_vlan_mac, + ecore_exeq_get_mac); + } +} + +/* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ +static void __storm_memset_mac_filters(struct bnx2x_softc *sc, struct + tstorm_eth_mac_filter_config + *mac_filters, uint16_t pf_id) +{ + size_t size = sizeof(struct tstorm_eth_mac_filter_config); + + uint32_t addr = BAR_TSTRORM_INTMEM + + TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id); + + ecore_storm_memset_struct(sc, addr, size, (uint32_t *) mac_filters); +} + +static int ecore_set_rx_mode_e1x(struct bnx2x_softc *sc, + struct ecore_rx_mode_ramrod_params *p) +{ + /* update the sc MAC filter structure */ + uint32_t mask = (1 << p->cl_id); + + struct tstorm_eth_mac_filter_config *mac_filters = + (struct tstorm_eth_mac_filter_config *)p->rdata; + + /* initial setting is drop-all */ + uint8_t drop_all_ucast = 1, drop_all_mcast = 1; + uint8_t accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0; + uint8_t unmatched_unicast = 0; + + /* In e1x there we only take into account rx accept flag since tx switching + * isn't enabled. */ + if (ECORE_TEST_BIT(ECORE_ACCEPT_UNICAST, &p->rx_accept_flags)) + /* accept matched ucast */ + drop_all_ucast = 0; + + if (ECORE_TEST_BIT(ECORE_ACCEPT_MULTICAST, &p->rx_accept_flags)) + /* accept matched mcast */ + drop_all_mcast = 0; + + if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) { + /* accept all mcast */ + drop_all_ucast = 0; + accp_all_ucast = 1; + } + if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) { + /* accept all mcast */ + drop_all_mcast = 0; + accp_all_mcast = 1; + } + if (ECORE_TEST_BIT(ECORE_ACCEPT_BROADCAST, &p->rx_accept_flags)) + /* accept (all) bcast */ + accp_all_bcast = 1; + if (ECORE_TEST_BIT(ECORE_ACCEPT_UNMATCHED, &p->rx_accept_flags)) + /* accept unmatched unicasts */ + unmatched_unicast = 1; + + mac_filters->ucast_drop_all = drop_all_ucast ? + mac_filters->ucast_drop_all | mask : + mac_filters->ucast_drop_all & ~mask; + + mac_filters->mcast_drop_all = drop_all_mcast ? + mac_filters->mcast_drop_all | mask : + mac_filters->mcast_drop_all & ~mask; + + mac_filters->ucast_accept_all = accp_all_ucast ? + mac_filters->ucast_accept_all | mask : + mac_filters->ucast_accept_all & ~mask; + + mac_filters->mcast_accept_all = accp_all_mcast ? + mac_filters->mcast_accept_all | mask : + mac_filters->mcast_accept_all & ~mask; + + mac_filters->bcast_accept_all = accp_all_bcast ? + mac_filters->bcast_accept_all | mask : + mac_filters->bcast_accept_all & ~mask; + + mac_filters->unmatched_unicast = unmatched_unicast ? + mac_filters->unmatched_unicast | mask : + mac_filters->unmatched_unicast & ~mask; + + ECORE_MSG("drop_ucast 0x%xdrop_mcast 0x%x accp_ucast 0x%x" + "accp_mcast 0x%xaccp_bcast 0x%x", + mac_filters->ucast_drop_all, mac_filters->mcast_drop_all, + mac_filters->ucast_accept_all, mac_filters->mcast_accept_all, + mac_filters->bcast_accept_all); + + /* write the MAC filter structure */ + __storm_memset_mac_filters(sc, mac_filters, p->func_id); + + /* The operation is completed */ + ECORE_CLEAR_BIT(p->state, p->pstate); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); + + return ECORE_SUCCESS; +} + +/* Setup ramrod data */ +static void ecore_rx_mode_set_rdata_hdr_e2(uint32_t cid, struct eth_classify_header + *hdr, uint8_t rule_cnt) +{ + hdr->echo = ECORE_CPU_TO_LE32(cid); + hdr->rule_cnt = rule_cnt; +} + +static void ecore_rx_mode_set_cmd_state_e2(unsigned long *accept_flags, struct eth_filter_rules_cmd + *cmd, int clear_accept_all) +{ + uint16_t state; + + /* start with 'drop-all' */ + state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL | + ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; + + if (ECORE_TEST_BIT(ECORE_ACCEPT_UNICAST, accept_flags)) + state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; + + if (ECORE_TEST_BIT(ECORE_ACCEPT_MULTICAST, accept_flags)) + state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; + + if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_UNICAST, accept_flags)) { + state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; + state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; + } + + if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_MULTICAST, accept_flags)) { + state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; + state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL; + } + if (ECORE_TEST_BIT(ECORE_ACCEPT_BROADCAST, accept_flags)) + state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; + + if (ECORE_TEST_BIT(ECORE_ACCEPT_UNMATCHED, accept_flags)) { + state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL; + state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; + } + if (ECORE_TEST_BIT(ECORE_ACCEPT_ANY_VLAN, accept_flags)) + state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN; + + /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */ + if (clear_accept_all) { + state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL; + state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL; + state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL; + state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED; + } + + cmd->state = ECORE_CPU_TO_LE16(state); +} + +static int ecore_set_rx_mode_e2(struct bnx2x_softc *sc, + struct ecore_rx_mode_ramrod_params *p) +{ + struct eth_filter_rules_ramrod_data *data = p->rdata; + int rc; + uint8_t rule_idx = 0; + + /* Reset the ramrod data buffer */ + ECORE_MEMSET(data, 0, sizeof(*data)); + + /* Setup ramrod data */ + + /* Tx (internal switching) */ + if (ECORE_TEST_BIT(RAMROD_TX, &p->ramrod_flags)) { + data->rules[rule_idx].client_id = p->cl_id; + data->rules[rule_idx].func_id = p->func_id; + + data->rules[rule_idx].cmd_general_data = + ETH_FILTER_RULES_CMD_TX_CMD; + + ecore_rx_mode_set_cmd_state_e2(&p->tx_accept_flags, + &(data->rules[rule_idx++]), + FALSE); + } + + /* Rx */ + if (ECORE_TEST_BIT(RAMROD_RX, &p->ramrod_flags)) { + data->rules[rule_idx].client_id = p->cl_id; + data->rules[rule_idx].func_id = p->func_id; + + data->rules[rule_idx].cmd_general_data = + ETH_FILTER_RULES_CMD_RX_CMD; + + ecore_rx_mode_set_cmd_state_e2(&p->rx_accept_flags, + &(data->rules[rule_idx++]), + FALSE); + } + + /* If FCoE Queue configuration has been requested configure the Rx and + * internal switching modes for this queue in separate rules. + * + * FCoE queue shell never be set to ACCEPT_ALL packets of any sort: + * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED. + */ + if (ECORE_TEST_BIT(ECORE_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) { + /* Tx (internal switching) */ + if (ECORE_TEST_BIT(RAMROD_TX, &p->ramrod_flags)) { + data->rules[rule_idx].client_id = ECORE_FCOE_CID(sc); + data->rules[rule_idx].func_id = p->func_id; + + data->rules[rule_idx].cmd_general_data = + ETH_FILTER_RULES_CMD_TX_CMD; + + ecore_rx_mode_set_cmd_state_e2(&p->tx_accept_flags, + &(data->rules + [rule_idx++]), TRUE); + } + + /* Rx */ + if (ECORE_TEST_BIT(RAMROD_RX, &p->ramrod_flags)) { + data->rules[rule_idx].client_id = ECORE_FCOE_CID(sc); + data->rules[rule_idx].func_id = p->func_id; + + data->rules[rule_idx].cmd_general_data = + ETH_FILTER_RULES_CMD_RX_CMD; + + ecore_rx_mode_set_cmd_state_e2(&p->rx_accept_flags, + &(data->rules + [rule_idx++]), TRUE); + } + } + + /* Set the ramrod header (most importantly - number of rules to + * configure). + */ + ecore_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx); + + ECORE_MSG + ("About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx", + data->header.rule_cnt, p->rx_accept_flags, p->tx_accept_flags); + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + /* Send a ramrod */ + rc = ecore_sp_post(sc, + RAMROD_CMD_ID_ETH_FILTER_RULES, + p->cid, p->rdata_mapping, ETH_CONNECTION_TYPE); + if (rc) + return rc; + + /* Ramrod completion is pending */ + return ECORE_PENDING; +} + +static int ecore_wait_rx_mode_comp_e2(struct bnx2x_softc *sc, + struct ecore_rx_mode_ramrod_params *p) +{ + return ecore_state_wait(sc, p->state, p->pstate); +} + +static int ecore_empty_rx_mode_wait(__rte_unused struct bnx2x_softc *sc, + __rte_unused struct + ecore_rx_mode_ramrod_params *p) +{ + /* Do nothing */ + return ECORE_SUCCESS; +} + +int ecore_config_rx_mode(struct bnx2x_softc *sc, + struct ecore_rx_mode_ramrod_params *p) +{ + int rc; + + /* Configure the new classification in the chip */ + if (p->rx_mode_obj->config_rx_mode) { + rc = p->rx_mode_obj->config_rx_mode(sc, p); + if (rc < 0) + return rc; + + /* Wait for a ramrod completion if was requested */ + if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) { + rc = p->rx_mode_obj->wait_comp(sc, p); + if (rc) + return rc; + } + } else { + ECORE_MSG("ERROR: config_rx_mode is NULL"); + return -1; + } + + return rc; +} + +void ecore_init_rx_mode_obj(struct bnx2x_softc *sc, struct ecore_rx_mode_obj *o) +{ + if (CHIP_IS_E1x(sc)) { + o->wait_comp = ecore_empty_rx_mode_wait; + o->config_rx_mode = ecore_set_rx_mode_e1x; + } else { + o->wait_comp = ecore_wait_rx_mode_comp_e2; + o->config_rx_mode = ecore_set_rx_mode_e2; + } +} + +/********************* Multicast verbs: SET, CLEAR ****************************/ +static uint8_t ecore_mcast_bin_from_mac(uint8_t * mac) +{ + return (ECORE_CRC32_LE(0, mac, ETH_ALEN) >> 24) & 0xff; +} + +struct ecore_mcast_mac_elem { + ecore_list_entry_t link; + uint8_t mac[ETH_ALEN]; + uint8_t pad[2]; /* For a natural alignment of the following buffer */ +}; + +struct ecore_pending_mcast_cmd { + ecore_list_entry_t link; + int type; /* ECORE_MCAST_CMD_X */ + union { + ecore_list_t macs_head; + uint32_t macs_num; /* Needed for DEL command */ + int next_bin; /* Needed for RESTORE flow with aprox match */ + } data; + + int done; /* set to TRUE, when the command has been handled, + * practically used in 57712 handling only, where one pending + * command may be handled in a few operations. As long as for + * other chips every operation handling is completed in a + * single ramrod, there is no need to utilize this field. + */ +}; + +static int ecore_mcast_wait(struct bnx2x_softc *sc, struct ecore_mcast_obj *o) +{ + if (ecore_state_wait(sc, o->sched_state, o->raw.pstate) || + o->raw.wait_comp(sc, &o->raw)) + return ECORE_TIMEOUT; + + return ECORE_SUCCESS; +} + +static int ecore_mcast_enqueue_cmd(struct bnx2x_softc *sc __rte_unused, + struct ecore_mcast_obj *o, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd) +{ + int total_sz; + struct ecore_pending_mcast_cmd *new_cmd; + struct ecore_mcast_mac_elem *cur_mac = NULL; + struct ecore_mcast_list_elem *pos; + int macs_list_len = ((cmd == ECORE_MCAST_CMD_ADD) ? + p->mcast_list_len : 0); + + /* If the command is empty ("handle pending commands only"), break */ + if (!p->mcast_list_len) + return ECORE_SUCCESS; + + total_sz = sizeof(*new_cmd) + + macs_list_len * sizeof(struct ecore_mcast_mac_elem); + + /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */ + new_cmd = ECORE_ZALLOC(total_sz, GFP_ATOMIC, sc); + + if (!new_cmd) + return ECORE_NOMEM; + + ECORE_MSG("About to enqueue a new %d command. macs_list_len=%d", + cmd, macs_list_len); + + ECORE_LIST_INIT(&new_cmd->data.macs_head); + + new_cmd->type = cmd; + new_cmd->done = FALSE; + + switch (cmd) { + case ECORE_MCAST_CMD_ADD: + cur_mac = (struct ecore_mcast_mac_elem *) + ((uint8_t *) new_cmd + sizeof(*new_cmd)); + + /* Push the MACs of the current command into the pending command + * MACs list: FIFO + */ + ECORE_LIST_FOR_EACH_ENTRY(pos, &p->mcast_list, link, + struct ecore_mcast_list_elem) { + ECORE_MEMCPY(cur_mac->mac, pos->mac, ETH_ALEN); + ECORE_LIST_PUSH_TAIL(&cur_mac->link, + &new_cmd->data.macs_head); + cur_mac++; + } + + break; + + case ECORE_MCAST_CMD_DEL: + new_cmd->data.macs_num = p->mcast_list_len; + break; + + case ECORE_MCAST_CMD_RESTORE: + new_cmd->data.next_bin = 0; + break; + + default: + ECORE_FREE(sc, new_cmd, total_sz); + PMD_DRV_LOG(ERR, "Unknown command: %d", cmd); + return ECORE_INVAL; + } + + /* Push the new pending command to the tail of the pending list: FIFO */ + ECORE_LIST_PUSH_TAIL(&new_cmd->link, &o->pending_cmds_head); + + o->set_sched(o); + + return ECORE_PENDING; +} + +/** + * ecore_mcast_get_next_bin - get the next set bin (index) + * + * @o: + * @last: index to start looking from (including) + * + * returns the next found (set) bin or a negative value if none is found. + */ +static int ecore_mcast_get_next_bin(struct ecore_mcast_obj *o, int last) +{ + int i, j, inner_start = last % BIT_VEC64_ELEM_SZ; + + for (i = last / BIT_VEC64_ELEM_SZ; i < ECORE_MCAST_VEC_SZ; i++) { + if (o->registry.aprox_match.vec[i]) + for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) { + int cur_bit = j + BIT_VEC64_ELEM_SZ * i; + if (BIT_VEC64_TEST_BIT + (o->registry.aprox_match.vec, cur_bit)) { + return cur_bit; + } + } + inner_start = 0; + } + + /* None found */ + return -1; +} + +/** + * ecore_mcast_clear_first_bin - find the first set bin and clear it + * + * @o: + * + * returns the index of the found bin or -1 if none is found + */ +static int ecore_mcast_clear_first_bin(struct ecore_mcast_obj *o) +{ + int cur_bit = ecore_mcast_get_next_bin(o, 0); + + if (cur_bit >= 0) + BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit); + + return cur_bit; +} + +static uint8_t ecore_mcast_get_rx_tx_flag(struct ecore_mcast_obj *o) +{ + struct ecore_raw_obj *raw = &o->raw; + uint8_t rx_tx_flag = 0; + + if ((raw->obj_type == ECORE_OBJ_TYPE_TX) || + (raw->obj_type == ECORE_OBJ_TYPE_RX_TX)) + rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD; + + if ((raw->obj_type == ECORE_OBJ_TYPE_RX) || + (raw->obj_type == ECORE_OBJ_TYPE_RX_TX)) + rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD; + + return rx_tx_flag; +} + +static void ecore_mcast_set_one_rule_e2(struct bnx2x_softc *sc __rte_unused, + struct ecore_mcast_obj *o, int idx, + union ecore_mcast_config_data *cfg_data, + enum ecore_mcast_cmd cmd) +{ + struct ecore_raw_obj *r = &o->raw; + struct eth_multicast_rules_ramrod_data *data = + (struct eth_multicast_rules_ramrod_data *)(r->rdata); + uint8_t func_id = r->func_id; + uint8_t rx_tx_add_flag = ecore_mcast_get_rx_tx_flag(o); + int bin; + + if ((cmd == ECORE_MCAST_CMD_ADD) || (cmd == ECORE_MCAST_CMD_RESTORE)) + rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD; + + data->rules[idx].cmd_general_data |= rx_tx_add_flag; + + /* Get a bin and update a bins' vector */ + switch (cmd) { + case ECORE_MCAST_CMD_ADD: + bin = ecore_mcast_bin_from_mac(cfg_data->mac); + BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin); + break; + + case ECORE_MCAST_CMD_DEL: + /* If there were no more bins to clear + * (ecore_mcast_clear_first_bin() returns -1) then we would + * clear any (0xff) bin. + * See ecore_mcast_validate_e2() for explanation when it may + * happen. + */ + bin = ecore_mcast_clear_first_bin(o); + break; + + case ECORE_MCAST_CMD_RESTORE: + bin = cfg_data->bin; + break; + + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", cmd); + return; + } + + ECORE_MSG("%s bin %d", + ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ? + "Setting" : "Clearing"), bin); + + data->rules[idx].bin_id = (uint8_t) bin; + data->rules[idx].func_id = func_id; + data->rules[idx].engine_id = o->engine_id; +} + +/** + * ecore_mcast_handle_restore_cmd_e2 - restore configuration from the registry + * + * @sc: device handle + * @o: + * @start_bin: index in the registry to start from (including) + * @rdata_idx: index in the ramrod data to start from + * + * returns last handled bin index or -1 if all bins have been handled + */ +static int ecore_mcast_handle_restore_cmd_e2(struct bnx2x_softc *sc, + struct ecore_mcast_obj *o, + int start_bin, int *rdata_idx) +{ + int cur_bin, cnt = *rdata_idx; + union ecore_mcast_config_data cfg_data = { NULL }; + + /* go through the registry and configure the bins from it */ + for (cur_bin = ecore_mcast_get_next_bin(o, start_bin); cur_bin >= 0; + cur_bin = ecore_mcast_get_next_bin(o, cur_bin + 1)) { + + cfg_data.bin = (uint8_t) cur_bin; + o->set_one_rule(sc, o, cnt, &cfg_data, ECORE_MCAST_CMD_RESTORE); + + cnt++; + + ECORE_MSG("About to configure a bin %d", cur_bin); + + /* Break if we reached the maximum number + * of rules. + */ + if (cnt >= o->max_cmd_len) + break; + } + + *rdata_idx = cnt; + + return cur_bin; +} + +static void ecore_mcast_hdl_pending_add_e2(struct bnx2x_softc *sc, + struct ecore_mcast_obj *o, + struct ecore_pending_mcast_cmd + *cmd_pos, int *line_idx) +{ + struct ecore_mcast_mac_elem *pmac_pos, *pmac_pos_n; + int cnt = *line_idx; + union ecore_mcast_config_data cfg_data = { NULL }; + + ECORE_LIST_FOR_EACH_ENTRY_SAFE(pmac_pos, pmac_pos_n, + &cmd_pos->data.macs_head, link, + struct ecore_mcast_mac_elem) { + + cfg_data.mac = &pmac_pos->mac[0]; + o->set_one_rule(sc, o, cnt, &cfg_data, cmd_pos->type); + + cnt++; + + ECORE_MSG + ("About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC", + pmac_pos->mac[0], pmac_pos->mac[1], pmac_pos->mac[2], + pmac_pos->mac[3], pmac_pos->mac[4], pmac_pos->mac[5]); + + ECORE_LIST_REMOVE_ENTRY(&pmac_pos->link, + &cmd_pos->data.macs_head); + + /* Break if we reached the maximum number + * of rules. + */ + if (cnt >= o->max_cmd_len) + break; + } + + *line_idx = cnt; + + /* if no more MACs to configure - we are done */ + if (ECORE_LIST_IS_EMPTY(&cmd_pos->data.macs_head)) + cmd_pos->done = TRUE; +} + +static void ecore_mcast_hdl_pending_del_e2(struct bnx2x_softc *sc, + struct ecore_mcast_obj *o, + struct ecore_pending_mcast_cmd + *cmd_pos, int *line_idx) +{ + int cnt = *line_idx; + + while (cmd_pos->data.macs_num) { + o->set_one_rule(sc, o, cnt, NULL, cmd_pos->type); + + cnt++; + + cmd_pos->data.macs_num--; + + ECORE_MSG("Deleting MAC. %d left,cnt is %d", + cmd_pos->data.macs_num, cnt); + + /* Break if we reached the maximum + * number of rules. + */ + if (cnt >= o->max_cmd_len) + break; + } + + *line_idx = cnt; + + /* If we cleared all bins - we are done */ + if (!cmd_pos->data.macs_num) + cmd_pos->done = TRUE; +} + +static void ecore_mcast_hdl_pending_restore_e2(struct bnx2x_softc *sc, + struct ecore_mcast_obj *o, struct + ecore_pending_mcast_cmd + *cmd_pos, int *line_idx) +{ + cmd_pos->data.next_bin = o->hdl_restore(sc, o, cmd_pos->data.next_bin, + line_idx); + + if (cmd_pos->data.next_bin < 0) + /* If o->set_restore returned -1 we are done */ + cmd_pos->done = TRUE; + else + /* Start from the next bin next time */ + cmd_pos->data.next_bin++; +} + +static int ecore_mcast_handle_pending_cmds_e2(struct bnx2x_softc *sc, struct + ecore_mcast_ramrod_params + *p) +{ + struct ecore_pending_mcast_cmd *cmd_pos, *cmd_pos_n; + int cnt = 0; + struct ecore_mcast_obj *o = p->mcast_obj; + + ECORE_LIST_FOR_EACH_ENTRY_SAFE(cmd_pos, cmd_pos_n, + &o->pending_cmds_head, link, + struct ecore_pending_mcast_cmd) { + switch (cmd_pos->type) { + case ECORE_MCAST_CMD_ADD: + ecore_mcast_hdl_pending_add_e2(sc, o, cmd_pos, &cnt); + break; + + case ECORE_MCAST_CMD_DEL: + ecore_mcast_hdl_pending_del_e2(sc, o, cmd_pos, &cnt); + break; + + case ECORE_MCAST_CMD_RESTORE: + ecore_mcast_hdl_pending_restore_e2(sc, o, cmd_pos, + &cnt); + break; + + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", cmd_pos->type); + return ECORE_INVAL; + } + + /* If the command has been completed - remove it from the list + * and free the memory + */ + if (cmd_pos->done) { + ECORE_LIST_REMOVE_ENTRY(&cmd_pos->link, + &o->pending_cmds_head); + ECORE_FREE(sc, cmd_pos, cmd_pos->alloc_len); + } + + /* Break if we reached the maximum number of rules */ + if (cnt >= o->max_cmd_len) + break; + } + + return cnt; +} + +static void ecore_mcast_hdl_add(struct bnx2x_softc *sc, + struct ecore_mcast_obj *o, + struct ecore_mcast_ramrod_params *p, + int *line_idx) +{ + struct ecore_mcast_list_elem *mlist_pos; + union ecore_mcast_config_data cfg_data = { NULL }; + int cnt = *line_idx; + + ECORE_LIST_FOR_EACH_ENTRY(mlist_pos, &p->mcast_list, link, + struct ecore_mcast_list_elem) { + cfg_data.mac = mlist_pos->mac; + o->set_one_rule(sc, o, cnt, &cfg_data, ECORE_MCAST_CMD_ADD); + + cnt++; + + ECORE_MSG + ("About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC", + mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2], + mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5]); + } + + *line_idx = cnt; +} + +static void ecore_mcast_hdl_del(struct bnx2x_softc *sc, + struct ecore_mcast_obj *o, + struct ecore_mcast_ramrod_params *p, + int *line_idx) +{ + int cnt = *line_idx, i; + + for (i = 0; i < p->mcast_list_len; i++) { + o->set_one_rule(sc, o, cnt, NULL, ECORE_MCAST_CMD_DEL); + + cnt++; + + ECORE_MSG("Deleting MAC. %d left", p->mcast_list_len - i - 1); + } + + *line_idx = cnt; +} + +/** + * ecore_mcast_handle_current_cmd - + * + * @sc: device handle + * @p: + * @cmd: + * @start_cnt: first line in the ramrod data that may be used + * + * This function is called iff there is enough place for the current command in + * the ramrod data. + * Returns number of lines filled in the ramrod data in total. + */ +static int ecore_mcast_handle_current_cmd(struct bnx2x_softc *sc, struct + ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd, + int start_cnt) +{ + struct ecore_mcast_obj *o = p->mcast_obj; + int cnt = start_cnt; + + ECORE_MSG("p->mcast_list_len=%d", p->mcast_list_len); + + switch (cmd) { + case ECORE_MCAST_CMD_ADD: + ecore_mcast_hdl_add(sc, o, p, &cnt); + break; + + case ECORE_MCAST_CMD_DEL: + ecore_mcast_hdl_del(sc, o, p, &cnt); + break; + + case ECORE_MCAST_CMD_RESTORE: + o->hdl_restore(sc, o, 0, &cnt); + break; + + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", cmd); + return ECORE_INVAL; + } + + /* The current command has been handled */ + p->mcast_list_len = 0; + + return cnt; +} + +static int ecore_mcast_validate_e2(__rte_unused struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd) +{ + struct ecore_mcast_obj *o = p->mcast_obj; + int reg_sz = o->get_registry_size(o); + + switch (cmd) { + /* DEL command deletes all currently configured MACs */ + case ECORE_MCAST_CMD_DEL: + o->set_registry_size(o, 0); + /* Don't break */ + + /* RESTORE command will restore the entire multicast configuration */ + case ECORE_MCAST_CMD_RESTORE: + /* Here we set the approximate amount of work to do, which in + * fact may be only less as some MACs in postponed ADD + * command(s) scheduled before this command may fall into + * the same bin and the actual number of bins set in the + * registry would be less than we estimated here. See + * ecore_mcast_set_one_rule_e2() for further details. + */ + p->mcast_list_len = reg_sz; + break; + + case ECORE_MCAST_CMD_ADD: + case ECORE_MCAST_CMD_CONT: + /* Here we assume that all new MACs will fall into new bins. + * However we will correct the real registry size after we + * handle all pending commands. + */ + o->set_registry_size(o, reg_sz + p->mcast_list_len); + break; + + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", cmd); + return ECORE_INVAL; + } + + /* Increase the total number of MACs pending to be configured */ + o->total_pending_num += p->mcast_list_len; + + return ECORE_SUCCESS; +} + +static void ecore_mcast_revert_e2(__rte_unused struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + int old_num_bins) +{ + struct ecore_mcast_obj *o = p->mcast_obj; + + o->set_registry_size(o, old_num_bins); + o->total_pending_num -= p->mcast_list_len; +} + +/** + * ecore_mcast_set_rdata_hdr_e2 - sets a header values + * + * @sc: device handle + * @p: + * @len: number of rules to handle + */ +static void ecore_mcast_set_rdata_hdr_e2(__rte_unused struct bnx2x_softc + *sc, struct ecore_mcast_ramrod_params + *p, uint8_t len) +{ + struct ecore_raw_obj *r = &p->mcast_obj->raw; + struct eth_multicast_rules_ramrod_data *data = + (struct eth_multicast_rules_ramrod_data *)(r->rdata); + + data->header.echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) | + (ECORE_FILTER_MCAST_PENDING << + ECORE_SWCID_SHIFT)); + data->header.rule_cnt = len; +} + +/** + * ecore_mcast_refresh_registry_e2 - recalculate the actual number of set bins + * + * @sc: device handle + * @o: + * + * Recalculate the actual number of set bins in the registry using Brian + * Kernighan's algorithm: it's execution complexity is as a number of set bins. + */ +static int ecore_mcast_refresh_registry_e2(struct ecore_mcast_obj *o) +{ + int i, cnt = 0; + uint64_t elem; + + for (i = 0; i < ECORE_MCAST_VEC_SZ; i++) { + elem = o->registry.aprox_match.vec[i]; + for (; elem; cnt++) + elem &= elem - 1; + } + + o->set_registry_size(o, cnt); + + return ECORE_SUCCESS; +} + +static int ecore_mcast_setup_e2(struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd) +{ + struct ecore_raw_obj *raw = &p->mcast_obj->raw; + struct ecore_mcast_obj *o = p->mcast_obj; + struct eth_multicast_rules_ramrod_data *data = + (struct eth_multicast_rules_ramrod_data *)(raw->rdata); + int cnt = 0, rc; + + /* Reset the ramrod data buffer */ + ECORE_MEMSET(data, 0, sizeof(*data)); + + cnt = ecore_mcast_handle_pending_cmds_e2(sc, p); + + /* If there are no more pending commands - clear SCHEDULED state */ + if (ECORE_LIST_IS_EMPTY(&o->pending_cmds_head)) + o->clear_sched(o); + + /* The below may be TRUE iff there was enough room in ramrod + * data for all pending commands and for the current + * command. Otherwise the current command would have been added + * to the pending commands and p->mcast_list_len would have been + * zeroed. + */ + if (p->mcast_list_len > 0) + cnt = ecore_mcast_handle_current_cmd(sc, p, cmd, cnt); + + /* We've pulled out some MACs - update the total number of + * outstanding. + */ + o->total_pending_num -= cnt; + + /* send a ramrod */ + ECORE_DBG_BREAK_IF(o->total_pending_num < 0); + ECORE_DBG_BREAK_IF(cnt > o->max_cmd_len); + + ecore_mcast_set_rdata_hdr_e2(sc, p, (uint8_t) cnt); + + /* Update a registry size if there are no more pending operations. + * + * We don't want to change the value of the registry size if there are + * pending operations because we want it to always be equal to the + * exact or the approximate number (see ecore_mcast_validate_e2()) of + * set bins after the last requested operation in order to properly + * evaluate the size of the next DEL/RESTORE operation. + * + * Note that we update the registry itself during command(s) handling + * - see ecore_mcast_set_one_rule_e2(). That's because for 57712 we + * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but + * with a limited amount of update commands (per MAC/bin) and we don't + * know in this scope what the actual state of bins configuration is + * going to be after this ramrod. + */ + if (!o->total_pending_num) + ecore_mcast_refresh_registry_e2(o); + + /* If CLEAR_ONLY was requested - don't send a ramrod and clear + * RAMROD_PENDING status immediately. + */ + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { + raw->clear_pending(raw); + return ECORE_SUCCESS; + } else { + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + /* Send a ramrod */ + rc = ecore_sp_post(sc, + RAMROD_CMD_ID_ETH_MULTICAST_RULES, + raw->cid, + raw->rdata_mapping, ETH_CONNECTION_TYPE); + if (rc) + return rc; + + /* Ramrod completion is pending */ + return ECORE_PENDING; + } +} + +static int ecore_mcast_validate_e1h(__rte_unused struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd) +{ + /* Mark, that there is a work to do */ + if ((cmd == ECORE_MCAST_CMD_DEL) || (cmd == ECORE_MCAST_CMD_RESTORE)) + p->mcast_list_len = 1; + + return ECORE_SUCCESS; +} + +static void ecore_mcast_revert_e1h(__rte_unused struct bnx2x_softc *sc, + __rte_unused struct ecore_mcast_ramrod_params + *p, __rte_unused int old_num_bins) +{ + /* Do nothing */ +} + +#define ECORE_57711_SET_MC_FILTER(filter, bit) \ +do { \ + (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \ +} while (0) + +static void ecore_mcast_hdl_add_e1h(struct bnx2x_softc *sc __rte_unused, + struct ecore_mcast_obj *o, + struct ecore_mcast_ramrod_params *p, + uint32_t * mc_filter) +{ + struct ecore_mcast_list_elem *mlist_pos; + int bit; + + ECORE_LIST_FOR_EACH_ENTRY(mlist_pos, &p->mcast_list, link, + struct ecore_mcast_list_elem) { + bit = ecore_mcast_bin_from_mac(mlist_pos->mac); + ECORE_57711_SET_MC_FILTER(mc_filter, bit); + + ECORE_MSG + ("About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC, bin %d", + mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2], + mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5], + bit); + + /* bookkeeping... */ + BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bit); + } +} + +static void ecore_mcast_hdl_restore_e1h(struct bnx2x_softc *sc + __rte_unused, + struct ecore_mcast_obj *o, + uint32_t * mc_filter) +{ + int bit; + + for (bit = ecore_mcast_get_next_bin(o, 0); + bit >= 0; bit = ecore_mcast_get_next_bin(o, bit + 1)) { + ECORE_57711_SET_MC_FILTER(mc_filter, bit); + ECORE_MSG("About to set bin %d", bit); + } +} + +/* On 57711 we write the multicast MACs' approximate match + * table by directly into the TSTORM's internal RAM. So we don't + * really need to handle any tricks to make it work. + */ +static int ecore_mcast_setup_e1h(struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd) +{ + int i; + struct ecore_mcast_obj *o = p->mcast_obj; + struct ecore_raw_obj *r = &o->raw; + + /* If CLEAR_ONLY has been requested - clear the registry + * and clear a pending bit. + */ + if (!ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) { + uint32_t mc_filter[ECORE_MC_HASH_SIZE] = { 0 }; + + /* Set the multicast filter bits before writing it into + * the internal memory. + */ + switch (cmd) { + case ECORE_MCAST_CMD_ADD: + ecore_mcast_hdl_add_e1h(sc, o, p, mc_filter); + break; + + case ECORE_MCAST_CMD_DEL: + ECORE_MSG(sc, + "Invalidating multicast MACs configuration"); + + /* clear the registry */ + ECORE_MEMSET(o->registry.aprox_match.vec, 0, + sizeof(o->registry.aprox_match.vec)); + break; + + case ECORE_MCAST_CMD_RESTORE: + ecore_mcast_hdl_restore_e1h(sc, o, mc_filter); + break; + + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", cmd); + return ECORE_INVAL; + } + + /* Set the mcast filter in the internal memory */ + for (i = 0; i < ECORE_MC_HASH_SIZE; i++) + REG_WR(sc, ECORE_MC_HASH_OFFSET(sc, i), mc_filter[i]); + } else + /* clear the registry */ + ECORE_MEMSET(o->registry.aprox_match.vec, 0, + sizeof(o->registry.aprox_match.vec)); + + /* We are done */ + r->clear_pending(r); + + return ECORE_SUCCESS; +} + +static int ecore_mcast_get_registry_size_aprox(struct ecore_mcast_obj *o) +{ + return o->registry.aprox_match.num_bins_set; +} + +static void ecore_mcast_set_registry_size_aprox(struct ecore_mcast_obj *o, + int n) +{ + o->registry.aprox_match.num_bins_set = n; +} + +int ecore_config_mcast(struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd) +{ + struct ecore_mcast_obj *o = p->mcast_obj; + struct ecore_raw_obj *r = &o->raw; + int rc = 0, old_reg_size; + + /* This is needed to recover number of currently configured mcast macs + * in case of failure. + */ + old_reg_size = o->get_registry_size(o); + + /* Do some calculations and checks */ + rc = o->validate(sc, p, cmd); + if (rc) + return rc; + + /* Return if there is no work to do */ + if ((!p->mcast_list_len) && (!o->check_sched(o))) + return ECORE_SUCCESS; + + ECORE_MSG + ("o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d", + o->total_pending_num, p->mcast_list_len, o->max_cmd_len); + + /* Enqueue the current command to the pending list if we can't complete + * it in the current iteration + */ + if (r->check_pending(r) || + ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) { + rc = o->enqueue_cmd(sc, p->mcast_obj, p, cmd); + if (rc < 0) + goto error_exit1; + + /* As long as the current command is in a command list we + * don't need to handle it separately. + */ + p->mcast_list_len = 0; + } + + if (!r->check_pending(r)) { + + /* Set 'pending' state */ + r->set_pending(r); + + /* Configure the new classification in the chip */ + rc = o->config_mcast(sc, p, cmd); + if (rc < 0) + goto error_exit2; + + /* Wait for a ramrod completion if was requested */ + if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) + rc = o->wait_comp(sc, o); + } + + return rc; + +error_exit2: + r->clear_pending(r); + +error_exit1: + o->revert(sc, p, old_reg_size); + + return rc; +} + +static void ecore_mcast_clear_sched(struct ecore_mcast_obj *o) +{ + ECORE_SMP_MB_BEFORE_CLEAR_BIT(); + ECORE_CLEAR_BIT(o->sched_state, o->raw.pstate); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); +} + +static void ecore_mcast_set_sched(struct ecore_mcast_obj *o) +{ + ECORE_SMP_MB_BEFORE_CLEAR_BIT(); + ECORE_SET_BIT(o->sched_state, o->raw.pstate); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); +} + +static int ecore_mcast_check_sched(struct ecore_mcast_obj *o) +{ + return ! !ECORE_TEST_BIT(o->sched_state, o->raw.pstate); +} + +static int ecore_mcast_check_pending(struct ecore_mcast_obj *o) +{ + return o->raw.check_pending(&o->raw) || o->check_sched(o); +} + +void ecore_init_mcast_obj(struct bnx2x_softc *sc, + struct ecore_mcast_obj *mcast_obj, + uint8_t mcast_cl_id, uint32_t mcast_cid, + uint8_t func_id, uint8_t engine_id, void *rdata, + ecore_dma_addr_t rdata_mapping, int state, + unsigned long *pstate, ecore_obj_type type) +{ + ECORE_MEMSET(mcast_obj, 0, sizeof(*mcast_obj)); + + ecore_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id, + rdata, rdata_mapping, state, pstate, type); + + mcast_obj->engine_id = engine_id; + + ECORE_LIST_INIT(&mcast_obj->pending_cmds_head); + + mcast_obj->sched_state = ECORE_FILTER_MCAST_SCHED; + mcast_obj->check_sched = ecore_mcast_check_sched; + mcast_obj->set_sched = ecore_mcast_set_sched; + mcast_obj->clear_sched = ecore_mcast_clear_sched; + + if (CHIP_IS_E1H(sc)) { + mcast_obj->config_mcast = ecore_mcast_setup_e1h; + mcast_obj->enqueue_cmd = NULL; + mcast_obj->hdl_restore = NULL; + mcast_obj->check_pending = ecore_mcast_check_pending; + + /* 57711 doesn't send a ramrod, so it has unlimited credit + * for one command. + */ + mcast_obj->max_cmd_len = -1; + mcast_obj->wait_comp = ecore_mcast_wait; + mcast_obj->set_one_rule = NULL; + mcast_obj->validate = ecore_mcast_validate_e1h; + mcast_obj->revert = ecore_mcast_revert_e1h; + mcast_obj->get_registry_size = + ecore_mcast_get_registry_size_aprox; + mcast_obj->set_registry_size = + ecore_mcast_set_registry_size_aprox; + } else { + mcast_obj->config_mcast = ecore_mcast_setup_e2; + mcast_obj->enqueue_cmd = ecore_mcast_enqueue_cmd; + mcast_obj->hdl_restore = ecore_mcast_handle_restore_cmd_e2; + mcast_obj->check_pending = ecore_mcast_check_pending; + mcast_obj->max_cmd_len = 16; + mcast_obj->wait_comp = ecore_mcast_wait; + mcast_obj->set_one_rule = ecore_mcast_set_one_rule_e2; + mcast_obj->validate = ecore_mcast_validate_e2; + mcast_obj->revert = ecore_mcast_revert_e2; + mcast_obj->get_registry_size = + ecore_mcast_get_registry_size_aprox; + mcast_obj->set_registry_size = + ecore_mcast_set_registry_size_aprox; + } +} + +/*************************** Credit handling **********************************/ + +/** + * atomic_add_ifless - add if the result is less than a given value. + * + * @v: pointer of type ecore_atomic_t + * @a: the amount to add to v... + * @u: ...if (v + a) is less than u. + * + * returns TRUE if (v + a) was less than u, and FALSE otherwise. + * + */ +static int __atomic_add_ifless(ecore_atomic_t * v, int a, int u) +{ + int c, old; + + c = ECORE_ATOMIC_READ(v); + for (;;) { + if (ECORE_UNLIKELY(c + a >= u)) + return FALSE; + + old = ECORE_ATOMIC_CMPXCHG((v), c, c + a); + if (ECORE_LIKELY(old == c)) + break; + c = old; + } + + return TRUE; +} + +/** + * atomic_dec_ifmoe - dec if the result is more or equal than a given value. + * + * @v: pointer of type ecore_atomic_t + * @a: the amount to dec from v... + * @u: ...if (v - a) is more or equal than u. + * + * returns TRUE if (v - a) was more or equal than u, and FALSE + * otherwise. + */ +static int __atomic_dec_ifmoe(ecore_atomic_t * v, int a, int u) +{ + int c, old; + + c = ECORE_ATOMIC_READ(v); + for (;;) { + if (ECORE_UNLIKELY(c - a < u)) + return FALSE; + + old = ECORE_ATOMIC_CMPXCHG((v), c, c - a); + if (ECORE_LIKELY(old == c)) + break; + c = old; + } + + return TRUE; +} + +static int ecore_credit_pool_get(struct ecore_credit_pool_obj *o, int cnt) +{ + int rc; + + ECORE_SMP_MB(); + rc = __atomic_dec_ifmoe(&o->credit, cnt, 0); + ECORE_SMP_MB(); + + return rc; +} + +static int ecore_credit_pool_put(struct ecore_credit_pool_obj *o, int cnt) +{ + int rc; + + ECORE_SMP_MB(); + + /* Don't let to refill if credit + cnt > pool_sz */ + rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1); + + ECORE_SMP_MB(); + + return rc; +} + +static int ecore_credit_pool_check(struct ecore_credit_pool_obj *o) +{ + int cur_credit; + + ECORE_SMP_MB(); + cur_credit = ECORE_ATOMIC_READ(&o->credit); + + return cur_credit; +} + +static int ecore_credit_pool_always_TRUE(__rte_unused struct + ecore_credit_pool_obj *o, + __rte_unused int cnt) +{ + return TRUE; +} + +static int ecore_credit_pool_get_entry(struct ecore_credit_pool_obj *o, + int *offset) +{ + int idx, vec, i; + + *offset = -1; + + /* Find "internal cam-offset" then add to base for this object... */ + for (vec = 0; vec < ECORE_POOL_VEC_SIZE; vec++) { + + /* Skip the current vector if there are no free entries in it */ + if (!o->pool_mirror[vec]) + continue; + + /* If we've got here we are going to find a free entry */ + for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0; + i < BIT_VEC64_ELEM_SZ; idx++, i++) + + if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) { + /* Got one!! */ + BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx); + *offset = o->base_pool_offset + idx; + return TRUE; + } + } + + return FALSE; +} + +static int ecore_credit_pool_put_entry(struct ecore_credit_pool_obj *o, + int offset) +{ + if (offset < o->base_pool_offset) + return FALSE; + + offset -= o->base_pool_offset; + + if (offset >= o->pool_sz) + return FALSE; + + /* Return the entry to the pool */ + BIT_VEC64_SET_BIT(o->pool_mirror, offset); + + return TRUE; +} + +static int ecore_credit_pool_put_entry_always_TRUE(__rte_unused struct + ecore_credit_pool_obj *o, + __rte_unused int offset) +{ + return TRUE; +} + +static int ecore_credit_pool_get_entry_always_TRUE(__rte_unused struct + ecore_credit_pool_obj *o, + __rte_unused int *offset) +{ + *offset = -1; + return TRUE; +} + +/** + * ecore_init_credit_pool - initialize credit pool internals. + * + * @p: + * @base: Base entry in the CAM to use. + * @credit: pool size. + * + * If base is negative no CAM entries handling will be performed. + * If credit is negative pool operations will always succeed (unlimited pool). + * + */ +static void ecore_init_credit_pool(struct ecore_credit_pool_obj *p, + int base, int credit) +{ + /* Zero the object first */ + ECORE_MEMSET(p, 0, sizeof(*p)); + + /* Set the table to all 1s */ + ECORE_MEMSET(&p->pool_mirror, 0xff, sizeof(p->pool_mirror)); + + /* Init a pool as full */ + ECORE_ATOMIC_SET(&p->credit, credit); + + /* The total poll size */ + p->pool_sz = credit; + + p->base_pool_offset = base; + + /* Commit the change */ + ECORE_SMP_MB(); + + p->check = ecore_credit_pool_check; + + /* if pool credit is negative - disable the checks */ + if (credit >= 0) { + p->put = ecore_credit_pool_put; + p->get = ecore_credit_pool_get; + p->put_entry = ecore_credit_pool_put_entry; + p->get_entry = ecore_credit_pool_get_entry; + } else { + p->put = ecore_credit_pool_always_TRUE; + p->get = ecore_credit_pool_always_TRUE; + p->put_entry = ecore_credit_pool_put_entry_always_TRUE; + p->get_entry = ecore_credit_pool_get_entry_always_TRUE; + } + + /* If base is negative - disable entries handling */ + if (base < 0) { + p->put_entry = ecore_credit_pool_put_entry_always_TRUE; + p->get_entry = ecore_credit_pool_get_entry_always_TRUE; + } +} + +void ecore_init_mac_credit_pool(struct bnx2x_softc *sc, + struct ecore_credit_pool_obj *p, + uint8_t func_id, uint8_t func_num) +{ + +#define ECORE_CAM_SIZE_EMUL 5 + + int cam_sz; + + if (CHIP_IS_E1H(sc)) { + /* CAM credit is equally divided between all active functions + * on the PORT!. + */ + if ((func_num > 0)) { + if (!CHIP_REV_IS_SLOW(sc)) + cam_sz = (MAX_MAC_CREDIT_E1H / (2 * func_num)); + else + cam_sz = ECORE_CAM_SIZE_EMUL; + ecore_init_credit_pool(p, func_id * cam_sz, cam_sz); + } else { + /* this should never happen! Block MAC operations. */ + ecore_init_credit_pool(p, 0, 0); + } + + } else { + + /* + * CAM credit is equaly divided between all active functions + * on the PATH. + */ + if ((func_num > 0)) { + if (!CHIP_REV_IS_SLOW(sc)) + cam_sz = (MAX_MAC_CREDIT_E2 / func_num); + else + cam_sz = ECORE_CAM_SIZE_EMUL; + + /* No need for CAM entries handling for 57712 and + * newer. + */ + ecore_init_credit_pool(p, -1, cam_sz); + } else { + /* this should never happen! Block MAC operations. */ + ecore_init_credit_pool(p, 0, 0); + } + } +} + +void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc, + struct ecore_credit_pool_obj *p, + uint8_t func_id, uint8_t func_num) +{ + if (CHIP_IS_E1x(sc)) { + /* There is no VLAN credit in HW on 57711 only + * MAC / MAC-VLAN can be set + */ + ecore_init_credit_pool(p, 0, -1); + } else { + /* CAM credit is equally divided between all active functions + * on the PATH. + */ + if (func_num > 0) { + int credit = MAX_VLAN_CREDIT_E2 / func_num; + ecore_init_credit_pool(p, func_id * credit, credit); + } else + /* this should never happen! Block VLAN operations. */ + ecore_init_credit_pool(p, 0, 0); + } +} + +/****************** RSS Configuration ******************/ + +/** + * ecore_setup_rss - configure RSS + * + * @sc: device handle + * @p: rss configuration + * + * sends on UPDATE ramrod for that matter. + */ +static int ecore_setup_rss(struct bnx2x_softc *sc, + struct ecore_config_rss_params *p) +{ + struct ecore_rss_config_obj *o = p->rss_obj; + struct ecore_raw_obj *r = &o->raw; + struct eth_rss_update_ramrod_data *data = + (struct eth_rss_update_ramrod_data *)(r->rdata); + uint8_t rss_mode = 0; + int rc; + + ECORE_MEMSET(data, 0, sizeof(*data)); + + ECORE_MSG("Configuring RSS"); + + /* Set an echo field */ + data->echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) | + (r->state << ECORE_SWCID_SHIFT)); + + /* RSS mode */ + if (ECORE_TEST_BIT(ECORE_RSS_MODE_DISABLED, &p->rss_flags)) + rss_mode = ETH_RSS_MODE_DISABLED; + else if (ECORE_TEST_BIT(ECORE_RSS_MODE_REGULAR, &p->rss_flags)) + rss_mode = ETH_RSS_MODE_REGULAR; + + data->rss_mode = rss_mode; + + ECORE_MSG("rss_mode=%d", rss_mode); + + /* RSS capabilities */ + if (ECORE_TEST_BIT(ECORE_RSS_IPV4, &p->rss_flags)) + data->capabilities |= + ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY; + + if (ECORE_TEST_BIT(ECORE_RSS_IPV4_TCP, &p->rss_flags)) + data->capabilities |= + ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY; + + if (ECORE_TEST_BIT(ECORE_RSS_IPV4_UDP, &p->rss_flags)) + data->capabilities |= + ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY; + + if (ECORE_TEST_BIT(ECORE_RSS_IPV6, &p->rss_flags)) + data->capabilities |= + ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY; + + if (ECORE_TEST_BIT(ECORE_RSS_IPV6_TCP, &p->rss_flags)) + data->capabilities |= + ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY; + + if (ECORE_TEST_BIT(ECORE_RSS_IPV6_UDP, &p->rss_flags)) + data->capabilities |= + ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY; + + if (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) { + data->udp_4tuple_dst_port_mask = + ECORE_CPU_TO_LE16(p->tunnel_mask); + data->udp_4tuple_dst_port_value = + ECORE_CPU_TO_LE16(p->tunnel_value); + } + + /* Hashing mask */ + data->rss_result_mask = p->rss_result_mask; + + /* RSS engine ID */ + data->rss_engine_id = o->engine_id; + + ECORE_MSG("rss_engine_id=%d", data->rss_engine_id); + + /* Indirection table */ + ECORE_MEMCPY(data->indirection_table, p->ind_table, + T_ETH_INDIRECTION_TABLE_SIZE); + + /* Remember the last configuration */ + ECORE_MEMCPY(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE); + + /* RSS keys */ + if (ECORE_TEST_BIT(ECORE_RSS_SET_SRCH, &p->rss_flags)) { + ECORE_MEMCPY(&data->rss_key[0], &p->rss_key[0], + sizeof(data->rss_key)); + data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY; + } + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + /* Send a ramrod */ + rc = ecore_sp_post(sc, + RAMROD_CMD_ID_ETH_RSS_UPDATE, + r->cid, r->rdata_mapping, ETH_CONNECTION_TYPE); + + if (rc < 0) + return rc; + + return ECORE_PENDING; +} + +int ecore_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *p) +{ + int rc; + struct ecore_rss_config_obj *o = p->rss_obj; + struct ecore_raw_obj *r = &o->raw; + + /* Do nothing if only driver cleanup was requested */ + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) + return ECORE_SUCCESS; + + r->set_pending(r); + + rc = o->config_rss(sc, p); + if (rc < 0) { + r->clear_pending(r); + return rc; + } + + if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) + rc = r->wait_comp(sc, r); + + return rc; +} + +void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj, + uint8_t cl_id, uint32_t cid, uint8_t func_id, + uint8_t engine_id, void *rdata, + ecore_dma_addr_t rdata_mapping, int state, + unsigned long *pstate, ecore_obj_type type) +{ + ecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata, + rdata_mapping, state, pstate, type); + + rss_obj->engine_id = engine_id; + rss_obj->config_rss = ecore_setup_rss; +} + +/********************** Queue state object ***********************************/ + +/** + * ecore_queue_state_change - perform Queue state change transition + * + * @sc: device handle + * @params: parameters to perform the transition + * + * returns 0 in case of successfully completed transition, negative error + * code in case of failure, positive (EBUSY) value if there is a completion + * to that is still pending (possible only if RAMROD_COMP_WAIT is + * not set in params->ramrod_flags for asynchronous commands). + * + */ +int ecore_queue_state_change(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + int rc, pending_bit; + unsigned long *pending = &o->pending; + + /* Check that the requested transition is legal */ + rc = o->check_transition(sc, o, params); + if (rc) { + PMD_DRV_LOG(ERR, "check transition returned an error. rc %d", + rc); + return ECORE_INVAL; + } + + /* Set "pending" bit */ + ECORE_MSG("pending bit was=%lx", o->pending); + pending_bit = o->set_pending(o, params); + ECORE_MSG("pending bit now=%lx", o->pending); + + /* Don't send a command if only driver cleanup was requested */ + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) + o->complete_cmd(sc, o, pending_bit); + else { + /* Send a ramrod */ + rc = o->send_cmd(sc, params); + if (rc) { + o->next_state = ECORE_Q_STATE_MAX; + ECORE_CLEAR_BIT(pending_bit, pending); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); + return rc; + } + + if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { + rc = o->wait_comp(sc, o, pending_bit); + if (rc) + return rc; + + return ECORE_SUCCESS; + } + } + + return ECORE_RET_PENDING(pending_bit, pending); +} + +static int ecore_queue_set_pending(struct ecore_queue_sp_obj *obj, + struct ecore_queue_state_params *params) +{ + enum ecore_queue_cmd cmd = params->cmd, bit; + + /* ACTIVATE and DEACTIVATE commands are implemented on top of + * UPDATE command. + */ + if ((cmd == ECORE_Q_CMD_ACTIVATE) || (cmd == ECORE_Q_CMD_DEACTIVATE)) + bit = ECORE_Q_CMD_UPDATE; + else + bit = cmd; + + ECORE_SET_BIT(bit, &obj->pending); + return bit; +} + +static int ecore_queue_wait_comp(struct bnx2x_softc *sc, + struct ecore_queue_sp_obj *o, + enum ecore_queue_cmd cmd) +{ + return ecore_state_wait(sc, cmd, &o->pending); +} + +/** + * ecore_queue_comp_cmd - complete the state change command. + * + * @sc: device handle + * @o: + * @cmd: + * + * Checks that the arrived completion is expected. + */ +static int ecore_queue_comp_cmd(struct bnx2x_softc *sc __rte_unused, + struct ecore_queue_sp_obj *o, + enum ecore_queue_cmd cmd) +{ + unsigned long cur_pending = o->pending; + + if (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) { + PMD_DRV_LOG(ERR, + "Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d", + cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->state, + cur_pending, o->next_state); + return ECORE_INVAL; + } + + if (o->next_tx_only >= o->max_cos) + /* >= because tx only must always be smaller than cos since the + * primary connection supports COS 0 + */ + PMD_DRV_LOG(ERR, + "illegal value for next tx_only: %d. max cos was %d", + o->next_tx_only, o->max_cos); + + ECORE_MSG(sc, + "Completing command %d for queue %d, setting state to %d", + cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->next_state); + + if (o->next_tx_only) /* print num tx-only if any exist */ + ECORE_MSG("primary cid %d: num tx-only cons %d", + o->cids[ECORE_PRIMARY_CID_INDEX], o->next_tx_only); + + o->state = o->next_state; + o->num_tx_only = o->next_tx_only; + o->next_state = ECORE_Q_STATE_MAX; + + /* It's important that o->state and o->next_state are + * updated before o->pending. + */ + wmb(); + + ECORE_CLEAR_BIT(cmd, &o->pending); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); + + return ECORE_SUCCESS; +} + +static void ecore_q_fill_setup_data_e2(struct ecore_queue_state_params + *cmd_params, + struct client_init_ramrod_data *data) +{ + struct ecore_queue_setup_params *params = &cmd_params->params.setup; + + /* Rx data */ + + /* IPv6 TPA supported for E2 and above only */ + data->rx.tpa_en |= ECORE_TEST_BIT(ECORE_Q_FLG_TPA_IPV6, + ¶ms->flags) * + CLIENT_INIT_RX_DATA_TPA_EN_IPV6; +} + +static void ecore_q_fill_init_general_data(struct bnx2x_softc *sc __rte_unused, + struct ecore_queue_sp_obj *o, + struct ecore_general_setup_params + *params, struct client_init_general_data + *gen_data, unsigned long *flags) +{ + gen_data->client_id = o->cl_id; + + if (ECORE_TEST_BIT(ECORE_Q_FLG_STATS, flags)) { + gen_data->statistics_counter_id = params->stat_id; + gen_data->statistics_en_flg = 1; + gen_data->statistics_zero_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_ZERO_STATS, flags); + } else + gen_data->statistics_counter_id = + DISABLE_STATISTIC_COUNTER_ID_VALUE; + + gen_data->is_fcoe_flg = ECORE_TEST_BIT(ECORE_Q_FLG_FCOE, flags); + gen_data->activate_flg = ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE, flags); + gen_data->sp_client_id = params->spcl_id; + gen_data->mtu = ECORE_CPU_TO_LE16(params->mtu); + gen_data->func_id = o->func_id; + + gen_data->cos = params->cos; + + gen_data->traffic_type = + ECORE_TEST_BIT(ECORE_Q_FLG_FCOE, flags) ? + LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW; + + ECORE_MSG("flags: active %d, cos %d, stats en %d", + gen_data->activate_flg, gen_data->cos, + gen_data->statistics_en_flg); +} + +static void ecore_q_fill_init_tx_data(struct ecore_txq_setup_params *params, + struct client_init_tx_data *tx_data, + unsigned long *flags) +{ + tx_data->enforce_security_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_TX_SEC, flags); + tx_data->default_vlan = ECORE_CPU_TO_LE16(params->default_vlan); + tx_data->default_vlan_flg = ECORE_TEST_BIT(ECORE_Q_FLG_DEF_VLAN, flags); + tx_data->tx_switching_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_TX_SWITCH, flags); + tx_data->anti_spoofing_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_ANTI_SPOOF, flags); + tx_data->force_default_pri_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_FORCE_DEFAULT_PRI, flags); + tx_data->refuse_outband_vlan_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, flags); + tx_data->tunnel_non_lso_pcsum_location = + ECORE_TEST_BIT(ECORE_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT : + CSUM_ON_BD; + + tx_data->tx_status_block_id = params->fw_sb_id; + tx_data->tx_sb_index_number = params->sb_cq_index; + tx_data->tss_leading_client_id = params->tss_leading_cl_id; + + tx_data->tx_bd_page_base.lo = + ECORE_CPU_TO_LE32(U64_LO(params->dscr_map)); + tx_data->tx_bd_page_base.hi = + ECORE_CPU_TO_LE32(U64_HI(params->dscr_map)); + + /* Don't configure any Tx switching mode during queue SETUP */ + tx_data->state = 0; +} + +static void ecore_q_fill_init_pause_data(struct rxq_pause_params *params, + struct client_init_rx_data *rx_data) +{ + /* flow control data */ + rx_data->cqe_pause_thr_low = ECORE_CPU_TO_LE16(params->rcq_th_lo); + rx_data->cqe_pause_thr_high = ECORE_CPU_TO_LE16(params->rcq_th_hi); + rx_data->bd_pause_thr_low = ECORE_CPU_TO_LE16(params->bd_th_lo); + rx_data->bd_pause_thr_high = ECORE_CPU_TO_LE16(params->bd_th_hi); + rx_data->sge_pause_thr_low = ECORE_CPU_TO_LE16(params->sge_th_lo); + rx_data->sge_pause_thr_high = ECORE_CPU_TO_LE16(params->sge_th_hi); + rx_data->rx_cos_mask = ECORE_CPU_TO_LE16(params->pri_map); +} + +static void ecore_q_fill_init_rx_data(struct ecore_rxq_setup_params *params, + struct client_init_rx_data *rx_data, + unsigned long *flags) +{ + rx_data->tpa_en = ECORE_TEST_BIT(ECORE_Q_FLG_TPA, flags) * + CLIENT_INIT_RX_DATA_TPA_EN_IPV4; + rx_data->tpa_en |= ECORE_TEST_BIT(ECORE_Q_FLG_TPA_GRO, flags) * + CLIENT_INIT_RX_DATA_TPA_MODE; + rx_data->vmqueue_mode_en_flg = 0; + + rx_data->extra_data_over_sgl_en_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_OOO, flags); + rx_data->cache_line_alignment_log_size = params->cache_line_log; + rx_data->enable_dynamic_hc = ECORE_TEST_BIT(ECORE_Q_FLG_DHC, flags); + rx_data->client_qzone_id = params->cl_qzone_id; + rx_data->max_agg_size = ECORE_CPU_TO_LE16(params->tpa_agg_sz); + + /* Always start in DROP_ALL mode */ + rx_data->state = ECORE_CPU_TO_LE16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL | + CLIENT_INIT_RX_DATA_MCAST_DROP_ALL); + + /* We don't set drop flags */ + rx_data->drop_ip_cs_err_flg = 0; + rx_data->drop_tcp_cs_err_flg = 0; + rx_data->drop_ttl0_flg = 0; + rx_data->drop_udp_cs_err_flg = 0; + rx_data->inner_vlan_removal_enable_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_VLAN, flags); + rx_data->outer_vlan_removal_enable_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_OV, flags); + rx_data->status_block_id = params->fw_sb_id; + rx_data->rx_sb_index_number = params->sb_cq_index; + rx_data->max_tpa_queues = params->max_tpa_queues; + rx_data->max_bytes_on_bd = ECORE_CPU_TO_LE16(params->buf_sz); + rx_data->bd_page_base.lo = ECORE_CPU_TO_LE32(U64_LO(params->dscr_map)); + rx_data->bd_page_base.hi = ECORE_CPU_TO_LE32(U64_HI(params->dscr_map)); + rx_data->cqe_page_base.lo = ECORE_CPU_TO_LE32(U64_LO(params->rcq_map)); + rx_data->cqe_page_base.hi = ECORE_CPU_TO_LE32(U64_HI(params->rcq_map)); + rx_data->is_leading_rss = ECORE_TEST_BIT(ECORE_Q_FLG_LEADING_RSS, + flags); + + if (ECORE_TEST_BIT(ECORE_Q_FLG_MCAST, flags)) { + rx_data->approx_mcast_engine_id = params->mcast_engine_id; + rx_data->is_approx_mcast = 1; + } + + rx_data->rss_engine_id = params->rss_engine_id; + + /* silent vlan removal */ + rx_data->silent_vlan_removal_flg = + ECORE_TEST_BIT(ECORE_Q_FLG_SILENT_VLAN_REM, flags); + rx_data->silent_vlan_value = + ECORE_CPU_TO_LE16(params->silent_removal_value); + rx_data->silent_vlan_mask = + ECORE_CPU_TO_LE16(params->silent_removal_mask); +} + +/* initialize the general, tx and rx parts of a queue object */ +static void ecore_q_fill_setup_data_cmn(struct bnx2x_softc *sc, struct ecore_queue_state_params + *cmd_params, + struct client_init_ramrod_data *data) +{ + ecore_q_fill_init_general_data(sc, cmd_params->q_obj, + &cmd_params->params.setup.gen_params, + &data->general, + &cmd_params->params.setup.flags); + + ecore_q_fill_init_tx_data(&cmd_params->params.setup.txq_params, + &data->tx, &cmd_params->params.setup.flags); + + ecore_q_fill_init_rx_data(&cmd_params->params.setup.rxq_params, + &data->rx, &cmd_params->params.setup.flags); + + ecore_q_fill_init_pause_data(&cmd_params->params.setup.pause_params, + &data->rx); +} + +/* initialize the general and tx parts of a tx-only queue object */ +static void ecore_q_fill_setup_tx_only(struct bnx2x_softc *sc, struct ecore_queue_state_params + *cmd_params, + struct tx_queue_init_ramrod_data *data) +{ + ecore_q_fill_init_general_data(sc, cmd_params->q_obj, + &cmd_params->params.tx_only.gen_params, + &data->general, + &cmd_params->params.tx_only.flags); + + ecore_q_fill_init_tx_data(&cmd_params->params.tx_only.txq_params, + &data->tx, &cmd_params->params.tx_only.flags); + + ECORE_MSG("cid %d, tx bd page lo %x hi %x", + cmd_params->q_obj->cids[0], + data->tx.tx_bd_page_base.lo, data->tx.tx_bd_page_base.hi); +} + +/** + * ecore_q_init - init HW/FW queue + * + * @sc: device handle + * @params: + * + * HW/FW initial Queue configuration: + * - HC: Rx and Tx + * - CDU context validation + * + */ +static int ecore_q_init(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + struct ecore_queue_init_params *init = ¶ms->params.init; + uint16_t hc_usec; + uint8_t cos; + + /* Tx HC configuration */ + if (ECORE_TEST_BIT(ECORE_Q_TYPE_HAS_TX, &o->type) && + ECORE_TEST_BIT(ECORE_Q_FLG_HC, &init->tx.flags)) { + hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0; + + ECORE_UPDATE_COALESCE_SB_INDEX(sc, init->tx.fw_sb_id, + init->tx.sb_cq_index, + !ECORE_TEST_BIT + (ECORE_Q_FLG_HC_EN, + &init->tx.flags), hc_usec); + } + + /* Rx HC configuration */ + if (ECORE_TEST_BIT(ECORE_Q_TYPE_HAS_RX, &o->type) && + ECORE_TEST_BIT(ECORE_Q_FLG_HC, &init->rx.flags)) { + hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0; + + ECORE_UPDATE_COALESCE_SB_INDEX(sc, init->rx.fw_sb_id, + init->rx.sb_cq_index, + !ECORE_TEST_BIT + (ECORE_Q_FLG_HC_EN, + &init->rx.flags), hc_usec); + } + + /* Set CDU context validation values */ + for (cos = 0; cos < o->max_cos; cos++) { + ECORE_MSG("setting context validation. cid %d, cos %d", + o->cids[cos], cos); + ECORE_MSG("context pointer %p", init->cxts[cos]); + ECORE_SET_CTX_VALIDATION(sc, init->cxts[cos], o->cids[cos]); + } + + /* As no ramrod is sent, complete the command immediately */ + o->complete_cmd(sc, o, ECORE_Q_CMD_INIT); + + ECORE_MMIOWB(); + ECORE_SMP_MB(); + + return ECORE_SUCCESS; +} + +static int ecore_q_send_setup_e1x(struct bnx2x_softc *sc, struct ecore_queue_state_params + *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + struct client_init_ramrod_data *rdata = + (struct client_init_ramrod_data *)o->rdata; + ecore_dma_addr_t data_mapping = o->rdata_mapping; + int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; + + /* Clear the ramrod data */ + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data */ + ecore_q_fill_setup_data_cmn(sc, params, rdata); + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + return ecore_sp_post(sc, + ramrod, + o->cids[ECORE_PRIMARY_CID_INDEX], + data_mapping, ETH_CONNECTION_TYPE); +} + +static int ecore_q_send_setup_e2(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + struct client_init_ramrod_data *rdata = + (struct client_init_ramrod_data *)o->rdata; + ecore_dma_addr_t data_mapping = o->rdata_mapping; + int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP; + + /* Clear the ramrod data */ + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data */ + ecore_q_fill_setup_data_cmn(sc, params, rdata); + ecore_q_fill_setup_data_e2(params, rdata); + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + return ecore_sp_post(sc, + ramrod, + o->cids[ECORE_PRIMARY_CID_INDEX], + data_mapping, ETH_CONNECTION_TYPE); +} + +static int ecore_q_send_setup_tx_only(struct bnx2x_softc *sc, struct ecore_queue_state_params + *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + struct tx_queue_init_ramrod_data *rdata = + (struct tx_queue_init_ramrod_data *)o->rdata; + ecore_dma_addr_t data_mapping = o->rdata_mapping; + int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP; + struct ecore_queue_setup_tx_only_params *tx_only_params = + ¶ms->params.tx_only; + uint8_t cid_index = tx_only_params->cid_index; + + if (ECORE_TEST_BIT(ECORE_Q_TYPE_FWD, &o->type)) + ramrod = RAMROD_CMD_ID_ETH_FORWARD_SETUP; + ECORE_MSG("sending forward tx-only ramrod"); + + if (cid_index >= o->max_cos) { + PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range", + o->cl_id, cid_index); + return ECORE_INVAL; + } + + ECORE_MSG("parameters received: cos: %d sp-id: %d", + tx_only_params->gen_params.cos, + tx_only_params->gen_params.spcl_id); + + /* Clear the ramrod data */ + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data */ + ecore_q_fill_setup_tx_only(sc, params, rdata); + + ECORE_MSG + ("sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d", + o->cids[cid_index], rdata->general.client_id, + rdata->general.sp_client_id, rdata->general.cos); + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + return ecore_sp_post(sc, ramrod, o->cids[cid_index], + data_mapping, ETH_CONNECTION_TYPE); +} + +static void ecore_q_fill_update_data(struct ecore_queue_sp_obj *obj, + struct ecore_queue_update_params *params, + struct client_update_ramrod_data *data) +{ + /* Client ID of the client to update */ + data->client_id = obj->cl_id; + + /* Function ID of the client to update */ + data->func_id = obj->func_id; + + /* Default VLAN value */ + data->default_vlan = ECORE_CPU_TO_LE16(params->def_vlan); + + /* Inner VLAN stripping */ + data->inner_vlan_removal_enable_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags); + data->inner_vlan_removal_change_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, + ¶ms->update_flags); + + /* Outer VLAN stripping */ + data->outer_vlan_removal_enable_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags); + data->outer_vlan_removal_change_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, + ¶ms->update_flags); + + /* Drop packets that have source MAC that doesn't belong to this + * Queue. + */ + data->anti_spoofing_enable_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags); + data->anti_spoofing_change_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, + ¶ms->update_flags); + + /* Activate/Deactivate */ + data->activate_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE, ¶ms->update_flags); + data->activate_change_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags); + + /* Enable default VLAN */ + data->default_vlan_enable_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags); + data->default_vlan_change_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, + ¶ms->update_flags); + + /* silent vlan removal */ + data->silent_vlan_change_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, + ¶ms->update_flags); + data->silent_vlan_removal_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_SILENT_VLAN_REM, + ¶ms->update_flags); + data->silent_vlan_value = + ECORE_CPU_TO_LE16(params->silent_removal_value); + data->silent_vlan_mask = ECORE_CPU_TO_LE16(params->silent_removal_mask); + + /* tx switching */ + data->tx_switching_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_TX_SWITCHING, ¶ms->update_flags); + data->tx_switching_change_flg = + ECORE_TEST_BIT(ECORE_Q_UPDATE_TX_SWITCHING_CHNG, + ¶ms->update_flags); +} + +static int ecore_q_send_update(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + struct client_update_ramrod_data *rdata = + (struct client_update_ramrod_data *)o->rdata; + ecore_dma_addr_t data_mapping = o->rdata_mapping; + struct ecore_queue_update_params *update_params = + ¶ms->params.update; + uint8_t cid_index = update_params->cid_index; + + if (cid_index >= o->max_cos) { + PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range", + o->cl_id, cid_index); + return ECORE_INVAL; + } + + /* Clear the ramrod data */ + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data */ + ecore_q_fill_update_data(o, update_params, rdata); + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + return ecore_sp_post(sc, RAMROD_CMD_ID_ETH_CLIENT_UPDATE, + o->cids[cid_index], data_mapping, + ETH_CONNECTION_TYPE); +} + +/** + * ecore_q_send_deactivate - send DEACTIVATE command + * + * @sc: device handle + * @params: + * + * implemented using the UPDATE command. + */ +static int ecore_q_send_deactivate(struct bnx2x_softc *sc, struct ecore_queue_state_params + *params) +{ + struct ecore_queue_update_params *update = ¶ms->params.update; + + ECORE_MEMSET(update, 0, sizeof(*update)); + + ECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); + + return ecore_q_send_update(sc, params); +} + +/** + * ecore_q_send_activate - send ACTIVATE command + * + * @sc: device handle + * @params: + * + * implemented using the UPDATE command. + */ +static int ecore_q_send_activate(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_update_params *update = ¶ms->params.update; + + ECORE_MEMSET(update, 0, sizeof(*update)); + + ECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE, &update->update_flags); + ECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags); + + return ecore_q_send_update(sc, params); +} + +static int ecore_q_send_update_tpa(__rte_unused struct bnx2x_softc *sc, + __rte_unused struct + ecore_queue_state_params *params) +{ + /* Not implemented yet. */ + return -1; +} + +static int ecore_q_send_halt(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + + /* build eth_halt_ramrod_data.client_id in a big-endian friendly way */ + ecore_dma_addr_t data_mapping = 0; + data_mapping = (ecore_dma_addr_t) o->cl_id; + + return ecore_sp_post(sc, + RAMROD_CMD_ID_ETH_HALT, + o->cids[ECORE_PRIMARY_CID_INDEX], + data_mapping, ETH_CONNECTION_TYPE); +} + +static int ecore_q_send_cfc_del(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + uint8_t cid_idx = params->params.cfc_del.cid_index; + + if (cid_idx >= o->max_cos) { + PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range", + o->cl_id, cid_idx); + return ECORE_INVAL; + } + + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_CFC_DEL, + o->cids[cid_idx], 0, NONE_CONNECTION_TYPE); +} + +static int ecore_q_send_terminate(struct bnx2x_softc *sc, struct ecore_queue_state_params + *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + uint8_t cid_index = params->params.terminate.cid_index; + + if (cid_index >= o->max_cos) { + PMD_DRV_LOG(ERR, "queue[%d]: cid_index (%d) is out of range", + o->cl_id, cid_index); + return ECORE_INVAL; + } + + return ecore_sp_post(sc, RAMROD_CMD_ID_ETH_TERMINATE, + o->cids[cid_index], 0, ETH_CONNECTION_TYPE); +} + +static int ecore_q_send_empty(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + struct ecore_queue_sp_obj *o = params->q_obj; + + return ecore_sp_post(sc, RAMROD_CMD_ID_ETH_EMPTY, + o->cids[ECORE_PRIMARY_CID_INDEX], 0, + ETH_CONNECTION_TYPE); +} + +static int ecore_queue_send_cmd_cmn(struct bnx2x_softc *sc, struct ecore_queue_state_params + *params) +{ + switch (params->cmd) { + case ECORE_Q_CMD_INIT: + return ecore_q_init(sc, params); + case ECORE_Q_CMD_SETUP_TX_ONLY: + return ecore_q_send_setup_tx_only(sc, params); + case ECORE_Q_CMD_DEACTIVATE: + return ecore_q_send_deactivate(sc, params); + case ECORE_Q_CMD_ACTIVATE: + return ecore_q_send_activate(sc, params); + case ECORE_Q_CMD_UPDATE: + return ecore_q_send_update(sc, params); + case ECORE_Q_CMD_UPDATE_TPA: + return ecore_q_send_update_tpa(sc, params); + case ECORE_Q_CMD_HALT: + return ecore_q_send_halt(sc, params); + case ECORE_Q_CMD_CFC_DEL: + return ecore_q_send_cfc_del(sc, params); + case ECORE_Q_CMD_TERMINATE: + return ecore_q_send_terminate(sc, params); + case ECORE_Q_CMD_EMPTY: + return ecore_q_send_empty(sc, params); + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd); + return ECORE_INVAL; + } +} + +static int ecore_queue_send_cmd_e1x(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + switch (params->cmd) { + case ECORE_Q_CMD_SETUP: + return ecore_q_send_setup_e1x(sc, params); + case ECORE_Q_CMD_INIT: + case ECORE_Q_CMD_SETUP_TX_ONLY: + case ECORE_Q_CMD_DEACTIVATE: + case ECORE_Q_CMD_ACTIVATE: + case ECORE_Q_CMD_UPDATE: + case ECORE_Q_CMD_UPDATE_TPA: + case ECORE_Q_CMD_HALT: + case ECORE_Q_CMD_CFC_DEL: + case ECORE_Q_CMD_TERMINATE: + case ECORE_Q_CMD_EMPTY: + return ecore_queue_send_cmd_cmn(sc, params); + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd); + return ECORE_INVAL; + } +} + +static int ecore_queue_send_cmd_e2(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params) +{ + switch (params->cmd) { + case ECORE_Q_CMD_SETUP: + return ecore_q_send_setup_e2(sc, params); + case ECORE_Q_CMD_INIT: + case ECORE_Q_CMD_SETUP_TX_ONLY: + case ECORE_Q_CMD_DEACTIVATE: + case ECORE_Q_CMD_ACTIVATE: + case ECORE_Q_CMD_UPDATE: + case ECORE_Q_CMD_UPDATE_TPA: + case ECORE_Q_CMD_HALT: + case ECORE_Q_CMD_CFC_DEL: + case ECORE_Q_CMD_TERMINATE: + case ECORE_Q_CMD_EMPTY: + return ecore_queue_send_cmd_cmn(sc, params); + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd); + return ECORE_INVAL; + } +} + +/** + * ecore_queue_chk_transition - check state machine of a regular Queue + * + * @sc: device handle + * @o: + * @params: + * + * (not Forwarding) + * It both checks if the requested command is legal in a current + * state and, if it's legal, sets a `next_state' in the object + * that will be used in the completion flow to set the `state' + * of the object. + * + * returns 0 if a requested command is a legal transition, + * ECORE_INVAL otherwise. + */ +static int ecore_queue_chk_transition(struct bnx2x_softc *sc __rte_unused, + struct ecore_queue_sp_obj *o, + struct ecore_queue_state_params *params) +{ + enum ecore_q_state state = o->state, next_state = ECORE_Q_STATE_MAX; + enum ecore_queue_cmd cmd = params->cmd; + struct ecore_queue_update_params *update_params = + ¶ms->params.update; + uint8_t next_tx_only = o->num_tx_only; + + /* Forget all pending for completion commands if a driver only state + * transition has been requested. + */ + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { + o->pending = 0; + o->next_state = ECORE_Q_STATE_MAX; + } + + /* Don't allow a next state transition if we are in the middle of + * the previous one. + */ + if (o->pending) { + PMD_DRV_LOG(ERR, "Blocking transition since pending was %lx", + o->pending); + return ECORE_BUSY; + } + + switch (state) { + case ECORE_Q_STATE_RESET: + if (cmd == ECORE_Q_CMD_INIT) + next_state = ECORE_Q_STATE_INITIALIZED; + + break; + case ECORE_Q_STATE_INITIALIZED: + if (cmd == ECORE_Q_CMD_SETUP) { + if (ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE, + ¶ms->params.setup.flags)) + next_state = ECORE_Q_STATE_ACTIVE; + else + next_state = ECORE_Q_STATE_INACTIVE; + } + + break; + case ECORE_Q_STATE_ACTIVE: + if (cmd == ECORE_Q_CMD_DEACTIVATE) + next_state = ECORE_Q_STATE_INACTIVE; + + else if ((cmd == ECORE_Q_CMD_EMPTY) || + (cmd == ECORE_Q_CMD_UPDATE_TPA)) + next_state = ECORE_Q_STATE_ACTIVE; + + else if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) { + next_state = ECORE_Q_STATE_MULTI_COS; + next_tx_only = 1; + } + + else if (cmd == ECORE_Q_CMD_HALT) + next_state = ECORE_Q_STATE_STOPPED; + + else if (cmd == ECORE_Q_CMD_UPDATE) { + /* If "active" state change is requested, update the + * state accordingly. + */ + if (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG, + &update_params->update_flags) && + !ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE, + &update_params->update_flags)) + next_state = ECORE_Q_STATE_INACTIVE; + else + next_state = ECORE_Q_STATE_ACTIVE; + } + + break; + case ECORE_Q_STATE_MULTI_COS: + if (cmd == ECORE_Q_CMD_TERMINATE) + next_state = ECORE_Q_STATE_MCOS_TERMINATED; + + else if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) { + next_state = ECORE_Q_STATE_MULTI_COS; + next_tx_only = o->num_tx_only + 1; + } + + else if ((cmd == ECORE_Q_CMD_EMPTY) || + (cmd == ECORE_Q_CMD_UPDATE_TPA)) + next_state = ECORE_Q_STATE_MULTI_COS; + + else if (cmd == ECORE_Q_CMD_UPDATE) { + /* If "active" state change is requested, update the + * state accordingly. + */ + if (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG, + &update_params->update_flags) && + !ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE, + &update_params->update_flags)) + next_state = ECORE_Q_STATE_INACTIVE; + else + next_state = ECORE_Q_STATE_MULTI_COS; + } + + break; + case ECORE_Q_STATE_MCOS_TERMINATED: + if (cmd == ECORE_Q_CMD_CFC_DEL) { + next_tx_only = o->num_tx_only - 1; + if (next_tx_only == 0) + next_state = ECORE_Q_STATE_ACTIVE; + else + next_state = ECORE_Q_STATE_MULTI_COS; + } + + break; + case ECORE_Q_STATE_INACTIVE: + if (cmd == ECORE_Q_CMD_ACTIVATE) + next_state = ECORE_Q_STATE_ACTIVE; + + else if ((cmd == ECORE_Q_CMD_EMPTY) || + (cmd == ECORE_Q_CMD_UPDATE_TPA)) + next_state = ECORE_Q_STATE_INACTIVE; + + else if (cmd == ECORE_Q_CMD_HALT) + next_state = ECORE_Q_STATE_STOPPED; + + else if (cmd == ECORE_Q_CMD_UPDATE) { + /* If "active" state change is requested, update the + * state accordingly. + */ + if (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG, + &update_params->update_flags) && + ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE, + &update_params->update_flags)) { + if (o->num_tx_only == 0) + next_state = ECORE_Q_STATE_ACTIVE; + else /* tx only queues exist for this queue */ + next_state = ECORE_Q_STATE_MULTI_COS; + } else + next_state = ECORE_Q_STATE_INACTIVE; + } + + break; + case ECORE_Q_STATE_STOPPED: + if (cmd == ECORE_Q_CMD_TERMINATE) + next_state = ECORE_Q_STATE_TERMINATED; + + break; + case ECORE_Q_STATE_TERMINATED: + if (cmd == ECORE_Q_CMD_CFC_DEL) + next_state = ECORE_Q_STATE_RESET; + + break; + default: + PMD_DRV_LOG(ERR, "Illegal state: %d", state); + } + + /* Transition is assured */ + if (next_state != ECORE_Q_STATE_MAX) { + ECORE_MSG("Good state transition: %d(%d)->%d", + state, cmd, next_state); + o->next_state = next_state; + o->next_tx_only = next_tx_only; + return ECORE_SUCCESS; + } + + ECORE_MSG("Bad state transition request: %d %d", state, cmd); + + return ECORE_INVAL; +} + +/** + * ecore_queue_chk_fwd_transition - check state machine of a Forwarding Queue. + * + * @sc: device handle + * @o: + * @params: + * + * It both checks if the requested command is legal in a current + * state and, if it's legal, sets a `next_state' in the object + * that will be used in the completion flow to set the `state' + * of the object. + * + * returns 0 if a requested command is a legal transition, + * ECORE_INVAL otherwise. + */ +static int ecore_queue_chk_fwd_transition(struct bnx2x_softc *sc __rte_unused, + struct ecore_queue_sp_obj *o, + struct ecore_queue_state_params + *params) +{ + enum ecore_q_state state = o->state, next_state = ECORE_Q_STATE_MAX; + enum ecore_queue_cmd cmd = params->cmd; + + switch (state) { + case ECORE_Q_STATE_RESET: + if (cmd == ECORE_Q_CMD_INIT) + next_state = ECORE_Q_STATE_INITIALIZED; + + break; + case ECORE_Q_STATE_INITIALIZED: + if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) { + if (ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE, + ¶ms->params.tx_only.flags)) + next_state = ECORE_Q_STATE_ACTIVE; + else + next_state = ECORE_Q_STATE_INACTIVE; + } + + break; + case ECORE_Q_STATE_ACTIVE: + case ECORE_Q_STATE_INACTIVE: + if (cmd == ECORE_Q_CMD_CFC_DEL) + next_state = ECORE_Q_STATE_RESET; + + break; + default: + PMD_DRV_LOG(ERR, "Illegal state: %d", state); + } + + /* Transition is assured */ + if (next_state != ECORE_Q_STATE_MAX) { + ECORE_MSG("Good state transition: %d(%d)->%d", + state, cmd, next_state); + o->next_state = next_state; + return ECORE_SUCCESS; + } + + ECORE_MSG("Bad state transition request: %d %d", state, cmd); + return ECORE_INVAL; +} + +void ecore_init_queue_obj(struct bnx2x_softc *sc, + struct ecore_queue_sp_obj *obj, + uint8_t cl_id, uint32_t * cids, uint8_t cid_cnt, + uint8_t func_id, void *rdata, + ecore_dma_addr_t rdata_mapping, unsigned long type) +{ + ECORE_MEMSET(obj, 0, sizeof(*obj)); + + /* We support only ECORE_MULTI_TX_COS Tx CoS at the moment */ + ECORE_BUG_ON(ECORE_MULTI_TX_COS < cid_cnt); + + rte_memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt); + obj->max_cos = cid_cnt; + obj->cl_id = cl_id; + obj->func_id = func_id; + obj->rdata = rdata; + obj->rdata_mapping = rdata_mapping; + obj->type = type; + obj->next_state = ECORE_Q_STATE_MAX; + + if (CHIP_IS_E1x(sc)) + obj->send_cmd = ecore_queue_send_cmd_e1x; + else + obj->send_cmd = ecore_queue_send_cmd_e2; + + if (ECORE_TEST_BIT(ECORE_Q_TYPE_FWD, &type)) + obj->check_transition = ecore_queue_chk_fwd_transition; + else + obj->check_transition = ecore_queue_chk_transition; + + obj->complete_cmd = ecore_queue_comp_cmd; + obj->wait_comp = ecore_queue_wait_comp; + obj->set_pending = ecore_queue_set_pending; +} + +/********************** Function state object *********************************/ +enum ecore_func_state ecore_func_get_state(__rte_unused struct bnx2x_softc *sc, + struct ecore_func_sp_obj *o) +{ + /* in the middle of transaction - return INVALID state */ + if (o->pending) + return ECORE_F_STATE_MAX; + + /* unsure the order of reading of o->pending and o->state + * o->pending should be read first + */ + rmb(); + + return o->state; +} + +static int ecore_func_wait_comp(struct bnx2x_softc *sc, + struct ecore_func_sp_obj *o, + enum ecore_func_cmd cmd) +{ + return ecore_state_wait(sc, cmd, &o->pending); +} + +/** + * ecore_func_state_change_comp - complete the state machine transition + * + * @sc: device handle + * @o: + * @cmd: + * + * Called on state change transition. Completes the state + * machine transition only - no HW interaction. + */ +static int +ecore_func_state_change_comp(struct bnx2x_softc *sc __rte_unused, + struct ecore_func_sp_obj *o, + enum ecore_func_cmd cmd) +{ + unsigned long cur_pending = o->pending; + + if (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) { + PMD_DRV_LOG(ERR, + "Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d", + cmd, ECORE_FUNC_ID(sc), o->state, cur_pending, + o->next_state); + return ECORE_INVAL; + } + + ECORE_MSG(sc, + "Completing command %d for func %d, setting state to %d", + cmd, ECORE_FUNC_ID(sc), o->next_state); + + o->state = o->next_state; + o->next_state = ECORE_F_STATE_MAX; + + /* It's important that o->state and o->next_state are + * updated before o->pending. + */ + wmb(); + + ECORE_CLEAR_BIT(cmd, &o->pending); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); + + return ECORE_SUCCESS; +} + +/** + * ecore_func_comp_cmd - complete the state change command + * + * @sc: device handle + * @o: + * @cmd: + * + * Checks that the arrived completion is expected. + */ +static int ecore_func_comp_cmd(struct bnx2x_softc *sc, + struct ecore_func_sp_obj *o, + enum ecore_func_cmd cmd) +{ + /* Complete the state machine part first, check if it's a + * legal completion. + */ + int rc = ecore_func_state_change_comp(sc, o, cmd); + return rc; +} + +/** + * ecore_func_chk_transition - perform function state machine transition + * + * @sc: device handle + * @o: + * @params: + * + * It both checks if the requested command is legal in a current + * state and, if it's legal, sets a `next_state' in the object + * that will be used in the completion flow to set the `state' + * of the object. + * + * returns 0 if a requested command is a legal transition, + * ECORE_INVAL otherwise. + */ +static int ecore_func_chk_transition(struct bnx2x_softc *sc __rte_unused, + struct ecore_func_sp_obj *o, + struct ecore_func_state_params *params) +{ + enum ecore_func_state state = o->state, next_state = ECORE_F_STATE_MAX; + enum ecore_func_cmd cmd = params->cmd; + + /* Forget all pending for completion commands if a driver only state + * transition has been requested. + */ + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { + o->pending = 0; + o->next_state = ECORE_F_STATE_MAX; + } + + /* Don't allow a next state transition if we are in the middle of + * the previous one. + */ + if (o->pending) + return ECORE_BUSY; + + switch (state) { + case ECORE_F_STATE_RESET: + if (cmd == ECORE_F_CMD_HW_INIT) + next_state = ECORE_F_STATE_INITIALIZED; + + break; + case ECORE_F_STATE_INITIALIZED: + if (cmd == ECORE_F_CMD_START) + next_state = ECORE_F_STATE_STARTED; + + else if (cmd == ECORE_F_CMD_HW_RESET) + next_state = ECORE_F_STATE_RESET; + + break; + case ECORE_F_STATE_STARTED: + if (cmd == ECORE_F_CMD_STOP) + next_state = ECORE_F_STATE_INITIALIZED; + /* afex ramrods can be sent only in started mode, and only + * if not pending for function_stop ramrod completion + * for these events - next state remained STARTED. + */ + else if ((cmd == ECORE_F_CMD_AFEX_UPDATE) && + (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending))) + next_state = ECORE_F_STATE_STARTED; + + else if ((cmd == ECORE_F_CMD_AFEX_VIFLISTS) && + (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending))) + next_state = ECORE_F_STATE_STARTED; + + /* Switch_update ramrod can be sent in either started or + * tx_stopped state, and it doesn't change the state. + */ + else if ((cmd == ECORE_F_CMD_SWITCH_UPDATE) && + (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending))) + next_state = ECORE_F_STATE_STARTED; + + else if (cmd == ECORE_F_CMD_TX_STOP) + next_state = ECORE_F_STATE_TX_STOPPED; + + break; + case ECORE_F_STATE_TX_STOPPED: + if ((cmd == ECORE_F_CMD_SWITCH_UPDATE) && + (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending))) + next_state = ECORE_F_STATE_TX_STOPPED; + + else if (cmd == ECORE_F_CMD_TX_START) + next_state = ECORE_F_STATE_STARTED; + + break; + default: + PMD_DRV_LOG(ERR, "Unknown state: %d", state); + } + + /* Transition is assured */ + if (next_state != ECORE_F_STATE_MAX) { + ECORE_MSG("Good function state transition: %d(%d)->%d", + state, cmd, next_state); + o->next_state = next_state; + return ECORE_SUCCESS; + } + + ECORE_MSG("Bad function state transition request: %d %d", state, cmd); + + return ECORE_INVAL; +} + +/** + * ecore_func_init_func - performs HW init at function stage + * + * @sc: device handle + * @drv: + * + * Init HW when the current phase is + * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only + * HW blocks. + */ +static int ecore_func_init_func(struct bnx2x_softc *sc, + const struct ecore_func_sp_drv_ops *drv) +{ + return drv->init_hw_func(sc); +} + +/** + * ecore_func_init_port - performs HW init at port stage + * + * @sc: device handle + * @drv: + * + * Init HW when the current phase is + * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and + * FUNCTION-only HW blocks. + * + */ +static int ecore_func_init_port(struct bnx2x_softc *sc, + const struct ecore_func_sp_drv_ops *drv) +{ + int rc = drv->init_hw_port(sc); + if (rc) + return rc; + + return ecore_func_init_func(sc, drv); +} + +/** + * ecore_func_init_cmn_chip - performs HW init at chip-common stage + * + * @sc: device handle + * @drv: + * + * Init HW when the current phase is + * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP, + * PORT-only and FUNCTION-only HW blocks. + */ +static int ecore_func_init_cmn_chip(struct bnx2x_softc *sc, const struct ecore_func_sp_drv_ops + *drv) +{ + int rc = drv->init_hw_cmn_chip(sc); + if (rc) + return rc; + + return ecore_func_init_port(sc, drv); +} + +/** + * ecore_func_init_cmn - performs HW init at common stage + * + * @sc: device handle + * @drv: + * + * Init HW when the current phase is + * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON, + * PORT-only and FUNCTION-only HW blocks. + */ +static int ecore_func_init_cmn(struct bnx2x_softc *sc, + const struct ecore_func_sp_drv_ops *drv) +{ + int rc = drv->init_hw_cmn(sc); + if (rc) + return rc; + + return ecore_func_init_port(sc, drv); +} + +static int ecore_func_hw_init(struct bnx2x_softc *sc, + struct ecore_func_state_params *params) +{ + uint32_t load_code = params->params.hw_init.load_phase; + struct ecore_func_sp_obj *o = params->f_obj; + const struct ecore_func_sp_drv_ops *drv = o->drv; + int rc = 0; + + ECORE_MSG("function %d load_code %x", + ECORE_ABS_FUNC_ID(sc), load_code); + + /* Prepare FW */ + rc = drv->init_fw(sc); + if (rc) { + PMD_DRV_LOG(ERR, "Error loading firmware"); + goto init_err; + } + + /* Handle the beginning of COMMON_XXX pases separately... */ + switch (load_code) { + case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: + rc = ecore_func_init_cmn_chip(sc, drv); + if (rc) + goto init_err; + + break; + case FW_MSG_CODE_DRV_LOAD_COMMON: + rc = ecore_func_init_cmn(sc, drv); + if (rc) + goto init_err; + + break; + case FW_MSG_CODE_DRV_LOAD_PORT: + rc = ecore_func_init_port(sc, drv); + if (rc) + goto init_err; + + break; + case FW_MSG_CODE_DRV_LOAD_FUNCTION: + rc = ecore_func_init_func(sc, drv); + if (rc) + goto init_err; + + break; + default: + PMD_DRV_LOG(ERR, "Unknown load_code (0x%x) from MCP", + load_code); + rc = ECORE_INVAL; + } + +init_err: + /* In case of success, complete the command immediately: no ramrods + * have been sent. + */ + if (!rc) + o->complete_cmd(sc, o, ECORE_F_CMD_HW_INIT); + + return rc; +} + +/** + * ecore_func_reset_func - reset HW at function stage + * + * @sc: device handle + * @drv: + * + * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only + * FUNCTION-only HW blocks. + */ +static void ecore_func_reset_func(struct bnx2x_softc *sc, const struct ecore_func_sp_drv_ops + *drv) +{ + drv->reset_hw_func(sc); +} + +/** + * ecore_func_reset_port - reser HW at port stage + * + * @sc: device handle + * @drv: + * + * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset + * FUNCTION-only and PORT-only HW blocks. + * + * !!!IMPORTANT!!! + * + * It's important to call reset_port before reset_func() as the last thing + * reset_func does is pf_disable() thus disabling PGLUE_B, which + * makes impossible any DMAE transactions. + */ +static void ecore_func_reset_port(struct bnx2x_softc *sc, const struct ecore_func_sp_drv_ops + *drv) +{ + drv->reset_hw_port(sc); + ecore_func_reset_func(sc, drv); +} + +/** + * ecore_func_reset_cmn - reser HW at common stage + * + * @sc: device handle + * @drv: + * + * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and + * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON, + * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks. + */ +static void ecore_func_reset_cmn(struct bnx2x_softc *sc, + const struct ecore_func_sp_drv_ops *drv) +{ + ecore_func_reset_port(sc, drv); + drv->reset_hw_cmn(sc); +} + +static int ecore_func_hw_reset(struct bnx2x_softc *sc, + struct ecore_func_state_params *params) +{ + uint32_t reset_phase = params->params.hw_reset.reset_phase; + struct ecore_func_sp_obj *o = params->f_obj; + const struct ecore_func_sp_drv_ops *drv = o->drv; + + ECORE_MSG("function %d reset_phase %x", ECORE_ABS_FUNC_ID(sc), + reset_phase); + + switch (reset_phase) { + case FW_MSG_CODE_DRV_UNLOAD_COMMON: + ecore_func_reset_cmn(sc, drv); + break; + case FW_MSG_CODE_DRV_UNLOAD_PORT: + ecore_func_reset_port(sc, drv); + break; + case FW_MSG_CODE_DRV_UNLOAD_FUNCTION: + ecore_func_reset_func(sc, drv); + break; + default: + PMD_DRV_LOG(ERR, "Unknown reset_phase (0x%x) from MCP", + reset_phase); + break; + } + + /* Complete the command immediately: no ramrods have been sent. */ + o->complete_cmd(sc, o, ECORE_F_CMD_HW_RESET); + + return ECORE_SUCCESS; +} + +static int ecore_func_send_start(struct bnx2x_softc *sc, + struct ecore_func_state_params *params) +{ + struct ecore_func_sp_obj *o = params->f_obj; + struct function_start_data *rdata = + (struct function_start_data *)o->rdata; + ecore_dma_addr_t data_mapping = o->rdata_mapping; + struct ecore_func_start_params *start_params = ¶ms->params.start; + + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data with provided parameters */ + rdata->function_mode = (uint8_t) start_params->mf_mode; + rdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag); + rdata->path_id = ECORE_PATH_ID(sc); + rdata->network_cos_mode = start_params->network_cos_mode; + rdata->gre_tunnel_mode = start_params->gre_tunnel_mode; + rdata->gre_tunnel_rss = start_params->gre_tunnel_rss; + + /* + * No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, + data_mapping, NONE_CONNECTION_TYPE); +} + +static int ecore_func_send_switch_update(struct bnx2x_softc *sc, struct ecore_func_state_params + *params) +{ + struct ecore_func_sp_obj *o = params->f_obj; + struct function_update_data *rdata = + (struct function_update_data *)o->rdata; + ecore_dma_addr_t data_mapping = o->rdata_mapping; + struct ecore_func_switch_update_params *switch_update_params = + ¶ms->params.switch_update; + + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data with provided parameters */ + rdata->tx_switch_suspend_change_flg = 1; + rdata->tx_switch_suspend = switch_update_params->suspend; + rdata->echo = SWITCH_UPDATE; + + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, + data_mapping, NONE_CONNECTION_TYPE); +} + +static int ecore_func_send_afex_update(struct bnx2x_softc *sc, struct ecore_func_state_params + *params) +{ + struct ecore_func_sp_obj *o = params->f_obj; + struct function_update_data *rdata = + (struct function_update_data *)o->afex_rdata; + ecore_dma_addr_t data_mapping = o->afex_rdata_mapping; + struct ecore_func_afex_update_params *afex_update_params = + ¶ms->params.afex_update; + + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data with provided parameters */ + rdata->vif_id_change_flg = 1; + rdata->vif_id = ECORE_CPU_TO_LE16(afex_update_params->vif_id); + rdata->afex_default_vlan_change_flg = 1; + rdata->afex_default_vlan = + ECORE_CPU_TO_LE16(afex_update_params->afex_default_vlan); + rdata->allowed_priorities_change_flg = 1; + rdata->allowed_priorities = afex_update_params->allowed_priorities; + rdata->echo = AFEX_UPDATE; + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + ECORE_MSG(sc, + "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x", + rdata->vif_id, + rdata->afex_default_vlan, rdata->allowed_priorities); + + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0, + data_mapping, NONE_CONNECTION_TYPE); +} + +static +inline int ecore_func_send_afex_viflists(struct bnx2x_softc *sc, + struct ecore_func_state_params *params) +{ + struct ecore_func_sp_obj *o = params->f_obj; + struct afex_vif_list_ramrod_data *rdata = + (struct afex_vif_list_ramrod_data *)o->afex_rdata; + struct ecore_func_afex_viflists_params *afex_vif_params = + ¶ms->params.afex_viflists; + uint64_t *p_rdata = (uint64_t *) rdata; + + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + /* Fill the ramrod data with provided parameters */ + rdata->vif_list_index = + ECORE_CPU_TO_LE16(afex_vif_params->vif_list_index); + rdata->func_bit_map = afex_vif_params->func_bit_map; + rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command; + rdata->func_to_clear = afex_vif_params->func_to_clear; + + /* send in echo type of sub command */ + rdata->echo = afex_vif_params->afex_vif_list_command; + + /* No need for an explicit memory barrier here as long we would + * need to ensure the ordering of writing to the SPQ element + * and updating of the SPQ producer which involves a memory + * read and we will have to put a full memory barrier there + * (inside ecore_sp_post()). + */ + + ECORE_MSG + ("afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x", + rdata->afex_vif_list_command, rdata->vif_list_index, + rdata->func_bit_map, rdata->func_to_clear); + + /* this ramrod sends data directly and not through DMA mapping */ + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0, + *p_rdata, NONE_CONNECTION_TYPE); +} + +static int ecore_func_send_stop(struct bnx2x_softc *sc, __rte_unused struct + ecore_func_state_params *params) +{ + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, + NONE_CONNECTION_TYPE); +} + +static int ecore_func_send_tx_stop(struct bnx2x_softc *sc, __rte_unused struct + ecore_func_state_params *params) +{ + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, + NONE_CONNECTION_TYPE); +} + +static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_state_params + *params) +{ + struct ecore_func_sp_obj *o = params->f_obj; + struct flow_control_configuration *rdata = + (struct flow_control_configuration *)o->rdata; + ecore_dma_addr_t data_mapping = o->rdata_mapping; + struct ecore_func_tx_start_params *tx_start_params = + ¶ms->params.tx_start; + uint32_t i; + + ECORE_MEMSET(rdata, 0, sizeof(*rdata)); + + rdata->dcb_enabled = tx_start_params->dcb_enabled; + rdata->dcb_version = tx_start_params->dcb_version; + rdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0; + + for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++) + rdata->traffic_type_to_priority_cos[i] = + tx_start_params->traffic_type_to_priority_cos[i]; + + return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0, + data_mapping, NONE_CONNECTION_TYPE); +} + +static int ecore_func_send_cmd(struct bnx2x_softc *sc, + struct ecore_func_state_params *params) +{ + switch (params->cmd) { + case ECORE_F_CMD_HW_INIT: + return ecore_func_hw_init(sc, params); + case ECORE_F_CMD_START: + return ecore_func_send_start(sc, params); + case ECORE_F_CMD_STOP: + return ecore_func_send_stop(sc, params); + case ECORE_F_CMD_HW_RESET: + return ecore_func_hw_reset(sc, params); + case ECORE_F_CMD_AFEX_UPDATE: + return ecore_func_send_afex_update(sc, params); + case ECORE_F_CMD_AFEX_VIFLISTS: + return ecore_func_send_afex_viflists(sc, params); + case ECORE_F_CMD_TX_STOP: + return ecore_func_send_tx_stop(sc, params); + case ECORE_F_CMD_TX_START: + return ecore_func_send_tx_start(sc, params); + case ECORE_F_CMD_SWITCH_UPDATE: + return ecore_func_send_switch_update(sc, params); + default: + PMD_DRV_LOG(ERR, "Unknown command: %d", params->cmd); + return ECORE_INVAL; + } +} + +void ecore_init_func_obj(__rte_unused struct bnx2x_softc *sc, + struct ecore_func_sp_obj *obj, + void *rdata, ecore_dma_addr_t rdata_mapping, + void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, + struct ecore_func_sp_drv_ops *drv_iface) +{ + ECORE_MEMSET(obj, 0, sizeof(*obj)); + + ECORE_MUTEX_INIT(&obj->one_pending_mutex); + + obj->rdata = rdata; + obj->rdata_mapping = rdata_mapping; + obj->afex_rdata = afex_rdata; + obj->afex_rdata_mapping = afex_rdata_mapping; + obj->send_cmd = ecore_func_send_cmd; + obj->check_transition = ecore_func_chk_transition; + obj->complete_cmd = ecore_func_comp_cmd; + obj->wait_comp = ecore_func_wait_comp; + obj->drv = drv_iface; +} + +/** + * ecore_func_state_change - perform Function state change transition + * + * @sc: device handle + * @params: parameters to perform the transaction + * + * returns 0 in case of successfully completed transition, + * negative error code in case of failure, positive + * (EBUSY) value if there is a completion to that is + * still pending (possible only if RAMROD_COMP_WAIT is + * not set in params->ramrod_flags for asynchronous + * commands). + */ +int ecore_func_state_change(struct bnx2x_softc *sc, + struct ecore_func_state_params *params) +{ + struct ecore_func_sp_obj *o = params->f_obj; + int rc, cnt = 300; + enum ecore_func_cmd cmd = params->cmd; + unsigned long *pending = &o->pending; + + ECORE_MUTEX_LOCK(&o->one_pending_mutex); + + /* Check that the requested transition is legal */ + rc = o->check_transition(sc, o, params); + if ((rc == ECORE_BUSY) && + (ECORE_TEST_BIT(RAMROD_RETRY, ¶ms->ramrod_flags))) { + while ((rc == ECORE_BUSY) && (--cnt > 0)) { + ECORE_MUTEX_UNLOCK(&o->one_pending_mutex); + ECORE_MSLEEP(10); + ECORE_MUTEX_LOCK(&o->one_pending_mutex); + rc = o->check_transition(sc, o, params); + } + if (rc == ECORE_BUSY) { + ECORE_MUTEX_UNLOCK(&o->one_pending_mutex); + PMD_DRV_LOG(ERR, + "timeout waiting for previous ramrod completion"); + return rc; + } + } else if (rc) { + ECORE_MUTEX_UNLOCK(&o->one_pending_mutex); + return rc; + } + + /* Set "pending" bit */ + ECORE_SET_BIT(cmd, pending); + + /* Don't send a command if only driver cleanup was requested */ + if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) { + ecore_func_state_change_comp(sc, o, cmd); + ECORE_MUTEX_UNLOCK(&o->one_pending_mutex); + } else { + /* Send a ramrod */ + rc = o->send_cmd(sc, params); + + ECORE_MUTEX_UNLOCK(&o->one_pending_mutex); + + if (rc) { + o->next_state = ECORE_F_STATE_MAX; + ECORE_CLEAR_BIT(cmd, pending); + ECORE_SMP_MB_AFTER_CLEAR_BIT(); + return rc; + } + + if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) { + rc = o->wait_comp(sc, o, cmd); + if (rc) + return rc; + + return ECORE_SUCCESS; + } + } + + return ECORE_RET_PENDING(cmd, pending); +} + +/****************************************************************************** + * Description: + * Calculates crc 8 on a word value: polynomial 0-1-2-8 + * Code was translated from Verilog. + * Return: + *****************************************************************************/ +uint8_t ecore_calc_crc8(uint32_t data, uint8_t crc) +{ + uint8_t D[32]; + uint8_t NewCRC[8]; + uint8_t C[8]; + uint8_t crc_res; + uint8_t i; + + /* split the data into 31 bits */ + for (i = 0; i < 32; i++) { + D[i] = (uint8_t) (data & 1); + data = data >> 1; + } + + /* split the crc into 8 bits */ + for (i = 0; i < 8; i++) { + C[i] = crc & 1; + crc = crc >> 1; + } + + NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ + D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ + C[6] ^ C[7]; + NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ + D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ + D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; + NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ + D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ + C[0] ^ C[1] ^ C[4] ^ C[5]; + NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ + D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ + C[1] ^ C[2] ^ C[5] ^ C[6]; + NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ + D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ + C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; + NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ + D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ + C[3] ^ C[4] ^ C[7]; + NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ + D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5]; + NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ + D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6]; + + crc_res = 0; + for (i = 0; i < 8; i++) { + crc_res |= (NewCRC[i] << i); + } + + return crc_res; +} + +uint32_t +ecore_calc_crc32(uint32_t crc, uint8_t const *p, uint32_t len, uint32_t magic) +{ + int i; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? magic : 0); + } + return crc; +} diff --git a/lib/librte_pmd_bnx2x/ecore_sp.h b/lib/librte_pmd_bnx2x/ecore_sp.h new file mode 100644 index 0000000..c721cc1 --- /dev/null +++ b/lib/librte_pmd_bnx2x/ecore_sp.h @@ -0,0 +1,1795 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ECORE_SP_H +#define ECORE_SP_H + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN +#endif +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN +#endif +#undef BIG_ENDIAN +#undef __BIG_ENDIAN +#else /* _BIG_ENDIAN */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN +#endif +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN +#endif +#undef LITTLE_ENDIAN +#undef __LITTLE_ENDIAN +#endif + +#include "ecore_mfw_req.h" +#include "ecore_fw_defs.h" +#include "ecore_hsi.h" +#include "ecore_reg.h" + +struct bnx2x_softc; +typedef phys_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */ +typedef volatile int ecore_atomic_t; + + +#define ETH_ALEN ETHER_ADDR_LEN /* 6 */ + +#define ECORE_SWCID_SHIFT 17 +#define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1) + +#define ECORE_MC_HASH_SIZE 8 +#define ECORE_MC_HASH_OFFSET(sc, i) \ + (BAR_TSTRORM_INTMEM + \ + TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4) + +#define ECORE_MAX_MULTICAST 64 +#define ECORE_MAX_EMUL_MULTI 1 + +#define IRO sc->iro_array + +typedef rte_spinlock_t ECORE_MUTEX; +#define ECORE_MUTEX_INIT(_mutex) rte_spinlock_init(_mutex) +#define ECORE_MUTEX_LOCK(_mutex) rte_spinlock_lock(_mutex) +#define ECORE_MUTEX_UNLOCK(_mutex) rte_spinlock_unlock(_mutex) + +typedef rte_spinlock_t ECORE_MUTEX_SPIN; +#define ECORE_SPIN_LOCK_INIT(_spin, _sc) rte_spinlock_init(_spin) +#define ECORE_SPIN_LOCK_BH(_spin) rte_spinlock_lock(_spin) /* bh = bottom-half */ +#define ECORE_SPIN_UNLOCK_BH(_spin) rte_spinlock_unlock(_spin) /* bh = bottom-half */ + +#define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb() +#define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb() +#define ECORE_SMP_MB() mb() +#define ECORE_SMP_RMB() rmb() +#define ECORE_SMP_WMB() wmb() +#define ECORE_MMIOWB() wmb() + +#define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit)) +#define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit)) + +#define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var) +#define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var) +#define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var) +#define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var) + +#define atomic_load_acq_int (int)* +#define atomic_store_rel_int(a, v) (*a = v) +#define atomic_cmpset_acq_int(a, o, n) ((*a = (o & (n)) | (n)) ^ o) + +#define atomic_load_acq_long (long)* +#define atomic_store_rel_long(a, v) (*a = v) +#define atomic_set_acq_long(a, v) (*a |= v) +#define atomic_clear_acq_long(a, v) (*a &= ~v) +#define atomic_cmpset_acq_long(a, o, n) ((*a = (o & (n)) | (n)) ^ o) +#define atomic_subtract_acq_long(a, v) (*a -= v) +#define atomic_add_acq_long(a, v) (*a += v) + +#define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a) +#define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v) +#define ECORE_ATOMIC_CMPXCHG(a, o, n) bnx2x_cmpxchg((volatile int *)a, o, n) + +#define ECORE_RET_PENDING(pending_bit, pending) \ + (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS) + +#define ECORE_SET_FLAG(value, mask, flag) \ + do { \ + (value) &= ~(mask); \ + (value) |= ((flag) << (mask##_SHIFT)); \ + } while (0) + +#define ECORE_GET_FLAG(value, mask) \ + (((value) &= (mask)) >> (mask##_SHIFT)) + +#define ECORE_MIGHT_SLEEP() + +#define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) + +#define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s) +#define ECORE_MEMCPY(_a, _b, _s) (void)rte_memcpy(_a, _b, _s) +#define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s) + +#define ECORE_CPU_TO_LE16(x) htole16(x) +#define ECORE_CPU_TO_LE32(x) htole32(x) + +#define ECORE_WAIT(_s, _t) DELAY(1000) +#define ECORE_MSLEEP(_t) DELAY((_t) * 1000) + +#define ECORE_LIKELY(x) likely(x) +#define ECORE_UNLIKELY(x) unlikely(x) + +#define ECORE_ZALLOC(_size, _flags, _sc) \ + rte_zmalloc("", _size, RTE_CACHE_LINE_SIZE) + +#define ECORE_CALLOC(_len, _size, _flags, _sc) \ + rte_calloc("", _len, _size, RTE_CACHE_LINE_SIZE) + +#define ECORE_FREE(_s, _buf, _size) \ + rte_free(_buf) + +#define SC_ILT(sc) ((sc)->ilt) +#define ILOG2(x) bnx2x_ilog2(x) + +#define ECORE_ILT_ZALLOC(x, y, size, str) \ + do { \ + x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \ + if (x) { \ + if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \ + size, (struct bnx2x_dma *)x, \ + str, RTE_CACHE_LINE_SIZE) != 0) { \ + rte_free(x); \ + x = NULL; \ + *y = 0; \ + } else { \ + *y = ((struct bnx2x_dma *)x)->paddr; \ + } \ + } \ + } while (0) + +#define ECORE_ILT_FREE(x, y, size) \ + do { \ + if (x) { \ + rte_free(x); \ + x = NULL; \ + y = 0; \ + } \ + } while (0) + +#define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE + +#define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE +#define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE +#define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE + +#define ECORE_SET_CTX_VALIDATION bnx2x_set_ctx_validation + +#define ECORE_UPDATE_COALESCE_SB_INDEX bnx2x_update_coalesce_sb_index + +#define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a)) + +#define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN + +#define ECORE_PATH_ID SC_PATH +#define ECORE_PORT_ID SC_PORT +#define ECORE_FUNC_ID SC_FUNC +#define ECORE_ABS_FUNC_ID SC_ABS_FUNC + +#define CRCPOLY_LE 0xedb88320 +uint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p, + uint32_t len, uint32_t magic); + +uint8_t ecore_calc_crc8(uint32_t data, uint8_t crc); + + +static inline uint32_t +ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len) +{ + return ecore_calc_crc32(seed, mac, len, CRCPOLY_LE); +} + +#define ecore_sp_post(_sc, _a, _b, _c, _d) \ + bnx2x_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d) + +#define ECORE_DBG_BREAK_IF(exp) \ + do { \ + if (unlikely(exp)) { \ + rte_panic("ECORE"); \ + } \ + } while (0) + +#define ECORE_BUG() \ + do { \ + rte_panic("BUG (%s:%d)", __FILE__, __LINE__); \ + } while(0); + +#define ECORE_BUG_ON(exp) \ + do { \ + if (likely(exp)) { \ + rte_panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \ + } \ + } while (0) + + +#define ECORE_MSG(m, ...) \ + PMD_DRV_LOG(DEBUG, m, ##__VA_ARGS__) + +typedef struct _ecore_list_entry_t +{ + struct _ecore_list_entry_t *next, *prev; +} ecore_list_entry_t; + +typedef struct ecore_list_t +{ + ecore_list_entry_t *head, *tail; + unsigned long cnt; +} ecore_list_t; + +/* initialize the list */ +#define ECORE_LIST_INIT(_list) \ + do { \ + (_list)->head = NULL; \ + (_list)->tail = NULL; \ + (_list)->cnt = 0; \ + } while (0) + +/* return TRUE if the element is the last on the list */ +#define ECORE_LIST_IS_LAST(_elem, _list) \ + (_elem == (_list)->tail) + +/* return TRUE if the list is empty */ +#define ECORE_LIST_IS_EMPTY(_list) \ + ((_list)->cnt == 0) + +/* return the first element */ +#define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \ + (cast *)((_list)->head) + +/* return the next element */ +#define ECORE_LIST_NEXT(_elem, _link, cast) \ + (cast *)((&((_elem)->_link))->next) + +/* push an element on the head of the list */ +#define ECORE_LIST_PUSH_HEAD(_elem, _list) \ + do { \ + (_elem)->prev = (ecore_list_entry_t *)0; \ + (_elem)->next = (_list)->head; \ + if ((_list)->tail == (ecore_list_entry_t *)0) { \ + (_list)->tail = (_elem); \ + } else { \ + (_list)->head->prev = (_elem); \ + } \ + (_list)->head = (_elem); \ + (_list)->cnt++; \ + } while (0) + +/* push an element on the tail of the list */ +#define ECORE_LIST_PUSH_TAIL(_elem, _list) \ + do { \ + (_elem)->next = (ecore_list_entry_t *)0; \ + (_elem)->prev = (_list)->tail; \ + if ((_list)->tail) { \ + (_list)->tail->next = (_elem); \ + } else { \ + (_list)->head = (_elem); \ + } \ + (_list)->tail = (_elem); \ + (_list)->cnt++; \ + } while (0) + +/* push list1 on the head of list2 and return with list1 as empty */ +#define ECORE_LIST_SPLICE_INIT(_list1, _list2) \ + do { \ + (_list1)->tail->next = (_list2)->head; \ + if ((_list2)->head) { \ + (_list2)->head->prev = (_list1)->tail; \ + } else { \ + (_list2)->tail = (_list1)->tail; \ + } \ + (_list2)->head = (_list1)->head; \ + (_list2)->cnt += (_list1)->cnt; \ + (_list1)->head = NULL; \ + (_list1)->tail = NULL; \ + (_list1)->cnt = 0; \ + } while (0) + +/* remove an element from the list */ +#define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \ + do { \ + if ((_list)->head == (_elem)) { \ + if ((_list)->head) { \ + (_list)->head = (_list)->head->next; \ + if ((_list)->head) { \ + (_list)->head->prev = (ecore_list_entry_t *)0; \ + } else { \ + (_list)->tail = (ecore_list_entry_t *)0; \ + } \ + (_list)->cnt--; \ + } \ + } else if ((_list)->tail == (_elem)) { \ + if ((_list)->tail) { \ + (_list)->tail = (_list)->tail->prev; \ + if ((_list)->tail) { \ + (_list)->tail->next = (ecore_list_entry_t *)0; \ + } else { \ + (_list)->head = (ecore_list_entry_t *)0; \ + } \ + (_list)->cnt--; \ + } \ + } else { \ + (_elem)->prev->next = (_elem)->next; \ + (_elem)->next->prev = (_elem)->prev; \ + (_list)->cnt--; \ + } \ + } while (0) + +/* walk the list */ +#define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \ + for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \ + pos; \ + pos = ECORE_LIST_NEXT(pos, _link, cast)) + +/* walk the list (safely) */ +#define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \ + for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \ + n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \ + pos != NULL; \ + pos = (cast *)n, \ + n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL) + + +/* Manipulate a bit vector defined as an array of uint64_t */ + +/* Number of bits in one sge_mask array element */ +#define BIT_VEC64_ELEM_SZ 64 +#define BIT_VEC64_ELEM_SHIFT 6 +#define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1) + +#define __BIT_VEC64_SET_BIT(el, bit) \ + do { \ + el = ((el) | ((uint64_t)0x1 << (bit))); \ + } while (0) + +#define __BIT_VEC64_CLEAR_BIT(el, bit) \ + do { \ + el = ((el) & (~((uint64_t)0x1 << (bit)))); \ + } while (0) + +#define BIT_VEC64_SET_BIT(vec64, idx) \ + __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ + (idx) & BIT_VEC64_ELEM_MASK) + +#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ + __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ + (idx) & BIT_VEC64_ELEM_MASK) + +#define BIT_VEC64_TEST_BIT(vec64, idx) \ + (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ + ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) + +/* + * Creates a bitmask of all ones in less significant bits. + * idx - index of the most significant bit in the created mask + */ +#define BIT_VEC64_ONES_MASK(idx) \ + (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) +#define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0)) + +/* fill in a MAC address the way the FW likes it */ +static inline void +ecore_set_fw_mac_addr(uint16_t *fw_hi, + uint16_t *fw_mid, + uint16_t *fw_lo, + uint8_t *mac) +{ + ((uint8_t *)fw_hi)[0] = mac[1]; + ((uint8_t *)fw_hi)[1] = mac[0]; + ((uint8_t *)fw_mid)[0] = mac[3]; + ((uint8_t *)fw_mid)[1] = mac[2]; + ((uint8_t *)fw_lo)[0] = mac[5]; + ((uint8_t *)fw_lo)[1] = mac[4]; +} + + +enum ecore_status_t { + ECORE_EXISTS = -6, + ECORE_IO = -5, + ECORE_TIMEOUT = -4, + ECORE_INVAL = -3, + ECORE_BUSY = -2, + ECORE_NOMEM = -1, + ECORE_SUCCESS = 0, + /* PENDING is not an error and should be positive */ + ECORE_PENDING = 1, +}; + +enum { + SWITCH_UPDATE, + AFEX_UPDATE, +}; + + + + +struct bnx2x_softc; +struct eth_context; + +/* Bits representing general command's configuration */ +enum { + RAMROD_TX, + RAMROD_RX, + /* Wait until all pending commands complete */ + RAMROD_COMP_WAIT, + /* Don't send a ramrod, only update a registry */ + RAMROD_DRV_CLR_ONLY, + /* Configure HW according to the current object state */ + RAMROD_RESTORE, + /* Execute the next command now */ + RAMROD_EXEC, + /* Don't add a new command and continue execution of posponed + * commands. If not set a new command will be added to the + * pending commands list. + */ + RAMROD_CONT, + /* If there is another pending ramrod, wait until it finishes and + * re-try to submit this one. This flag can be set only in sleepable + * context, and should not be set from the context that completes the + * ramrods as deadlock will occur. + */ + RAMROD_RETRY, +}; + +typedef enum { + ECORE_OBJ_TYPE_RX, + ECORE_OBJ_TYPE_TX, + ECORE_OBJ_TYPE_RX_TX, +} ecore_obj_type; + +/* Public slow path states */ +enum { + ECORE_FILTER_MAC_PENDING, + ECORE_FILTER_VLAN_PENDING, + ECORE_FILTER_VLAN_MAC_PENDING, + ECORE_FILTER_RX_MODE_PENDING, + ECORE_FILTER_RX_MODE_SCHED, + ECORE_FILTER_ISCSI_ETH_START_SCHED, + ECORE_FILTER_ISCSI_ETH_STOP_SCHED, + ECORE_FILTER_FCOE_ETH_START_SCHED, + ECORE_FILTER_FCOE_ETH_STOP_SCHED, + ECORE_FILTER_MCAST_PENDING, + ECORE_FILTER_MCAST_SCHED, + ECORE_FILTER_RSS_CONF_PENDING, + ECORE_AFEX_FCOE_Q_UPDATE_PENDING, + ECORE_AFEX_PENDING_VIFSET_MCP_ACK +}; + +struct ecore_raw_obj { + uint8_t func_id; + + /* Queue params */ + uint8_t cl_id; + uint32_t cid; + + /* Ramrod data buffer params */ + void *rdata; + ecore_dma_addr_t rdata_mapping; + + /* Ramrod state params */ + int state; /* "ramrod is pending" state bit */ + unsigned long *pstate; /* pointer to state buffer */ + + ecore_obj_type obj_type; + + int (*wait_comp)(struct bnx2x_softc *sc, + struct ecore_raw_obj *o); + + int (*check_pending)(struct ecore_raw_obj *o); + void (*clear_pending)(struct ecore_raw_obj *o); + void (*set_pending)(struct ecore_raw_obj *o); +}; + +/************************* VLAN-MAC commands related parameters ***************/ +struct ecore_mac_ramrod_data { + uint8_t mac[ETH_ALEN]; + uint8_t is_inner_mac; +}; + +struct ecore_vlan_ramrod_data { + uint16_t vlan; +}; + +struct ecore_vlan_mac_ramrod_data { + uint8_t mac[ETH_ALEN]; + uint8_t is_inner_mac; + uint16_t vlan; +}; + +union ecore_classification_ramrod_data { + struct ecore_mac_ramrod_data mac; + struct ecore_vlan_ramrod_data vlan; + struct ecore_vlan_mac_ramrod_data vlan_mac; +}; + +/* VLAN_MAC commands */ +enum ecore_vlan_mac_cmd { + ECORE_VLAN_MAC_ADD, + ECORE_VLAN_MAC_DEL, + ECORE_VLAN_MAC_MOVE, +}; + +struct ecore_vlan_mac_data { + /* Requested command: ECORE_VLAN_MAC_XX */ + enum ecore_vlan_mac_cmd cmd; + /* used to contain the data related vlan_mac_flags bits from + * ramrod parameters. + */ + unsigned long vlan_mac_flags; + + /* Needed for MOVE command */ + struct ecore_vlan_mac_obj *target_obj; + + union ecore_classification_ramrod_data u; +}; + +/*************************** Exe Queue obj ************************************/ +union ecore_exe_queue_cmd_data { + struct ecore_vlan_mac_data vlan_mac; + + struct { + } mcast; +}; + +struct ecore_exeq_elem { + ecore_list_entry_t link; + + /* Length of this element in the exe_chunk. */ + int cmd_len; + + union ecore_exe_queue_cmd_data cmd_data; +}; + +union ecore_qable_obj; + +union ecore_exeq_comp_elem { + union event_ring_elem *elem; +}; + +struct ecore_exe_queue_obj; + +typedef int (*exe_q_validate)(struct bnx2x_softc *sc, + union ecore_qable_obj *o, + struct ecore_exeq_elem *elem); + +typedef int (*exe_q_remove)(struct bnx2x_softc *sc, + union ecore_qable_obj *o, + struct ecore_exeq_elem *elem); + +/* Return positive if entry was optimized, 0 - if not, negative + * in case of an error. + */ +typedef int (*exe_q_optimize)(struct bnx2x_softc *sc, + union ecore_qable_obj *o, + struct ecore_exeq_elem *elem); +typedef int (*exe_q_execute)(struct bnx2x_softc *sc, + union ecore_qable_obj *o, + ecore_list_t *exe_chunk, + unsigned long *ramrod_flags); +typedef struct ecore_exeq_elem * + (*exe_q_get)(struct ecore_exe_queue_obj *o, + struct ecore_exeq_elem *elem); + +struct ecore_exe_queue_obj { + /* Commands pending for an execution. */ + ecore_list_t exe_queue; + + /* Commands pending for an completion. */ + ecore_list_t pending_comp; + + ECORE_MUTEX_SPIN lock; + + /* Maximum length of commands' list for one execution */ + int exe_chunk_len; + + union ecore_qable_obj *owner; + + /****** Virtual functions ******/ + /** + * Called before commands execution for commands that are really + * going to be executed (after 'optimize'). + * + * Must run under exe_queue->lock + */ + exe_q_validate validate; + + /** + * Called before removing pending commands, cleaning allocated + * resources (e.g., credits from validate) + */ + exe_q_remove remove; + + /** + * This will try to cancel the current pending commands list + * considering the new command. + * + * Returns the number of optimized commands or a negative error code + * + * Must run under exe_queue->lock + */ + exe_q_optimize optimize; + + /** + * Run the next commands chunk (owner specific). + */ + exe_q_execute execute; + + /** + * Return the exe_queue element containing the specific command + * if any. Otherwise return NULL. + */ + exe_q_get get; +}; +/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ +/* + * Element in the VLAN_MAC registry list having all current configured + * rules. + */ +struct ecore_vlan_mac_registry_elem { + ecore_list_entry_t link; + + /* Used to store the cam offset used for the mac/vlan/vlan-mac. + * Relevant for 57711 only. VLANs and MACs share the + * same CAM for these chips. + */ + int cam_offset; + + /* Needed for DEL and RESTORE flows */ + unsigned long vlan_mac_flags; + + union ecore_classification_ramrod_data u; +}; + +/* Bits representing VLAN_MAC commands specific flags */ +enum { + ECORE_UC_LIST_MAC, + ECORE_ETH_MAC, + ECORE_ISCSI_ETH_MAC, + ECORE_NETQ_ETH_MAC, + ECORE_DONT_CONSUME_CAM_CREDIT, + ECORE_DONT_CONSUME_CAM_CREDIT_DEST, +}; + +struct ecore_vlan_mac_ramrod_params { + /* Object to run the command from */ + struct ecore_vlan_mac_obj *vlan_mac_obj; + + /* General command flags: COMP_WAIT, etc. */ + unsigned long ramrod_flags; + + /* Command specific configuration request */ + struct ecore_vlan_mac_data user_req; +}; + +struct ecore_vlan_mac_obj { + struct ecore_raw_obj raw; + + /* Bookkeeping list: will prevent the addition of already existing + * entries. + */ + ecore_list_t head; + /* Implement a simple reader/writer lock on the head list. + * all these fields should only be accessed under the exe_queue lock + */ + uint8_t head_reader; /* Num. of readers accessing head list */ + int head_exe_request; /* Pending execution request. */ + unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ + + /* Execution queue interface instance */ + struct ecore_exe_queue_obj exe_queue; + + /* MACs credit pool */ + struct ecore_credit_pool_obj *macs_pool; + + /* VLANs credit pool */ + struct ecore_credit_pool_obj *vlans_pool; + + /* RAMROD command to be used */ + int ramrod_cmd; + + /* copy first n elements onto preallocated buffer + * + * @param n number of elements to get + * @param buf buffer preallocated by caller into which elements + * will be copied. Note elements are 4-byte aligned + * so buffer size must be able to accommodate the + * aligned elements. + * + * @return number of copied bytes + */ + + int (*get_n_elements)(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, int n, uint8_t *base, + uint8_t stride, uint8_t size); + + /** + * Checks if ADD-ramrod with the given params may be performed. + * + * @return zero if the element may be added + */ + + int (*check_add)(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + union ecore_classification_ramrod_data *data); + + /** + * Checks if DEL-ramrod with the given params may be performed. + * + * @return TRUE if the element may be deleted + */ + struct ecore_vlan_mac_registry_elem * + (*check_del)(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + union ecore_classification_ramrod_data *data); + + /** + * Checks if DEL-ramrod with the given params may be performed. + * + * @return TRUE if the element may be deleted + */ + int (*check_move)(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *src_o, + struct ecore_vlan_mac_obj *dst_o, + union ecore_classification_ramrod_data *data); + + /** + * Update the relevant credit object(s) (consume/return + * correspondingly). + */ + int (*get_credit)(struct ecore_vlan_mac_obj *o); + int (*put_credit)(struct ecore_vlan_mac_obj *o); + int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset); + int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset); + + /** + * Configures one rule in the ramrod data buffer. + */ + void (*set_one_rule)(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + struct ecore_exeq_elem *elem, int rule_idx, + int cam_offset); + + /** + * Delete all configured elements having the given + * vlan_mac_flags specification. Assumes no pending for + * execution commands. Will schedule all all currently + * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags + * specification for deletion and will use the given + * ramrod_flags for the last DEL operation. + * + * @param sc + * @param o + * @param ramrod_flags RAMROD_XX flags + * + * @return 0 if the last operation has completed successfully + * and there are no more elements left, positive value + * if there are pending for completion commands, + * negative value in case of failure. + */ + int (*delete_all)(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o, + unsigned long *vlan_mac_flags, + unsigned long *ramrod_flags); + + /** + * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously + * configured elements list. + * + * @param sc + * @param p Command parameters (RAMROD_COMP_WAIT bit in + * ramrod_flags is only taken into an account) + * @param ppos a pointer to the cookie that should be given back in the + * next call to make function handle the next element. If + * *ppos is set to NULL it will restart the iterator. + * If returned *ppos == NULL this means that the last + * element has been handled. + * + * @return int + */ + int (*restore)(struct bnx2x_softc *sc, + struct ecore_vlan_mac_ramrod_params *p, + struct ecore_vlan_mac_registry_elem **ppos); + + /** + * Should be called on a completion arrival. + * + * @param sc + * @param o + * @param cqe Completion element we are handling + * @param ramrod_flags if RAMROD_CONT is set the next bulk of + * pending commands will be executed. + * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE + * may also be set if needed. + * + * @return 0 if there are neither pending nor waiting for + * completion commands. Positive value if there are + * pending for execution or for completion commands. + * Negative value in case of an error (including an + * error in the cqe). + */ + int (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o, + union event_ring_elem *cqe, + unsigned long *ramrod_flags); + + /** + * Wait for completion of all commands. Don't schedule new ones, + * just wait. It assumes that the completion code will schedule + * for new commands. + */ + int (*wait)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o); +}; + +enum { + ECORE_LLH_CAM_ISCSI_ETH_LINE = 0, + ECORE_LLH_CAM_ETH_LINE, + ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 +}; + +/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ + +/* RX_MODE ramrod special flags: set in rx_mode_flags field in + * a ecore_rx_mode_ramrod_params. + */ +enum { + ECORE_RX_MODE_FCOE_ETH, + ECORE_RX_MODE_ISCSI_ETH, +}; + +enum { + ECORE_ACCEPT_UNICAST, + ECORE_ACCEPT_MULTICAST, + ECORE_ACCEPT_ALL_UNICAST, + ECORE_ACCEPT_ALL_MULTICAST, + ECORE_ACCEPT_BROADCAST, + ECORE_ACCEPT_UNMATCHED, + ECORE_ACCEPT_ANY_VLAN +}; + +struct ecore_rx_mode_ramrod_params { + struct ecore_rx_mode_obj *rx_mode_obj; + unsigned long *pstate; + int state; + uint8_t cl_id; + uint32_t cid; + uint8_t func_id; + unsigned long ramrod_flags; + unsigned long rx_mode_flags; + + /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to + * a tstorm_eth_mac_filter_config (e1x). + */ + void *rdata; + ecore_dma_addr_t rdata_mapping; + + /* Rx mode settings */ + unsigned long rx_accept_flags; + + /* internal switching settings */ + unsigned long tx_accept_flags; +}; + +struct ecore_rx_mode_obj { + int (*config_rx_mode)(struct bnx2x_softc *sc, + struct ecore_rx_mode_ramrod_params *p); + + int (*wait_comp)(struct bnx2x_softc *sc, + struct ecore_rx_mode_ramrod_params *p); +}; + +/********************** Set multicast group ***********************************/ + +struct ecore_mcast_list_elem { + ecore_list_entry_t link; + uint8_t *mac; +}; + +union ecore_mcast_config_data { + uint8_t *mac; + uint8_t bin; /* used in a RESTORE flow */ +}; + +struct ecore_mcast_ramrod_params { + struct ecore_mcast_obj *mcast_obj; + + /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ + unsigned long ramrod_flags; + + ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ + int mcast_list_len; +}; + +enum ecore_mcast_cmd { + ECORE_MCAST_CMD_ADD, + ECORE_MCAST_CMD_CONT, + ECORE_MCAST_CMD_DEL, + ECORE_MCAST_CMD_RESTORE, +}; + +struct ecore_mcast_obj { + struct ecore_raw_obj raw; + + union { + struct { + #define ECORE_MCAST_BINS_NUM 256 + #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64) + uint64_t vec[ECORE_MCAST_VEC_SZ]; + + /** Number of BINs to clear. Should be updated + * immediately when a command arrives in order to + * properly create DEL commands. + */ + int num_bins_set; + } aprox_match; + + struct { + ecore_list_t macs; + int num_macs_set; + } exact_match; + } registry; + + /* Pending commands */ + ecore_list_t pending_cmds_head; + + /* A state that is set in raw.pstate, when there are pending commands */ + int sched_state; + + /* Maximal number of mcast MACs configured in one command */ + int max_cmd_len; + + /* Total number of currently pending MACs to configure: both + * in the pending commands list and in the current command. + */ + int total_pending_num; + + uint8_t engine_id; + + /** + * @param cmd command to execute (ECORE_MCAST_CMD_X, see above) + */ + int (*config_mcast)(struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd); + + /** + * Fills the ramrod data during the RESTORE flow. + * + * @param sc + * @param o + * @param start_idx Registry index to start from + * @param rdata_idx Index in the ramrod data to start from + * + * @return -1 if we handled the whole registry or index of the last + * handled registry element. + */ + int (*hdl_restore)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o, + int start_bin, int *rdata_idx); + + int (*enqueue_cmd)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd); + + void (*set_one_rule)(struct bnx2x_softc *sc, + struct ecore_mcast_obj *o, int idx, + union ecore_mcast_config_data *cfg_data, + enum ecore_mcast_cmd cmd); + + /** Checks if there are more mcast MACs to be set or a previous + * command is still pending. + */ + int (*check_pending)(struct ecore_mcast_obj *o); + + /** + * Set/Clear/Check SCHEDULED state of the object + */ + void (*set_sched)(struct ecore_mcast_obj *o); + void (*clear_sched)(struct ecore_mcast_obj *o); + int (*check_sched)(struct ecore_mcast_obj *o); + + /* Wait until all pending commands complete */ + int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o); + + /** + * Handle the internal object counters needed for proper + * commands handling. Checks that the provided parameters are + * feasible. + */ + int (*validate)(struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd); + + /** + * Restore the values of internal counters in case of a failure. + */ + void (*revert)(struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + int old_num_bins); + + int (*get_registry_size)(struct ecore_mcast_obj *o); + void (*set_registry_size)(struct ecore_mcast_obj *o, int n); +}; + +/*************************** Credit handling **********************************/ +struct ecore_credit_pool_obj { + + /* Current amount of credit in the pool */ + ecore_atomic_t credit; + + /* Maximum allowed credit. put() will check against it. */ + int pool_sz; + + /* Allocate a pool table statically. + * + * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) + * + * The set bit in the table will mean that the entry is available. + */ +#define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) + uint64_t pool_mirror[ECORE_POOL_VEC_SIZE]; + + /* Base pool offset (initialized differently */ + int base_pool_offset; + + /** + * Get the next free pool entry. + * + * @return TRUE if there was a free entry in the pool + */ + int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry); + + /** + * Return the entry back to the pool. + * + * @return TRUE if entry is legal and has been successfully + * returned to the pool. + */ + int (*put_entry)(struct ecore_credit_pool_obj *o, int entry); + + /** + * Get the requested amount of credit from the pool. + * + * @param cnt Amount of requested credit + * @return TRUE if the operation is successful + */ + int (*get)(struct ecore_credit_pool_obj *o, int cnt); + + /** + * Returns the credit to the pool. + * + * @param cnt Amount of credit to return + * @return TRUE if the operation is successful + */ + int (*put)(struct ecore_credit_pool_obj *o, int cnt); + + /** + * Reads the current amount of credit. + */ + int (*check)(struct ecore_credit_pool_obj *o); +}; + +/*************************** RSS configuration ********************************/ +enum { + /* RSS_MODE bits are mutually exclusive */ + ECORE_RSS_MODE_DISABLED, + ECORE_RSS_MODE_REGULAR, + + ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ + + ECORE_RSS_IPV4, + ECORE_RSS_IPV4_TCP, + ECORE_RSS_IPV4_UDP, + ECORE_RSS_IPV6, + ECORE_RSS_IPV6_TCP, + ECORE_RSS_IPV6_UDP, + + ECORE_RSS_TUNNELING, +}; + +struct ecore_config_rss_params { + struct ecore_rss_config_obj *rss_obj; + + /* may have RAMROD_COMP_WAIT set only */ + unsigned long ramrod_flags; + + /* ECORE_RSS_X bits */ + unsigned long rss_flags; + + /* Number hash bits to take into an account */ + uint8_t rss_result_mask; + + /* Indirection table */ + uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; + + /* RSS hash values */ + uint32_t rss_key[10]; + + /* valid only iff ECORE_RSS_UPDATE_TOE is set */ + uint16_t toe_rss_bitmap; + + /* valid iff ECORE_RSS_TUNNELING is set */ + uint16_t tunnel_value; + uint16_t tunnel_mask; +}; + +struct ecore_rss_config_obj { + struct ecore_raw_obj raw; + + /* RSS engine to use */ + uint8_t engine_id; + + /* Last configured indirection table */ + uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; + + /* flags for enabling 4-tupple hash on UDP */ + uint8_t udp_rss_v4; + uint8_t udp_rss_v6; + + int (*config_rss)(struct bnx2x_softc *sc, + struct ecore_config_rss_params *p); +}; + +/*********************** Queue state update ***********************************/ + +/* UPDATE command options */ +enum { + ECORE_Q_UPDATE_IN_VLAN_REM, + ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, + ECORE_Q_UPDATE_OUT_VLAN_REM, + ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, + ECORE_Q_UPDATE_ANTI_SPOOF, + ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, + ECORE_Q_UPDATE_ACTIVATE, + ECORE_Q_UPDATE_ACTIVATE_CHNG, + ECORE_Q_UPDATE_DEF_VLAN_EN, + ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, + ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, + ECORE_Q_UPDATE_SILENT_VLAN_REM, + ECORE_Q_UPDATE_TX_SWITCHING_CHNG, + ECORE_Q_UPDATE_TX_SWITCHING, +}; + +/* Allowed Queue states */ +enum ecore_q_state { + ECORE_Q_STATE_RESET, + ECORE_Q_STATE_INITIALIZED, + ECORE_Q_STATE_ACTIVE, + ECORE_Q_STATE_MULTI_COS, + ECORE_Q_STATE_MCOS_TERMINATED, + ECORE_Q_STATE_INACTIVE, + ECORE_Q_STATE_STOPPED, + ECORE_Q_STATE_TERMINATED, + ECORE_Q_STATE_FLRED, + ECORE_Q_STATE_MAX, +}; + +/* Allowed Queue states */ +enum ecore_q_logical_state { + ECORE_Q_LOGICAL_STATE_ACTIVE, + ECORE_Q_LOGICAL_STATE_STOPPED, +}; + +/* Allowed commands */ +enum ecore_queue_cmd { + ECORE_Q_CMD_INIT, + ECORE_Q_CMD_SETUP, + ECORE_Q_CMD_SETUP_TX_ONLY, + ECORE_Q_CMD_DEACTIVATE, + ECORE_Q_CMD_ACTIVATE, + ECORE_Q_CMD_UPDATE, + ECORE_Q_CMD_UPDATE_TPA, + ECORE_Q_CMD_HALT, + ECORE_Q_CMD_CFC_DEL, + ECORE_Q_CMD_TERMINATE, + ECORE_Q_CMD_EMPTY, + ECORE_Q_CMD_MAX, +}; + +/* queue SETUP + INIT flags */ +enum { + ECORE_Q_FLG_TPA, + ECORE_Q_FLG_TPA_IPV6, + ECORE_Q_FLG_TPA_GRO, + ECORE_Q_FLG_STATS, + ECORE_Q_FLG_ZERO_STATS, + ECORE_Q_FLG_ACTIVE, + ECORE_Q_FLG_OV, + ECORE_Q_FLG_VLAN, + ECORE_Q_FLG_COS, + ECORE_Q_FLG_HC, + ECORE_Q_FLG_HC_EN, + ECORE_Q_FLG_DHC, + ECORE_Q_FLG_OOO, + ECORE_Q_FLG_FCOE, + ECORE_Q_FLG_LEADING_RSS, + ECORE_Q_FLG_MCAST, + ECORE_Q_FLG_DEF_VLAN, + ECORE_Q_FLG_TX_SWITCH, + ECORE_Q_FLG_TX_SEC, + ECORE_Q_FLG_ANTI_SPOOF, + ECORE_Q_FLG_SILENT_VLAN_REM, + ECORE_Q_FLG_FORCE_DEFAULT_PRI, + ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, + ECORE_Q_FLG_PCSUM_ON_PKT, + ECORE_Q_FLG_TUN_INC_INNER_IP_ID +}; + +/* Queue type options: queue type may be a combination of below. */ +enum ecore_q_type { + ECORE_Q_TYPE_FWD, + ECORE_Q_TYPE_HAS_RX, + ECORE_Q_TYPE_HAS_TX, +}; + +#define ECORE_PRIMARY_CID_INDEX 0 +#define ECORE_MULTI_TX_COS_E1X 3 /* QM only */ +#define ECORE_MULTI_TX_COS_E2_E3A0 2 +#define ECORE_MULTI_TX_COS_E3B0 3 +#define ECORE_MULTI_TX_COS 3 /* Maximum possible */ +#define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN) + +struct ecore_queue_init_params { + struct { + unsigned long flags; + uint16_t hc_rate; + uint8_t fw_sb_id; + uint8_t sb_cq_index; + } tx; + + struct { + unsigned long flags; + uint16_t hc_rate; + uint8_t fw_sb_id; + uint8_t sb_cq_index; + } rx; + + /* CID context in the host memory */ + struct eth_context *cxts[ECORE_MULTI_TX_COS]; + + /* maximum number of cos supported by hardware */ + uint8_t max_cos; +}; + +struct ecore_queue_terminate_params { + /* index within the tx_only cids of this queue object */ + uint8_t cid_index; +}; + +struct ecore_queue_cfc_del_params { + /* index within the tx_only cids of this queue object */ + uint8_t cid_index; +}; + +struct ecore_queue_update_params { + unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */ + uint16_t def_vlan; + uint16_t silent_removal_value; + uint16_t silent_removal_mask; +/* index within the tx_only cids of this queue object */ + uint8_t cid_index; +}; + +struct rxq_pause_params { + uint16_t bd_th_lo; + uint16_t bd_th_hi; + uint16_t rcq_th_lo; + uint16_t rcq_th_hi; + uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */ + uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */ + uint16_t pri_map; +}; + +/* general */ +struct ecore_general_setup_params { + /* valid iff ECORE_Q_FLG_STATS */ + uint8_t stat_id; + + uint8_t spcl_id; + uint16_t mtu; + uint8_t cos; +}; + +struct ecore_rxq_setup_params { + /* dma */ + ecore_dma_addr_t dscr_map; + ecore_dma_addr_t rcq_map; + ecore_dma_addr_t rcq_np_map; + + uint16_t drop_flags; + uint16_t buf_sz; + uint8_t fw_sb_id; + uint8_t cl_qzone_id; + + /* valid iff ECORE_Q_FLG_TPA */ + uint16_t tpa_agg_sz; + uint8_t max_tpa_queues; + uint8_t rss_engine_id; + + /* valid iff ECORE_Q_FLG_MCAST */ + uint8_t mcast_engine_id; + + uint8_t cache_line_log; + + uint8_t sb_cq_index; + + /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ + uint16_t silent_removal_value; + uint16_t silent_removal_mask; +}; + +struct ecore_txq_setup_params { + /* dma */ + ecore_dma_addr_t dscr_map; + + uint8_t fw_sb_id; + uint8_t sb_cq_index; + uint8_t cos; /* valid iff ECORE_Q_FLG_COS */ + uint16_t traffic_type; + /* equals to the leading rss client id, used for TX classification*/ + uint8_t tss_leading_cl_id; + + /* valid iff ECORE_Q_FLG_DEF_VLAN */ + uint16_t default_vlan; +}; + +struct ecore_queue_setup_params { + struct ecore_general_setup_params gen_params; + struct ecore_txq_setup_params txq_params; + struct ecore_rxq_setup_params rxq_params; + struct rxq_pause_params pause_params; + unsigned long flags; +}; + +struct ecore_queue_setup_tx_only_params { + struct ecore_general_setup_params gen_params; + struct ecore_txq_setup_params txq_params; + unsigned long flags; + /* index within the tx_only cids of this queue object */ + uint8_t cid_index; +}; + +struct ecore_queue_state_params { + struct ecore_queue_sp_obj *q_obj; + + /* Current command */ + enum ecore_queue_cmd cmd; + + /* may have RAMROD_COMP_WAIT set only */ + unsigned long ramrod_flags; + + /* Params according to the current command */ + union { + struct ecore_queue_update_params update; + struct ecore_queue_setup_params setup; + struct ecore_queue_init_params init; + struct ecore_queue_setup_tx_only_params tx_only; + struct ecore_queue_terminate_params terminate; + struct ecore_queue_cfc_del_params cfc_del; + } params; +}; + +struct ecore_viflist_params { + uint8_t echo_res; + uint8_t func_bit_map_res; +}; + +struct ecore_queue_sp_obj { + uint32_t cids[ECORE_MULTI_TX_COS]; + uint8_t cl_id; + uint8_t func_id; + + /* number of traffic classes supported by queue. + * The primary connection of the queue supports the first traffic + * class. Any further traffic class is supported by a tx-only + * connection. + * + * Therefore max_cos is also a number of valid entries in the cids + * array. + */ + uint8_t max_cos; + uint8_t num_tx_only, next_tx_only; + + enum ecore_q_state state, next_state; + + /* bits from enum ecore_q_type */ + unsigned long type; + + /* ECORE_Q_CMD_XX bits. This object implements "one + * pending" paradigm but for debug and tracing purposes it's + * more convenient to have different bits for different + * commands. + */ + unsigned long pending; + + /* Buffer to use as a ramrod data and its mapping */ + void *rdata; + ecore_dma_addr_t rdata_mapping; + + /** + * Performs one state change according to the given parameters. + * + * @return 0 in case of success and negative value otherwise. + */ + int (*send_cmd)(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params); + + /** + * Sets the pending bit according to the requested transition. + */ + int (*set_pending)(struct ecore_queue_sp_obj *o, + struct ecore_queue_state_params *params); + + /** + * Checks that the requested state transition is legal. + */ + int (*check_transition)(struct bnx2x_softc *sc, + struct ecore_queue_sp_obj *o, + struct ecore_queue_state_params *params); + + /** + * Completes the pending command. + */ + int (*complete_cmd)(struct bnx2x_softc *sc, + struct ecore_queue_sp_obj *o, + enum ecore_queue_cmd); + + int (*wait_comp)(struct bnx2x_softc *sc, + struct ecore_queue_sp_obj *o, + enum ecore_queue_cmd cmd); +}; + +/********************** Function state update *********************************/ +/* Allowed Function states */ +enum ecore_func_state { + ECORE_F_STATE_RESET, + ECORE_F_STATE_INITIALIZED, + ECORE_F_STATE_STARTED, + ECORE_F_STATE_TX_STOPPED, + ECORE_F_STATE_MAX, +}; + +/* Allowed Function commands */ +enum ecore_func_cmd { + ECORE_F_CMD_HW_INIT, + ECORE_F_CMD_START, + ECORE_F_CMD_STOP, + ECORE_F_CMD_HW_RESET, + ECORE_F_CMD_AFEX_UPDATE, + ECORE_F_CMD_AFEX_VIFLISTS, + ECORE_F_CMD_TX_STOP, + ECORE_F_CMD_TX_START, + ECORE_F_CMD_SWITCH_UPDATE, + ECORE_F_CMD_MAX, +}; + +struct ecore_func_hw_init_params { + /* A load phase returned by MCP. + * + * May be: + * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP + * FW_MSG_CODE_DRV_LOAD_COMMON + * FW_MSG_CODE_DRV_LOAD_PORT + * FW_MSG_CODE_DRV_LOAD_FUNCTION + */ + uint32_t load_phase; +}; + +struct ecore_func_hw_reset_params { + /* A load phase returned by MCP. + * + * May be: + * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP + * FW_MSG_CODE_DRV_LOAD_COMMON + * FW_MSG_CODE_DRV_LOAD_PORT + * FW_MSG_CODE_DRV_LOAD_FUNCTION + */ + uint32_t reset_phase; +}; + +struct ecore_func_start_params { + /* Multi Function mode: + * - Single Function + * - Switch Dependent + * - Switch Independent + */ + uint16_t mf_mode; + + /* Switch Dependent mode outer VLAN tag */ + uint16_t sd_vlan_tag; + + /* Function cos mode */ + uint8_t network_cos_mode; + + /* NVGRE classification enablement */ + uint8_t nvgre_clss_en; + + /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ + uint8_t gre_tunnel_mode; + + /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ + uint8_t gre_tunnel_rss; + +}; + +struct ecore_func_switch_update_params { + uint8_t suspend; +}; + +struct ecore_func_afex_update_params { + uint16_t vif_id; + uint16_t afex_default_vlan; + uint8_t allowed_priorities; +}; + +struct ecore_func_afex_viflists_params { + uint16_t vif_list_index; + uint8_t func_bit_map; + uint8_t afex_vif_list_command; + uint8_t func_to_clear; +}; +struct ecore_func_tx_start_params { + struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; + uint8_t dcb_enabled; + uint8_t dcb_version; + uint8_t dont_add_pri_0; +}; + +struct ecore_func_state_params { + struct ecore_func_sp_obj *f_obj; + + /* Current command */ + enum ecore_func_cmd cmd; + + /* may have RAMROD_COMP_WAIT set only */ + unsigned long ramrod_flags; + + /* Params according to the current command */ + union { + struct ecore_func_hw_init_params hw_init; + struct ecore_func_hw_reset_params hw_reset; + struct ecore_func_start_params start; + struct ecore_func_switch_update_params switch_update; + struct ecore_func_afex_update_params afex_update; + struct ecore_func_afex_viflists_params afex_viflists; + struct ecore_func_tx_start_params tx_start; + } params; +}; + +struct ecore_func_sp_drv_ops { + /* Init tool + runtime initialization: + * - Common Chip + * - Common (per Path) + * - Port + * - Function phases + */ + int (*init_hw_cmn_chip)(struct bnx2x_softc *sc); + int (*init_hw_cmn)(struct bnx2x_softc *sc); + int (*init_hw_port)(struct bnx2x_softc *sc); + int (*init_hw_func)(struct bnx2x_softc *sc); + + /* Reset Function HW: Common, Port, Function phases. */ + void (*reset_hw_cmn)(struct bnx2x_softc *sc); + void (*reset_hw_port)(struct bnx2x_softc *sc); + void (*reset_hw_func)(struct bnx2x_softc *sc); + + /* Prepare/Release FW resources */ + int (*init_fw)(struct bnx2x_softc *sc); + void (*release_fw)(struct bnx2x_softc *sc); +}; + +struct ecore_func_sp_obj { + enum ecore_func_state state, next_state; + + /* ECORE_FUNC_CMD_XX bits. This object implements "one + * pending" paradigm but for debug and tracing purposes it's + * more convenient to have different bits for different + * commands. + */ + unsigned long pending; + + /* Buffer to use as a ramrod data and its mapping */ + void *rdata; + ecore_dma_addr_t rdata_mapping; + + /* Buffer to use as a afex ramrod data and its mapping. + * This can't be same rdata as above because afex ramrod requests + * can arrive to the object in parallel to other ramrod requests. + */ + void *afex_rdata; + ecore_dma_addr_t afex_rdata_mapping; + + /* this mutex validates that when pending flag is taken, the next + * ramrod to be sent will be the one set the pending bit + */ + ECORE_MUTEX one_pending_mutex; + + /* Driver interface */ + struct ecore_func_sp_drv_ops *drv; + + /** + * Performs one state change according to the given parameters. + * + * @return 0 in case of success and negative value otherwise. + */ + int (*send_cmd)(struct bnx2x_softc *sc, + struct ecore_func_state_params *params); + + /** + * Checks that the requested state transition is legal. + */ + int (*check_transition)(struct bnx2x_softc *sc, + struct ecore_func_sp_obj *o, + struct ecore_func_state_params *params); + + /** + * Completes the pending command. + */ + int (*complete_cmd)(struct bnx2x_softc *sc, + struct ecore_func_sp_obj *o, + enum ecore_func_cmd cmd); + + int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_func_sp_obj *o, + enum ecore_func_cmd cmd); +}; + +/********************** Interfaces ********************************************/ +/* Queueable objects set */ +union ecore_qable_obj { + struct ecore_vlan_mac_obj vlan_mac; +}; +/************** Function state update *********/ +void ecore_init_func_obj(struct bnx2x_softc *sc, + struct ecore_func_sp_obj *obj, + void *rdata, ecore_dma_addr_t rdata_mapping, + void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, + struct ecore_func_sp_drv_ops *drv_iface); + +int ecore_func_state_change(struct bnx2x_softc *sc, + struct ecore_func_state_params *params); + +enum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc, + struct ecore_func_sp_obj *o); +/******************* Queue State **************/ +void ecore_init_queue_obj(struct bnx2x_softc *sc, + struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, + uint8_t cid_cnt, uint8_t func_id, void *rdata, + ecore_dma_addr_t rdata_mapping, unsigned long type); + +int ecore_queue_state_change(struct bnx2x_softc *sc, + struct ecore_queue_state_params *params); + +/********************* VLAN-MAC ****************/ +void ecore_init_mac_obj(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *mac_obj, + uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, + ecore_dma_addr_t rdata_mapping, int state, + unsigned long *pstate, ecore_obj_type type, + struct ecore_credit_pool_obj *macs_pool); + +void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o); +int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o); +void ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc, + struct ecore_vlan_mac_obj *o); +int ecore_config_vlan_mac(struct bnx2x_softc *sc, + struct ecore_vlan_mac_ramrod_params *p); + +int ecore_vlan_mac_move(struct bnx2x_softc *sc, + struct ecore_vlan_mac_ramrod_params *p, + struct ecore_vlan_mac_obj *dest_o); + +/********************* RX MODE ****************/ + +void ecore_init_rx_mode_obj(struct bnx2x_softc *sc, + struct ecore_rx_mode_obj *o); + +/** + * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. + * + * @p: Command parameters + * + * Return: 0 - if operation was successful and there is no pending completions, + * positive number - if there are pending completions, + * negative - if there were errors + */ +int ecore_config_rx_mode(struct bnx2x_softc *sc, + struct ecore_rx_mode_ramrod_params *p); + +/****************** MULTICASTS ****************/ + +void ecore_init_mcast_obj(struct bnx2x_softc *sc, + struct ecore_mcast_obj *mcast_obj, + uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, + uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, + int state, unsigned long *pstate, + ecore_obj_type type); + +/** + * ecore_config_mcast - Configure multicast MACs list. + * + * @cmd: command to execute: BNX2X_MCAST_CMD_X + * + * May configure a new list + * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up + * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current + * configuration, continue to execute the pending commands + * (ECORE_MCAST_CMD_CONT). + * + * If previous command is still pending or if number of MACs to + * configure is more that maximum number of MACs in one command, + * the current command will be enqueued to the tail of the + * pending commands list. + * + * Return: 0 is operation was successfull and there are no pending completions, + * negative if there were errors, positive if there are pending + * completions. + */ +int ecore_config_mcast(struct bnx2x_softc *sc, + struct ecore_mcast_ramrod_params *p, + enum ecore_mcast_cmd cmd); + +/****************** CREDIT POOL ****************/ +void ecore_init_mac_credit_pool(struct bnx2x_softc *sc, + struct ecore_credit_pool_obj *p, uint8_t func_id, + uint8_t func_num); +void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc, + struct ecore_credit_pool_obj *p, uint8_t func_id, + uint8_t func_num); + +/****************** RSS CONFIGURATION ****************/ +void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj, + uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, + void *rdata, ecore_dma_addr_t rdata_mapping, + int state, unsigned long *pstate, + ecore_obj_type type); + +/** + * ecore_config_rss - Updates RSS configuration according to provided parameters + * + * Return: 0 in case of success + */ +int ecore_config_rss(struct bnx2x_softc *sc, + struct ecore_config_rss_params *p); + + +#endif /* ECORE_SP_H */ diff --git a/lib/librte_pmd_bnx2x/elink.c b/lib/librte_pmd_bnx2x/elink.c new file mode 100644 index 0000000..f05aac1 --- /dev/null +++ b/lib/librte_pmd_bnx2x/elink.c @@ -0,0 +1,13378 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "bnx2x.h" +#include "elink.h" +#include "ecore_mfw_req.h" +#include "ecore_fw_defs.h" +#include "ecore_hsi.h" +#include "ecore_reg.h" + +static elink_status_t elink_link_reset(struct elink_params *params, + struct elink_vars *vars, + uint8_t reset_ext_phy); +static elink_status_t elink_check_half_open_conn(struct elink_params *params, + struct elink_vars *vars, + uint8_t notify); +static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, + struct elink_params *params); + +#define MDIO_REG_BANK_CL73_IEEEB0 0x0 +#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 +#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 +#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 +#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 + +#define MDIO_REG_BANK_CL73_IEEEB1 0x10 +#define MDIO_CL73_IEEEB1_AN_ADV1 0x00 +#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 +#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 +#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 +#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 +#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 +#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 +#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 +#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 +#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 +#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 +#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 +#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 +#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 +#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 +#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 + +#define MDIO_REG_BANK_RX0 0x80b0 +#define MDIO_RX0_RX_STATUS 0x10 +#define MDIO_RX0_RX_STATUS_SIGDET 0x8000 +#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 +#define MDIO_RX0_RX_EQ_BOOST 0x1c +#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 +#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 + +#define MDIO_REG_BANK_RX1 0x80c0 +#define MDIO_RX1_RX_EQ_BOOST 0x1c +#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 +#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 + +#define MDIO_REG_BANK_RX2 0x80d0 +#define MDIO_RX2_RX_EQ_BOOST 0x1c +#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 +#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 + +#define MDIO_REG_BANK_RX3 0x80e0 +#define MDIO_RX3_RX_EQ_BOOST 0x1c +#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 +#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 + +#define MDIO_REG_BANK_RX_ALL 0x80f0 +#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c +#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 +#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 + +#define MDIO_REG_BANK_TX0 0x8060 +#define MDIO_TX0_TX_DRIVER 0x17 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 +#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 +#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 +#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e +#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 +#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + +#define MDIO_REG_BANK_TX1 0x8070 +#define MDIO_TX1_TX_DRIVER 0x17 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 +#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 +#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 +#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e +#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 +#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + +#define MDIO_REG_BANK_TX2 0x8080 +#define MDIO_TX2_TX_DRIVER 0x17 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 +#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 +#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 +#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e +#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 +#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + +#define MDIO_REG_BANK_TX3 0x8090 +#define MDIO_TX3_TX_DRIVER 0x17 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 +#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 +#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 +#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 +#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 +#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e +#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 +#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + +#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 +#define MDIO_BLOCK0_XGXS_CONTROL 0x10 + +#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 +#define MDIO_BLOCK1_LANE_CTRL0 0x15 +#define MDIO_BLOCK1_LANE_CTRL1 0x16 +#define MDIO_BLOCK1_LANE_CTRL2 0x17 +#define MDIO_BLOCK1_LANE_PRBS 0x19 + +#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 +#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 +#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 +#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 +#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 +#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 +#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 +#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 +#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 +#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 + +#define MDIO_REG_BANK_GP_STATUS 0x8120 +#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B +#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 +#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 + +#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 +#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 +#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 +#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 +#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 +#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 +#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) + +#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 +#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 +#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 +#define MDIO_SERDES_DIGITAL_MISC1 0x18 +#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 +#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 +#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 +#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 +#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 +#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 +#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 + +#define MDIO_REG_BANK_OVER_1G 0x8320 +#define MDIO_OVER_1G_DIGCTL_3_4 0x14 +#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 +#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 +#define MDIO_OVER_1G_UP1 0x19 +#define MDIO_OVER_1G_UP1_2_5G 0x0001 +#define MDIO_OVER_1G_UP1_5G 0x0002 +#define MDIO_OVER_1G_UP1_6G 0x0004 +#define MDIO_OVER_1G_UP1_10G 0x0010 +#define MDIO_OVER_1G_UP1_10GH 0x0008 +#define MDIO_OVER_1G_UP1_12G 0x0020 +#define MDIO_OVER_1G_UP1_12_5G 0x0040 +#define MDIO_OVER_1G_UP1_13G 0x0080 +#define MDIO_OVER_1G_UP1_15G 0x0100 +#define MDIO_OVER_1G_UP1_16G 0x0200 +#define MDIO_OVER_1G_UP2 0x1A +#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 +#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 +#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 +#define MDIO_OVER_1G_UP3 0x1B +#define MDIO_OVER_1G_UP3_HIGIG2 0x0001 +#define MDIO_OVER_1G_LP_UP1 0x1C +#define MDIO_OVER_1G_LP_UP2 0x1D +#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff +#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 +#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 +#define MDIO_OVER_1G_LP_UP3 0x1E + +#define MDIO_REG_BANK_REMOTE_PHY 0x8330 +#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 +#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 +#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 + +#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 +#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 +#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 +#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 + +#define MDIO_REG_BANK_CL73_USERB0 0x8370 +#define MDIO_CL73_USERB0_CL73_UCTRL 0x10 +#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 +#define MDIO_CL73_USERB0_CL73_USTAT1 0x11 +#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 +#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 +#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 +#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 +#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 +#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 +#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 +#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 + +#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 +#define MDIO_AER_BLOCK_AER_REG 0x1E + +#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 +#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 +#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 +#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 +#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 +#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 +#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 +#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 +#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 +#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 +#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 +#define MDIO_COMBO_IEEE0_MII_STATUS 0x11 +#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 +#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 +#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 +/*WhenthelinkpartnerisinSGMIImode(bit0=1),then +bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. +Theotherbitsarereservedandshouldbezero*/ +#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 + +#define MDIO_PMA_DEVAD 0x1 +/*ieee*/ +#define MDIO_PMA_REG_CTRL 0x0 +#define MDIO_PMA_REG_STATUS 0x1 +#define MDIO_PMA_REG_10G_CTRL2 0x7 +#define MDIO_PMA_REG_TX_DISABLE 0x0009 +#define MDIO_PMA_REG_RX_SD 0xa +/*bnx2x*/ +#define MDIO_PMA_REG_BNX2X_CTRL 0x0096 +#define MDIO_PMA_REG_FEC_CTRL 0x00ab +#define MDIO_PMA_LASI_RXCTRL 0x9000 +#define MDIO_PMA_LASI_TXCTRL 0x9001 +#define MDIO_PMA_LASI_CTRL 0x9002 +#define MDIO_PMA_LASI_RXSTAT 0x9003 +#define MDIO_PMA_LASI_TXSTAT 0x9004 +#define MDIO_PMA_LASI_STAT 0x9005 +#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 +#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 +#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 +#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 +#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 +#define MDIO_PMA_REG_MISC_CTRL 0xca0a +#define MDIO_PMA_REG_GEN_CTRL 0xca10 +#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 +#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a +#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 +#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 +#define MDIO_PMA_REG_ROM_VER1 0xca19 +#define MDIO_PMA_REG_ROM_VER2 0xca1a +#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b +#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d +#define MDIO_PMA_REG_PLL_CTRL 0xca1e +#define MDIO_PMA_REG_MISC_CTRL0 0xca23 +#define MDIO_PMA_REG_LRM_MODE 0xca3f +#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 +#define MDIO_PMA_REG_MISC_CTRL1 0xca85 + +#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 +#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c +#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 +#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 +#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 +#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff +#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 +#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 + +#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 +#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 +#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff +#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 +#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 +#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 +#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 +#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e +#define MDIO_PMA_REG_8727_PCS_GP 0xc842 +#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 + +#define MDIO_AN_REG_8727_MISC_CTRL 0x8309 +#define MDIO_PMA_REG_8073_CHIP_REV 0xc801 +#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 +#define MDIO_PMA_REG_8073_XAUI_WA 0xc841 +#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 + +#define MDIO_PMA_REG_7101_RESET 0xc000 +#define MDIO_PMA_REG_7107_LED_CNTL 0xc007 +#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 +#define MDIO_PMA_REG_7101_VER1 0xc026 +#define MDIO_PMA_REG_7101_VER2 0xc027 + +#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 +#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c +#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f +#define MDIO_PMA_REG_8481_LED3_MASK 0xa832 +#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 +#define MDIO_PMA_REG_8481_LED5_MASK 0xa838 +#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 +#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b +#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 +#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 + +#define MDIO_WIS_DEVAD 0x2 +/*bnx2x*/ +#define MDIO_WIS_REG_LASI_CNTL 0x9002 +#define MDIO_WIS_REG_LASI_STATUS 0x9005 + +#define MDIO_PCS_DEVAD 0x3 +#define MDIO_PCS_REG_STATUS 0x0020 +#define MDIO_PCS_REG_LASI_STATUS 0x9005 +#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 +#define MDIO_PCS_REG_7101_SPI_MUX 0xD008 +#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A +#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) +#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A +#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) +#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) +#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) +#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 + +#define MDIO_XS_DEVAD 0x4 +#define MDIO_XS_REG_STATUS 0x0001 +#define MDIO_XS_PLL_SEQUENCER 0x8000 +#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a + +#define MDIO_XS_8706_REG_BANK_RX0 0x80bc +#define MDIO_XS_8706_REG_BANK_RX1 0x80cc +#define MDIO_XS_8706_REG_BANK_RX2 0x80dc +#define MDIO_XS_8706_REG_BANK_RX3 0x80ec +#define MDIO_XS_8706_REG_BANK_RXA 0x80fc + +#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA + +#define MDIO_AN_DEVAD 0x7 +/*ieee*/ +#define MDIO_AN_REG_CTRL 0x0000 +#define MDIO_AN_REG_STATUS 0x0001 +#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 +#define MDIO_AN_REG_ADV_PAUSE 0x0010 +#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 +#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 +#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 +#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 +#define MDIO_AN_REG_ADV 0x0011 +#define MDIO_AN_REG_ADV2 0x0012 +#define MDIO_AN_REG_LP_AUTO_NEG 0x0013 +#define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 +#define MDIO_AN_REG_MASTER_STATUS 0x0021 +#define MDIO_AN_REG_EEE_ADV 0x003c +#define MDIO_AN_REG_LP_EEE_ADV 0x003d +/*bnx2x*/ +#define MDIO_AN_REG_LINK_STATUS 0x8304 +#define MDIO_AN_REG_CL37_CL73 0x8370 +#define MDIO_AN_REG_CL37_AN 0xffe0 +#define MDIO_AN_REG_CL37_FC_LD 0xffe4 +#define MDIO_AN_REG_CL37_FC_LP 0xffe5 +#define MDIO_AN_REG_1000T_STATUS 0xffea + +#define MDIO_AN_REG_8073_2_5G 0x8329 +#define MDIO_AN_REG_8073_BAM 0x8350 + +#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 +#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 +#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 +#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 +#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 +#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 +#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 +#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 +#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 +#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 +#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 +#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 +#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc + +/* BNX2X84823 only */ +#define MDIO_CTL_DEVAD 0x1e +#define MDIO_CTL_REG_84823_MEDIA 0x401a +#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 + /* These pins configure the BNX2X84823 interface to MAC after reset. */ +#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 +#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 + /* These pins configure the BNX2X84823 interface to Line after reset. */ +#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 +#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 +#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 + /* When this pin is active high during reset, 10GBASE-T core is power + * down, When it is active low the 10GBASE-T is power up + */ +#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 +#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 +#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 +#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 +#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 +#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 +#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 +#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b +#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f +#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 +#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec +#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 + +/* BNX2X84833 only */ +#define MDIO_84833_TOP_CFG_FW_REV 0x400f +#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 +#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 +#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a +#define MDIO_84833_SUPER_ISOLATE 0x8000 +/* These are mailbox register set used by 84833. */ +#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 +#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 +#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 +#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 +#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 +#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 +#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 +#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 +#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a +#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b +#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c +#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 +#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 +#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 +#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 +#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 +#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 +#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 + +/* Mailbox command set used by 84833. */ +#define PHY84833_CMD_SET_PAIR_SWAP 0x8001 +#define PHY84833_CMD_GET_EEE_MODE 0x8008 +#define PHY84833_CMD_SET_EEE_MODE 0x8009 +#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031 +/* Mailbox status set used by 84833. */ +#define PHY84833_STATUS_CMD_RECEIVED 0x0001 +#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 +#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 +#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 +#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 +#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 +#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 +#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 +#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 + +/* Warpcore clause 45 addressing */ +#define MDIO_WC_DEVAD 0x3 +#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 +#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 +#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 +#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 +#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 +#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 +#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 +#define MDIO_WC_REG_PCS_STATUS2 0x0021 +#define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 +#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 +#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e +#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 +#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 +#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 +#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 +#define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018 +#define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a +#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 +#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 +#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 +#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 +#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 +#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 +#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 +#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 +#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 +#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c +#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 +#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 +#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 +#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 +#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 +#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 +#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba +#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca +#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da +#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea +#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 +#define MDIO_WC_REG_XGXS_STATUS3 0x8129 +#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 +#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 +#define MDIO_WC_REG_XGXS_STATUS4 0x813c +#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 +#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 +#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B +#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 +#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 +#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 +#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 +#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 +#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 +#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 +#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 +#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 +#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 +#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE +#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 +#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc +#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE +#define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e +#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7) +#define MDIO_WC_REG_DSC_SMC 0x8213 +#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e +#define MDIO_WC_REG_TX_FIR_TAP 0x82e2 +#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 +#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f +#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 +#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 +#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a +#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 +#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 +#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 +#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 +#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 +#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 +#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 +#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec +#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 +#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 +#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 +#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 +#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 +#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 +#define MDIO_WC_REG_DIGITAL3_UP1 0x8329 +#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c +#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c +#define MDIO_WC_REG_DIGITAL4_MISC5 0x833e +#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 +#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 +#define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d +#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e +#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 +#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 +#define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 +#define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 +#define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 +#define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 +#define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 +#define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b +#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 +#define MDIO_WC_REG_TX66_CONTROL 0x83b0 +#define MDIO_WC_REG_RX66_CONTROL 0x83c0 +#define MDIO_WC_REG_RX66_SCW0 0x83c2 +#define MDIO_WC_REG_RX66_SCW1 0x83c3 +#define MDIO_WC_REG_RX66_SCW2 0x83c4 +#define MDIO_WC_REG_RX66_SCW3 0x83c5 +#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 +#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 +#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 +#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 +#define MDIO_WC_REG_FX100_CTRL1 0x8400 +#define MDIO_WC_REG_FX100_CTRL3 0x8402 +#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 +#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 +#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 +#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 +#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a +#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b +#define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 +#define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 +#define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 +#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 +#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 +#define MDIO_WC_REG_MICROBLK_CMD 0xffc2 +#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 +#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc + +#define MDIO_WC_REG_AERBLK_AER 0xffde +#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 +#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 + +#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A +#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 +#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 + +#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 + +#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f + +/* 54618se */ +#define MDIO_REG_GPHY_MII_STATUS 0x1 +#define MDIO_REG_GPHY_PHYID_LSB 0x3 +#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd +#define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 +#define MDIO_REG_GPHY_CL45_REG_READ 0xc000 +#define MDIO_REG_GPHY_CL45_DATA_REG 0xe +#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e +#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 +#define MDIO_REG_GPHY_EXP_ACCESS 0x17 +#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 +#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 +#define MDIO_REG_GPHY_AUX_STATUS 0x19 +#define MDIO_REG_INTR_STATUS 0x1a +#define MDIO_REG_INTR_MASK 0x1b +#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) +#define MDIO_REG_GPHY_SHADOW 0x1c +#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) +#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) +#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) +#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) +#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) + +typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy, + struct elink_params * + params, + uint8_t dev_addr, + uint16_t addr, + uint8_t byte_cnt, + uint8_t * o_buf, + uint8_t); +/********************************************************/ +#define ELINK_ETH_HLEN 14 +/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ +#define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8) +#define ELINK_ETH_MIN_PACKET_SIZE 60 +#define ELINK_ETH_MAX_PACKET_SIZE 1500 +#define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600 +#define ELINK_MDIO_ACCESS_TIMEOUT 1000 +#define WC_LANE_MAX 4 +#define I2C_SWITCH_WIDTH 2 +#define I2C_BSC0 0 +#define I2C_BSC1 1 +#define I2C_WA_RETRY_CNT 3 +#define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) +#define MCPR_IMC_COMMAND_READ_OP 1 +#define MCPR_IMC_COMMAND_WRITE_OP 2 + +/* LED Blink rate that will achieve ~15.9Hz */ +#define LED_BLINK_RATE_VAL_E3 354 +#define LED_BLINK_RATE_VAL_E1X_E2 480 +/***********************************************************/ +/* Shortcut definitions */ +/***********************************************************/ + +#define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0 + +#define ELINK_NIG_STATUS_EMAC0_MI_INT \ + NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT +#define ELINK_NIG_STATUS_XGXS0_LINK10G \ + NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G +#define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \ + NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS +#define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ + NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE +#define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \ + NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS +#define ELINK_NIG_MASK_MI_INT \ + NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT +#define ELINK_NIG_MASK_XGXS0_LINK10G \ + NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G +#define ELINK_NIG_MASK_XGXS0_LINK_STATUS \ + NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS +#define ELINK_NIG_MASK_SERDES0_LINK_STATUS \ + NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS + +#define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \ + (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ + MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) + +#define ELINK_XGXS_RESET_BITS \ + (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ + MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ + MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ + MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ + MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) + +#define ELINK_SERDES_RESET_BITS \ + (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ + MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ + MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ + MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) + +#define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 +#define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 +#define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM +#define ELINK_AUTONEG_PARALLEL \ + SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION +#define ELINK_AUTONEG_SGMII_FIBER_AUTODET \ + SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT +#define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY + +#define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ + MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE +#define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ + MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE +#define ELINK_GP_STATUS_SPEED_MASK \ + MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK +#define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M +#define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M +#define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G +#define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G +#define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G +#define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G +#define ELINK_GP_STATUS_10G_HIG \ + MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG +#define ELINK_GP_STATUS_10G_CX4 \ + MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 +#define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX +#define ELINK_GP_STATUS_10G_KX4 \ + MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 +#define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR +#define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI +#define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS +#define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI +#define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 +#define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD +#define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD +#define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD +#define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 +#define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD +#define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD +#define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD +#define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD +#define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD +#define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD +#define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD +#define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD +#define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD +#define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD +#define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD + +#define ELINK_LINK_UPDATE_MASK \ + (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ + LINK_STATUS_LINK_UP | \ + LINK_STATUS_PHYSICAL_LINK_FLAG | \ + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ + LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ + LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ + LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ + LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ + LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) + +#define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2 +#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 +#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 +#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 + +#define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3 +#define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) +#define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) +#define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) + +#define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8 +#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 +#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 + +#define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40 +#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 +#define ELINK_SFP_EEPROM_OPTIONS_SIZE 2 + +#define ELINK_EDC_MODE_LINEAR 0x0022 +#define ELINK_EDC_MODE_LIMITING 0x0044 +#define ELINK_EDC_MODE_PASSIVE_DAC 0x0055 +#define ELINK_EDC_MODE_ACTIVE_DAC 0x0066 + +/* ETS defines*/ +#define DCBX_INVALID_COS (0xFF) + +#define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) +#define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) +#define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) +#define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) +#define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000) + +#define ELINK_MAX_PACKET_SIZE (9700) +#define MAX_KR_LINK_RETRY 4 + +/**********************************************************/ +/* INTERFACE */ +/**********************************************************/ + +#define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \ + elink_cl45_write(_sc, _phy, \ + (_phy)->def_md_devad, \ + (_bank + (_addr & 0xf)), \ + _val) + +#define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \ + elink_cl45_read(_sc, _phy, \ + (_phy)->def_md_devad, \ + (_bank + (_addr & 0xf)), \ + _val) + +static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits) +{ + uint32_t val = REG_RD(sc, reg); + + val |= bits; + REG_WR(sc, reg, val); + return val; +} + +static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg, + uint32_t bits) +{ + uint32_t val = REG_RD(sc, reg); + + val &= ~bits; + REG_WR(sc, reg, val); + return val; +} + +/* + * elink_check_lfa - This function checks if link reinitialization is required, + * or link flap can be avoided. + * + * @params: link parameters + * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed + * condition code. + */ +static int elink_check_lfa(struct elink_params *params) +{ + uint32_t link_status, cfg_idx, lfa_mask, cfg_size; + uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; + uint32_t saved_val, req_val, eee_status; + struct bnx2x_softc *sc = params->sc; + + additional_config = + REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, additional_config)); + + /* NOTE: must be first condition checked - + * to verify DCC bit is cleared in any case! + */ + if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { + PMD_DRV_LOG(DEBUG, "No LFA due to DCC flap after clp exit"); + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, additional_config), + additional_config & ~NO_LFA_DUE_TO_DCC_MASK); + return LFA_DCC_LFA_DISABLED; + } + + /* Verify that link is up */ + link_status = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + port_mb[params->port].link_status)); + if (!(link_status & LINK_STATUS_LINK_UP)) + return LFA_LINK_DOWN; + + /* if loaded after BOOT from SAN, don't flap the link in any case and + * rely on link set by preboot driver + */ + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN) + return 0; + + /* Verify that loopback mode is not set */ + if (params->loopback_mode) + return LFA_LOOPBACK_ENABLED; + + /* Verify that MFW supports LFA */ + if (!params->lfa_base) + return LFA_MFW_IS_TOO_OLD; + + if (params->num_phys == 3) { + cfg_size = 2; + lfa_mask = 0xffffffff; + } else { + cfg_size = 1; + lfa_mask = 0xffff; + } + + /* Compare Duplex */ + saved_val = REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, req_duplex)); + req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); + if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { + PMD_DRV_LOG(INFO, "Duplex mismatch %x vs. %x", + (saved_val & lfa_mask), (req_val & lfa_mask)); + return LFA_DUPLEX_MISMATCH; + } + /* Compare Flow Control */ + saved_val = REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, req_flow_ctrl)); + req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); + if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { + PMD_DRV_LOG(DEBUG, "Flow control mismatch %x vs. %x", + (saved_val & lfa_mask), (req_val & lfa_mask)); + return LFA_FLOW_CTRL_MISMATCH; + } + /* Compare Link Speed */ + saved_val = REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, req_line_speed)); + req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); + if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { + PMD_DRV_LOG(DEBUG, "Link speed mismatch %x vs. %x", + (saved_val & lfa_mask), (req_val & lfa_mask)); + return LFA_LINK_SPEED_MISMATCH; + } + + for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { + cur_speed_cap_mask = REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, + speed_cap_mask[cfg_idx])); + + if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { + PMD_DRV_LOG(DEBUG, "Speed Cap mismatch %x vs. %x", + cur_speed_cap_mask, + params->speed_cap_mask[cfg_idx]); + return LFA_SPEED_CAP_MISMATCH; + } + } + + cur_req_fc_auto_adv = + REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, additional_config)) & + REQ_FC_AUTO_ADV_MASK; + + if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) { + PMD_DRV_LOG(DEBUG, "Flow Ctrl AN mismatch %x vs. %x", + cur_req_fc_auto_adv, params->req_fc_auto_adv); + return LFA_FLOW_CTRL_MISMATCH; + } + + eee_status = REG_RD(sc, params->shmem2_base + + offsetof(struct shmem2_region, + eee_status[params->port])); + + if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ + (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || + ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ + (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { + PMD_DRV_LOG(DEBUG, "EEE mismatch %x vs. %x", params->eee_mode, + eee_status); + return LFA_EEE_MISMATCH; + } + + /* LFA conditions are met */ + return 0; +} + +/******************************************************************/ +/* EPIO/GPIO section */ +/******************************************************************/ +static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin, + uint32_t * en) +{ + uint32_t epio_mask, gp_oenable; + *en = 0; + /* Sanity check */ + if (epio_pin > 31) { + PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to get", epio_pin); + return; + } + + epio_mask = 1 << epio_pin; + /* Set this EPIO to output */ + gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE); + REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); + + *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; +} + +static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en) +{ + uint32_t epio_mask, gp_output, gp_oenable; + + /* Sanity check */ + if (epio_pin > 31) { + PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to set", epio_pin); + return; + } + PMD_DRV_LOG(DEBUG, "Setting EPIO pin %d to %d", epio_pin, en); + epio_mask = 1 << epio_pin; + /* Set this EPIO to output */ + gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS); + if (en) + gp_output |= epio_mask; + else + gp_output &= ~epio_mask; + + REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output); + + /* Set the value for this EPIO */ + gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE); + REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); +} + +static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg, + uint32_t val) +{ + if (pin_cfg == PIN_CFG_NA) + return; + if (pin_cfg >= PIN_CFG_EPIO0) { + elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); + } else { + uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; + uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; + elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port); + } +} + +static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg, + uint32_t * val) +{ + if (pin_cfg == PIN_CFG_NA) + return ELINK_STATUS_ERROR; + if (pin_cfg >= PIN_CFG_EPIO0) { + elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); + } else { + uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; + uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; + *val = elink_cb_gpio_read(sc, gpio_num, gpio_port); + } + return ELINK_STATUS_OK; + +} + +/******************************************************************/ +/* PFC section */ +/******************************************************************/ +static void elink_update_pfc_xmac(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t xmac_base; + uint32_t pause_val, pfc0_val, pfc1_val; + + /* XMAC base adrr */ + xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + + /* Initialize pause and pfc registers */ + pause_val = 0x18000; + pfc0_val = 0xFFFF8000; + pfc1_val = 0x2; + + /* No PFC support */ + if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) { + + /* RX flow control - Process pause frame in receive direction + */ + if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) + pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; + + /* TX flow control - Send pause packet when buffer is full */ + if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) + pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; + } else { /* PFC support */ + pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | + XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | + XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | + XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | + XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; + /* Write pause and PFC registers */ + REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); + REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); + REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); + pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; + + } + + /* Write pause and PFC registers */ + REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); + REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); + REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); + + /* Set MAC address for source TX Pause/PFC frames */ + REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO, + ((params->mac_addr[2] << 24) | + (params->mac_addr[3] << 16) | + (params->mac_addr[4] << 8) | (params->mac_addr[5]))); + REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI, + ((params->mac_addr[0] << 8) | (params->mac_addr[1]))); + + DELAY(30); +} + +/******************************************************************/ +/* MAC/PBF section */ +/******************************************************************/ +static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base) +{ + uint32_t new_mode, cur_mode; + uint32_t clc_cnt; + /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz + * (a value of 49==0x31) and make sure that the AUTO poll is off + */ + cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE); + + if (USES_WARPCORE(sc)) + clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; + else + clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; + + if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && + (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) + return; + + new_mode = cur_mode & + ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); + new_mode |= clc_cnt; + new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); + + PMD_DRV_LOG(DEBUG, "Changing emac_mode from 0x%x to 0x%x", + cur_mode, new_mode); + REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); + DELAY(40); +} + +static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc, + struct elink_params *params) +{ + uint8_t phy_index; + /* Set mdio clock per phy */ + for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; + phy_index++) + elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl); +} + +static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc) +{ + uint32_t port4mode_ovwr_val; + /* Check 4-port override enabled */ + port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); + if (port4mode_ovwr_val & (1 << 0)) { + /* Return 4-port mode override value */ + return ((port4mode_ovwr_val & (1 << 1)) == (1 << 1)); + } + /* Return 4-port mode from input pin */ + return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN); +} + +static void elink_emac_init(struct elink_params *params) +{ + /* reset and unreset the emac core */ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + uint32_t val; + uint16_t timeout; + + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); + DELAY(5); + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); + + /* init emac - use read-modify-write */ + /* self clear reset */ + val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, + (val | EMAC_MODE_RESET)); + + timeout = 200; + do { + val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); + PMD_DRV_LOG(DEBUG, "EMAC reset reg is %u", val); + if (!timeout) { + PMD_DRV_LOG(DEBUG, "EMAC timeout!"); + return; + } + timeout--; + } while (val & EMAC_MODE_RESET); + + elink_set_mdio_emac_per_phy(sc, params); + /* Set mac address */ + val = ((params->mac_addr[0] << 8) | params->mac_addr[1]); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val); + + val = ((params->mac_addr[2] << 24) | + (params->mac_addr[3] << 16) | + (params->mac_addr[4] << 8) | params->mac_addr[5]); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val); +} + +static void elink_set_xumac_nig(struct elink_params *params, + uint16_t tx_pause_en, uint8_t enable) +{ + struct bnx2x_softc *sc = params->sc; + + REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, + enable); + REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, + enable); + REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : + NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); +} + +static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en) +{ + uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; + uint32_t val; + struct bnx2x_softc *sc = params->sc; + if (!(REG_RD(sc, MISC_REG_RESET_REG_2) & + (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) + return; + val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG); + if (en) + val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | + UMAC_COMMAND_CONFIG_REG_RX_ENA); + else + val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | + UMAC_COMMAND_CONFIG_REG_RX_ENA); + /* Disable RX and TX */ + REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); +} + +static void elink_umac_enable(struct elink_params *params, + struct elink_vars *vars, uint8_t lb) +{ + uint32_t val; + uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; + struct bnx2x_softc *sc = params->sc; + /* Reset UMAC */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); + DELAY(1000 * 1); + + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); + + PMD_DRV_LOG(DEBUG, "enabling UMAC"); + + /* This register opens the gate for the UMAC despite its name */ + REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1); + + val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | + UMAC_COMMAND_CONFIG_REG_PAD_EN | + UMAC_COMMAND_CONFIG_REG_SW_RESET | + UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; + switch (vars->line_speed) { + case ELINK_SPEED_10: + val |= (0 << 2); + break; + case ELINK_SPEED_100: + val |= (1 << 2); + break; + case ELINK_SPEED_1000: + val |= (2 << 2); + break; + case ELINK_SPEED_2500: + val |= (3 << 2); + break; + default: + PMD_DRV_LOG(DEBUG, "Invalid speed for UMAC %d", + vars->line_speed); + break; + } + if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) + val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; + + if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) + val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; + + if (vars->duplex == DUPLEX_HALF) + val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; + + REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); + DELAY(50); + + /* Configure UMAC for EEE */ + if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { + PMD_DRV_LOG(DEBUG, "configured UMAC for EEE"); + REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, + UMAC_UMAC_EEE_CTRL_REG_EEE_EN); + REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); + } else { + REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); + } + + /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ + REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0, + ((params->mac_addr[2] << 24) | + (params->mac_addr[3] << 16) | + (params->mac_addr[4] << 8) | (params->mac_addr[5]))); + REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1, + ((params->mac_addr[0] << 8) | (params->mac_addr[1]))); + + /* Enable RX and TX */ + val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; + val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA; + REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); + DELAY(50); + + /* Remove SW Reset */ + val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; + + /* Check loopback mode */ + if (lb) + val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; + REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); + + /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame + * length used by the MAC receive logic to check frames. + */ + REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); + elink_set_xumac_nig(params, + ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); + vars->mac_type = ELINK_MAC_TYPE_UMAC; + +} + +/* Define the XMAC mode */ +static void elink_xmac_init(struct elink_params *params, uint32_t max_speed) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t is_port4mode = elink_is_4_port_mode(sc); + + /* In 4-port mode, need to set the mode only once, so if XMAC is + * already out of reset, it means the mode has already been set, + * and it must not* reset the XMAC again, since it controls both + * ports of the path + */ + + if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || + (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) || + (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) && + is_port4mode && + (REG_RD(sc, MISC_REG_RESET_REG_2) & + MISC_REGISTERS_RESET_REG_2_XMAC)) { + PMD_DRV_LOG(DEBUG, "XMAC already out of reset in 4-port mode"); + return; + } + + /* Hard reset */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + MISC_REGISTERS_RESET_REG_2_XMAC); + DELAY(1000 * 1); + + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + MISC_REGISTERS_RESET_REG_2_XMAC); + if (is_port4mode) { + PMD_DRV_LOG(DEBUG, "Init XMAC to 2 ports x 10G per path"); + + /* Set the number of ports on the system side to up to 2 */ + REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1); + + /* Set the number of ports on the Warp Core to 10G */ + REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); + } else { + /* Set the number of ports on the system side to 1 */ + REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0); + if (max_speed == ELINK_SPEED_10000) { + PMD_DRV_LOG(DEBUG, + "Init XMAC to 10G x 1 port per path"); + /* Set the number of ports on the Warp Core to 10G */ + REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); + } else { + PMD_DRV_LOG(DEBUG, + "Init XMAC to 20G x 2 ports per path"); + /* Set the number of ports on the Warp Core to 20G */ + REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1); + } + } + /* Soft reset */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); + DELAY(1000 * 1); + + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); + +} + +static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en) +{ + uint8_t port = params->port; + struct bnx2x_softc *sc = params->sc; + uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + uint32_t val; + + if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) { + /* Send an indication to change the state in the NIG back to XON + * Clearing this bit enables the next set of this bit to get + * rising edge + */ + pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI); + REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, + (pfc_ctrl & ~(1 << 1))); + REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, + (pfc_ctrl | (1 << 1))); + PMD_DRV_LOG(DEBUG, "Disable XMAC on port %x", port); + val = REG_RD(sc, xmac_base + XMAC_REG_CTRL); + if (en) + val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); + else + val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); + REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); + } +} + +static elink_status_t elink_xmac_enable(struct elink_params *params, + struct elink_vars *vars, uint8_t lb) +{ + uint32_t val, xmac_base; + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "enabling XMAC"); + + xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + + elink_xmac_init(params, vars->line_speed); + + /* This register determines on which events the MAC will assert + * error on the i/f to the NIG along w/ EOP. + */ + + /* This register tells the NIG whether to send traffic to UMAC + * or XMAC + */ + REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0); + + /* When XMAC is in XLGMII mode, disable sending idles for fault + * detection. + */ + if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { + REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL, + (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | + XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); + REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); + REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, + XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | + XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); + } + /* Set Max packet size */ + REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); + + /* CRC append for Tx packets */ + REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800); + + /* update PFC */ + elink_update_pfc_xmac(params, vars); + + if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { + PMD_DRV_LOG(DEBUG, "Setting XMAC for EEE"); + REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); + REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1); + } else { + REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0); + } + + /* Enable TX and RX */ + val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; + + /* Set MAC in XLGMII mode for dual-mode */ + if ((vars->line_speed == ELINK_SPEED_20000) && + (params->phy[ELINK_INT_PHY].supported & + ELINK_SUPPORTED_20000baseKR2_Full)) + val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; + + /* Check loopback mode */ + if (lb) + val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; + REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); + elink_set_xumac_nig(params, + ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); + + vars->mac_type = ELINK_MAC_TYPE_XMAC; + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_emac_enable(struct elink_params *params, + struct elink_vars *vars, uint8_t lb) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + uint32_t val; + + PMD_DRV_LOG(DEBUG, "enabling EMAC"); + + /* Disable BMAC */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + + /* enable emac and not bmac */ + REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1); + +#ifdef ELINK_INCLUDE_EMUL + /* for paladium */ + if (CHIP_REV_IS_EMUL(sc)) { + /* Use lane 1 (of lanes 0-3) */ + REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1); + REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1); + } + /* for fpga */ + else +#endif +#ifdef ELINK_INCLUDE_FPGA + if (CHIP_REV_IS_FPGA(sc)) { + /* Use lane 1 (of lanes 0-3) */ + PMD_DRV_LOG(DEBUG, "elink_emac_enable: Setting FPGA"); + + REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1); + REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0); + } else +#endif + /* ASIC */ + if (vars->phy_flags & PHY_XGXS_FLAG) { + uint32_t ser_lane = ((params->lane_config & + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + + PMD_DRV_LOG(DEBUG, "XGXS"); + /* select the master lanes (out of 0-3) */ + REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane); + /* select XGXS */ + REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1); + + } else { /* SerDes */ + PMD_DRV_LOG(DEBUG, "SerDes"); + /* select SerDes */ + REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0); + } + + elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE, + EMAC_RX_MODE_RESET); + elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, + EMAC_TX_MODE_RESET); + +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + if (CHIP_REV_IS_SLOW(sc)) { + /* config GMII mode */ + val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, + (val | EMAC_MODE_PORT_GMII)); + } else { /* ASIC */ +#endif + /* pause enable/disable */ + elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE, + EMAC_RX_MODE_FLOW_EN); + + elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE, + (EMAC_TX_MODE_EXT_PAUSE_EN | + EMAC_TX_MODE_FLOW_EN)); + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED)) { + if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) + elink_bits_en(sc, emac_base + + EMAC_REG_EMAC_RX_MODE, + EMAC_RX_MODE_FLOW_EN); + + if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) + elink_bits_en(sc, emac_base + + EMAC_REG_EMAC_TX_MODE, + (EMAC_TX_MODE_EXT_PAUSE_EN | + EMAC_TX_MODE_FLOW_EN)); + } else + elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, + EMAC_TX_MODE_FLOW_EN); +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + } +#endif + + /* KEEP_VLAN_TAG, promiscuous */ + val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE); + val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; + + /* Setting this bit causes MAC control frames (except for pause + * frames) to be passed on for processing. This setting has no + * affect on the operation of the pause frames. This bit effects + * all packets regardless of RX Parser packet sorting logic. + * Turn the PFC off to make sure we are in Xon state before + * enabling it. + */ + elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0); + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { + PMD_DRV_LOG(DEBUG, "PFC is enabled"); + /* Enable PFC again */ + elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, + EMAC_REG_RX_PFC_MODE_RX_EN | + EMAC_REG_RX_PFC_MODE_TX_EN | + EMAC_REG_RX_PFC_MODE_PRIORITIES); + + elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM, + ((0x0101 << + EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | + (0x00ff << + EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); + val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; + } + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val); + + /* Set Loopback */ + val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); + if (lb) + val |= 0x810; + else + val &= ~0x810; + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val); + + /* Enable emac */ + REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1); + + /* Enable emac for jumbo packets */ + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE, + (EMAC_RX_MTU_SIZE_JUMBO_ENA | + (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + + ELINK_ETH_OVREHEAD))); + + /* Strip CRC */ + REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1); + + /* Disable the NIG in/out to the bmac */ + REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0); + REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0); + REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0); + + /* Enable the NIG in/out to the emac */ + REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1); + val = 0; + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED) || + (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) + val = 1; + + REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val); + REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1); + +#ifdef ELINK_INCLUDE_EMUL + if (CHIP_REV_IS_EMUL(sc)) { + /* Take the BigMac out of reset */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + + /* Enable access for bmac registers */ + REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1); + } else +#endif + REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0); + + vars->mac_type = ELINK_MAC_TYPE_EMAC; + return ELINK_STATUS_OK; +} + +static void elink_update_pfc_bmac1(struct elink_params *params, + struct elink_vars *vars) +{ + uint32_t wb_data[2]; + struct bnx2x_softc *sc = params->sc; + uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : + NIG_REG_INGRESS_BMAC0_MEM; + + uint32_t val = 0x14; + if ((!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED)) && + (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) + /* Enable BigMAC to react on received Pause packets */ + val |= (1 << 5); + wb_data[0] = val; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); + + /* TX control */ + val = 0xc0; + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED) && + (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) + val |= 0x800000; + wb_data[0] = val; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); +} + +static void elink_update_pfc_bmac2(struct elink_params *params, + struct elink_vars *vars, uint8_t is_lb) +{ + /* Set rx control: Strip CRC and enable BigMAC to relay + * control packets to the system as well + */ + uint32_t wb_data[2]; + struct bnx2x_softc *sc = params->sc; + uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : + NIG_REG_INGRESS_BMAC0_MEM; + uint32_t val = 0x14; + + if ((!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED)) && + (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) + /* Enable BigMAC to react on received Pause packets */ + val |= (1 << 5); + wb_data[0] = val; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); + DELAY(30); + + /* Tx control */ + val = 0xc0; + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED) && + (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) + val |= 0x800000; + wb_data[0] = val; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); + + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { + PMD_DRV_LOG(DEBUG, "PFC is enabled"); + /* Enable PFC RX & TX & STATS and set 8 COS */ + wb_data[0] = 0x0; + wb_data[0] |= (1 << 0); /* RX */ + wb_data[0] |= (1 << 1); /* TX */ + wb_data[0] |= (1 << 2); /* Force initial Xon */ + wb_data[0] |= (1 << 3); /* 8 cos */ + wb_data[0] |= (1 << 5); /* STATS */ + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, + wb_data, 2); + /* Clear the force Xon */ + wb_data[0] &= ~(1 << 2); + } else { + PMD_DRV_LOG(DEBUG, "PFC is disabled"); + /* Disable PFC RX & TX & STATS and set 8 COS */ + wb_data[0] = 0x8; + wb_data[1] = 0; + } + + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); + + /* Set Time (based unit is 512 bit time) between automatic + * re-sending of PP packets amd enable automatic re-send of + * Per-Priroity Packet as long as pp_gen is asserted and + * pp_disable is low. + */ + val = 0x8000; + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) + val |= (1 << 16); /* enable automatic re-send */ + + wb_data[0] = val; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, + wb_data, 2); + + /* mac control */ + val = 0x3; /* Enable RX and TX */ + if (is_lb) { + val |= 0x4; /* Local loopback */ + PMD_DRV_LOG(DEBUG, "enable bmac loopback"); + } + /* When PFC enabled, Pass pause frames towards the NIG. */ + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) + val |= ((1 << 6) | (1 << 5)); + + wb_data[0] = val; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); +} + +/****************************************************************************** +* Description: +* This function is needed because NIG ARB_CREDIT_WEIGHT_X are +* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. +******************************************************************************/ +static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc, + uint8_t cos_entry, + uint32_t priority_mask, + uint8_t port) +{ + uint32_t nig_reg_rx_priority_mask_add = 0; + + switch (cos_entry) { + case 0: + nig_reg_rx_priority_mask_add = (port) ? + NIG_REG_P1_RX_COS0_PRIORITY_MASK : + NIG_REG_P0_RX_COS0_PRIORITY_MASK; + break; + case 1: + nig_reg_rx_priority_mask_add = (port) ? + NIG_REG_P1_RX_COS1_PRIORITY_MASK : + NIG_REG_P0_RX_COS1_PRIORITY_MASK; + break; + case 2: + nig_reg_rx_priority_mask_add = (port) ? + NIG_REG_P1_RX_COS2_PRIORITY_MASK : + NIG_REG_P0_RX_COS2_PRIORITY_MASK; + break; + case 3: + if (port) + return ELINK_STATUS_ERROR; + nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; + break; + case 4: + if (port) + return ELINK_STATUS_ERROR; + nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; + break; + case 5: + if (port) + return ELINK_STATUS_ERROR; + nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; + break; + } + + REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask); + + return ELINK_STATUS_OK; +} + +static void elink_update_mng(struct elink_params *params, uint32_t link_status) +{ + struct bnx2x_softc *sc = params->sc; + + REG_WR(sc, params->shmem_base + + offsetof(struct shmem_region, + port_mb[params->port].link_status), link_status); +} + +static void elink_update_link_attr(struct elink_params *params, + uint32_t link_attr) +{ + struct bnx2x_softc *sc = params->sc; + + if (SHMEM2_HAS(sc, link_attr_sync)) + REG_WR(sc, params->shmem2_base + + offsetof(struct shmem2_region, + link_attr_sync[params->port]), link_attr); +} + +static void elink_update_pfc_nig(struct elink_params *params, + struct elink_nig_brb_pfc_port_params + *nig_params) +{ + uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = + 0; + uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; + uint32_t pkt_priority_to_cos = 0; + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + + int set_pfc = params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED; + PMD_DRV_LOG(DEBUG, "updating pfc nig parameters"); + + /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set + * MAC control frames (that are not pause packets) + * will be forwarded to the XCM. + */ + xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK : + NIG_REG_LLH0_XCM_MASK); + /* NIG params will override non PFC params, since it's possible to + * do transition from PFC to SAFC + */ + if (set_pfc) { + pause_enable = 0; + llfc_out_en = 0; + llfc_enable = 0; + if (CHIP_IS_E3(sc)) + ppp_enable = 0; + else + ppp_enable = 1; + xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : + NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); + xcm_out_en = 0; + hwpfc_enable = 1; + } else { + if (nig_params) { + llfc_out_en = nig_params->llfc_out_en; + llfc_enable = nig_params->llfc_enable; + pause_enable = nig_params->pause_enable; + } else /* Default non PFC mode - PAUSE */ + pause_enable = 1; + + xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : + NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); + xcm_out_en = 1; + } + + if (CHIP_IS_E3(sc)) + REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN : + NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); + REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 : + NIG_REG_LLFC_OUT_EN_0, llfc_out_en); + REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 : + NIG_REG_LLFC_ENABLE_0, llfc_enable); + REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 : + NIG_REG_PAUSE_ENABLE_0, pause_enable); + + REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 : + NIG_REG_PPP_ENABLE_0, ppp_enable); + + REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK : + NIG_REG_LLH0_XCM_MASK, xcm_mask); + + REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : + NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); + + /* Output enable for RX_XCM # IF */ + REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN : + NIG_REG_XCM0_OUT_EN, xcm_out_en); + + /* HW PFC TX enable */ + REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE : + NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); + + if (nig_params) { + uint8_t i = 0; + pkt_priority_to_cos = nig_params->pkt_priority_to_cos; + + for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) + elink_pfc_nig_rx_priority_mask(sc, i, + nig_params-> + rx_cos_priority_mask[i], + port); + + REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : + NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, + nig_params->llfc_high_priority_classes); + + REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : + NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, + nig_params->llfc_low_priority_classes); + } + REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : + NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos); +} + +elink_status_t elink_update_pfc(struct elink_params *params, + struct elink_vars *vars, + struct elink_nig_brb_pfc_port_params + *pfc_params) +{ + /* The PFC and pause are orthogonal to one another, meaning when + * PFC is enabled, the pause are disabled, and when PFC is + * disabled, pause are set according to the pause result. + */ + uint32_t val; + struct bnx2x_softc *sc = params->sc; + elink_status_t elink_status = ELINK_STATUS_OK; + uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); + + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) + vars->link_status |= LINK_STATUS_PFC_ENABLED; + else + vars->link_status &= ~LINK_STATUS_PFC_ENABLED; + + elink_update_mng(params, vars->link_status); + + /* Update NIG params */ + elink_update_pfc_nig(params, pfc_params); + + if (!vars->link_up) + return elink_status; + + PMD_DRV_LOG(DEBUG, "About to update PFC in BMAC"); + + if (CHIP_IS_E3(sc)) { + if (vars->mac_type == ELINK_MAC_TYPE_XMAC) + elink_update_pfc_xmac(params, vars); + } else { + val = REG_RD(sc, MISC_REG_RESET_REG_2); + if ((val & + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) + == 0) { + PMD_DRV_LOG(DEBUG, "About to update PFC in EMAC"); + elink_emac_enable(params, vars, 0); + return elink_status; + } + if (CHIP_IS_E2(sc)) + elink_update_pfc_bmac2(params, vars, bmac_loopback); + else + elink_update_pfc_bmac1(params, vars); + + val = 0; + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED) || + (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) + val = 1; + REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val); + } + return elink_status; +} + +static elink_status_t elink_bmac1_enable(struct elink_params *params, + struct elink_vars *vars, uint8_t is_lb) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : + NIG_REG_INGRESS_BMAC0_MEM; + uint32_t wb_data[2]; + uint32_t val; + + PMD_DRV_LOG(DEBUG, "Enabling BigMAC1"); + + /* XGXS control */ + wb_data[0] = 0x3c; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, + wb_data, 2); + + /* TX MAC SA */ + wb_data[0] = ((params->mac_addr[2] << 24) | + (params->mac_addr[3] << 16) | + (params->mac_addr[4] << 8) | params->mac_addr[5]); + wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]); + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); + + /* MAC control */ + val = 0x3; + if (is_lb) { + val |= 0x4; + PMD_DRV_LOG(DEBUG, "enable bmac loopback"); + } + wb_data[0] = val; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); + + /* Set rx mtu */ + wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); + + elink_update_pfc_bmac1(params, vars); + + /* Set tx mtu */ + wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); + + /* Set cnt max size */ + wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); + + /* Configure SAFC */ + wb_data[0] = 0x1000200; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, + wb_data, 2); +#ifdef ELINK_INCLUDE_EMUL + /* Fix for emulation */ + if (CHIP_REV_IS_EMUL(sc)) { + wb_data[0] = 0xf000; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, + wb_data, 2); + } +#endif + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_bmac2_enable(struct elink_params *params, + struct elink_vars *vars, uint8_t is_lb) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : + NIG_REG_INGRESS_BMAC0_MEM; + uint32_t wb_data[2]; + + PMD_DRV_LOG(DEBUG, "Enabling BigMAC2"); + + wb_data[0] = 0; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); + DELAY(30); + + /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ + wb_data[0] = 0x3c; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, + wb_data, 2); + + DELAY(30); + + /* TX MAC SA */ + wb_data[0] = ((params->mac_addr[2] << 24) | + (params->mac_addr[3] << 16) | + (params->mac_addr[4] << 8) | params->mac_addr[5]); + wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]); + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, + wb_data, 2); + + DELAY(30); + + /* Configure SAFC */ + wb_data[0] = 0x1000200; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, + wb_data, 2); + DELAY(30); + + /* Set RX MTU */ + wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); + DELAY(30); + + /* Set TX MTU */ + wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); + DELAY(30); + /* Set cnt max size */ + wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); + DELAY(30); + elink_update_pfc_bmac2(params, vars, is_lb); + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_bmac_enable(struct elink_params *params, + struct elink_vars *vars, + uint8_t is_lb, uint8_t reset_bmac) +{ + elink_status_t rc = ELINK_STATUS_OK; + uint8_t port = params->port; + struct bnx2x_softc *sc = params->sc; + uint32_t val; + /* Reset and unreset the BigMac */ + if (reset_bmac) { + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + DELAY(1000 * 1); + } + + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + + /* Enable access for bmac registers */ + REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1); + + /* Enable BMAC according to BMAC type */ + if (CHIP_IS_E2(sc)) + rc = elink_bmac2_enable(params, vars, is_lb); + else + rc = elink_bmac1_enable(params, vars, is_lb); + REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1); + REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0); + REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0); + val = 0; + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED) || + (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) + val = 1; + REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val); + REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0); + REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0); + REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0); + REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1); + REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1); + + vars->mac_type = ELINK_MAC_TYPE_BMAC; + return rc; +} + +static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en) +{ + uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : + NIG_REG_INGRESS_BMAC0_MEM; + uint32_t wb_data[2]; + uint32_t nig_bmac_enable = + REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); + + if (CHIP_IS_E2(sc)) + bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; + else + bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; + /* Only if the bmac is out of reset */ + if (REG_RD(sc, MISC_REG_RESET_REG_2) & + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) { + /* Clear Rx Enable bit in BMAC_CONTROL register */ + REG_RD_DMAE(sc, bmac_addr, wb_data, 2); + if (en) + wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE; + else + wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; + REG_WR_DMAE(sc, bmac_addr, wb_data, 2); + DELAY(1000 * 1); + } +} + +static elink_status_t elink_pbf_update(struct elink_params *params, + uint32_t flow_ctrl, uint32_t line_speed) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint32_t init_crd, crd; + uint32_t count = 1000; + + /* Disable port */ + REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1); + + /* Wait for init credit */ + init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4); + crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); + PMD_DRV_LOG(DEBUG, "init_crd 0x%x crd 0x%x", init_crd, crd); + + while ((init_crd != crd) && count) { + DELAY(1000 * 5); + crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); + count--; + } + crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); + if (init_crd != crd) { + PMD_DRV_LOG(DEBUG, "BUG! init_crd 0x%x != crd 0x%x", + init_crd, crd); + return ELINK_STATUS_ERROR; + } + + if (flow_ctrl & ELINK_FLOW_CTRL_RX || + line_speed == ELINK_SPEED_10 || + line_speed == ELINK_SPEED_100 || + line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) { + REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1); + /* Update threshold */ + REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0); + /* Update init credit */ + init_crd = 778; /* (800-18-4) */ + + } else { + uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + + ELINK_ETH_OVREHEAD) / 16; + REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0); + /* Update threshold */ + REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh); + /* Update init credit */ + switch (line_speed) { + case ELINK_SPEED_10000: + init_crd = thresh + 553 - 22; + break; + default: + PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", + line_speed); + return ELINK_STATUS_ERROR; + } + } + REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd); + PMD_DRV_LOG(DEBUG, "PBF updated to speed %d credit %d", + line_speed, init_crd); + + /* Probe the credit changes */ + REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1); + DELAY(1000 * 5); + REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0); + + /* Enable port */ + REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0); + return ELINK_STATUS_OK; +} + +/** + * elink_get_emac_base - retrive emac base address + * + * @bp: driver handle + * @mdc_mdio_access: access type + * @port: port id + * + * This function selects the MDC/MDIO access (through emac0 or + * emac1) depend on the mdc_mdio_access, port, port swapped. Each + * phy has a default access mode, which could also be overridden + * by nvram configuration. This parameter, whether this is the + * default phy configuration, or the nvram overrun + * configuration, is passed here as mdc_mdio_access and selects + * the emac_base for the CL45 read/writes operations + */ +static uint32_t elink_get_emac_base(struct bnx2x_softc *sc, + uint32_t mdc_mdio_access, uint8_t port) +{ + uint32_t emac_base = 0; + switch (mdc_mdio_access) { + case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: + break; + case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: + if (REG_RD(sc, NIG_REG_PORT_SWAP)) + emac_base = GRCBASE_EMAC1; + else + emac_base = GRCBASE_EMAC0; + break; + case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: + if (REG_RD(sc, NIG_REG_PORT_SWAP)) + emac_base = GRCBASE_EMAC0; + else + emac_base = GRCBASE_EMAC1; + break; + case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: + emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + break; + case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: + emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; + break; + default: + break; + } + return emac_base; + +} + +/******************************************************************/ +/* CL22 access functions */ +/******************************************************************/ +static elink_status_t elink_cl22_write(struct bnx2x_softc *sc, + struct elink_phy *phy, + uint16_t reg, uint16_t val) +{ + uint32_t tmp, mode; + uint8_t i; + elink_status_t rc = ELINK_STATUS_OK; + /* Switch to CL22 */ + mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, + mode & ~EMAC_MDIO_MODE_CLAUSE_45); + + /* Address */ + tmp = ((phy->addr << 21) | (reg << 16) | val | + EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); + + for (i = 0; i < 50; i++) { + DELAY(10); + + tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); + if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + break; + } + } + if (tmp & EMAC_MDIO_COMM_START_BUSY) { + PMD_DRV_LOG(DEBUG, "write phy register failed"); + rc = ELINK_STATUS_TIMEOUT; + } + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); + return rc; +} + +static elink_status_t elink_cl22_read(struct bnx2x_softc *sc, + struct elink_phy *phy, + uint16_t reg, uint16_t * ret_val) +{ + uint32_t val, mode; + uint16_t i; + elink_status_t rc = ELINK_STATUS_OK; + + /* Switch to CL22 */ + mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, + mode & ~EMAC_MDIO_MODE_CLAUSE_45); + + /* Address */ + val = ((phy->addr << 21) | (reg << 16) | + EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); + + for (i = 0; i < 50; i++) { + DELAY(10); + + val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); + if (!(val & EMAC_MDIO_COMM_START_BUSY)) { + *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA); + DELAY(5); + break; + } + } + if (val & EMAC_MDIO_COMM_START_BUSY) { + PMD_DRV_LOG(DEBUG, "read phy register failed"); + + *ret_val = 0; + rc = ELINK_STATUS_TIMEOUT; + } + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); + return rc; +} + +/******************************************************************/ +/* CL45 access functions */ +/******************************************************************/ +static elink_status_t elink_cl45_read(struct bnx2x_softc *sc, + struct elink_phy *phy, uint8_t devad, + uint16_t reg, uint16_t * ret_val) +{ + uint32_t val; + uint16_t i; + elink_status_t rc = ELINK_STATUS_OK; + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { + elink_set_mdio_clk(sc, phy->mdio_ctrl); + } + + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) + elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); + /* Address */ + val = ((phy->addr << 21) | (devad << 16) | reg | + EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); + + for (i = 0; i < 50; i++) { + DELAY(10); + + val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); + if (!(val & EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + break; + } + } + if (val & EMAC_MDIO_COMM_START_BUSY) { + PMD_DRV_LOG(DEBUG, "read phy register failed"); + elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + + *ret_val = 0; + rc = ELINK_STATUS_TIMEOUT; + } else { + /* Data */ + val = ((phy->addr << 21) | (devad << 16) | + EMAC_MDIO_COMM_COMMAND_READ_45 | + EMAC_MDIO_COMM_START_BUSY); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); + + for (i = 0; i < 50; i++) { + DELAY(10); + + val = REG_RD(sc, phy->mdio_ctrl + + EMAC_REG_EMAC_MDIO_COMM); + if (!(val & EMAC_MDIO_COMM_START_BUSY)) { + *ret_val = + (uint16_t) (val & EMAC_MDIO_COMM_DATA); + break; + } + } + if (val & EMAC_MDIO_COMM_START_BUSY) { + PMD_DRV_LOG(DEBUG, "read phy register failed"); + elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + + *ret_val = 0; + rc = ELINK_STATUS_TIMEOUT; + } + } + /* Work around for E3 A0 */ + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { + phy->flags ^= ELINK_FLAGS_DUMMY_READ; + if (phy->flags & ELINK_FLAGS_DUMMY_READ) { + uint16_t temp_val; + elink_cl45_read(sc, phy, devad, 0xf, &temp_val); + } + } + + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) + elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); + return rc; +} + +static elink_status_t elink_cl45_write(struct bnx2x_softc *sc, + struct elink_phy *phy, uint8_t devad, + uint16_t reg, uint16_t val) +{ + uint32_t tmp; + uint8_t i; + elink_status_t rc = ELINK_STATUS_OK; + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { + elink_set_mdio_clk(sc, phy->mdio_ctrl); + } + + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) + elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); + + /* Address */ + tmp = ((phy->addr << 21) | (devad << 16) | reg | + EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); + + for (i = 0; i < 50; i++) { + DELAY(10); + + tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); + if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + break; + } + } + if (tmp & EMAC_MDIO_COMM_START_BUSY) { + PMD_DRV_LOG(DEBUG, "write phy register failed"); + elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + + rc = ELINK_STATUS_TIMEOUT; + } else { + /* Data */ + tmp = ((phy->addr << 21) | (devad << 16) | val | + EMAC_MDIO_COMM_COMMAND_WRITE_45 | + EMAC_MDIO_COMM_START_BUSY); + REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); + + for (i = 0; i < 50; i++) { + DELAY(10); + + tmp = REG_RD(sc, phy->mdio_ctrl + + EMAC_REG_EMAC_MDIO_COMM); + if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + break; + } + } + if (tmp & EMAC_MDIO_COMM_START_BUSY) { + PMD_DRV_LOG(DEBUG, "write phy register failed"); + elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + + rc = ELINK_STATUS_TIMEOUT; + } + } + /* Work around for E3 A0 */ + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { + phy->flags ^= ELINK_FLAGS_DUMMY_READ; + if (phy->flags & ELINK_FLAGS_DUMMY_READ) { + uint16_t temp_val; + elink_cl45_read(sc, phy, devad, 0xf, &temp_val); + } + } + if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) + elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, + EMAC_MDIO_STATUS_10MB); + return rc; +} + +/******************************************************************/ +/* EEE section */ +/******************************************************************/ +static uint8_t elink_eee_has_cap(struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + + if (REG_RD(sc, params->shmem2_base) <= + offsetof(struct shmem2_region, eee_status[params->port])) + return 0; + + return 1; +} + +static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, + uint32_t * idle_timer) +{ + switch (nvram_mode) { + case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: + *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME; + break; + case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: + *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME; + break; + case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: + *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME; + break; + default: + *idle_timer = 0; + break; + } + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, + uint32_t * nvram_mode) +{ + switch (idle_timer) { + case ELINK_EEE_MODE_NVRAM_BALANCED_TIME: + *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; + break; + case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME: + *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; + break; + case ELINK_EEE_MODE_NVRAM_LATENCY_TIME: + *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; + break; + default: + *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; + break; + } + + return ELINK_STATUS_OK; +} + +static uint32_t elink_eee_calc_timer(struct elink_params *params) +{ + uint32_t eee_mode, eee_idle; + struct bnx2x_softc *sc = params->sc; + + if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { + if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { + /* time value in eee_mode --> used directly */ + eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; + } else { + /* hsi value in eee_mode --> time */ + if (elink_eee_nvram_to_time(params->eee_mode & + ELINK_EEE_MODE_NVRAM_MASK, + &eee_idle)) + return 0; + } + } else { + /* hsi values in nvram --> time */ + eee_mode = ((REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_feature_config + [params-> + port].eee_power_mode)) & + PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> + PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); + + if (elink_eee_nvram_to_time(eee_mode, &eee_idle)) + return 0; + } + + return eee_idle; +} + +static elink_status_t elink_eee_set_timers(struct elink_params *params, + struct elink_vars *vars) +{ + uint32_t eee_idle = 0, eee_mode; + struct bnx2x_softc *sc = params->sc; + + eee_idle = elink_eee_calc_timer(params); + + if (eee_idle) { + REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), + eee_idle); + } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && + (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && + (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { + PMD_DRV_LOG(DEBUG, "Error: Tx LPI is enabled with timer 0"); + return ELINK_STATUS_ERROR; + } + + vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); + if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { + /* eee_idle in 1u --> eee_status in 16u */ + eee_idle >>= 4; + vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | + SHMEM_EEE_TIME_OUTPUT_BIT; + } else { + if (elink_eee_time_to_nvram(eee_idle, &eee_mode)) + return ELINK_STATUS_ERROR; + vars->eee_status |= eee_mode; + } + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_eee_initial_config(struct elink_params *params, + struct elink_vars *vars, + uint8_t mode) +{ + vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT; + + /* Propogate params' bits --> vars (for migration exposure) */ + if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) + vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; + else + vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; + + if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) + vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; + else + vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; + + return elink_eee_set_timers(params, vars); +} + +static elink_status_t elink_eee_disable(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + + /* Make Certain LPI is disabled */ + REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); + + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); + + vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_eee_advertise(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars, + uint8_t modes) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val = 0; + + /* Mask events preventing LPI generation */ + REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); + + if (modes & SHMEM_EEE_10G_ADV) { + PMD_DRV_LOG(DEBUG, "Advertise 10GBase-T EEE"); + val |= 0x8; + } + if (modes & SHMEM_EEE_1G_ADV) { + PMD_DRV_LOG(DEBUG, "Advertise 1GBase-T EEE"); + val |= 0x4; + } + + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); + + vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; + vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); + + return ELINK_STATUS_OK; +} + +static void elink_update_mng_eee(struct elink_params *params, + uint32_t eee_status) +{ + struct bnx2x_softc *sc = params->sc; + + if (elink_eee_has_cap(params)) + REG_WR(sc, params->shmem2_base + + offsetof(struct shmem2_region, + eee_status[params->port]), eee_status); +} + +static void elink_eee_an_resolve(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t adv = 0, lp = 0; + uint32_t lp_adv = 0; + uint8_t neg = 0; + + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); + + if (lp & 0x2) { + lp_adv |= SHMEM_EEE_100M_ADV; + if (adv & 0x2) { + if (vars->line_speed == ELINK_SPEED_100) + neg = 1; + PMD_DRV_LOG(DEBUG, "EEE negotiated - 100M"); + } + } + if (lp & 0x14) { + lp_adv |= SHMEM_EEE_1G_ADV; + if (adv & 0x14) { + if (vars->line_speed == ELINK_SPEED_1000) + neg = 1; + PMD_DRV_LOG(DEBUG, "EEE negotiated - 1G"); + } + } + if (lp & 0x68) { + lp_adv |= SHMEM_EEE_10G_ADV; + if (adv & 0x68) { + if (vars->line_speed == ELINK_SPEED_10000) + neg = 1; + PMD_DRV_LOG(DEBUG, "EEE negotiated - 10G"); + } + } + + vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; + vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); + + if (neg) { + PMD_DRV_LOG(DEBUG, "EEE is active"); + vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; + } +} + +/******************************************************************/ +/* BSC access functions from E3 */ +/******************************************************************/ +static void elink_bsc_module_sel(struct elink_params *params) +{ + int idx; + uint32_t board_cfg, sfp_ctrl; + uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + /* Read I2C output PINs */ + board_cfg = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.shared_hw_config.board)); + i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; + i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> + SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; + + /* Read I2C output value */ + sfp_ctrl = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + e3_cmn_pin_cfg)); + i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; + i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; + PMD_DRV_LOG(DEBUG, "Setting BSC switch"); + for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) + elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]); +} + +static elink_status_t elink_bsc_read(struct elink_params *params, + struct bnx2x_softc *sc, + uint8_t sl_devid, + uint16_t sl_addr, + uint8_t lc_addr, + uint8_t xfer_cnt, uint32_t * data_array) +{ + uint32_t val, i; + elink_status_t rc = ELINK_STATUS_OK; + + if (xfer_cnt > 16) { + PMD_DRV_LOG(DEBUG, "invalid xfer_cnt %d. Max is 16 bytes", + xfer_cnt); + return ELINK_STATUS_ERROR; + } + if (params) + elink_bsc_module_sel(params); + + xfer_cnt = 16 - lc_addr; + + /* Enable the engine */ + val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); + val |= MCPR_IMC_COMMAND_ENABLE; + REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); + + /* Program slave device ID */ + val = (sl_devid << 16) | sl_addr; + REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); + + /* Start xfer with 0 byte to update the address pointer ??? */ + val = (MCPR_IMC_COMMAND_ENABLE) | + (MCPR_IMC_COMMAND_WRITE_OP << + MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | + (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); + REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); + + /* Poll for completion */ + i = 0; + val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); + while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { + DELAY(10); + val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); + if (i++ > 1000) { + PMD_DRV_LOG(DEBUG, "wr 0 byte timed out after %d try", + i); + rc = ELINK_STATUS_TIMEOUT; + break; + } + } + if (rc == ELINK_STATUS_TIMEOUT) + return rc; + + /* Start xfer with read op */ + val = (MCPR_IMC_COMMAND_ENABLE) | + (MCPR_IMC_COMMAND_READ_OP << + MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | + (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | + (xfer_cnt); + REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); + + /* Poll for completion */ + i = 0; + val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); + while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { + DELAY(10); + val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); + if (i++ > 1000) { + PMD_DRV_LOG(DEBUG, "rd op timed out after %d try", i); + rc = ELINK_STATUS_TIMEOUT; + break; + } + } + if (rc == ELINK_STATUS_TIMEOUT) + return rc; + + for (i = (lc_addr >> 2); i < 4; i++) { + data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4)); +#ifdef __BIG_ENDIAN + data_array[i] = ((data_array[i] & 0x000000ff) << 24) | + ((data_array[i] & 0x0000ff00) << 8) | + ((data_array[i] & 0x00ff0000) >> 8) | + ((data_array[i] & 0xff000000) >> 24); +#endif + } + return rc; +} + +static void elink_cl45_read_or_write(struct bnx2x_softc *sc, + struct elink_phy *phy, uint8_t devad, + uint16_t reg, uint16_t or_val) +{ + uint16_t val; + elink_cl45_read(sc, phy, devad, reg, &val); + elink_cl45_write(sc, phy, devad, reg, val | or_val); +} + +static void elink_cl45_read_and_write(struct bnx2x_softc *sc, + struct elink_phy *phy, + uint8_t devad, uint16_t reg, + uint16_t and_val) +{ + uint16_t val; + elink_cl45_read(sc, phy, devad, reg, &val); + elink_cl45_write(sc, phy, devad, reg, val & and_val); +} + +static uint8_t elink_get_warpcore_lane(struct elink_params *params) +{ + uint8_t lane = 0; + struct bnx2x_softc *sc = params->sc; + uint32_t path_swap, path_swap_ovr; + uint8_t path, port; + + path = SC_PATH(sc); + port = params->port; + + if (elink_is_4_port_mode(sc)) { + uint32_t port_swap, port_swap_ovr; + + /* Figure out path swap value */ + path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); + if (path_swap_ovr & 0x1) + path_swap = (path_swap_ovr & 0x2); + else + path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP); + + if (path_swap) + path = path ^ 1; + + /* Figure out port swap value */ + port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); + if (port_swap_ovr & 0x1) + port_swap = (port_swap_ovr & 0x2); + else + port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP); + + if (port_swap) + port = port ^ 1; + + lane = (port << 1) + path; + } else { /* Two port mode - no port swap */ + + /* Figure out path swap value */ + path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); + if (path_swap_ovr & 0x1) { + path_swap = (path_swap_ovr & 0x2); + } else { + path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP); + } + if (path_swap) + path = path ^ 1; + + lane = path << 1; + } + return lane; +} + +static void elink_set_aer_mmd(struct elink_params *params, + struct elink_phy *phy) +{ + uint32_t ser_lane; + uint16_t offset, aer_val; + struct bnx2x_softc *sc = params->sc; + ser_lane = ((params->lane_config & + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + + offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? + (phy->addr + ser_lane) : 0; + + if (USES_WARPCORE(sc)) { + aer_val = elink_get_warpcore_lane(params); + /* In Dual-lane mode, two lanes are joined together, + * so in order to configure them, the AER broadcast method is + * used here. + * 0x200 is the broadcast address for lanes 0,1 + * 0x201 is the broadcast address for lanes 2,3 + */ + if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) + aer_val = (aer_val >> 1) | 0x200; + } else if (CHIP_IS_E2(sc)) + aer_val = 0x3800 + offset - 1; + else + aer_val = 0x3800 + offset; + + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, aer_val); + +} + +/******************************************************************/ +/* Internal phy section */ +/******************************************************************/ + +static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port) +{ + uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + + /* Set Clause 22 */ + REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1); + REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); + DELAY(500); + REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); + DELAY(500); + /* Set Clause 45 */ + REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0); +} + +static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port) +{ + uint32_t val; + + PMD_DRV_LOG(DEBUG, "elink_serdes_deassert"); + + val = ELINK_SERDES_RESET_BITS << (port * 16); + + /* Reset and unreset the SerDes/XGXS */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); + DELAY(500); + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); + + elink_set_serdes_access(sc, port); + + REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10, + ELINK_DEFAULT_PHY_DEV_ADDR); +} + +static void elink_xgxs_specific_func(struct elink_phy *phy, + struct elink_params *params, + uint32_t action) +{ + struct bnx2x_softc *sc = params->sc; + switch (action) { + case ELINK_PHY_INIT: + /* Set correct devad */ + REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0); + REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18, + phy->def_md_devad); + break; + } +} + +static void elink_xgxs_deassert(struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port; + uint32_t val; + PMD_DRV_LOG(DEBUG, "elink_xgxs_deassert"); + port = params->port; + + val = ELINK_XGXS_RESET_BITS << (port * 16); + + /* Reset and unreset the SerDes/XGXS */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); + DELAY(500); + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); + elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params, + ELINK_PHY_INIT); +} + +static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, + struct elink_params *params, + uint16_t * ieee_fc) +{ + *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; + /* Resolve pause mode and advertisement Please refer to Table + * 28B-3 of the 802.3ab-1999 spec + */ + + switch (phy->req_flow_ctrl) { + case ELINK_FLOW_CTRL_AUTO: + switch (params->req_fc_auto_adv) { + case ELINK_FLOW_CTRL_BOTH: + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + break; + case ELINK_FLOW_CTRL_RX: + case ELINK_FLOW_CTRL_TX: + *ieee_fc |= + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + break; + default: + break; + } + break; + case ELINK_FLOW_CTRL_TX: + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + break; + + case ELINK_FLOW_CTRL_RX: + case ELINK_FLOW_CTRL_BOTH: + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + break; + + case ELINK_FLOW_CTRL_NONE: + default: + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; + break; + } + PMD_DRV_LOG(DEBUG, "ieee_fc = 0x%x", *ieee_fc); +} + +static void set_phy_vars(struct elink_params *params, struct elink_vars *vars) +{ + uint8_t actual_phy_idx, phy_index, link_cfg_idx; + uint8_t phy_config_swapped = params->multi_phy_config & + PORT_HW_CFG_PHY_SWAPPED_ENABLED; + for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; + phy_index++) { + link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index); + actual_phy_idx = phy_index; + if (phy_config_swapped) { + if (phy_index == ELINK_EXT_PHY1) + actual_phy_idx = ELINK_EXT_PHY2; + else if (phy_index == ELINK_EXT_PHY2) + actual_phy_idx = ELINK_EXT_PHY1; + } + params->phy[actual_phy_idx].req_flow_ctrl = + params->req_flow_ctrl[link_cfg_idx]; + + params->phy[actual_phy_idx].req_line_speed = + params->req_line_speed[link_cfg_idx]; + + params->phy[actual_phy_idx].speed_cap_mask = + params->speed_cap_mask[link_cfg_idx]; + + params->phy[actual_phy_idx].req_duplex = + params->req_duplex[link_cfg_idx]; + + if (params->req_line_speed[link_cfg_idx] == + ELINK_SPEED_AUTO_NEG) + vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; + + PMD_DRV_LOG(DEBUG, "req_flow_ctrl %x, req_line_speed %x," + " speed_cap_mask %x", + params->phy[actual_phy_idx].req_flow_ctrl, + params->phy[actual_phy_idx].req_line_speed, + params->phy[actual_phy_idx].speed_cap_mask); + } +} + +static void elink_ext_phy_set_pause(struct elink_params *params, + struct elink_phy *phy, + struct elink_vars *vars) +{ + uint16_t val; + struct bnx2x_softc *sc = params->sc; + /* Read modify write pause advertizing */ + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); + + val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; + + /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ + elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { + val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; + } + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { + val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; + } + PMD_DRV_LOG(DEBUG, "Ext phy AN advertize 0x%x", val); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); +} + +static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result) +{ /* LD LP */ + switch (pause_result) { /* ASYM P ASYM P */ + case 0xb: /* 1 0 1 1 */ + vars->flow_ctrl = ELINK_FLOW_CTRL_TX; + break; + + case 0xe: /* 1 1 1 0 */ + vars->flow_ctrl = ELINK_FLOW_CTRL_RX; + break; + + case 0x5: /* 0 1 0 1 */ + case 0x7: /* 0 1 1 1 */ + case 0xd: /* 1 1 0 1 */ + case 0xf: /* 1 1 1 1 */ + vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; + break; + + default: + break; + } + if (pause_result & (1 << 0)) + vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; + if (pause_result & (1 << 1)) + vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; + +} + +static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + uint16_t ld_pause; /* local */ + uint16_t lp_pause; /* link partner */ + uint16_t pause_result; + struct bnx2x_softc *sc = params->sc; + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) { + elink_cl22_read(sc, phy, 0x4, &ld_pause); + elink_cl22_read(sc, phy, 0x5, &lp_pause); + } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) { + uint8_t lane = elink_get_warpcore_lane(params); + uint16_t gp_status, gp_mask; + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, + &gp_status); + gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | + MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << + lane; + if ((gp_status & gp_mask) == gp_mask) { + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_ADV_PAUSE, &ld_pause); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); + } else { + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LD, &ld_pause); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LP, &lp_pause); + ld_pause = ((ld_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) + << 3); + lp_pause = ((lp_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) + << 3); + } + } else { + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_ADV_PAUSE, &ld_pause); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); + } + pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; + pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; + PMD_DRV_LOG(DEBUG, "Ext PHY pause result 0x%x", pause_result); + elink_pause_resolve(vars, pause_result); + +} + +static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + uint8_t ret = 0; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { + /* Update the advertised flow-controled of LD/LP in AN */ + if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) + elink_ext_phy_update_adv_fc(phy, params, vars); + /* But set the flow-control result as the requested one */ + vars->flow_ctrl = phy->req_flow_ctrl; + } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) + vars->flow_ctrl = params->req_fc_auto_adv; + else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { + ret = 1; + elink_ext_phy_update_adv_fc(phy, params, vars); + } + return ret; +} + +/******************************************************************/ +/* Warpcore section */ +/******************************************************************/ +/* The init_internal_warpcore should mirror the xgxs, + * i.e. reset the lane (if needed), set aer for the + * init configuration, and set/clear SGMII flag. Internal + * phy init is done purely in phy_init stage. + */ +#define WC_TX_DRIVER(post2, idriver, ipre) \ + ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ + (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ + (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) + +#define WC_TX_FIR(post, main, pre) \ + ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ + (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ + (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) + +static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t i; + static struct elink_reg_set reg_set[] = { + /* Step 1 - Program the TX/RX alignment markers */ + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, + /* Step 2 - Configure the NP registers */ + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} + }; + PMD_DRV_LOG(DEBUG, "Enabling 20G-KR2"); + + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6)); + + for (i = 0; i < ARRAY_SIZE(reg_set); i++) + elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, + reg_set[i].val); + + /* Start KR2 work-around timer which handles BNX2X8073 link-parner */ + vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; + elink_update_link_attr(params, vars->link_attr_sync); +} + +static void elink_disable_kr2(struct elink_params *params, + struct elink_vars *vars, struct elink_phy *phy) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t i; + static struct elink_reg_set reg_set[] = { + /* Step 1 - Program the TX/RX alignment markers */ + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, + {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} + }; + PMD_DRV_LOG(DEBUG, "Disabling 20G-KR2"); + + for (i = 0; i < ARRAY_SIZE(reg_set); i++) + elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, + reg_set[i].val); + vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; + elink_update_link_attr(params, vars->link_attr_sync); + + vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; +} + +static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + + PMD_DRV_LOG(DEBUG, "Configure WC for LPI pass through"); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); +} + +static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, + struct elink_params *params) +{ + /* Restart autoneg on the leading lane only */ + struct bnx2x_softc *sc = params->sc; + uint16_t lane = elink_get_warpcore_lane(params); + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, lane); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); + + /* Restore AER */ + elink_set_aer_mmd(params, phy); +} + +static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + uint16_t lane, i, cl72_ctrl, an_adv = 0; + struct bnx2x_softc *sc = params->sc; + static struct elink_reg_set reg_set[] = { + {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, + {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, + {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, + {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, + /* Disable Autoneg: re-enable it after adv is done. */ + {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, + {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, + }; + PMD_DRV_LOG(DEBUG, "Enable Auto Negotiation for KR"); + /* Set to default registers that may be overriden by 10G force */ + for (i = 0; i < ARRAY_SIZE(reg_set); i++) + elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, + reg_set[i].val); + + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); + cl72_ctrl &= 0x08ff; + cl72_ctrl |= 0x3800; + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); + + /* Check adding advertisement for 1G KX */ + if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || + (vars->line_speed == ELINK_SPEED_1000)) { + uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; + an_adv |= (1 << 5); + + /* Enable CL37 1G Parallel Detect */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1); + PMD_DRV_LOG(DEBUG, "Advertize 1G"); + } + if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || + (vars->line_speed == ELINK_SPEED_10000)) { + /* Check adding advertisement for 10G KR */ + an_adv |= (1 << 7); + /* Enable 10G Parallel Detect */ + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, 0); + + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_WC_REG_PAR_DET_10G_CTRL, 1); + elink_set_aer_mmd(params, phy); + PMD_DRV_LOG(DEBUG, "Advertize 10G"); + } + + /* Set Transmit PMD settings */ + lane = elink_get_warpcore_lane(params); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, + WC_TX_DRIVER(0x02, 0x06, 0x09)); + /* Configure the next lane if dual mode */ + if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1), + WC_TX_DRIVER(0x02, 0x06, 0x09)); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0); + + /* Advertised speeds */ + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); + + /* Advertised and set FEC (Forward Error Correction) */ + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, + (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | + MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); + + /* Enable CL37 BAM */ + if (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + default_cfg)) & + PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, + 1); + PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR"); + } + + /* Advertise pause */ + elink_ext_phy_set_pause(params, phy, vars); + vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL5_MISC7, 0x100); + + /* Over 1G - AN local device user page 1 */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL3_UP1, 0x1f); + + if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || + (phy->req_line_speed == ELINK_SPEED_20000)) { + + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, lane); + + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX1_PCI_CTRL + + (0x10 * lane), (1 << 11)); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); + elink_set_aer_mmd(params, phy); + + elink_warpcore_enable_AN_KR2(phy, params, vars); + } else { + elink_disable_kr2(params, vars, phy); + } + + /* Enable Autoneg: only on the main lane */ + elink_warpcore_restart_AN_KR(phy, params); +} + +static void elink_warpcore_set_10G_KR(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val16, i, lane; + static struct elink_reg_set reg_set[] = { + /* Disable Autoneg */ + {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, + {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, + 0x3f00}, + {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, + {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, + {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, + {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, + /* Leave cl72 training enable, needed for KR */ + {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} + }; + + for (i = 0; i < ARRAY_SIZE(reg_set); i++) + elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, + reg_set[i].val); + + lane = elink_get_warpcore_lane(params); + /* Global registers */ + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, 0); + /* Disable CL36 PCS Tx */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); + val16 &= ~(0x0011 << lane); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); + + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); + val16 |= (0x0303 << (lane << 1)); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); + /* Restore AER */ + elink_set_aer_mmd(params, phy); + /* Set speed via PMA/PMD register */ + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); + + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, + MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); + + /* Enable encoded forced speed */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); + + /* Turn TX scramble payload only the 64/66 scrambler */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9); + + /* Turn RX scramble payload only the 64/66 scrambler */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_CONTROL, 0xF9); + + /* Set and clear loopback to cause a reset to 64/66 decoder */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); + +} + +static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, + struct elink_params *params, + uint8_t is_xfi) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t misc1_val, tap_val, tx_driver_val, lane, val; + uint32_t cfg_tap_val, tx_drv_brdct, tx_equal; + + /* Hold rxSeqStart */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); + + /* Hold tx_fifo_reset */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); + + /* Disable CL73 AN */ + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); + + /* Disable 100FX Enable and Auto-Detect */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_FX100_CTRL1, 0xFFFA); + + /* Disable 100FX Idle detect */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_FX100_CTRL3, 0x0080); + + /* Set Block address to Remote PHY & Clear forced_speed[5] */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); + + /* Turn off auto-detect & fiber mode */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, + 0xFFEE); + + /* Set filter_force_link, disable_false_link and parallel_detect */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, + ((val | 0x0006) & 0xFFFE)); + + /* Set XFI / SFI */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); + + misc1_val &= ~(0x1f); + + if (is_xfi) { + misc1_val |= 0x5; + tap_val = WC_TX_FIR(0x08, 0x37, 0x00); + tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); + } else { + cfg_tap_val = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params-> + port].sfi_tap_values)); + + tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; + + tx_drv_brdct = (cfg_tap_val & + PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> + PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; + + misc1_val |= 0x9; + + /* TAP values are controlled by nvram, if value there isn't 0 */ + if (tx_equal) + tap_val = (uint16_t) tx_equal; + else + tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); + + if (tx_drv_brdct) + tx_driver_val = + WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06); + else + tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); + } + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); + + /* Set Transmit PMD settings */ + lane = elink_get_warpcore_lane(params); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX_FIR_TAP, + tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, + tx_driver_val); + + /* Enable fiber mode, enable and invert sig_det */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); + + /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); + + elink_warpcore_set_lpi_passthrough(phy, params); + + /* 10G XFI Full Duplex */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); + + /* Release tx_fifo_reset */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, + 0xFFFE); + /* Release rxSeqStart */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); +} + +static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, + struct elink_params *params) +{ + uint16_t val; + struct bnx2x_softc *sc = params->sc; + /* Set global registers, so set AER lane to 0 */ + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, 0); + + /* Disable sequencer */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13)); + + elink_set_aer_mmd(params, phy); + + elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD, + MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1)); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); + /* Turn off CL73 */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL73_USERB0_CTRL, &val); + val &= ~(1 << 5); + val |= (1 << 6); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL73_USERB0_CTRL, val); + + /* Set 20G KR2 force speed */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); + + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7)); + + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); + val &= ~(3 << 14); + val |= (1 << 15); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); + + /* Enable sequencer (over lane 0) */ + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, 0); + + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13)); + + elink_set_aer_mmd(params, phy); +} + +static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc, + struct elink_phy *phy, uint16_t lane) +{ + /* Rx0 anaRxControl1G */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); + + /* Rx2 anaRxControl1G */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); + + /* Serdes Digital Misc1 */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); + + /* Serdes Digital4 Misc3 */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); + + /* Set Transmit PMD settings */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX_FIR_TAP, + (WC_TX_FIR(0x12, 0x2d, 0x00) | + MDIO_WC_REG_TX_FIR_TAP_ENABLE)); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, + WC_TX_DRIVER(0x02, 0x02, 0x02)); +} + +static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, + struct elink_params *params, + uint8_t fiber_mode, + uint8_t always_autoneg) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val16, digctrl_kx1, digctrl_kx2; + + /* Clear XFI clock comp in non-10G single lane mode. */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_CONTROL, ~(3 << 13)); + + elink_warpcore_set_lpi_passthrough(phy, params); + + if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { + /* SGMII Autoneg */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_COMBO_IEEE0_MIICTRL, + 0x1000); + PMD_DRV_LOG(DEBUG, "set SGMII AUTONEG"); + } else { + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); + val16 &= 0xcebf; + switch (phy->req_line_speed) { + case ELINK_SPEED_10: + break; + case ELINK_SPEED_100: + val16 |= 0x2000; + break; + case ELINK_SPEED_1000: + val16 |= 0x0040; + break; + default: + PMD_DRV_LOG(DEBUG, + "Speed not supported: 0x%x", + phy->req_line_speed); + return; + } + + if (phy->req_duplex == DUPLEX_FULL) + val16 |= 0x0100; + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); + + PMD_DRV_LOG(DEBUG, "set SGMII force speed %d", + phy->req_line_speed); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); + PMD_DRV_LOG(DEBUG, " (readback) %x", val16); + } + + /* SGMII Slave mode and disable signal detect */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); + if (fiber_mode) + digctrl_kx1 = 1; + else + digctrl_kx1 &= 0xff4a; + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1); + + /* Turn off parallel detect */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, + (digctrl_kx2 & ~(1 << 2))); + + /* Re-enable parallel detect */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, + (digctrl_kx2 | (1 << 2))); + + /* Enable autodet */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, + (digctrl_kx1 | 0x10)); +} + +static void elink_warpcore_reset_lane(struct bnx2x_softc *sc, + struct elink_phy *phy, uint8_t reset) +{ + uint16_t val; + /* Take lane out of reset after configuration is finished */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL5_MISC6, &val); + if (reset) + val |= 0xC000; + else + val &= 0x3FFF; + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL5_MISC6, val); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL5_MISC6, &val); +} + +/* Clear SFI/XFI link settings registers */ +static void elink_warpcore_clear_regs(struct elink_phy *phy, + struct elink_params *params, + uint16_t lane) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t i; + static struct elink_reg_set wc_regs[] = { + {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, + {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, + {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, + {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, + {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, + 0x0195}, + {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, + 0x0007}, + {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, + 0x0002}, + {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, + {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, + {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, + {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} + }; + /* Set XFI clock comp as default. */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_CONTROL, (3 << 13)); + + for (i = 0; i < ARRAY_SIZE(wc_regs); i++) + elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg, + wc_regs[i].val); + + lane = elink_get_warpcore_lane(params); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990); + +} + +static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc, + uint32_t shmem_base, + uint8_t port, + uint8_t * gpio_num, + uint8_t * gpio_port) +{ + uint32_t cfg_pin; + *gpio_num = 0; + *gpio_port = 0; + if (CHIP_IS_E3(sc)) { + cfg_pin = (REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + e3_sfp_ctrl)) & + PORT_HW_CFG_E3_MOD_ABS_MASK) >> + PORT_HW_CFG_E3_MOD_ABS_SHIFT; + + /* Should not happen. This function called upon interrupt + * triggered by GPIO ( since EPIO can only generate interrupts + * to MCP). + * So if this function was called and none of the GPIOs was set, + * it means the shit hit the fan. + */ + if ((cfg_pin < PIN_CFG_GPIO0_P0) || + (cfg_pin > PIN_CFG_GPIO3_P1)) { + PMD_DRV_LOG(DEBUG, + "No cfg pin %x for module detect indication", + cfg_pin); + return ELINK_STATUS_ERROR; + } + + *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; + *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; + } else { + *gpio_num = MISC_REGISTERS_GPIO_3; + *gpio_port = port; + } + + return ELINK_STATUS_OK; +} + +static int elink_is_sfp_module_plugged(struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t gpio_num, gpio_port; + uint32_t gpio_val; + if (elink_get_mod_abs_int_cfg(sc, + params->shmem_base, params->port, + &gpio_num, &gpio_port) != ELINK_STATUS_OK) + return 0; + gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port); + + /* Call the handling function in case module is detected */ + if (gpio_val == 0) + return 1; + else + return 0; +} + +static int elink_warpcore_get_sigdet(struct elink_phy *phy, + struct elink_params *params) +{ + uint16_t gp2_status_reg0, lane; + struct bnx2x_softc *sc = params->sc; + + lane = elink_get_warpcore_lane(params); + + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, + &gp2_status_reg0); + + return (gp2_status_reg0 >> (8 + lane)) & 0x1; +} + +static void elink_warpcore_config_runtime(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t serdes_net_if; + uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0; + + vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; + + if (!vars->turn_to_run_wc_rt) + return; + + if (vars->rx_tx_asic_rst) { + uint16_t lane = elink_get_warpcore_lane(params); + serdes_net_if = (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config + [params->port]. + default_cfg)) & + PORT_HW_CFG_NET_SERDES_IF_MASK); + + switch (serdes_net_if) { + case PORT_HW_CFG_NET_SERDES_IF_KR: + /* Do we get link yet? */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1, + &gp_status1); + lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */ + /*10G KR */ + lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1; + + if (lnkup_kr || lnkup) { + vars->rx_tx_asic_rst = 0; + } else { + /* Reset the lane to see if link comes up. */ + elink_warpcore_reset_lane(sc, phy, 1); + elink_warpcore_reset_lane(sc, phy, 0); + + /* Restart Autoneg */ + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, + 0x1200); + + vars->rx_tx_asic_rst--; + PMD_DRV_LOG(DEBUG, "0x%x retry left", + vars->rx_tx_asic_rst); + } + break; + + default: + break; + } + + } + /*params->rx_tx_asic_rst */ +} + +static void elink_warpcore_config_sfi(struct elink_phy *phy, + struct elink_params *params) +{ + uint16_t lane = elink_get_warpcore_lane(params); + + elink_warpcore_clear_regs(phy, params, lane); + if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == + ELINK_SPEED_10000) && + (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { + PMD_DRV_LOG(DEBUG, "Setting 10G SFI"); + elink_warpcore_set_10G_XFI(phy, params, 0); + } else { + PMD_DRV_LOG(DEBUG, "Setting 1G Fiber"); + elink_warpcore_set_sgmii_speed(phy, params, 1, 0); + } +} + +static void elink_sfp_e3_set_transmitter(struct elink_params *params, + struct elink_phy *phy, uint8_t tx_en) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t cfg_pin; + uint8_t port = params->port; + + cfg_pin = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port].e3_sfp_ctrl)) & + PORT_HW_CFG_E3_TX_LASER_MASK; + /* Set the !tx_en since this pin is DISABLE_TX_LASER */ + PMD_DRV_LOG(DEBUG, "Setting WC TX to %d", tx_en); + + /* For 20G, the expected pin to be used is 3 pins after the current */ + elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1); + if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) + elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1); +} + +static void elink_warpcore_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t serdes_net_if; + uint8_t fiber_mode; + uint16_t lane = elink_get_warpcore_lane(params); + serdes_net_if = (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + default_cfg)) & + PORT_HW_CFG_NET_SERDES_IF_MASK); + PMD_DRV_LOG(DEBUG, + "Begin Warpcore init, link_speed %d, " + "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if); + elink_set_aer_mmd(params, phy); + elink_warpcore_reset_lane(sc, phy, 1); + vars->phy_flags |= PHY_XGXS_FLAG; + if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || + (phy->req_line_speed && + ((phy->req_line_speed == ELINK_SPEED_100) || + (phy->req_line_speed == ELINK_SPEED_10)))) { + vars->phy_flags |= PHY_SGMII_FLAG; + PMD_DRV_LOG(DEBUG, "Setting SGMII mode"); + elink_warpcore_clear_regs(phy, params, lane); + elink_warpcore_set_sgmii_speed(phy, params, 0, 1); + } else { + switch (serdes_net_if) { + case PORT_HW_CFG_NET_SERDES_IF_KR: + /* Enable KR Auto Neg */ + if (params->loopback_mode != ELINK_LOOPBACK_EXT) + elink_warpcore_enable_AN_KR(phy, params, vars); + else { + PMD_DRV_LOG(DEBUG, "Setting KR 10G-Force"); + elink_warpcore_set_10G_KR(phy, params); + } + break; + + case PORT_HW_CFG_NET_SERDES_IF_XFI: + elink_warpcore_clear_regs(phy, params, lane); + if (vars->line_speed == ELINK_SPEED_10000) { + PMD_DRV_LOG(DEBUG, "Setting 10G XFI"); + elink_warpcore_set_10G_XFI(phy, params, 1); + } else { + if (ELINK_SINGLE_MEDIA_DIRECT(params)) { + PMD_DRV_LOG(DEBUG, "1G Fiber"); + fiber_mode = 1; + } else { + PMD_DRV_LOG(DEBUG, "10/100/1G SGMII"); + fiber_mode = 0; + } + elink_warpcore_set_sgmii_speed(phy, + params, + fiber_mode, 0); + } + + break; + + case PORT_HW_CFG_NET_SERDES_IF_SFI: + /* Issue Module detection if module is plugged, or + * enabled transmitter to avoid current leakage in case + * no module is connected + */ + if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || + (params->loopback_mode == ELINK_LOOPBACK_EXT)) { + if (elink_is_sfp_module_plugged(params)) + elink_sfp_module_detection(phy, params); + else + elink_sfp_e3_set_transmitter(params, + phy, 1); + } + + elink_warpcore_config_sfi(phy, params); + break; + + case PORT_HW_CFG_NET_SERDES_IF_DXGXS: + if (vars->line_speed != ELINK_SPEED_20000) { + PMD_DRV_LOG(DEBUG, "Speed not supported yet"); + return; + } + PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS"); + elink_warpcore_set_20G_DXGXS(sc, phy, lane); + /* Issue Module detection */ + + elink_sfp_module_detection(phy, params); + break; + case PORT_HW_CFG_NET_SERDES_IF_KR2: + if (!params->loopback_mode) { + elink_warpcore_enable_AN_KR(phy, params, vars); + } else { + PMD_DRV_LOG(DEBUG, "Setting KR 20G-Force"); + elink_warpcore_set_20G_force_KR2(phy, params); + } + break; + default: + PMD_DRV_LOG(DEBUG, + "Unsupported Serdes Net Interface 0x%x", + serdes_net_if); + return; + } + } + + /* Take lane out of reset after configuration is finished */ + elink_warpcore_reset_lane(sc, phy, 0); + PMD_DRV_LOG(DEBUG, "Exit config init"); +} + +static void elink_warpcore_link_reset(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val16, lane; + elink_sfp_e3_set_transmitter(params, phy, 0); + elink_set_mdio_emac_per_phy(sc, params); + elink_set_aer_mmd(params, phy); + /* Global register */ + elink_warpcore_reset_lane(sc, phy, 1); + + /* Clear loopback settings (if any) */ + /* 10G & 20G */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); + + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); + + /* Update those 1-copy registers */ + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, 0); + /* Enable 1G MDIO (1-copy) */ + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10); + + elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); + lane = elink_get_warpcore_lane(params); + /* Disable CL36 PCS Tx */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); + val16 |= (0x11 << lane); + if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) + val16 |= (0x22 << lane); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); + + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); + val16 &= ~(0x0303 << (lane << 1)); + val16 |= (0x0101 << (lane << 1)); + if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) { + val16 &= ~(0x0c0c << (lane << 1)); + val16 |= (0x0404 << (lane << 1)); + } + + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); + /* Restore AER */ + elink_set_aer_mmd(params, phy); + +} + +static void elink_set_warpcore_loopback(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val16; + uint32_t lane; + PMD_DRV_LOG(DEBUG, "Setting Warpcore loopback type %x, speed %d", + params->loopback_mode, phy->req_line_speed); + + if (phy->req_line_speed < ELINK_SPEED_10000 || + phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { + /* 10/100/1000/20G-KR2 */ + + /* Update those 1-copy registers */ + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, 0); + /* Enable 1G MDIO (1-copy) */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, + 0x10); + /* Set 1G loopback based on lane (1-copy) */ + lane = elink_get_warpcore_lane(params); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); + val16 |= (1 << lane); + if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) + val16 |= (2 << lane); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16); + + /* Switch back to 4-copy registers */ + elink_set_aer_mmd(params, phy); + } else { + /* 10G / 20G-DXGXS */ + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_COMBO_IEEE0_MIICTRL, + 0x4000); + elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); + } +} + +static void elink_sync_link(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t link_10g_plus; + if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) + vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; + vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); + if (vars->link_up) { + PMD_DRV_LOG(DEBUG, "phy link up"); + + vars->phy_link_up = 1; + vars->duplex = DUPLEX_FULL; + switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) { + case ELINK_LINK_10THD: + vars->duplex = DUPLEX_HALF; + /* Fall thru */ + case ELINK_LINK_10TFD: + vars->line_speed = ELINK_SPEED_10; + break; + + case ELINK_LINK_100TXHD: + vars->duplex = DUPLEX_HALF; + /* Fall thru */ + case ELINK_LINK_100T4: + case ELINK_LINK_100TXFD: + vars->line_speed = ELINK_SPEED_100; + break; + + case ELINK_LINK_1000THD: + vars->duplex = DUPLEX_HALF; + /* Fall thru */ + case ELINK_LINK_1000TFD: + vars->line_speed = ELINK_SPEED_1000; + break; + + case ELINK_LINK_2500THD: + vars->duplex = DUPLEX_HALF; + /* Fall thru */ + case ELINK_LINK_2500TFD: + vars->line_speed = ELINK_SPEED_2500; + break; + + case ELINK_LINK_10GTFD: + vars->line_speed = ELINK_SPEED_10000; + break; + case ELINK_LINK_20GTFD: + vars->line_speed = ELINK_SPEED_20000; + break; + default: + break; + } + vars->flow_ctrl = 0; + if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) + vars->flow_ctrl |= ELINK_FLOW_CTRL_TX; + + if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) + vars->flow_ctrl |= ELINK_FLOW_CTRL_RX; + + if (!vars->flow_ctrl) + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + + if (vars->line_speed && + ((vars->line_speed == ELINK_SPEED_10) || + (vars->line_speed == ELINK_SPEED_100))) { + vars->phy_flags |= PHY_SGMII_FLAG; + } else { + vars->phy_flags &= ~PHY_SGMII_FLAG; + } + if (vars->line_speed && + USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000)) + vars->phy_flags |= PHY_SGMII_FLAG; + /* Anything 10 and over uses the bmac */ + link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); + + if (link_10g_plus) { + if (USES_WARPCORE(sc)) + vars->mac_type = ELINK_MAC_TYPE_XMAC; + else + vars->mac_type = ELINK_MAC_TYPE_BMAC; + } else { + if (USES_WARPCORE(sc)) + vars->mac_type = ELINK_MAC_TYPE_UMAC; + else + vars->mac_type = ELINK_MAC_TYPE_EMAC; + } + } else { /* Link down */ + PMD_DRV_LOG(DEBUG, "phy link down"); + + vars->phy_link_up = 0; + + vars->line_speed = 0; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + + /* Indicate no mac active */ + vars->mac_type = ELINK_MAC_TYPE_NONE; + if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) + vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; + if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) + vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; + } +} + +void elink_link_status_update(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint32_t sync_offset, media_types; + /* Update PHY configuration */ + set_phy_vars(params, vars); + + vars->link_status = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + port_mb[port].link_status)); + + /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ + if (params->loopback_mode != ELINK_LOOPBACK_NONE && + params->loopback_mode != ELINK_LOOPBACK_EXT) + vars->link_status |= LINK_STATUS_LINK_UP; + + if (elink_eee_has_cap(params)) + vars->eee_status = REG_RD(sc, params->shmem2_base + + offsetof(struct shmem2_region, + eee_status[params->port])); + + vars->phy_flags = PHY_XGXS_FLAG; + elink_sync_link(params, vars); + /* Sync media type */ + sync_offset = params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port].media_type); + media_types = REG_RD(sc, sync_offset); + + params->phy[ELINK_INT_PHY].media_type = + (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> + PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; + params->phy[ELINK_EXT_PHY1].media_type = + (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> + PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; + params->phy[ELINK_EXT_PHY2].media_type = + (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> + PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; + PMD_DRV_LOG(DEBUG, "media_types = 0x%x", media_types); + + /* Sync AEU offset */ + sync_offset = params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port].aeu_int_mask); + + vars->aeu_int_mask = REG_RD(sc, sync_offset); + + /* Sync PFC status */ + if (vars->link_status & LINK_STATUS_PFC_ENABLED) + params->feature_config_flags |= + ELINK_FEATURE_CONFIG_PFC_ENABLED; + else + params->feature_config_flags &= + ~ELINK_FEATURE_CONFIG_PFC_ENABLED; + + if (SHMEM2_HAS(sc, link_attr_sync)) + vars->link_attr_sync = SHMEM2_RD(sc, + link_attr_sync[params->port]); + + PMD_DRV_LOG(DEBUG, "link_status 0x%x phy_link_up %x int_mask 0x%x", + vars->link_status, vars->phy_link_up, vars->aeu_int_mask); + PMD_DRV_LOG(DEBUG, "line_speed %x duplex %x flow_ctrl 0x%x", + vars->line_speed, vars->duplex, vars->flow_ctrl); +} + +static void elink_set_master_ln(struct elink_params *params, + struct elink_phy *phy) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t new_master_ln, ser_lane; + ser_lane = ((params->lane_config & + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + + /* Set the master_ln for AN */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_XGXS_BLOCK2, + MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln); + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_XGXS_BLOCK2, + MDIO_XGXS_BLOCK2_TEST_MODE_LANE, + (new_master_ln | ser_lane)); +} + +static elink_status_t elink_reset_unicore(struct elink_params *params, + struct elink_phy *phy, + uint8_t set_serdes) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t mii_control; + uint16_t i; + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); + + /* Reset the unicore */ + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, + (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); + if (set_serdes) + elink_set_serdes_access(sc, params->port); + + /* Wait for the reset to self clear */ + for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) { + DELAY(5); + + /* The reset erased the previous bank value */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); + + if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { + DELAY(5); + return ELINK_STATUS_OK; + } + } + + elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," + // " Port %d", + + PMD_DRV_LOG(DEBUG, "BUG! XGXS is still in reset!"); + return ELINK_STATUS_ERROR; + +} + +static void elink_set_swap_lanes(struct elink_params *params, + struct elink_phy *phy) +{ + struct bnx2x_softc *sc = params->sc; + /* Each two bits represents a lane number: + * No swap is 0123 => 0x1b no need to enable the swap + */ + uint16_t rx_lane_swap, tx_lane_swap; + + rx_lane_swap = ((params->lane_config & + PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); + tx_lane_swap = ((params->lane_config & + PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); + + if (rx_lane_swap != 0x1b) { + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_XGXS_BLOCK2, + MDIO_XGXS_BLOCK2_RX_LN_SWAP, + (rx_lane_swap | + MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | + MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); + } else { + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_XGXS_BLOCK2, + MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); + } + + if (tx_lane_swap != 0x1b) { + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_XGXS_BLOCK2, + MDIO_XGXS_BLOCK2_TX_LN_SWAP, + (tx_lane_swap | + MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); + } else { + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_XGXS_BLOCK2, + MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); + } +} + +static void elink_set_parallel_detection(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t control2; + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2); + if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) + control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; + else + control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; + PMD_DRV_LOG(DEBUG, "phy->speed_cap_mask = 0x%x, control2 = 0x%x", + phy->speed_cap_mask, control2); + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2); + + if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && + (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { + PMD_DRV_LOG(DEBUG, "XGXS"); + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_10G_PARALLEL_DETECT, + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); + + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_10G_PARALLEL_DETECT, + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, + &control2); + + control2 |= + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_10G_PARALLEL_DETECT, + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, + control2); + + /* Disable parallel detection of HiG */ + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_XGXS_BLOCK2, + MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, + MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | + MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); + } +} + +static void elink_set_autoneg(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars, uint8_t enable_cl73) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t reg_val; + + /* CL37 Autoneg */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); + + /* CL37 Autoneg Enabled */ + if (vars->line_speed == ELINK_SPEED_AUTO_NEG) + reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; + else /* CL37 Autoneg Disabled */ + reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | + MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); + + /* Enable/Disable Autodetection */ + + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); + reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); + reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; + if (vars->line_speed == ELINK_SPEED_AUTO_NEG) + reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; + else + reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); + + /* Enable TetonII and BAM autoneg */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_BAM_NEXT_PAGE, + MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val); + if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { + /* Enable BAM aneg Mode and TetonII aneg Mode */ + reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | + MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); + } else { + /* TetonII and BAM Autoneg Disabled */ + reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | + MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); + } + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_BAM_NEXT_PAGE, + MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val); + + if (enable_cl73) { + /* Enable Cl73 FSM status bits */ + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_USERB0, + MDIO_CL73_USERB0_CL73_UCTRL, 0xe); + + /* Enable BAM Station Manager */ + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_USERB0, + MDIO_CL73_USERB0_CL73_BAM_CTRL1, + MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | + MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN + | + MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); + + /* Advertise CL73 link speeds */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB1, + MDIO_CL73_IEEEB1_AN_ADV2, ®_val); + if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) + reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; + if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) + reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB1, + MDIO_CL73_IEEEB1_AN_ADV2, reg_val); + + /* CL73 Autoneg Enabled */ + reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; + + } else /* CL73 Autoneg Disabled */ + reg_val = 0; + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB0, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); +} + +/* Program SerDes, forced speed */ +static void elink_program_serdes(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t reg_val; + + /* Program duplex, disable autoneg and sgmii */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); + reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | + MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | + MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); + if (phy->req_duplex == DUPLEX_FULL) + reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); + + /* Program speed + * - needed only if the speed is greater than 1G (2.5G or 10G) + */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_MISC1, ®_val); + /* Clearing the speed value before setting the right speed */ + PMD_DRV_LOG(DEBUG, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val); + + reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | + MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); + + if (!((vars->line_speed == ELINK_SPEED_1000) || + (vars->line_speed == ELINK_SPEED_100) || + (vars->line_speed == ELINK_SPEED_10))) { + + reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | + MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); + if (vars->line_speed == ELINK_SPEED_10000) + reg_val |= + MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; + } + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_MISC1, reg_val); + +} + +static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val = 0; + + /* Set extended capabilities */ + if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) + val |= MDIO_OVER_1G_UP1_2_5G; + if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) + val |= MDIO_OVER_1G_UP1_10G; + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val); + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400); +} + +static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy, + struct elink_params *params, + uint16_t ieee_fc) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val; + /* For AN, we are always publishing full duplex */ + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB1, + MDIO_CL73_IEEEB1_AN_ADV1, &val); + val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; + val |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB1, + MDIO_CL73_IEEEB1_AN_ADV1, val); +} + +static void elink_restart_autoneg(struct elink_phy *phy, + struct elink_params *params, + uint8_t enable_cl73) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t mii_control; + + PMD_DRV_LOG(DEBUG, "elink_restart_autoneg"); + /* Enable and restart BAM/CL37 aneg */ + + if (enable_cl73) { + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB0, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, + &mii_control); + + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB0, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, + (mii_control | + MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | + MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); + } else { + + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); + PMD_DRV_LOG(DEBUG, + "elink_restart_autoneg mii_control before = 0x%x", + mii_control); + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, + (mii_control | + MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | + MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); + } +} + +static void elink_initialize_sgmii_process(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t control1; + + /* In SGMII mode, the unicore is always slave */ + + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1); + control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; + /* Set sgmii mode (and not fiber) */ + control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1); + + /* If forced speed */ + if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { + /* Set speed, disable autoneg */ + uint16_t mii_control; + + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); + mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | + MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK | + MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); + + switch (vars->line_speed) { + case ELINK_SPEED_100: + mii_control |= + MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; + break; + case ELINK_SPEED_1000: + mii_control |= + MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; + break; + case ELINK_SPEED_10: + /* There is nothing to set for 10M */ + break; + default: + /* Invalid speed for SGMII */ + PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", + vars->line_speed); + break; + } + + /* Setting the full duplex */ + if (phy->req_duplex == DUPLEX_FULL) + mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_MII_CONTROL, mii_control); + + } else { /* AN mode */ + /* Enable and restart AN */ + elink_restart_autoneg(phy, params, 0); + } +} + +/* Link management + */ +static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, + struct elink_params + *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t pd_10g, status2_1000x; + if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) + return ELINK_STATUS_OK; + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x); + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_SERDES_DIGITAL, + MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x); + if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { + PMD_DRV_LOG(DEBUG, "1G parallel detect link on port %d", + params->port); + return 1; + } + + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_10G_PARALLEL_DETECT, + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g); + + if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { + PMD_DRV_LOG(DEBUG, "10G parallel detect link on port %d", + params->port); + return 1; + } + return ELINK_STATUS_OK; +} + +static void elink_update_adv_fc(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars, uint32_t gp_status) +{ + uint16_t ld_pause; /* local driver */ + uint16_t lp_pause; /* link partner */ + uint16_t pause_result; + struct bnx2x_softc *sc = params->sc; + if ((gp_status & + (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | + MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == + (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | + MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { + + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB1, + MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause); + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB1, + MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause); + pause_result = (ld_pause & + MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; + pause_result |= (lp_pause & + MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; + PMD_DRV_LOG(DEBUG, "pause_result CL73 0x%x", pause_result); + } else { + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause); + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, + &lp_pause); + pause_result = (ld_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5; + pause_result |= (lp_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7; + PMD_DRV_LOG(DEBUG, "pause_result CL37 0x%x", pause_result); + } + elink_pause_resolve(vars, pause_result); + +} + +static void elink_flow_ctrl_resolve(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars, uint32_t gp_status) +{ + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + + /* Resolve from gp_status in case of AN complete and not sgmii */ + if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { + /* Update the advertised flow-controled of LD/LP in AN */ + if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) + elink_update_adv_fc(phy, params, vars, gp_status); + /* But set the flow-control result as the requested one */ + vars->flow_ctrl = phy->req_flow_ctrl; + } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) + vars->flow_ctrl = params->req_fc_auto_adv; + else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) && + (!(vars->phy_flags & PHY_SGMII_FLAG))) { + if (elink_direct_parallel_detect_used(phy, params)) { + vars->flow_ctrl = params->req_fc_auto_adv; + return; + } + elink_update_adv_fc(phy, params, vars, gp_status); + } + PMD_DRV_LOG(DEBUG, "flow_ctrl 0x%x", vars->flow_ctrl); +} + +static void elink_check_fallback_to_cl37(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t rx_status, ustat_val, cl37_fsm_received; + PMD_DRV_LOG(DEBUG, "elink_check_fallback_to_cl37"); + /* Step 1: Make sure signal is detected */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status); + if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != + (MDIO_RX0_RX_STATUS_SIGDET)) { + PMD_DRV_LOG(DEBUG, "Signal is not detected. Restoring CL73." + "rx_status(0x80b0) = 0x%x", rx_status); + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB0, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); + return; + } + /* Step 2: Check CL73 state machine */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_USERB0, + MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val); + if ((ustat_val & + (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | + MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != + (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | + MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { + PMD_DRV_LOG(DEBUG, "CL73 state-machine is not stable. " + "ustat_val(0x8371) = 0x%x", ustat_val); + return; + } + /* Step 3: Check CL37 Message Pages received to indicate LP + * supports only CL37 + */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_REMOTE_PHY, + MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received); + if ((cl37_fsm_received & + (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | + MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != + (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | + MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { + PMD_DRV_LOG(DEBUG, "No CL37 FSM were received. " + "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received); + return; + } + /* The combined cl37/cl73 fsm state information indicating that + * we are connected to a device which does not support cl73, but + * does support cl37 BAM. In this case we disable cl73 and + * restart cl37 auto-neg + */ + + /* Disable CL73 */ + CL22_WR_OVER_CL45(sc, phy, + MDIO_REG_BANK_CL73_IEEEB0, + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0); + /* Restart CL37 autoneg */ + elink_restart_autoneg(phy, params, 0); + PMD_DRV_LOG(DEBUG, "Disabling CL73, and restarting CL37 autoneg"); +} + +static void elink_xgxs_an_resolve(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars, uint32_t gp_status) +{ + if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) + vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + + if (elink_direct_parallel_detect_used(phy, params)) + vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; +} + +static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, + struct elink_params *params __rte_unused, + struct elink_vars *vars, + uint16_t is_link_up, + uint16_t speed_mask, + uint16_t is_duplex) +{ + if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) + vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; + if (is_link_up) { + PMD_DRV_LOG(DEBUG, "phy link up"); + + vars->phy_link_up = 1; + vars->link_status |= LINK_STATUS_LINK_UP; + + switch (speed_mask) { + case ELINK_GP_STATUS_10M: + vars->line_speed = ELINK_SPEED_10; + if (is_duplex == DUPLEX_FULL) + vars->link_status |= ELINK_LINK_10TFD; + else + vars->link_status |= ELINK_LINK_10THD; + break; + + case ELINK_GP_STATUS_100M: + vars->line_speed = ELINK_SPEED_100; + if (is_duplex == DUPLEX_FULL) + vars->link_status |= ELINK_LINK_100TXFD; + else + vars->link_status |= ELINK_LINK_100TXHD; + break; + + case ELINK_GP_STATUS_1G: + case ELINK_GP_STATUS_1G_KX: + vars->line_speed = ELINK_SPEED_1000; + if (is_duplex == DUPLEX_FULL) + vars->link_status |= ELINK_LINK_1000TFD; + else + vars->link_status |= ELINK_LINK_1000THD; + break; + + case ELINK_GP_STATUS_2_5G: + vars->line_speed = ELINK_SPEED_2500; + if (is_duplex == DUPLEX_FULL) + vars->link_status |= ELINK_LINK_2500TFD; + else + vars->link_status |= ELINK_LINK_2500THD; + break; + + case ELINK_GP_STATUS_5G: + case ELINK_GP_STATUS_6G: + PMD_DRV_LOG(DEBUG, + "link speed unsupported gp_status 0x%x", + speed_mask); + return ELINK_STATUS_ERROR; + + case ELINK_GP_STATUS_10G_KX4: + case ELINK_GP_STATUS_10G_HIG: + case ELINK_GP_STATUS_10G_CX4: + case ELINK_GP_STATUS_10G_KR: + case ELINK_GP_STATUS_10G_SFI: + case ELINK_GP_STATUS_10G_XFI: + vars->line_speed = ELINK_SPEED_10000; + vars->link_status |= ELINK_LINK_10GTFD; + break; + case ELINK_GP_STATUS_20G_DXGXS: + case ELINK_GP_STATUS_20G_KR2: + vars->line_speed = ELINK_SPEED_20000; + vars->link_status |= ELINK_LINK_20GTFD; + break; + default: + PMD_DRV_LOG(DEBUG, + "link speed unsupported gp_status 0x%x", + speed_mask); + return ELINK_STATUS_ERROR; + } + } else { /* link_down */ + PMD_DRV_LOG(DEBUG, "phy link down"); + + vars->phy_link_up = 0; + + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_NONE; + } + PMD_DRV_LOG(DEBUG, " phy_link_up %x line_speed %d", + vars->phy_link_up, vars->line_speed); + return ELINK_STATUS_OK; +} + +static elink_status_t elink_link_settings_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + + uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; + elink_status_t rc = ELINK_STATUS_OK; + + /* Read gp_status */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_GP_STATUS, + MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status); + if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) + duplex = DUPLEX_FULL; + if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) + link_up = 1; + speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK; + PMD_DRV_LOG(DEBUG, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x", + gp_status, link_up, speed_mask); + rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, + duplex); + if (rc == ELINK_STATUS_ERROR) + return rc; + + if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { + if (ELINK_SINGLE_MEDIA_DIRECT(params)) { + vars->duplex = duplex; + elink_flow_ctrl_resolve(phy, params, vars, gp_status); + if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) + elink_xgxs_an_resolve(phy, params, vars, + gp_status); + } + } else { /* Link_down */ + if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + ELINK_SINGLE_MEDIA_DIRECT(params)) { + /* Check signal is detected */ + elink_check_fallback_to_cl37(phy, params); + } + } + + /* Read LP advertised speeds */ + if (ELINK_SINGLE_MEDIA_DIRECT(params) && + (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { + uint16_t val; + + CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1, + MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); + + if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | + MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + + CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G, + MDIO_OVER_1G_LP_UP1, &val); + + if (val & MDIO_OVER_1G_UP1_2_5G) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; + if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + } + + PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x", + vars->duplex, vars->flow_ctrl, vars->link_status); + return rc; +} + +static elink_status_t elink_warpcore_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t lane; + uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; + elink_status_t rc = ELINK_STATUS_OK; + lane = elink_get_warpcore_lane(params); + /* Read gp_status */ + if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); + link_up &= 0x1; + } else if ((phy->req_line_speed > ELINK_SPEED_10000) && + (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { + uint16_t temp_link_up; + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up); + PMD_DRV_LOG(DEBUG, "PCS RX link status = 0x%x-->0x%x", + temp_link_up, link_up); + link_up &= (1 << 2); + if (link_up) + elink_ext_phy_resolve_fc(phy, params, vars); + } else { + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); + PMD_DRV_LOG(DEBUG, "0x81d1 = 0x%x", gp_status1); + /* Check for either KR, 1G, or AN up. */ + link_up = ((gp_status1 >> 8) | + (gp_status1 >> 12) | (gp_status1)) & (1 << lane); + if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { + uint16_t an_link; + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_STATUS, &an_link); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_STATUS, &an_link); + link_up |= (an_link & (1 << 2)); + } + if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) { + uint16_t pd, gp_status4; + if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { + /* Check Autoneg complete */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_GP2_STATUS_GP_2_4, + &gp_status4); + if (gp_status4 & ((1 << 12) << lane)) + vars->link_status |= + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + + /* Check parallel detect used */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_PAR_DET_10G_STATUS, + &pd); + if (pd & (1 << 15)) + vars->link_status |= + LINK_STATUS_PARALLEL_DETECTION_USED; + } + elink_ext_phy_resolve_fc(phy, params, vars); + vars->duplex = duplex; + } + } + + if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && + ELINK_SINGLE_MEDIA_DIRECT(params)) { + uint16_t val; + + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_LP_AUTO_NEG2, &val); + + if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | + MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL3_LP_UP1, &val); + + if (val & MDIO_OVER_1G_UP1_2_5G) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; + if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + + } + + if (lane < 2) { + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); + } else { + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); + } + PMD_DRV_LOG(DEBUG, "lane %d gp_speed 0x%x", lane, gp_speed); + + if ((lane & 1) == 0) + gp_speed <<= 8; + gp_speed &= 0x3f00; + link_up = ! !link_up; + + /* Reset the TX FIFO to fix SGMII issue */ + rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, + duplex); + + /* In case of KR link down, start up the recovering procedure */ + if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) && + (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) + vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; + + PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x", + vars->duplex, vars->flow_ctrl, vars->link_status); + return rc; +} + +static void elink_set_gmii_tx_driver(struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; + uint16_t lp_up2; + uint16_t tx_driver; + uint16_t bank; + + /* Read precomp */ + CL22_RD_OVER_CL45(sc, phy, + MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2); + + /* Bits [10:7] at lp_up2, positioned at [15:12] */ + lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> + MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << + MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); + + if (lp_up2 == 0) + return; + + for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; + bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { + CL22_RD_OVER_CL45(sc, phy, + bank, MDIO_TX0_TX_DRIVER, &tx_driver); + + /* Replace tx_driver bits [15:12] */ + if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { + tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; + tx_driver |= lp_up2; + CL22_WR_OVER_CL45(sc, phy, + bank, MDIO_TX0_TX_DRIVER, tx_driver); + } + } +} + +static elink_status_t elink_emac_program(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint16_t mode = 0; + + PMD_DRV_LOG(DEBUG, "setting link speed & duplex"); + elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 + + EMAC_REG_EMAC_MODE, + (EMAC_MODE_25G_MODE | + EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX)); + switch (vars->line_speed) { + case ELINK_SPEED_10: + mode |= EMAC_MODE_PORT_MII_10M; + break; + + case ELINK_SPEED_100: + mode |= EMAC_MODE_PORT_MII; + break; + + case ELINK_SPEED_1000: + mode |= EMAC_MODE_PORT_GMII; + break; + + case ELINK_SPEED_2500: + mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); + break; + + default: + /* 10G not valid for EMAC */ + PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", vars->line_speed); + return ELINK_STATUS_ERROR; + } + + if (vars->duplex == DUPLEX_HALF) + mode |= EMAC_MODE_HALF_DUPLEX; + elink_bits_en(sc, + GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode); + + elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); + return ELINK_STATUS_OK; +} + +static void elink_set_preemphasis(struct elink_phy *phy, + struct elink_params *params) +{ + + uint16_t bank, i = 0; + struct bnx2x_softc *sc = params->sc; + + for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; + bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) { + CL22_WR_OVER_CL45(sc, phy, + bank, + MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]); + } + + for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; + bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { + CL22_WR_OVER_CL45(sc, phy, + bank, + MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]); + } +} + +static void elink_xgxs_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) || + (params->loopback_mode == ELINK_LOOPBACK_XGXS)); + + if (!(vars->phy_flags & PHY_SGMII_FLAG)) { + if (ELINK_SINGLE_MEDIA_DIRECT(params) && + (params->feature_config_flags & + ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) + elink_set_preemphasis(phy, params); + + /* Forced speed requested? */ + if (vars->line_speed != ELINK_SPEED_AUTO_NEG || + (ELINK_SINGLE_MEDIA_DIRECT(params) && + params->loopback_mode == ELINK_LOOPBACK_EXT)) { + PMD_DRV_LOG(DEBUG, "not SGMII, no AN"); + + /* Disable autoneg */ + elink_set_autoneg(phy, params, vars, 0); + + /* Program speed and duplex */ + elink_program_serdes(phy, params, vars); + + } else { /* AN_mode */ + PMD_DRV_LOG(DEBUG, "not SGMII, AN"); + + /* AN enabled */ + elink_set_brcm_cl37_advertisement(phy, params); + + /* Program duplex & pause advertisement (for aneg) */ + elink_set_ieee_aneg_advertisement(phy, params, + vars->ieee_fc); + + /* Enable autoneg */ + elink_set_autoneg(phy, params, vars, enable_cl73); + + /* Enable and restart AN */ + elink_restart_autoneg(phy, params, enable_cl73); + } + + } else { /* SGMII mode */ + PMD_DRV_LOG(DEBUG, "SGMII"); + + elink_initialize_sgmii_process(phy, params, vars); + } +} + +static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + elink_status_t rc; + vars->phy_flags |= PHY_XGXS_FLAG; + if ((phy->req_line_speed && + ((phy->req_line_speed == ELINK_SPEED_100) || + (phy->req_line_speed == ELINK_SPEED_10))) || + (!phy->req_line_speed && + (phy->speed_cap_mask >= + PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && + (phy->speed_cap_mask < + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || + (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) + vars->phy_flags |= PHY_SGMII_FLAG; + else + vars->phy_flags &= ~PHY_SGMII_FLAG; + + elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); + elink_set_aer_mmd(params, phy); + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) + elink_set_master_ln(params, phy); + + rc = elink_reset_unicore(params, phy, 0); + /* Reset the SerDes and wait for reset bit return low */ + if (rc != ELINK_STATUS_OK) + return rc; + + elink_set_aer_mmd(params, phy); + /* Setting the masterLn_def again after the reset */ + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { + elink_set_master_ln(params, phy); + elink_set_swap_lanes(params, phy); + } + + return rc; +} + +static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc, + struct elink_phy *phy, + struct elink_params *params) +{ + uint16_t cnt, ctrl; + /* Wait for soft reset to get cleared up to 1 sec */ + for (cnt = 0; cnt < 1000; cnt++) { + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) + elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl); + else + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, &ctrl); + if (!(ctrl & (1 << 15))) + break; + DELAY(1000 * 1); + } + + if (cnt == 1000) + elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," + // " Port %d", + + PMD_DRV_LOG(DEBUG, "control reg 0x%x (after %d ms)", ctrl, cnt); + return cnt; +} + +static void elink_link_int_enable(struct elink_params *params) +{ + uint8_t port = params->port; + uint32_t mask; + struct bnx2x_softc *sc = params->sc; + + /* Setting the status to report on link up for either XGXS or SerDes */ + if (CHIP_IS_E3(sc)) { + mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS; + if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) + mask |= ELINK_NIG_MASK_MI_INT; + } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { + mask = (ELINK_NIG_MASK_XGXS0_LINK10G | + ELINK_NIG_MASK_XGXS0_LINK_STATUS); + PMD_DRV_LOG(DEBUG, "enabled XGXS interrupt"); + if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && + params->phy[ELINK_INT_PHY].type != + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { + mask |= ELINK_NIG_MASK_MI_INT; + PMD_DRV_LOG(DEBUG, "enabled external phy int"); + } + + } else { /* SerDes */ + mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS; + PMD_DRV_LOG(DEBUG, "enabled SerDes interrupt"); + if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && + params->phy[ELINK_INT_PHY].type != + PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { + mask |= ELINK_NIG_MASK_MI_INT; + PMD_DRV_LOG(DEBUG, "enabled external phy int"); + } + } + elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask); + + PMD_DRV_LOG(DEBUG, "port %x, is_xgxs %x, int_status 0x%x", port, + (params->switch_cfg == ELINK_SWITCH_CFG_10G), + REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); + PMD_DRV_LOG(DEBUG, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x", + REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), + REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18), + REG_RD(sc, + NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); + PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x", + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); +} + +static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port, + uint8_t exp_mi_int) +{ + uint32_t latch_status = 0; + + /* Disable the MI INT ( external phy int ) by writing 1 to the + * status register. Link down indication is high-active-signal, + * so in this case we need to write the status to clear the XOR + */ + /* Read Latched signals */ + latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8); + PMD_DRV_LOG(DEBUG, "latch_status = 0x%x", latch_status); + /* Handle only those with latched-signal=up. */ + if (exp_mi_int) + elink_bits_en(sc, + NIG_REG_STATUS_INTERRUPT_PORT0 + + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT); + else + elink_bits_dis(sc, + NIG_REG_STATUS_INTERRUPT_PORT0 + + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT); + + if (latch_status & 1) { + + /* For all latched-signal=up : Re-Arm Latch signals */ + REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8, + (latch_status & 0xfffe) | (latch_status & 1)); + } + /* For all latched-signal=up,Write original_signal to status */ +} + +static void elink_link_int_ack(struct elink_params *params, + struct elink_vars *vars, uint8_t is_10g_plus) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + uint32_t mask; + /* First reset all status we assume only one line will be + * change at a time + */ + elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, + (ELINK_NIG_STATUS_XGXS0_LINK10G | + ELINK_NIG_STATUS_XGXS0_LINK_STATUS | + ELINK_NIG_STATUS_SERDES0_LINK_STATUS)); + if (vars->phy_link_up) { + if (USES_WARPCORE(sc)) + mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS; + else { + if (is_10g_plus) + mask = ELINK_NIG_STATUS_XGXS0_LINK10G; + else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { + /* Disable the link interrupt by writing 1 to + * the relevant lane in the status register + */ + uint32_t ser_lane = + ((params->lane_config & + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + mask = ((1 << ser_lane) << + ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); + } else + mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS; + } + PMD_DRV_LOG(DEBUG, "Ack link up interrupt with mask 0x%x", + mask); + elink_bits_en(sc, + NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask); + } +} + +static elink_status_t elink_format_ver(uint32_t num, uint8_t * str, + uint16_t * len) +{ + uint8_t *str_ptr = str; + uint32_t mask = 0xf0000000; + uint8_t shift = 8 * 4; + uint8_t digit; + uint8_t remove_leading_zeros = 1; + if (*len < 10) { + /* Need more than 10chars for this format */ + *str_ptr = '\0'; + (*len)--; + return ELINK_STATUS_ERROR; + } + while (shift > 0) { + + shift -= 4; + digit = ((num & mask) >> shift); + if (digit == 0 && remove_leading_zeros) { + mask = mask >> 4; + continue; + } else if (digit < 0xa) + *str_ptr = digit + '0'; + else + *str_ptr = digit - 0xa + 'a'; + remove_leading_zeros = 0; + str_ptr++; + (*len)--; + mask = mask >> 4; + if (shift == 4 * 4) { + *str_ptr = '.'; + str_ptr++; + (*len)--; + remove_leading_zeros = 1; + } + } + return ELINK_STATUS_OK; +} + +static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver, + uint8_t * str, uint16_t * len) +{ + str[0] = '\0'; + (*len)--; + return ELINK_STATUS_OK; +} + +static void elink_set_xgxs_loopback(struct elink_phy *phy, + struct elink_params *params) +{ + uint8_t port = params->port; + struct bnx2x_softc *sc = params->sc; + + if (phy->req_line_speed != ELINK_SPEED_1000) { + uint32_t md_devad = 0; + + PMD_DRV_LOG(DEBUG, "XGXS 10G loopback enable"); + + if (!CHIP_IS_E3(sc)) { + /* Change the uni_phy_addr in the nig */ + md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD + + port * 0x18)); + + REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18, + 0x5); + } + + elink_cl45_write(sc, phy, + 5, + (MDIO_REG_BANK_AER_BLOCK + + (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800); + + elink_cl45_write(sc, phy, + 5, + (MDIO_REG_BANK_CL73_IEEEB0 + + (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), + 0x6041); + DELAY(1000 * 200); + /* Set aer mmd back */ + elink_set_aer_mmd(params, phy); + + if (!CHIP_IS_E3(sc)) { + /* And md_devad */ + REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18, + md_devad); + } + } else { + uint16_t mii_ctrl; + PMD_DRV_LOG(DEBUG, "XGXS 1G loopback enable"); + elink_cl45_read(sc, phy, 5, + (MDIO_REG_BANK_COMBO_IEEE0 + + (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), + &mii_ctrl); + elink_cl45_write(sc, phy, 5, + (MDIO_REG_BANK_COMBO_IEEE0 + + (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), + mii_ctrl | + MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); + } +} + +elink_status_t elink_set_led(struct elink_params *params, + struct elink_vars *vars, uint8_t mode, + uint32_t speed) +{ + uint8_t port = params->port; + uint16_t hw_led_mode = params->hw_led_mode; + elink_status_t rc = ELINK_STATUS_OK; + uint8_t phy_idx; + uint32_t tmp; + uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "elink_set_led: port %x, mode %d", port, mode); + PMD_DRV_LOG(DEBUG, "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode); + /* In case */ + for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) { + if (params->phy[phy_idx].set_link_led) { + params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx], + params, mode); + } + } +#ifdef ELINK_INCLUDE_EMUL + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC) + return rc; +#endif + + switch (mode) { + case ELINK_LED_MODE_FRONT_PANEL_OFF: + case ELINK_LED_MODE_OFF: + REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0); + REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, + SHARED_HW_CFG_LED_MAC1); + + tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); + if (params->phy[ELINK_EXT_PHY1].type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) + tmp &= ~(EMAC_LED_1000MB_OVERRIDE | + EMAC_LED_100MB_OVERRIDE | + EMAC_LED_10MB_OVERRIDE); + else + tmp |= EMAC_LED_OVERRIDE; + + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp); + break; + + case ELINK_LED_MODE_OPER: + /* For all other phys, OPER mode is same as ON, so in case + * link is down, do nothing + */ + if (!vars->link_up) + break; + case ELINK_LED_MODE_ON: + if (((params->phy[ELINK_EXT_PHY1].type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) || + (params->phy[ELINK_EXT_PHY1].type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) && + CHIP_IS_E2(sc) && params->num_phys == 2) { + /* This is a work-around for E2+8727 Configurations */ + if (mode == ELINK_LED_MODE_ON || + speed == ELINK_SPEED_10000) { + REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); + REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1); + + tmp = + elink_cb_reg_read(sc, + emac_base + + EMAC_REG_EMAC_LED); + elink_cb_reg_write(sc, + emac_base + + EMAC_REG_EMAC_LED, + (tmp | EMAC_LED_OVERRIDE)); + /* Return here without enabling traffic + * LED blink and setting rate in ON mode. + * In oper mode, enabling LED blink + * and setting rate is needed. + */ + if (mode == ELINK_LED_MODE_ON) + return rc; + } + } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) { + /* This is a work-around for HW issue found when link + * is up in CL73 + */ + if ((!CHIP_IS_E3(sc)) || + (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON)) + REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1); + + if (CHIP_IS_E1x(sc) || + CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON)) + REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); + else + REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, + hw_led_mode); + } else if ((params->phy[ELINK_EXT_PHY1].type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) && + (mode == ELINK_LED_MODE_ON)) { + REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); + tmp = + elink_cb_reg_read(sc, + emac_base + EMAC_REG_EMAC_LED); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, + tmp | EMAC_LED_OVERRIDE | + EMAC_LED_1000MB_OVERRIDE); + /* Break here; otherwise, it'll disable the + * intended override. + */ + break; + } else { + uint32_t nig_led_mode = ((params->hw_led_mode << + SHARED_HW_CFG_LED_MODE_SHIFT) + == + SHARED_HW_CFG_LED_EXTPHY2) + ? (SHARED_HW_CFG_LED_PHY1 >> + SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; + REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, + nig_led_mode); + } + + REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4, + 0); + /* Set blinking rate to ~15.9Hz */ + if (CHIP_IS_E3(sc)) + REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4, + LED_BLINK_RATE_VAL_E3); + else + REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4, + LED_BLINK_RATE_VAL_E1X_E2); + REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1); + tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, + (tmp & (~EMAC_LED_OVERRIDE))); + + break; + + default: + rc = ELINK_STATUS_ERROR; + PMD_DRV_LOG(DEBUG, "elink_set_led: Invalid led mode %d", mode); + break; + } + return rc; + +} + +static elink_status_t elink_link_initialize(struct elink_params *params, + struct elink_vars *vars) +{ + elink_status_t rc = ELINK_STATUS_OK; + uint8_t phy_index, non_ext_phy; + struct bnx2x_softc *sc = params->sc; + /* In case of external phy existence, the line speed would be the + * line speed linked up by the external phy. In case it is direct + * only, then the line_speed during initialization will be + * equal to the req_line_speed + */ + vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; + + /* Initialize the internal phy in case this is a direct board + * (no external phys), or this board has external phy which requires + * to first. + */ + if (!USES_WARPCORE(sc)) + elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars); + /* init ext phy and enable link state int */ + non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) || + (params->loopback_mode == ELINK_LOOPBACK_XGXS)); + + if (non_ext_phy || + (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) || + (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { + struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; + if (vars->line_speed == ELINK_SPEED_AUTO_NEG && + (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) + elink_set_parallel_detection(phy, params); + if (params->phy[ELINK_INT_PHY].config_init) + params->phy[ELINK_INT_PHY].config_init(phy, + params, vars); + } + + /* Re-read this value in case it was changed inside config_init due to + * limitations of optic module + */ + vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; + + /* Init external phy */ + if (non_ext_phy) { + if (params->phy[ELINK_INT_PHY].supported & + ELINK_SUPPORTED_FIBRE) + vars->link_status |= LINK_STATUS_SERDES_LINK; + } else { + for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; + phy_index++) { + /* No need to initialize second phy in case of first + * phy only selection. In case of second phy, we do + * need to initialize the first phy, since they are + * connected. + */ + if (params->phy[phy_index].supported & + ELINK_SUPPORTED_FIBRE) + vars->link_status |= LINK_STATUS_SERDES_LINK; + + if (phy_index == ELINK_EXT_PHY2 && + (elink_phy_selection(params) == + PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { + PMD_DRV_LOG(DEBUG, + "Not initializing second phy"); + continue; + } + params->phy[phy_index].config_init(¶ms-> + phy[phy_index], + params, vars); + } + } + /* Reset the interrupt indication after phy was initialized */ + elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + + params->port * 4, + (ELINK_NIG_STATUS_XGXS0_LINK10G | + ELINK_NIG_STATUS_XGXS0_LINK_STATUS | + ELINK_NIG_STATUS_SERDES0_LINK_STATUS | + ELINK_NIG_MASK_MI_INT)); + return rc; +} + +static void elink_int_link_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) +{ + /* Reset the SerDes/XGXS */ + REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, + (0x1ff << (params->port * 16))); +} + +static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t gpio_port; + /* HW reset */ + if (CHIP_IS_E2(sc)) + gpio_port = SC_PATH(sc); + else + gpio_port = params->port; + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); + PMD_DRV_LOG(DEBUG, "reset external PHY"); +} + +static elink_status_t elink_update_link_down(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port = params->port; + + PMD_DRV_LOG(DEBUG, "Port %x: Link is down", port); + elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); + vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; + /* Indicate no mac active */ + vars->mac_type = ELINK_MAC_TYPE_NONE; + + /* Update shared memory */ + vars->link_status &= ~ELINK_LINK_UPDATE_MASK; + vars->line_speed = 0; + elink_update_mng(params, vars->link_status); + + /* Activate nig drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1); + + /* Disable emac */ + if (!CHIP_IS_E3(sc)) + REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0); + + DELAY(1000 * 10); + /* Reset BigMac/Xmac */ + if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)) + elink_set_bmac_rx(sc, params->port, 0); + + if (CHIP_IS_E3(sc)) { + /* Prevent LPI Generation by chip */ + REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), + 0); + REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), + 0); + vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | + SHMEM_EEE_ACTIVE_BIT); + + elink_update_mng_eee(params, vars->eee_status); + elink_set_xmac_rxtx(params, 0); + elink_set_umac_rxtx(params, 0); + } + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_update_link_up(struct elink_params *params, + struct elink_vars *vars, + uint8_t link_10g) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t phy_idx, port = params->port; + elink_status_t rc = ELINK_STATUS_OK; + + vars->link_status |= (LINK_STATUS_LINK_UP | + LINK_STATUS_PHYSICAL_LINK_FLAG); + vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; + + if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) + vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED; + + if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) + vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED; + if (USES_WARPCORE(sc)) { + if (link_10g) { + if (elink_xmac_enable(params, vars, 0) == + ELINK_STATUS_NO_LINK) { + PMD_DRV_LOG(DEBUG, "Found errors on XMAC"); + vars->link_up = 0; + vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; + vars->link_status &= ~LINK_STATUS_LINK_UP; + } + } else + elink_umac_enable(params, vars, 0); + elink_set_led(params, vars, + ELINK_LED_MODE_OPER, vars->line_speed); + + if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && + (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { + PMD_DRV_LOG(DEBUG, "Enabling LPI assertion"); + REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + + (params->port << 2), 1); + REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1); + REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + + (params->port << 2), 0xfc20); + } + } + if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) { + if (link_10g) { + if (elink_bmac_enable(params, vars, 0, 1) == + ELINK_STATUS_NO_LINK) { + PMD_DRV_LOG(DEBUG, "Found errors on BMAC"); + vars->link_up = 0; + vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; + vars->link_status &= ~LINK_STATUS_LINK_UP; + } + + elink_set_led(params, vars, + ELINK_LED_MODE_OPER, ELINK_SPEED_10000); + } else { + rc = elink_emac_program(params, vars); + elink_emac_enable(params, vars, 0); + + /* AN complete? */ + if ((vars->link_status & + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) + && (!(vars->phy_flags & PHY_SGMII_FLAG)) && + ELINK_SINGLE_MEDIA_DIRECT(params)) + elink_set_gmii_tx_driver(params); + } + } + + /* PBF - link up */ + if (CHIP_IS_E1x(sc)) + rc |= elink_pbf_update(params, vars->flow_ctrl, + vars->line_speed); + + /* Disable drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0); + + /* Update shared memory */ + elink_update_mng(params, vars->link_status); + elink_update_mng_eee(params, vars->eee_status); + /* Check remote fault */ + for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { + if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { + elink_check_half_open_conn(params, vars, 0); + break; + } + } + DELAY(1000 * 20); + return rc; +} + +/* The elink_link_update function should be called upon link + * interrupt. + * Link is considered up as follows: + * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs + * to be up + * - SINGLE_MEDIA - The link between the 577xx and the external + * phy (XGXS) need to up as well as the external link of the + * phy (PHY_EXT1) + * - DUAL_MEDIA - The link between the 577xx and the first + * external phy needs to be up, and at least one of the 2 + * external phy link must be up. + */ +elink_status_t elink_link_update(struct elink_params * params, + struct elink_vars * vars) +{ + struct bnx2x_softc *sc = params->sc; + struct elink_vars phy_vars[ELINK_MAX_PHYS]; + uint8_t port = params->port; + uint8_t link_10g_plus, phy_index; + uint8_t ext_phy_link_up = 0, cur_link_up; + elink_status_t rc = ELINK_STATUS_OK; + __rte_unused uint8_t is_mi_int = 0; + uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; + uint8_t active_external_phy = ELINK_INT_PHY; + vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; + vars->link_status &= ~ELINK_LINK_UPDATE_MASK; + for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; + phy_index++) { + phy_vars[phy_index].flow_ctrl = 0; + phy_vars[phy_index].link_status = 0; + phy_vars[phy_index].line_speed = 0; + phy_vars[phy_index].duplex = DUPLEX_FULL; + phy_vars[phy_index].phy_link_up = 0; + phy_vars[phy_index].link_up = 0; + phy_vars[phy_index].fault_detected = 0; + /* different consideration, since vars holds inner state */ + phy_vars[phy_index].eee_status = vars->eee_status; + } + + if (USES_WARPCORE(sc)) + elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); + + PMD_DRV_LOG(DEBUG, "port %x, XGXS?%x, int_status 0x%x", + port, (vars->phy_flags & PHY_XGXS_FLAG), + REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); + + is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + + port * 0x18) > 0); + PMD_DRV_LOG(DEBUG, "int_mask 0x%x MI_INT %x, SERDES_LINK %x", + REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), + is_mi_int, + REG_RD(sc, + NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); + + PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x", + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); + + /* Disable emac */ + if (!CHIP_IS_E3(sc)) + REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0); + + /* Step 1: + * Check external link change only for external phys, and apply + * priority selection between them in case the link on both phys + * is up. Note that instead of the common vars, a temporary + * vars argument is used since each phy may have different link/ + * speed/duplex result + */ + for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; + phy_index++) { + struct elink_phy *phy = ¶ms->phy[phy_index]; + if (!phy->read_status) + continue; + /* Read link status and params of this ext phy */ + cur_link_up = phy->read_status(phy, params, + &phy_vars[phy_index]); + if (cur_link_up) { + PMD_DRV_LOG(DEBUG, "phy in index %d link is up", + phy_index); + } else { + PMD_DRV_LOG(DEBUG, "phy in index %d link is down", + phy_index); + continue; + } + + if (!ext_phy_link_up) { + ext_phy_link_up = 1; + active_external_phy = phy_index; + } else { + switch (elink_phy_selection(params)) { + case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: + case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: + /* In this option, the first PHY makes sure to pass the + * traffic through itself only. + * Its not clear how to reset the link on the second phy + */ + active_external_phy = ELINK_EXT_PHY1; + break; + case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: + /* In this option, the first PHY makes sure to pass the + * traffic through the second PHY. + */ + active_external_phy = ELINK_EXT_PHY2; + break; + default: + /* Link indication on both PHYs with the following cases + * is invalid: + * - FIRST_PHY means that second phy wasn't initialized, + * hence its link is expected to be down + * - SECOND_PHY means that first phy should not be able + * to link up by itself (using configuration) + * - DEFAULT should be overriden during initialiazation + */ + PMD_DRV_LOG(DEBUG, "Invalid link indication" + "mpc=0x%x. DISABLING LINK !!!", + params->multi_phy_config); + ext_phy_link_up = 0; + break; + } + } + } + prev_line_speed = vars->line_speed; + /* Step 2: + * Read the status of the internal phy. In case of + * DIRECT_SINGLE_MEDIA board, this link is the external link, + * otherwise this is the link between the 577xx and the first + * external phy + */ + if (params->phy[ELINK_INT_PHY].read_status) + params->phy[ELINK_INT_PHY].read_status(¶ms-> + phy[ELINK_INT_PHY], + params, vars); + /* The INT_PHY flow control reside in the vars. This include the + * case where the speed or flow control are not set to AUTO. + * Otherwise, the active external phy flow control result is set + * to the vars. The ext_phy_line_speed is needed to check if the + * speed is different between the internal phy and external phy. + * This case may be result of intermediate link speed change. + */ + if (active_external_phy > ELINK_INT_PHY) { + vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; + /* Link speed is taken from the XGXS. AN and FC result from + * the external phy. + */ + vars->link_status |= phy_vars[active_external_phy].link_status; + + /* if active_external_phy is first PHY and link is up - disable + * disable TX on second external PHY + */ + if (active_external_phy == ELINK_EXT_PHY1) { + if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { + PMD_DRV_LOG(DEBUG, "Disabling TX on EXT_PHY2"); + params->phy[ELINK_EXT_PHY2]. + phy_specific_func(¶ms-> + phy[ELINK_EXT_PHY2], + params, ELINK_DISABLE_TX); + } + } + + ext_phy_line_speed = phy_vars[active_external_phy].line_speed; + vars->duplex = phy_vars[active_external_phy].duplex; + if (params->phy[active_external_phy].supported & + ELINK_SUPPORTED_FIBRE) + vars->link_status |= LINK_STATUS_SERDES_LINK; + else + vars->link_status &= ~LINK_STATUS_SERDES_LINK; + + vars->eee_status = phy_vars[active_external_phy].eee_status; + + PMD_DRV_LOG(DEBUG, "Active external phy selected: %x", + active_external_phy); + } + + for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; + phy_index++) { + if (params->phy[phy_index].flags & + ELINK_FLAGS_REARM_LATCH_SIGNAL) { + elink_rearm_latch_signal(sc, port, + phy_index == + active_external_phy); + break; + } + } + PMD_DRV_LOG(DEBUG, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," + " ext_phy_line_speed = %d", vars->flow_ctrl, + vars->link_status, ext_phy_line_speed); + /* Upon link speed change set the NIG into drain mode. Comes to + * deals with possible FIFO glitch due to clk change when speed + * is decreased without link down indicator + */ + + if (vars->phy_link_up) { + if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && + (ext_phy_line_speed != vars->line_speed)) { + PMD_DRV_LOG(DEBUG, "Internal link speed %d is" + " different than the external" + " link speed %d", vars->line_speed, + ext_phy_line_speed); + vars->phy_link_up = 0; + } else if (prev_line_speed != vars->line_speed) { + REG_WR(sc, + NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, + 0); + DELAY(1000 * 1); + } + } + + /* Anything 10 and over uses the bmac */ + link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); + + elink_link_int_ack(params, vars, link_10g_plus); + + /* In case external phy link is up, and internal link is down + * (not initialized yet probably after link initialization, it + * needs to be initialized. + * Note that after link down-up as result of cable plug, the xgxs + * link would probably become up again without the need + * initialize it + */ + if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) { + PMD_DRV_LOG(DEBUG, "ext_phy_link_up = %d, int_link_up = %d," + " init_preceding = %d", ext_phy_link_up, + vars->phy_link_up, + params->phy[ELINK_EXT_PHY1].flags & + ELINK_FLAGS_INIT_XGXS_FIRST); + if (!(params->phy[ELINK_EXT_PHY1].flags & + ELINK_FLAGS_INIT_XGXS_FIRST) + && ext_phy_link_up && !vars->phy_link_up) { + vars->line_speed = ext_phy_line_speed; + if (vars->line_speed < ELINK_SPEED_1000) + vars->phy_flags |= PHY_SGMII_FLAG; + else + vars->phy_flags &= ~PHY_SGMII_FLAG; + + if (params->phy[ELINK_INT_PHY].config_init) + params->phy[ELINK_INT_PHY].config_init(¶ms-> + phy + [ELINK_INT_PHY], + params, + vars); + } + } + /* Link is up only if both local phy and external phy (in case of + * non-direct board) are up and no fault detected on active PHY. + */ + vars->link_up = (vars->phy_link_up && + (ext_phy_link_up || + ELINK_SINGLE_MEDIA_DIRECT(params)) && + (phy_vars[active_external_phy].fault_detected == 0)); + + /* Update the PFC configuration in case it was changed */ + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) + vars->link_status |= LINK_STATUS_PFC_ENABLED; + else + vars->link_status &= ~LINK_STATUS_PFC_ENABLED; + + if (vars->link_up) + rc = elink_update_link_up(params, vars, link_10g_plus); + else + rc = elink_update_link_down(params, vars); + + /* Update MCP link status was changed */ + if (params-> + feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) + elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); + + return rc; +} + +/*****************************************************************************/ +/* External Phy section */ +/*****************************************************************************/ +static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port) +{ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + DELAY(1000 * 1); + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); +} + +static void elink_save_spirom_version(struct bnx2x_softc *sc, + __rte_unused uint8_t port, + uint32_t spirom_ver, uint32_t ver_addr) +{ + PMD_DRV_LOG(DEBUG, "FW version 0x%x:0x%x for port %d", + (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port); + + if (ver_addr) + REG_WR(sc, ver_addr, spirom_ver); +} + +static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc, + struct elink_phy *phy, uint8_t port) +{ + uint16_t fw_ver1, fw_ver2; + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER1, &fw_ver1); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, &fw_ver2); + elink_save_spirom_version(sc, port, + (uint32_t) (fw_ver1 << 16 | fw_ver2), + phy->ver_addr); +} + +static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc, + struct elink_phy *phy, + struct elink_vars *vars) +{ + uint16_t val; + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val); + if (val & (1 << 5)) + vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + if ((val & (1 << 0)) == 0) + vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; +} + +/******************************************************************/ +/* common BNX2X8073/BNX2X8727 PHY SECTION */ +/******************************************************************/ +static void elink_8073_resolve_fc(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + if (phy->req_line_speed == ELINK_SPEED_10 || + phy->req_line_speed == ELINK_SPEED_100) { + vars->flow_ctrl = phy->req_flow_ctrl; + return; + } + + if (elink_ext_phy_resolve_fc(phy, params, vars) && + (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { + uint16_t pause_result; + uint16_t ld_pause; /* local */ + uint16_t lp_pause; /* link partner */ + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LD, &ld_pause); + + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LP, &lp_pause); + pause_result = (ld_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; + pause_result |= (lp_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; + + elink_pause_resolve(vars, pause_result); + PMD_DRV_LOG(DEBUG, "Ext PHY CL37 pause result 0x%x", + pause_result); + } +} + +static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc, + struct elink_phy *phy, + uint8_t port) +{ + uint32_t count = 0; + uint16_t fw_ver1, fw_msgout; + elink_status_t rc = ELINK_STATUS_OK; + + /* Boot port from external ROM */ + /* EDC grst */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); + + /* Ucode reboot and rst */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001); + + /* Reset internal microprocessor */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, + MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); + + /* Release srst bit */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, + MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); + + /* Delay 100ms per the PHY specifications */ + DELAY(1000 * 100); + + /* 8073 sometimes taking longer to download */ + do { + count++; + if (count > 300) { + PMD_DRV_LOG(DEBUG, + "elink_8073_8727_external_rom_boot port %x:" + "Download failed. fw version = 0x%x", + port, fw_ver1); + rc = ELINK_STATUS_ERROR; + break; + } + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER1, &fw_ver1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); + + DELAY(1000 * 1); + } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || + ((fw_msgout & 0xff) != 0x03 && (phy->type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073))); + + /* Clear ser_boot_ctl bit */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000); + elink_save_bnx2x_spirom_ver(sc, phy, port); + + PMD_DRV_LOG(DEBUG, + "elink_8073_8727_external_rom_boot port %x:" + "Download complete. fw version = 0x%x", port, fw_ver1); + + return rc; +} + +/******************************************************************/ +/* BNX2X8073 PHY SECTION */ +/******************************************************************/ +static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc, + struct elink_phy *phy) +{ + /* This is only required for 8073A1, version 102 only */ + uint16_t val; + + /* Read 8073 HW revision */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val); + + if (val != 1) { + /* No need to workaround in 8073 A1 */ + return ELINK_STATUS_OK; + } + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val); + + /* SNR should be applied only for version 0x102 */ + if (val != 0x102) + return ELINK_STATUS_OK; + + return 1; +} + +static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc, + struct elink_phy *phy) +{ + uint16_t val, cnt, cnt1; + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val); + + if (val > 0) { + /* No need to workaround in 8073 A1 */ + return ELINK_STATUS_OK; + } + /* XAUI workaround in 8073 A0: */ + + /* After loading the boot ROM and restarting Autoneg, poll + * Dev1, Reg $C820: + */ + + for (cnt = 0; cnt < 1000; cnt++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val); + /* If bit [14] = 0 or bit [13] = 0, continue on with + * system initialization (XAUI work-around not required, as + * these bits indicate 2.5G or 1G link up). + */ + if (!(val & (1 << 14)) || !(val & (1 << 13))) { + PMD_DRV_LOG(DEBUG, "XAUI work-around not required"); + return ELINK_STATUS_OK; + } else if (!(val & (1 << 15))) { + PMD_DRV_LOG(DEBUG, "bit 15 went off"); + /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's + * MSB (bit15) goes to 1 (indicating that the XAUI + * workaround has completed), then continue on with + * system initialization. + */ + for (cnt1 = 0; cnt1 < 1000; cnt1++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_XAUI_WA, + &val); + if (val & (1 << 15)) { + PMD_DRV_LOG(DEBUG, + "XAUI workaround has completed"); + return ELINK_STATUS_OK; + } + DELAY(1000 * 3); + } + break; + } + DELAY(1000 * 3); + } + PMD_DRV_LOG(DEBUG, "Warning: XAUI work-around timeout !!!"); + return ELINK_STATUS_ERROR; +} + +static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy) +{ + /* Force KR or KX */ + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); +} + +static void elink_8073_set_pause_cl37(struct elink_params *params, + struct elink_phy *phy, + struct elink_vars *vars) +{ + uint16_t cl37_val; + struct bnx2x_softc *sc = params->sc; + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); + + cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ + elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; + } + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + } + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + } + PMD_DRV_LOG(DEBUG, "Ext phy AN advertize cl37 0x%x", cl37_val); + + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); + DELAY(1000 * 500); +} + +static void elink_8073_specific_func(struct elink_phy *phy, + struct elink_params *params, + uint32_t action) +{ + struct bnx2x_softc *sc = params->sc; + switch (action) { + case ELINK_PHY_INIT: + /* Enable LASI */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, + (1 << 2)); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, + 0x0004); + break; + } +} + +static elink_status_t elink_8073_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val = 0, tmp1; + uint8_t gpio_port; + PMD_DRV_LOG(DEBUG, "Init 8073"); + + if (CHIP_IS_E2(sc)) + gpio_port = SC_PATH(sc); + else + gpio_port = params->port; + /* Restore normal power mode */ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); + + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); + + elink_8073_specific_func(phy, params, ELINK_PHY_INIT); + elink_8073_set_pause_cl37(params, phy, vars); + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); + + PMD_DRV_LOG(DEBUG, "Before rom RX_ALARM(port1): 0x%x", tmp1); + + /* Swap polarity if required - Must be done only in non-1G mode */ + if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { + /* Configure the 8073 to swap _P and _N of the KR lines */ + PMD_DRV_LOG(DEBUG, "Swapping polarity for the 8073"); + /* 10G Rx/Tx and 1G Tx signal polarity swap */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, + (val | (3 << 9))); + } + + /* Enable CL37 BAM */ + if (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + default_cfg)) & + PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { + + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1); + PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR"); + } + if (params->loopback_mode == ELINK_LOOPBACK_EXT) { + elink_807x_force_10G(sc, phy); + PMD_DRV_LOG(DEBUG, "Forced speed 10G on 807X"); + return ELINK_STATUS_OK; + } else { + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002); + } + if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { + if (phy->req_line_speed == ELINK_SPEED_10000) { + val = (1 << 7); + } else if (phy->req_line_speed == ELINK_SPEED_2500) { + val = (1 << 5); + /* Note that 2.5G works only when used with 1G + * advertisement + */ + } else + val = (1 << 5); + } else { + val = 0; + if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) + val |= (1 << 7); + + /* Note that 2.5G works only when used with 1G advertisement */ + if (phy->speed_cap_mask & + (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | + PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) + val |= (1 << 5); + PMD_DRV_LOG(DEBUG, "807x autoneg val = 0x%x", val); + } + + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); + + if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && + (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) || + (phy->req_line_speed == ELINK_SPEED_2500)) { + uint16_t phy_ver; + /* Allow 2.5G for A1 and above */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, + &phy_ver); + PMD_DRV_LOG(DEBUG, "Add 2.5G"); + if (phy_ver > 0) + tmp1 |= 1; + else + tmp1 &= 0xfffe; + } else { + PMD_DRV_LOG(DEBUG, "Disable 2.5G"); + tmp1 &= 0xfffe; + } + + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); + /* Add support for CL37 (passive mode) II */ + + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, + (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? + 0x20 : 0x40))); + + /* Add support for CL37 (passive mode) III */ + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); + + /* The SNR will improve about 2db by changing BW and FEE main + * tap. Rest commands are executed after link is up + * Change FFE main cursor to 5 in EDC register + */ + if (elink_8073_is_snr_needed(sc, phy)) + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, + 0xFB0C); + + /* Enable FEC (Forware Error Correction) Request in the AN */ + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); + tmp1 |= (1 << 15); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); + + elink_ext_phy_set_pause(params, phy, vars); + + /* Restart autoneg */ + DELAY(1000 * 500); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); + PMD_DRV_LOG(DEBUG, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x", + ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0)); + return ELINK_STATUS_OK; +} + +static uint8_t elink_8073_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t link_up = 0; + uint16_t val1, val2; + uint16_t link_status = 0; + uint16_t an1000_status = 0; + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + + PMD_DRV_LOG(DEBUG, "8703 LASI status 0x%x", val1); + + /* Clear the interrupt LASI status register */ + elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); + elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); + PMD_DRV_LOG(DEBUG, "807x PCS status 0x%x->0x%x", val2, val1); + /* Clear MSG-OUT */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); + + /* Check the LASI */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); + + PMD_DRV_LOG(DEBUG, "KR 0x9003 0x%x", val2); + + /* Check the link status */ + elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); + PMD_DRV_LOG(DEBUG, "KR PCS status 0x%x", val2); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); + link_up = ((val1 & 4) == 4); + PMD_DRV_LOG(DEBUG, "PMA_REG_STATUS=0x%x", val1); + + if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) { + if (elink_8073_xaui_wa(sc, phy) != 0) + return 0; + } + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); + + /* Check the link status on 1.1.2 */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); + PMD_DRV_LOG(DEBUG, "KR PMA status 0x%x->0x%x," + "an_link_status=0x%x", val2, val1, an1000_status); + + link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1))); + if (link_up && elink_8073_is_snr_needed(sc, phy)) { + /* The SNR will improve about 2dbby changing the BW and FEE main + * tap. The 1st write to change FFE main tap is set before + * restart AN. Change PLL Bandwidth in EDC register + */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, + 0x26BC); + + /* Change CDR Bandwidth in EDC register */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, + 0x0333); + } + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, + &link_status); + + /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ + if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) { + link_up = 1; + vars->line_speed = ELINK_SPEED_10000; + PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G", + params->port); + } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) { + link_up = 1; + vars->line_speed = ELINK_SPEED_2500; + PMD_DRV_LOG(DEBUG, "port %x: External link up in 2.5G", + params->port); + } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) { + link_up = 1; + vars->line_speed = ELINK_SPEED_1000; + PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G", + params->port); + } else { + link_up = 0; + PMD_DRV_LOG(DEBUG, "port %x: External link is down", + params->port); + } + + if (link_up) { + /* Swap polarity if required */ + if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { + /* Configure the 8073 to swap P and N of the KR lines */ + elink_cl45_read(sc, phy, + MDIO_XS_DEVAD, + MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); + /* Set bit 3 to invert Rx in 1G mode and clear this bit + * when it`s in 10G mode. + */ + if (vars->line_speed == ELINK_SPEED_1000) { + PMD_DRV_LOG(DEBUG, "Swapping 1G polarity for" + "the 8073"); + val1 |= (1 << 3); + } else + val1 &= ~(1 << 3); + + elink_cl45_write(sc, phy, + MDIO_XS_DEVAD, + MDIO_XS_REG_8073_RX_CTRL_PCIE, val1); + } + elink_ext_phy_10G_an_resolve(sc, phy, vars); + elink_8073_resolve_fc(phy, params, vars); + vars->duplex = DUPLEX_FULL; + } + + if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_LP_AUTO_NEG2, &val1); + + if (val1 & (1 << 5)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + if (val1 & (1 << 7)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + } + + return link_up; +} + +static void elink_8073_link_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t gpio_port; + if (CHIP_IS_E2(sc)) + gpio_port = SC_PATH(sc); + else + gpio_port = params->port; + PMD_DRV_LOG(DEBUG, "Setting 8073 port %d into low power mode", + gpio_port); + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); +} + +/******************************************************************/ +/* BNX2X8705 PHY SECTION */ +/******************************************************************/ +static elink_status_t elink_8705_config_init(struct elink_phy *phy, + struct elink_params *params, + __rte_unused struct elink_vars + *vars) +{ + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "init 8705"); + /* Restore normal power mode */ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + /* HW reset */ + elink_ext_phy_hw_reset(sc, params->port); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); + elink_wait_reset_complete(sc, phy, params); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); + elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); + /* BNX2X8705 doesn't have microcode, hence the 0 */ + elink_save_spirom_version(sc, params->port, params->shmem_base, 0); + return ELINK_STATUS_OK; +} + +static uint8_t elink_8705_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + uint8_t link_up = 0; + uint16_t val1, rx_sd; + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "read status 8705"); + elink_cl45_read(sc, phy, + MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); + PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1); + + elink_cl45_read(sc, phy, + MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); + PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1); + + PMD_DRV_LOG(DEBUG, "8705 1.c809 val=0x%x", val1); + link_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) + && ((val1 & (1 << 8)) == 0)); + if (link_up) { + vars->line_speed = ELINK_SPEED_10000; + elink_ext_phy_resolve_fc(phy, params, vars); + } + return link_up; +} + +/******************************************************************/ +/* SFP+ module Section */ +/******************************************************************/ +static void elink_set_disable_pmd_transmit(struct elink_params *params, + struct elink_phy *phy, + uint8_t pmd_dis) +{ + struct bnx2x_softc *sc = params->sc; + /* Disable transmitter only for bootcodes which can enable it afterwards + * (for D3 link) + */ + if (pmd_dis) { + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { + PMD_DRV_LOG(DEBUG, "Disabling PMD transmitter"); + } else { + PMD_DRV_LOG(DEBUG, "NOT disabling PMD transmitter"); + return; + } + } else { + PMD_DRV_LOG(DEBUG, "Enabling PMD transmitter"); + } + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis); +} + +static uint8_t elink_get_gpio_port(struct elink_params *params) +{ + uint8_t gpio_port; + uint32_t swap_val, swap_override; + struct bnx2x_softc *sc = params->sc; + if (CHIP_IS_E2(sc)) { + gpio_port = SC_PATH(sc); + } else { + gpio_port = params->port; + } + swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); + swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); + return gpio_port ^ (swap_val && swap_override); +} + +static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, + struct elink_phy *phy, uint8_t tx_en) +{ + uint16_t val; + uint8_t port = params->port; + struct bnx2x_softc *sc = params->sc; + uint32_t tx_en_mode; + + /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */ + tx_en_mode = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port].sfp_ctrl)) & + PORT_HW_CFG_TX_LASER_MASK; + PMD_DRV_LOG(DEBUG, "Setting transmitter tx_en=%x for port %x " + "mode = %x", tx_en, port, tx_en_mode); + switch (tx_en_mode) { + case PORT_HW_CFG_TX_LASER_MDIO: + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, &val); + + if (tx_en) + val &= ~(1 << 15); + else + val |= (1 << 15); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, val); + break; + case PORT_HW_CFG_TX_LASER_GPIO0: + case PORT_HW_CFG_TX_LASER_GPIO1: + case PORT_HW_CFG_TX_LASER_GPIO2: + case PORT_HW_CFG_TX_LASER_GPIO3: + { + uint16_t gpio_pin; + uint8_t gpio_port, gpio_mode; + if (tx_en) + gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; + else + gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; + + gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; + gpio_port = elink_get_gpio_port(params); + elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); + break; + } + default: + PMD_DRV_LOG(DEBUG, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode); + break; + } +} + +static void elink_sfp_set_transmitter(struct elink_params *params, + struct elink_phy *phy, uint8_t tx_en) +{ + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "Setting SFP+ transmitter to %d", tx_en); + if (CHIP_IS_E3(sc)) + elink_sfp_e3_set_transmitter(params, phy, tx_en); + else + elink_sfp_e1e2_set_transmitter(params, phy, tx_en); +} + +static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, + struct elink_params + *params, + uint8_t dev_addr, + uint16_t addr, + uint8_t byte_cnt, + uint8_t * o_buf, + __rte_unused uint8_t + is_init) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val = 0; + uint16_t i; + if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { + PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf"); + return ELINK_STATUS_ERROR; + } + /* Set the read command byte count */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, + (byte_cnt | (dev_addr << 8))); + + /* Set the read command address */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, + addr); + + /* Activate read command */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, + 0x2c0f); + + /* Wait up to 500us for command complete status */ + for (i = 0; i < 100; i++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); + if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) + break; + DELAY(5); + } + + if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { + PMD_DRV_LOG(DEBUG, + "Got bad status 0x%x when reading from SFP+ EEPROM", + (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); + return ELINK_STATUS_ERROR; + } + + /* Read the buffer */ + for (i = 0; i < byte_cnt; i++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); + o_buf[i] = + (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); + } + + for (i = 0; i < 100; i++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); + if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) + return ELINK_STATUS_OK; + DELAY(1000 * 1); + } + return ELINK_STATUS_ERROR; +} + +static void elink_warpcore_power_module(struct elink_params *params, + uint8_t power) +{ + uint32_t pin_cfg; + struct bnx2x_softc *sc = params->sc; + + pin_cfg = (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK) + >> PORT_HW_CFG_E3_PWR_DIS_SHIFT; + + if (pin_cfg == PIN_CFG_NA) + return; + PMD_DRV_LOG(DEBUG, "Setting SFP+ module power to %d using pin cfg %d", + power, pin_cfg); + /* Low ==> corresponding SFP+ module is powered + * high ==> the SFP+ module is powered down + */ + elink_set_cfg_pin(sc, pin_cfg, power ^ 1); +} + +static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct + elink_phy *phy, + struct elink_params + *params, + uint8_t dev_addr, + uint16_t addr, + uint8_t byte_cnt, + uint8_t * o_buf, + uint8_t is_init) +{ + elink_status_t rc = ELINK_STATUS_OK; + uint8_t i, j = 0, cnt = 0; + uint32_t data_array[4]; + uint16_t addr32; + struct bnx2x_softc *sc = params->sc; + + if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { + PMD_DRV_LOG(DEBUG, + "Reading from eeprom is limited to 16 bytes"); + return ELINK_STATUS_ERROR; + } + + /* 4 byte aligned address */ + addr32 = addr & (~0x3); + do { + if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { + elink_warpcore_power_module(params, 0); + /* Note that 100us are not enough here */ + DELAY(1000 * 1); + elink_warpcore_power_module(params, 1); + } + rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt, + data_array); + } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT)); + + if (rc == ELINK_STATUS_OK) { + for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { + o_buf[j] = *((uint8_t *) data_array + i); + j++; + } + } + + return rc; +} + +static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, + struct elink_params + *params, + uint8_t dev_addr, + uint16_t addr, + uint8_t byte_cnt, + uint8_t * o_buf, + __rte_unused uint8_t + is_init) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val, i; + + if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { + PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf"); + return ELINK_STATUS_ERROR; + } + + /* Set 2-wire transfer rate of SFP+ module EEPROM + * to 100Khz since some DACs(direct attached cables) do + * not work at 400Khz. + */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, + ((dev_addr << 8) | 1)); + + /* Need to read from 1.8000 to clear it */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); + + /* Set the read command byte count */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, + ((byte_cnt < 2) ? 2 : byte_cnt)); + + /* Set the read command address */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr); + /* Set the destination address */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); + + /* Activate read command */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002); + /* Wait appropriate time for two-wire command to finish before + * polling the status register + */ + DELAY(1000 * 1); + + /* Wait up to 500us for command complete status */ + for (i = 0; i < 100; i++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); + if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) + break; + DELAY(5); + } + + if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { + PMD_DRV_LOG(DEBUG, + "Got bad status 0x%x when reading from SFP+ EEPROM", + (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); + return ELINK_STATUS_TIMEOUT; + } + + /* Read the buffer */ + for (i = 0; i < byte_cnt; i++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); + o_buf[i] = + (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); + } + + for (i = 0; i < 100; i++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); + if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) + return ELINK_STATUS_OK; + DELAY(1000 * 1); + } + + return ELINK_STATUS_ERROR; +} + +static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, + struct elink_params *params, + uint8_t dev_addr, + uint16_t addr, + uint16_t byte_cnt, + uint8_t * o_buf) +{ + elink_status_t rc = 0; + uint8_t xfer_size; + uint8_t *user_data = o_buf; + read_sfp_module_eeprom_func_p read_func; + + if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { + PMD_DRV_LOG(DEBUG, "invalid dev_addr 0x%x", dev_addr); + return ELINK_STATUS_ERROR; + } + + switch (phy->type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: + read_func = elink_8726_read_sfp_module_eeprom; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: + read_func = elink_8727_read_sfp_module_eeprom; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: + read_func = elink_warpcore_read_sfp_module_eeprom; + break; + default: + return ELINK_OP_NOT_SUPPORTED; + } + + while (!rc && (byte_cnt > 0)) { + xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ? + ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; + rc = read_func(phy, params, dev_addr, addr, xfer_size, + user_data, 0); + byte_cnt -= xfer_size; + user_data += xfer_size; + addr += xfer_size; + } + return rc; +} + +static elink_status_t elink_get_edc_mode(struct elink_phy *phy, + struct elink_params *params, + uint16_t * edc_mode) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t sync_offset = 0, phy_idx, media_types; + uint8_t gport, val[2], check_limiting_mode = 0; + *edc_mode = ELINK_EDC_MODE_LIMITING; + phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; + /* First check for copper cable */ + if (elink_read_sfp_module_eeprom(phy, + params, + ELINK_I2C_DEV_ADDR_A0, + ELINK_SFP_EEPROM_CON_TYPE_ADDR, + 2, (uint8_t *) val) != 0) { + PMD_DRV_LOG(DEBUG, "Failed to read from SFP+ module EEPROM"); + return ELINK_STATUS_ERROR; + } + + switch (val[0]) { + case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: + { + uint8_t copper_module_type; + phy->media_type = ELINK_ETH_PHY_DA_TWINAX; + /* Check if its active cable (includes SFP+ module) + * of passive cable + */ + if (elink_read_sfp_module_eeprom(phy, + params, + ELINK_I2C_DEV_ADDR_A0, + ELINK_SFP_EEPROM_FC_TX_TECH_ADDR, + 1, + &copper_module_type) != + 0) { + PMD_DRV_LOG(DEBUG, + "Failed to read copper-cable-type" + " from SFP+ EEPROM"); + return ELINK_STATUS_ERROR; + } + + if (copper_module_type & + ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { + PMD_DRV_LOG(DEBUG, + "Active Copper cable detected"); + if (phy->type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) + *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; + else + check_limiting_mode = 1; + } else if (copper_module_type & + ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) + { + PMD_DRV_LOG(DEBUG, + "Passive Copper cable detected"); + *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC; + } else { + PMD_DRV_LOG(DEBUG, + "Unknown copper-cable-type 0x%x !!!", + copper_module_type); + return ELINK_STATUS_ERROR; + } + break; + } + case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: + case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: + check_limiting_mode = 1; + if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK | + ELINK_SFP_EEPROM_COMP_CODE_LR_MASK | + ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { + PMD_DRV_LOG(DEBUG, "1G SFP module detected"); + gport = params->port; + phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; + if (phy->req_line_speed != ELINK_SPEED_1000) { + phy->req_line_speed = ELINK_SPEED_1000; + if (!CHIP_IS_E1x(sc)) { + gport = SC_PATH(sc) + + (params->port << 1); + } + elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps." + // " Current SFP module in port %d is not" + // " compliant with 10G Ethernet", + + } + } else { + int idx, cfg_idx = 0; + PMD_DRV_LOG(DEBUG, "10G Optic module detected"); + for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) { + if (params->phy[idx].type == phy->type) { + cfg_idx = ELINK_LINK_CONFIG_IDX(idx); + break; + } + } + phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; + phy->req_line_speed = params->req_line_speed[cfg_idx]; + } + break; + default: + PMD_DRV_LOG(DEBUG, "Unable to determine module type 0x%x !!!", + val[0]); + return ELINK_STATUS_ERROR; + } + sync_offset = params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port].media_type); + media_types = REG_RD(sc, sync_offset); + /* Update media type for non-PMF sync */ + for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { + if (&(params->phy[phy_idx]) == phy) { + media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << + (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * + phy_idx)); + media_types |= + ((phy-> + media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << + (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); + break; + } + } + REG_WR(sc, sync_offset, media_types); + if (check_limiting_mode) { + uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE]; + if (elink_read_sfp_module_eeprom(phy, + params, + ELINK_I2C_DEV_ADDR_A0, + ELINK_SFP_EEPROM_OPTIONS_ADDR, + ELINK_SFP_EEPROM_OPTIONS_SIZE, + options) != 0) { + PMD_DRV_LOG(DEBUG, + "Failed to read Option field from module EEPROM"); + return ELINK_STATUS_ERROR; + } + if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) + *edc_mode = ELINK_EDC_MODE_LINEAR; + else + *edc_mode = ELINK_EDC_MODE_LIMITING; + } + PMD_DRV_LOG(DEBUG, "EDC mode is set to 0x%x", *edc_mode); + return ELINK_STATUS_OK; +} + +/* This function read the relevant field from the module (SFP+), and verify it + * is compliant with this board + */ +static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t val, cmd; + uint32_t fw_resp, fw_cmd_param; + char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1]; + char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1]; + phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; + val = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_feature_config[params->port]. + config)); + if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == + PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { + PMD_DRV_LOG(DEBUG, "NOT enforcing module verification"); + return ELINK_STATUS_OK; + } + + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { + /* Use specific phy request */ + cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; + } else if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { + /* Use first phy request only in case of non-dual media */ + if (ELINK_DUAL_MEDIA(params)) { + PMD_DRV_LOG(DEBUG, + "FW does not support OPT MDL verification"); + return ELINK_STATUS_ERROR; + } + cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; + } else { + /* No support in OPT MDL detection */ + PMD_DRV_LOG(DEBUG, "FW does not support OPT MDL verification"); + return ELINK_STATUS_ERROR; + } + + fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); + fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param); + if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { + PMD_DRV_LOG(DEBUG, "Approved module"); + return ELINK_STATUS_OK; + } + + /* Format the warning message */ + if (elink_read_sfp_module_eeprom(phy, + params, + ELINK_I2C_DEV_ADDR_A0, + ELINK_SFP_EEPROM_VENDOR_NAME_ADDR, + ELINK_SFP_EEPROM_VENDOR_NAME_SIZE, + (uint8_t *) vendor_name)) + vendor_name[0] = '\0'; + else + vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; + if (elink_read_sfp_module_eeprom(phy, + params, + ELINK_I2C_DEV_ADDR_A0, + ELINK_SFP_EEPROM_PART_NO_ADDR, + ELINK_SFP_EEPROM_PART_NO_SIZE, + (uint8_t *) vendor_pn)) + vendor_pn[0] = '\0'; + else + vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0'; + + elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected," + // " Port %d from %s part number %s", + + if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != + PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) + phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED; + return ELINK_STATUS_ERROR; +} + +static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy + *phy, + struct elink_params + *params) +{ + uint8_t val; + elink_status_t rc; + uint16_t timeout; + /* Initialization time after hot-plug may take up to 300ms for + * some phys type ( e.g. JDSU ) + */ + + for (timeout = 0; timeout < 60; timeout++) { + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) + rc = elink_warpcore_read_sfp_module_eeprom(phy, params, + ELINK_I2C_DEV_ADDR_A0, + 1, 1, &val, + 1); + else + rc = elink_read_sfp_module_eeprom(phy, params, + ELINK_I2C_DEV_ADDR_A0, + 1, 1, &val); + if (rc == 0) { + PMD_DRV_LOG(DEBUG, + "SFP+ module initialization took %d ms", + timeout * 5); + return ELINK_STATUS_OK; + } + DELAY(1000 * 5); + } + rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, + 1, 1, &val); + return rc; +} + +static void elink_8727_power_module(struct bnx2x_softc *sc, + struct elink_phy *phy, uint8_t is_power_up) +{ + /* Make sure GPIOs are not using for LED mode */ + uint16_t val; + /* In the GPIO register, bit 4 is use to determine if the GPIOs are + * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for + * output + * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 + * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 + * where the 1st bit is the over-current(only input), and 2nd bit is + * for power( only output ) + * + * In case of NOC feature is disabled and power is up, set GPIO control + * as input to enable listening of over-current indication + */ + if (phy->flags & ELINK_FLAGS_NOC) + return; + if (is_power_up) + val = (1 << 4); + else + /* Set GPIO control to OUTPUT, and set the power bit + * to according to the is_power_up + */ + val = (1 << 1); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val); +} + +static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc, + struct elink_phy *phy, + uint16_t edc_mode) +{ + uint16_t cur_limiting_mode; + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode); + PMD_DRV_LOG(DEBUG, "Current Limiting mode is 0x%x", cur_limiting_mode); + + if (edc_mode == ELINK_EDC_MODE_LIMITING) { + PMD_DRV_LOG(DEBUG, "Setting LIMITING MODE"); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, + ELINK_EDC_MODE_LIMITING); + } else { /* LRM mode ( default ) */ + + PMD_DRV_LOG(DEBUG, "Setting LRM MODE"); + + /* Changing to LRM mode takes quite few seconds. So do it only + * if current mode is limiting (default is LRM) + */ + if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING) + return ELINK_STATUS_OK; + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_MISC_CTRL0, 0x4008); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa); + } + return ELINK_STATUS_OK; +} + +static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc, + struct elink_phy *phy, + uint16_t edc_mode) +{ + uint16_t phy_identifier; + uint16_t rom_ver2_val; + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, + (phy_identifier & ~(1 << 9))); + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val); + /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, + (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, + (phy_identifier | (1 << 9))); + + return ELINK_STATUS_OK; +} + +static void elink_8727_specific_func(struct elink_phy *phy, + struct elink_params *params, + uint32_t action) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val; + switch (action) { + case ELINK_DISABLE_TX: + elink_sfp_set_transmitter(params, phy, 0); + break; + case ELINK_ENABLE_TX: + if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) + elink_sfp_set_transmitter(params, phy, 1); + break; + case ELINK_PHY_INIT: + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, + (1 << 2) | (1 << 5)); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); + /* Make MOD_ABS give interrupt on change */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val); + val |= (1 << 12); + if (phy->flags & ELINK_FLAGS_NOC) + val |= (3 << 5); + /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 + * status which reflect SFP+ module over-current + */ + if (!(phy->flags & ELINK_FLAGS_NOC)) + val &= 0xff8f; /* Reset bits 4-6 */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, + val); + break; + default: + PMD_DRV_LOG(DEBUG, "Function 0x%x not supported by 8727", + action); + return; + } +} + +static void elink_set_e1e2_module_fault_led(struct elink_params *params, + uint8_t gpio_mode) +{ + struct bnx2x_softc *sc = params->sc; + + uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info. + port_hw_config[params->port]. + sfp_ctrl)) & + PORT_HW_CFG_FAULT_MODULE_LED_MASK; + switch (fault_led_gpio) { + case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: + return; + case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: + case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: + case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: + case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: + { + uint8_t gpio_port = elink_get_gpio_port(params); + uint16_t gpio_pin = fault_led_gpio - + PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; + PMD_DRV_LOG(DEBUG, "Set fault module-detected led " + "pin %x port %x mode %x", + gpio_pin, gpio_port, gpio_mode); + elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); + } + break; + default: + PMD_DRV_LOG(DEBUG, "Error: Invalid fault led mode 0x%x", + fault_led_gpio); + } +} + +static void elink_set_e3_module_fault_led(struct elink_params *params, + uint8_t gpio_mode) +{ + uint32_t pin_cfg; + uint8_t port = params->port; + struct bnx2x_softc *sc = params->sc; + pin_cfg = (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port].e3_sfp_ctrl)) & + PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> + PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; + PMD_DRV_LOG(DEBUG, "Setting Fault LED to %d using pin cfg %d", + gpio_mode, pin_cfg); + elink_set_cfg_pin(sc, pin_cfg, gpio_mode); +} + +static void elink_set_sfp_module_fault_led(struct elink_params *params, + uint8_t gpio_mode) +{ + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "Setting SFP+ module fault LED to %d", gpio_mode); + if (CHIP_IS_E3(sc)) { + /* Low ==> if SFP+ module is supported otherwise + * High ==> if SFP+ module is not on the approved vendor list + */ + elink_set_e3_module_fault_led(params, gpio_mode); + } else + elink_set_e1e2_module_fault_led(params, gpio_mode); +} + +static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + elink_warpcore_power_module(params, 0); + /* Put Warpcore in low power mode */ + REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e); + + /* Put LCPLL in low power mode */ + REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1); + REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0); + REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0); +} + +static void elink_power_sfp_module(struct elink_params *params, + struct elink_phy *phy, uint8_t power) +{ + PMD_DRV_LOG(DEBUG, "Setting SFP+ power to %x", power); + + switch (phy->type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: + elink_8727_power_module(params->sc, phy, power); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: + elink_warpcore_power_module(params, power); + break; + default: + break; + } +} + +static void elink_warpcore_set_limiting_mode(struct elink_params *params, + struct elink_phy *phy, + uint16_t edc_mode) +{ + uint16_t val = 0; + uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; + struct bnx2x_softc *sc = params->sc; + + uint8_t lane = elink_get_warpcore_lane(params); + /* This is a global register which controls all lanes */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); + val &= ~(0xf << (lane << 2)); + + switch (edc_mode) { + case ELINK_EDC_MODE_LINEAR: + case ELINK_EDC_MODE_LIMITING: + mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; + break; + case ELINK_EDC_MODE_PASSIVE_DAC: + case ELINK_EDC_MODE_ACTIVE_DAC: + mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; + break; + default: + break; + } + + val |= (mode << (lane << 2)); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); + /* A must read */ + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); + + /* Restart microcode to re-read the new mode */ + elink_warpcore_reset_lane(sc, phy, 1); + elink_warpcore_reset_lane(sc, phy, 0); + +} + +static void elink_set_limiting_mode(struct elink_params *params, + struct elink_phy *phy, uint16_t edc_mode) +{ + switch (phy->type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: + elink_8726_set_limiting_mode(params->sc, phy, edc_mode); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: + elink_8727_set_limiting_mode(params->sc, phy, edc_mode); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: + elink_warpcore_set_limiting_mode(params, phy, edc_mode); + break; + } +} + +static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t edc_mode; + elink_status_t rc = ELINK_STATUS_OK; + + uint32_t val = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_feature_config[params-> + port]. + config)); + /* Enabled transmitter by default */ + elink_sfp_set_transmitter(params, phy, 1); + PMD_DRV_LOG(DEBUG, "SFP+ module plugged in/out detected on port %d", + params->port); + /* Power up module */ + elink_power_sfp_module(params, phy, 1); + if (elink_get_edc_mode(phy, params, &edc_mode) != 0) { + PMD_DRV_LOG(DEBUG, "Failed to get valid module type"); + return ELINK_STATUS_ERROR; + } else if (elink_verify_sfp_module(phy, params) != 0) { + /* Check SFP+ module compatibility */ + PMD_DRV_LOG(DEBUG, "Module verification failed!!"); + rc = ELINK_STATUS_ERROR; + /* Turn on fault module-detected led */ + elink_set_sfp_module_fault_led(params, + MISC_REGISTERS_GPIO_HIGH); + + /* Check if need to power down the SFP+ module */ + if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == + PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { + PMD_DRV_LOG(DEBUG, "Shutdown SFP+ module!!"); + elink_power_sfp_module(params, phy, 0); + return rc; + } + } else { + /* Turn off fault module-detected led */ + elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); + } + + /* Check and set limiting mode / LRM mode on 8726. On 8727 it + * is done automatically + */ + elink_set_limiting_mode(params, phy, edc_mode); + + /* Disable transmit for this module if the module is not approved, and + * laser needs to be disabled. + */ + if ((rc != 0) && + ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == + PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) + elink_sfp_set_transmitter(params, phy, 0); + + return rc; +} + +void elink_handle_module_detect_int(struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + struct elink_phy *phy; + uint32_t gpio_val; + uint8_t gpio_num, gpio_port; + if (CHIP_IS_E3(sc)) { + phy = ¶ms->phy[ELINK_INT_PHY]; + /* Always enable TX laser,will be disabled in case of fault */ + elink_sfp_set_transmitter(params, phy, 1); + } else { + phy = ¶ms->phy[ELINK_EXT_PHY1]; + } + if (elink_get_mod_abs_int_cfg(sc, params->shmem_base, + params->port, &gpio_num, &gpio_port) == + ELINK_STATUS_ERROR) { + PMD_DRV_LOG(DEBUG, "Failed to get MOD_ABS interrupt config"); + return; + } + + /* Set valid module led off */ + elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); + + /* Get current gpio val reflecting module plugged in / out */ + gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port); + + /* Call the handling function in case module is detected */ + if (gpio_val == 0) { + elink_set_mdio_emac_per_phy(sc, params); + elink_set_aer_mmd(params, phy); + + elink_power_sfp_module(params, phy, 1); + elink_cb_gpio_int_write(sc, gpio_num, + MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, + gpio_port); + if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { + elink_sfp_module_detection(phy, params); + if (CHIP_IS_E3(sc)) { + uint16_t rx_tx_in_reset; + /* In case WC is out of reset, reconfigure the + * link speed while taking into account 1G + * module limitation. + */ + elink_cl45_read(sc, phy, + MDIO_WC_DEVAD, + MDIO_WC_REG_DIGITAL5_MISC6, + &rx_tx_in_reset); + if ((!rx_tx_in_reset) && + (params->link_flags & + ELINK_PHY_INITIALIZED)) { + elink_warpcore_reset_lane(sc, phy, 1); + elink_warpcore_config_sfi(phy, params); + elink_warpcore_reset_lane(sc, phy, 0); + } + } + } else { + PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized"); + } + } else { + elink_cb_gpio_int_write(sc, gpio_num, + MISC_REGISTERS_GPIO_INT_OUTPUT_SET, + gpio_port); + /* Module was plugged out. + * Disable transmit for this module + */ + phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; + } +} + +/******************************************************************/ +/* Used by 8706 and 8727 */ +/******************************************************************/ +static void elink_sfp_mask_fault(struct bnx2x_softc *sc, + struct elink_phy *phy, + uint16_t alarm_status_offset, + uint16_t alarm_ctrl_offset) +{ + uint16_t alarm_status, val; + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status); + /* Mask or enable the fault event. */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); + if (alarm_status & (1 << 0)) + val &= ~(1 << 0); + else + val |= (1 << 0); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); +} + +/******************************************************************/ +/* common BNX2X8706/BNX2X8726 PHY SECTION */ +/******************************************************************/ +static uint8_t elink_8706_8726_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + uint8_t link_up = 0; + uint16_t val1, val2, rx_sd, pcs_status; + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "XGXS 8706/8726"); + /* Clear RX Alarm */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); + + elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, + MDIO_PMA_LASI_TXCTRL); + + /* Clear LASI indication */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); + PMD_DRV_LOG(DEBUG, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); + elink_cl45_read(sc, phy, + MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); + + PMD_DRV_LOG(DEBUG, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" + " link_status 0x%x", rx_sd, pcs_status, val2); + /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status + * are set, or if the autoneg bit 1 is set + */ + link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1))); + if (link_up) { + if (val2 & (1 << 1)) + vars->line_speed = ELINK_SPEED_1000; + else + vars->line_speed = ELINK_SPEED_10000; + elink_ext_phy_resolve_fc(phy, params, vars); + vars->duplex = DUPLEX_FULL; + } + + /* Capture 10G link fault. Read twice to clear stale value. */ + if (vars->line_speed == ELINK_SPEED_10000) { + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_LASI_TXSTAT, &val1); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_LASI_TXSTAT, &val1); + if (val1 & (1 << 0)) + vars->fault_detected = 1; + } + + return link_up; +} + +/******************************************************************/ +/* BNX2X8706 PHY SECTION */ +/******************************************************************/ +static uint8_t elink_8706_config_init(struct elink_phy *phy, + struct elink_params *params, + __rte_unused struct elink_vars *vars) +{ + uint32_t tx_en_mode; + uint16_t cnt, val, tmp1; + struct bnx2x_softc *sc = params->sc; + + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + /* HW reset */ + elink_ext_phy_hw_reset(sc, params->port); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); + elink_wait_reset_complete(sc, phy, params); + + /* Wait until fw is loaded */ + for (cnt = 0; cnt < 100; cnt++) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); + if (val) + break; + DELAY(1000 * 10); + } + PMD_DRV_LOG(DEBUG, "XGXS 8706 is initialized after %d ms", cnt); + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { + uint8_t i; + uint16_t reg; + for (i = 0; i < 4; i++) { + reg = MDIO_XS_8706_REG_BANK_RX0 + + i * (MDIO_XS_8706_REG_BANK_RX1 - + MDIO_XS_8706_REG_BANK_RX0); + elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val); + /* Clear first 3 bits of the control */ + val &= ~0x7; + /* Set control bits according to configuration */ + val |= (phy->rx_preemphasis[i] & 0x7); + PMD_DRV_LOG(DEBUG, "Setting RX Equalizer to BNX2X8706" + " reg 0x%x <-- val 0x%x", reg, val); + elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val); + } + } + /* Force speed */ + if (phy->req_line_speed == ELINK_SPEED_10000) { + PMD_DRV_LOG(DEBUG, "XGXS 8706 force 10Gbps"); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_DIGITAL_CTRL, 0x400); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0); + /* Arm LASI for link and Tx fault. */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); + } else { + /* Force 1Gbps using autoneg with 1G advertisement */ + + /* Allow CL37 through CL73 */ + PMD_DRV_LOG(DEBUG, "XGXS 8706 AutoNeg"); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); + + /* Enable Full-Duplex advertisement on CL37 */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); + /* Enable CL37 AN */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); + /* 1G support */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5)); + + /* Enable clause 73 AN */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); + } + elink_save_bnx2x_spirom_ver(sc, phy, params->port); + + /* If TX Laser is controlled by GPIO_0, do not let PHY go into low + * power mode, if TX Laser is disabled + */ + + tx_en_mode = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + sfp_ctrl)) + & PORT_HW_CFG_TX_LASER_MASK; + + if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { + PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS"); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, + &tmp1); + tmp1 |= 0x1; + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, + tmp1); + } + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_8706_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + return elink_8706_8726_read_status(phy, params, vars); +} + +/******************************************************************/ +/* BNX2X8726 PHY SECTION */ +/******************************************************************/ +static void elink_8726_config_loopback(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "PMA/PMD ext_phy_loopback: 8726"); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); +} + +static void elink_8726_external_rom_boot(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + /* Need to wait 100ms after reset */ + DELAY(1000 * 100); + + /* Micro controller re-boot */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); + + /* Set soft reset */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, + MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, + MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); + + /* Wait for 150ms for microcode load */ + DELAY(1000 * 150); + + /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000); + + DELAY(1000 * 200); + elink_save_bnx2x_spirom_ver(sc, phy, params->port); +} + +static uint8_t elink_8726_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val1; + uint8_t link_up = elink_8706_8726_read_status(phy, params, vars); + if (link_up) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, + &val1); + if (val1 & (1 << 15)) { + PMD_DRV_LOG(DEBUG, "Tx is disabled"); + link_up = 0; + vars->line_speed = 0; + } + } + return link_up; +} + +static elink_status_t elink_8726_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726"); + + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); + elink_wait_reset_complete(sc, phy, params); + + elink_8726_external_rom_boot(phy, params); + + /* Need to call module detected on initialization since the module + * detection triggered by actual module insertion might occur before + * driver is loaded, and when driver is loaded, it reset all + * registers, including the transmitter + */ + elink_sfp_module_detection(phy, params); + + if (phy->req_line_speed == ELINK_SPEED_1000) { + PMD_DRV_LOG(DEBUG, "Setting 1G force"); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400); + } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && + ((phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { + PMD_DRV_LOG(DEBUG, "Setting 1G clause37"); + /* Set Flow control */ + elink_ext_phy_set_pause(params, phy, vars); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); + /* Enable RX-ALARM control to receive interrupt for 1G speed + * change + */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400); + + } else { /* Default 10G. Set only LASI control */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); + } + + /* Set TX PreEmphasis if needed */ + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { + PMD_DRV_LOG(DEBUG, + "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", + phy->tx_preemphasis[0], phy->tx_preemphasis[1]); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8726_TX_CTRL1, + phy->tx_preemphasis[0]); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8726_TX_CTRL2, + phy->tx_preemphasis[1]); + } + + return ELINK_STATUS_OK; + +} + +static void elink_8726_link_reset(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "elink_8726_link_reset port %d", params->port); + /* Set serial boot control for external load */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); +} + +/******************************************************************/ +/* BNX2X8727 PHY SECTION */ +/******************************************************************/ + +static void elink_8727_set_link_led(struct elink_phy *phy, + struct elink_params *params, uint8_t mode) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t led_mode_bitmask = 0; + uint16_t gpio_pins_bitmask = 0; + uint16_t val; + /* Only NOC flavor requires to set the LED specifically */ + if (!(phy->flags & ELINK_FLAGS_NOC)) + return; + switch (mode) { + case ELINK_LED_MODE_FRONT_PANEL_OFF: + case ELINK_LED_MODE_OFF: + led_mode_bitmask = 0; + gpio_pins_bitmask = 0x03; + break; + case ELINK_LED_MODE_ON: + led_mode_bitmask = 0; + gpio_pins_bitmask = 0x02; + break; + case ELINK_LED_MODE_OPER: + led_mode_bitmask = 0x60; + gpio_pins_bitmask = 0x11; + break; + } + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val); + val &= 0xff8f; + val |= led_mode_bitmask; + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val); + val &= 0xffe0; + val |= gpio_pins_bitmask; + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val); +} + +static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) +{ + uint32_t swap_val, swap_override; + uint8_t port; + /* The PHY reset is controlled by GPIO 1. Fake the port number + * to cancel the swap done in set_gpio() + */ + struct bnx2x_softc *sc = params->sc; + swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); + swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); + port = (swap_val && swap_override) ^ 1; + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); +} + +static void elink_8727_config_speed(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t tmp1, val; + /* Set option 1G speed */ + if ((phy->req_line_speed == ELINK_SPEED_1000) || + (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { + PMD_DRV_LOG(DEBUG, "Setting 1G force"); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); + PMD_DRV_LOG(DEBUG, "1.7 = 0x%x", tmp1); + /* Power down the XAUI until link is up in case of dual-media + * and 1G + */ + if (ELINK_DUAL_MEDIA(params)) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_PCS_GP, &val); + val |= (3 << 10); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_PCS_GP, val); + } + } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + ((phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && + ((phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { + + PMD_DRV_LOG(DEBUG, "Setting 1G clause37"); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); + } else { + /* Since the 8727 has only single reset pin, need to set the 10G + * registers although it is default + */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, + 0x0020); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, + 0x0008); + } +} + +static elink_status_t elink_8727_config_init(struct elink_phy *phy, + struct elink_params *params, + __rte_unused struct elink_vars + *vars) +{ + uint32_t tx_en_mode; + uint16_t tmp1, mod_abs, tmp2; + struct bnx2x_softc *sc = params->sc; + /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ + + elink_wait_reset_complete(sc, phy, params); + + PMD_DRV_LOG(DEBUG, "Initializing BNX2X8727"); + + elink_8727_specific_func(phy, params, ELINK_PHY_INIT); + /* Initially configure MOD_ABS to interrupt when module is + * presence( bit 8) + */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); + /* Set EDC off by setting OPTXLOS signal input to low (bit 9). + * When the EDC is off it locks onto a reference clock and avoids + * becoming 'lost' + */ + mod_abs &= ~(1 << 8); + if (!(phy->flags & ELINK_FLAGS_NOC)) + mod_abs &= ~(1 << 9); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); + + /* Enable/Disable PHY transmitter output */ + elink_set_disable_pmd_transmit(params, phy, 0); + + elink_8727_power_module(sc, phy, 1); + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); + + elink_8727_config_speed(phy, params); + + /* Set TX PreEmphasis if needed */ + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { + PMD_DRV_LOG(DEBUG, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", + phy->tx_preemphasis[0], phy->tx_preemphasis[1]); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, + phy->tx_preemphasis[0]); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, + phy->tx_preemphasis[1]); + } + + /* If TX Laser is controlled by GPIO_0, do not let PHY go into low + * power mode, if TX Laser is disabled + */ + tx_en_mode = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + sfp_ctrl)) + & PORT_HW_CFG_TX_LASER_MASK; + + if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { + + PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS"); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, + &tmp2); + tmp2 |= 0x1000; + tmp2 &= 0xFFEF; + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, + tmp2); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff)); + } + + return ELINK_STATUS_OK; +} + +static void elink_8727_handle_mod_abs(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t mod_abs, rx_alarm_status; + uint32_t val = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_feature_config[params-> + port].config)); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, + &mod_abs); + if (mod_abs & (1 << 8)) { + + /* Module is absent */ + PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is absent"); + phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; + /* 1. Set mod_abs to detect next module + * presence event + * 2. Set EDC off by setting OPTXLOS signal input to low + * (bit 9). + * When the EDC is off it locks onto a reference clock and + * avoids becoming 'lost'. + */ + mod_abs &= ~(1 << 8); + if (!(phy->flags & ELINK_FLAGS_NOC)) + mod_abs &= ~(1 << 9); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); + + /* Clear RX alarm since it stays up as long as + * the mod_abs wasn't changed + */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); + + } else { + /* Module is present */ + PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is present"); + /* First disable transmitter, and if the module is ok, the + * module_detection will enable it + * 1. Set mod_abs to detect next module absent event ( bit 8) + * 2. Restore the default polarity of the OPRXLOS signal and + * this signal will then correctly indicate the presence or + * absence of the Rx signal. (bit 9) + */ + mod_abs |= (1 << 8); + if (!(phy->flags & ELINK_FLAGS_NOC)) + mod_abs |= (1 << 9); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); + + /* Clear RX alarm since it stays up as long as the mod_abs + * wasn't changed. This is need to be done before calling the + * module detection, otherwise it will clear* the link update + * alarm + */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); + + if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == + PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) + elink_sfp_set_transmitter(params, phy, 0); + + if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { + elink_sfp_module_detection(phy, params); + } else { + PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized"); + } + + /* Reconfigure link speed based on module type limitations */ + elink_8727_config_speed(phy, params); + } + + PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status); + /* No need to check link status in case of module plugged in/out */ +} + +static uint8_t elink_8727_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t link_up = 0, oc_port = params->port; + uint16_t link_status = 0; + uint16_t rx_alarm_status, lasi_ctrl, val1; + + /* If PHY is not initialized, do not check link status */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl); + if (!lasi_ctrl) + return 0; + + /* Check the LASI on Rx */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); + vars->line_speed = 0; + PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status); + + elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, + MDIO_PMA_LASI_TXCTRL); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + + PMD_DRV_LOG(DEBUG, "8727 LASI status 0x%x", val1); + + /* Clear MSG-OUT */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); + + /* If a module is present and there is need to check + * for over current + */ + if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) { + /* Check over-current using 8727 GPIO0 input */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, + &val1); + + if ((val1 & (1 << 8)) == 0) { + if (!CHIP_IS_E1x(sc)) + oc_port = SC_PATH(sc) + (params->port << 1); + PMD_DRV_LOG(DEBUG, + "8727 Power fault has been detected on port %d", + oc_port); + elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has " + // "been detected and the power to " + // "that SFP+ module has been removed " + // "to prevent failure of the card. " + // "Please remove the SFP+ module and " + // "restart the system to clear this " + // "error.", + /* Disable all RX_ALARMs except for mod_abs */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_LASI_RXCTRL, (1 << 5)); + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, &val1); + /* Wait for module_absent_event */ + val1 |= (1 << 8); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, val1); + /* Clear RX alarm */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); + elink_8727_power_module(params->sc, phy, 0); + return 0; + } + } + + /* Over current check */ + /* When module absent bit is set, check module */ + if (rx_alarm_status & (1 << 5)) { + elink_8727_handle_mod_abs(phy, params); + /* Enable all mod_abs and link detection bits */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, + ((1 << 5) | (1 << 2))); + } + + if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { + PMD_DRV_LOG(DEBUG, "Enabling 8727 TX laser"); + elink_sfp_set_transmitter(params, phy, 1); + } else { + PMD_DRV_LOG(DEBUG, "Tx is disabled"); + return 0; + } + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); + + /* Bits 0..2 --> speed detected, + * Bits 13..15--> link is down + */ + if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) { + link_up = 1; + vars->line_speed = ELINK_SPEED_10000; + PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G", + params->port); + } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) { + link_up = 1; + vars->line_speed = ELINK_SPEED_1000; + PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G", + params->port); + } else { + link_up = 0; + PMD_DRV_LOG(DEBUG, "port %x: External link is down", + params->port); + } + + /* Capture 10G link fault. */ + if (vars->line_speed == ELINK_SPEED_10000) { + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_LASI_TXSTAT, &val1); + + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, + MDIO_PMA_LASI_TXSTAT, &val1); + + if (val1 & (1 << 0)) { + vars->fault_detected = 1; + } + } + + if (link_up) { + elink_ext_phy_resolve_fc(phy, params, vars); + vars->duplex = DUPLEX_FULL; + PMD_DRV_LOG(DEBUG, "duplex = 0x%x", vars->duplex); + } + + if ((ELINK_DUAL_MEDIA(params)) && + (phy->req_line_speed == ELINK_SPEED_1000)) { + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_PCS_GP, &val1); + /* In case of dual-media board and 1G, power up the XAUI side, + * otherwise power it down. For 10G it is done automatically + */ + if (link_up) + val1 &= ~(3 << 10); + else + val1 |= (3 << 10); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_PCS_GP, val1); + } + return link_up; +} + +static void elink_8727_link_reset(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + + /* Enable/Disable PHY transmitter output */ + elink_set_disable_pmd_transmit(params, phy, 1); + + /* Disable Transmitter */ + elink_sfp_set_transmitter(params, phy, 0); + /* Clear LASI */ + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); + +} + +/******************************************************************/ +/* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */ +/******************************************************************/ +static void elink_save_848xx_spirom_version(struct elink_phy *phy, + struct bnx2x_softc *sc, uint8_t port) +{ + uint16_t val, fw_ver2, cnt, i; + static struct elink_reg_set reg_set[] = { + {MDIO_PMA_DEVAD, 0xA819, 0x0014}, + {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, + {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, + {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, + {MDIO_PMA_DEVAD, 0xA817, 0x0009} + }; + uint16_t fw_ver1; + + if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); + elink_save_spirom_version(sc, port, fw_ver1 & 0xfff, + phy->ver_addr); + } else { + /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ + /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ + for (i = 0; i < ARRAY_SIZE(reg_set); i++) + elink_cl45_write(sc, phy, reg_set[i].devad, + reg_set[i].reg, reg_set[i].val); + + for (cnt = 0; cnt < 100; cnt++) { + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val); + if (val & 1) + break; + DELAY(5); + } + if (cnt == 100) { + PMD_DRV_LOG(DEBUG, "Unable to read 848xx " + "phy fw version(1)"); + elink_save_spirom_version(sc, port, 0, phy->ver_addr); + return; + } + + /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); + for (cnt = 0; cnt < 100; cnt++) { + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val); + if (val & 1) + break; + DELAY(5); + } + if (cnt == 100) { + PMD_DRV_LOG(DEBUG, "Unable to read 848xx phy fw " + "version(2)"); + elink_save_spirom_version(sc, port, 0, phy->ver_addr); + return; + } + + /* lower 16 bits of the register SPI_FW_STATUS */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); + /* upper 16 bits of register SPI_FW_STATUS */ + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); + + elink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1, + phy->ver_addr); + } + +} + +static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy) +{ + uint16_t val, offset, i; + static struct elink_reg_set reg_set[] = { + {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, + {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, + {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, + {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, + {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, + MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, + {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} + }; + /* PHYC_CTL_LED_CTL */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + val &= 0xFE00; + val |= 0x0092; + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val); + + for (i = 0; i < ARRAY_SIZE(reg_set); i++) + elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, + reg_set[i].val); + + if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) + offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; + else + offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; + + /* stretch_en for LED3 */ + elink_cl45_read_or_write(sc, phy, + MDIO_PMA_DEVAD, offset, + MDIO_PMA_REG_84823_LED3_STRETCH_EN); +} + +static void elink_848xx_specific_func(struct elink_phy *phy, + struct elink_params *params, + uint32_t action) +{ + struct bnx2x_softc *sc = params->sc; + switch (action) { + case ELINK_PHY_INIT: + if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && + (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + /* Save spirom version */ + elink_save_848xx_spirom_version(phy, sc, params->port); + } + /* This phy uses the NIG latch mechanism since link indication + * arrives through its LED4 and not via its LASI signal, so we + * get steady signal instead of clear on read + */ + elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4, + 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); + + elink_848xx_set_led(sc, phy); + break; + } +} + +static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t autoneg_val, an_1000_val, an_10_100_val; + + elink_848xx_specific_func(phy, params, ELINK_PHY_INIT); + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); + + /* set 1000 speed advertisement */ + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, + &an_1000_val); + + elink_ext_phy_set_pause(params, phy, vars); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, + &autoneg_val); + /* Disable forced speed */ + autoneg_val &= + ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13)); + an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8)); + + if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || + (phy->req_line_speed == ELINK_SPEED_1000)) { + an_1000_val |= (1 << 8); + autoneg_val |= (1 << 9 | 1 << 12); + if (phy->req_duplex == DUPLEX_FULL) + an_1000_val |= (1 << 9); + PMD_DRV_LOG(DEBUG, "Advertising 1G"); + } else + an_1000_val &= ~((1 << 8) | (1 << 9)); + + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, + an_1000_val); + + /* Set 10/100 speed advertisement */ + if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { + /* Enable autoneg and restart autoneg for legacy speeds + */ + autoneg_val |= (1 << 9 | 1 << 12); + an_10_100_val |= (1 << 8); + PMD_DRV_LOG(DEBUG, "Advertising 100M-FD"); + } + + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { + /* Enable autoneg and restart autoneg for legacy speeds + */ + autoneg_val |= (1 << 9 | 1 << 12); + an_10_100_val |= (1 << 7); + PMD_DRV_LOG(DEBUG, "Advertising 100M-HD"); + } + + if ((phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && + (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { + an_10_100_val |= (1 << 6); + autoneg_val |= (1 << 9 | 1 << 12); + PMD_DRV_LOG(DEBUG, "Advertising 10M-FD"); + } + + if ((phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && + (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { + an_10_100_val |= (1 << 5); + autoneg_val |= (1 << 9 | 1 << 12); + PMD_DRV_LOG(DEBUG, "Advertising 10M-HD"); + } + } + + /* Only 10/100 are allowed to work in FORCE mode */ + if ((phy->req_line_speed == ELINK_SPEED_100) && + (phy->supported & + (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) { + autoneg_val |= (1 << 13); + /* Enabled AUTO-MDIX when autoneg is disabled */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, + (1 << 15 | 1 << 9 | 7 << 0)); + /* The PHY needs this set even for forced link. */ + an_10_100_val |= (1 << 8) | (1 << 7); + PMD_DRV_LOG(DEBUG, "Setting 100M force"); + } + if ((phy->req_line_speed == ELINK_SPEED_10) && + (phy->supported & + (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) { + /* Enabled AUTO-MDIX when autoneg is disabled */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, + (1 << 15 | 1 << 9 | 7 << 0)); + PMD_DRV_LOG(DEBUG, "Setting 10M force"); + } + + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, + an_10_100_val); + + if (phy->req_duplex == DUPLEX_FULL) + autoneg_val |= (1 << 8); + + /* Always write this if this is not 84833/4. + * For 84833/4, write it only when it's a forced speed. + */ + if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && + (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) || + ((autoneg_val & (1 << 12)) == 0)) + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); + + if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || + (phy->req_line_speed == ELINK_SPEED_10000)) { + PMD_DRV_LOG(DEBUG, "Advertising 10G"); + /* Restart autoneg for 10G */ + + elink_cl45_read_or_write(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, + 0x1000); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200); + } else + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1); + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_8481_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + /* Restore normal power mode */ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + + /* HW reset */ + elink_ext_phy_hw_reset(sc, params->port); + elink_wait_reset_complete(sc, phy, params); + + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); + return elink_848xx_cmn_config_init(phy, params, vars); +} + +#define PHY84833_CMDHDLR_WAIT 300 +#define PHY84833_CMDHDLR_MAX_ARGS 5 +static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, + struct elink_params *params, + uint16_t fw_cmd, uint16_t cmd_args[], + int argc) +{ + int idx; + uint16_t val; + struct bnx2x_softc *sc = params->sc; + /* Write CMD_OPEN_OVERRIDE to STATUS reg */ + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_CMD_HDLR_STATUS, + PHY84833_STATUS_CMD_OPEN_OVERRIDE); + for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_CMD_HDLR_STATUS, &val); + if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) + break; + DELAY(1000 * 1); + } + if (idx >= PHY84833_CMDHDLR_WAIT) { + PMD_DRV_LOG(DEBUG, "FW cmd: FW not ready."); + return ELINK_STATUS_ERROR; + } + + /* Prepare argument(s) and issue command */ + for (idx = 0; idx < argc; idx++) { + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_CMD_HDLR_DATA1 + idx, + cmd_args[idx]); + } + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); + for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_CMD_HDLR_STATUS, &val); + if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || + (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) + break; + DELAY(1000 * 1); + } + if ((idx >= PHY84833_CMDHDLR_WAIT) || + (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { + PMD_DRV_LOG(DEBUG, "FW cmd failed."); + return ELINK_STATUS_ERROR; + } + /* Gather returning data */ + for (idx = 0; idx < argc; idx++) { + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_CMD_HDLR_DATA1 + idx, + &cmd_args[idx]); + } + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_CMD_HDLR_STATUS, + PHY84833_STATUS_CMD_CLEAR_COMPLETE); + return ELINK_STATUS_OK; +} + +static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy, + struct elink_params *params, + __rte_unused struct elink_vars + *vars) +{ + uint32_t pair_swap; + uint16_t data[PHY84833_CMDHDLR_MAX_ARGS]; + elink_status_t status; + struct bnx2x_softc *sc = params->sc; + + /* Check for configuration. */ + pair_swap = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + xgbt_phy_cfg)) & + PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; + + if (pair_swap == 0) + return ELINK_STATUS_OK; + + /* Only the second argument is used for this command */ + data[1] = (uint16_t) pair_swap; + + status = elink_84833_cmd_hdlr(phy, params, + PHY84833_CMD_SET_PAIR_SWAP, data, + PHY84833_CMDHDLR_MAX_ARGS); + if (status == ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "Pairswap OK, val=0x%x", data[1]); + } + + return status; +} + +static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc, + uint32_t shmem_base_path[], + __rte_unused uint32_t chip_id) +{ + uint32_t reset_pin[2]; + uint32_t idx; + uint8_t reset_gpios; + if (CHIP_IS_E3(sc)) { + /* Assume that these will be GPIOs, not EPIOs. */ + for (idx = 0; idx < 2; idx++) { + /* Map config param to register bit. */ + reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + + offsetof(struct shmem_region, + dev_info. + port_hw_config[0]. + e3_cmn_pin_cfg)); + reset_pin[idx] = + (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >> + PORT_HW_CFG_E3_PHY_RESET_SHIFT; + reset_pin[idx] -= PIN_CFG_GPIO0_P0; + reset_pin[idx] = (1 << reset_pin[idx]); + } + reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]); + } else { + /* E2, look from diff place of shmem. */ + for (idx = 0; idx < 2; idx++) { + reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + + offsetof(struct shmem_region, + dev_info. + port_hw_config[0]. + default_cfg)); + reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; + reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; + reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; + reset_pin[idx] = (1 << reset_pin[idx]); + } + reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]); + } + + return reset_gpios; +} + +static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t reset_gpios; + uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base + + offsetof(struct shmem2_region, + other_shmem_base_addr)); + + uint32_t shmem_base_path[2]; + + /* Work around for 84833 LED failure inside RESET status */ + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_8481_LEGACY_MII_CTRL, + MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_8481_1G_100T_EXT_CTRL, + MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); + + shmem_base_path[0] = params->shmem_base; + shmem_base_path[1] = other_shmem_base_addr; + + reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, + params->chip_id); + + elink_cb_gpio_mult_write(sc, reset_gpios, + MISC_REGISTERS_GPIO_OUTPUT_LOW); + DELAY(10); + PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios); + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + elink_status_t rc; + uint16_t cmd_args = 0; + + PMD_DRV_LOG(DEBUG, "Don't Advertise 10GBase-T EEE"); + + /* Prevent Phy from working in EEE and advertising it */ + rc = elink_84833_cmd_hdlr(phy, params, + PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); + if (rc != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "EEE disable failed."); + return rc; + } + + return elink_eee_disable(phy, params, vars); +} + +static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + elink_status_t rc; + uint16_t cmd_args = 1; + + rc = elink_84833_cmd_hdlr(phy, params, + PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); + if (rc != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "EEE enable failed."); + return rc; + } + + return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); +} + +#define PHY84833_CONSTANT_LATENCY 1193 +static elink_status_t elink_848x3_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port, initialize = 1; + uint16_t val; + uint32_t actual_phy_selection; + uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; + elink_status_t rc = ELINK_STATUS_OK; + + DELAY(1000 * 1); + + if (!(CHIP_IS_E1x(sc))) + port = SC_PATH(sc); + else + port = params->port; + + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); + } else { + /* MDIO reset */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000); + } + + elink_wait_reset_complete(sc, phy, params); + + /* Wait for GPHY to come out of reset */ + DELAY(1000 * 50); + if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && + (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + /* BNX2X84823 requires that XGXS links up first @ 10G for normal + * behavior. + */ + uint16_t temp; + temp = vars->line_speed; + vars->line_speed = ELINK_SPEED_10000; + elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0); + elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); + vars->line_speed = temp; + } + + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_CTL_REG_84823_MEDIA, &val); + val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | + MDIO_CTL_REG_84823_MEDIA_LINE_MASK | + MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | + MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | + MDIO_CTL_REG_84823_MEDIA_FIBER_1G); + + if (CHIP_IS_E3(sc)) { + val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | + MDIO_CTL_REG_84823_MEDIA_LINE_MASK); + } else { + val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | + MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); + } + + actual_phy_selection = elink_phy_selection(params); + + switch (actual_phy_selection) { + case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: + /* Do nothing. Essentially this is like the priority copper */ + break; + case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: + val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; + break; + case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: + val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; + break; + case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: + /* Do nothing here. The first PHY won't be initialized at all */ + break; + case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: + val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; + initialize = 0; + break; + } + if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000) + val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; + + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_CTL_REG_84823_MEDIA, val); + PMD_DRV_LOG(DEBUG, "Multi_phy config = 0x%x, Media control = 0x%x", + params->multi_phy_config, val); + + if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + elink_84833_pair_swap_cfg(phy, params, vars); + + /* Keep AutogrEEEn disabled. */ + cmd_args[0] = 0x0; + cmd_args[1] = 0x0; + cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; + cmd_args[3] = PHY84833_CONSTANT_LATENCY; + rc = elink_84833_cmd_hdlr(phy, params, + PHY84833_CMD_SET_EEE_MODE, cmd_args, + PHY84833_CMDHDLR_MAX_ARGS); + if (rc != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "Cfg AutogrEEEn failed."); + } + } + if (initialize) { + rc = elink_848xx_cmn_config_init(phy, params, vars); + } else { + elink_save_848xx_spirom_version(phy, sc, params->port); + } + /* 84833 PHY has a better feature and doesn't need to support this. */ + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { + uint32_t cms_enable = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info. + port_hw_config[params-> + port]. + default_cfg)) & + PORT_HW_CFG_ENABLE_CMS_MASK; + + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_CTL_REG_84823_USER_CTRL_REG, &val); + if (cms_enable) + val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; + else + val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_CTL_REG_84823_USER_CTRL_REG, val); + } + + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_84833_TOP_CFG_FW_REV, &val); + + /* Configure EEE support */ + if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && + (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && + elink_eee_has_cap(params)) { + rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); + if (rc != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers"); + elink_8483x_disable_eee(phy, params, vars); + return rc; + } + + if ((phy->req_duplex == DUPLEX_FULL) && + (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && + (elink_eee_calc_timer(params) || + !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) + rc = elink_8483x_enable_eee(phy, params, vars); + else + rc = elink_8483x_disable_eee(phy, params, vars); + if (rc != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "Failed to set EEE advertisement"); + return rc; + } + } else { + vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; + } + + if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + /* Bring PHY out of super isolate mode as the final step. */ + elink_cl45_read_and_write(sc, phy, + MDIO_CTL_DEVAD, + MDIO_84833_TOP_CFG_XGPHY_STRAP1, + (uint16_t) ~ + MDIO_84833_SUPER_ISOLATE); + } + return rc; +} + +static uint8_t elink_848xx_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val, val1, val2; + uint8_t link_up = 0; + + /* Check 10G-BaseT link status */ + /* Check PMD signal ok */ + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2); + PMD_DRV_LOG(DEBUG, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2); + + /* Check link 10G */ + if (val2 & (1 << 11)) { + vars->line_speed = ELINK_SPEED_10000; + vars->duplex = DUPLEX_FULL; + link_up = 1; + elink_ext_phy_10G_an_resolve(sc, phy, vars); + } else { /* Check Legacy speed link */ + uint16_t legacy_status, legacy_speed, mii_ctrl; + + /* Enable expansion register 0x42 (Operation mode status) */ + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); + + /* Get legacy speed operation status */ + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, + &legacy_status); + + PMD_DRV_LOG(DEBUG, "Legacy speed status = 0x%x", legacy_status); + link_up = ((legacy_status & (1 << 11)) == (1 << 11)); + legacy_speed = (legacy_status & (3 << 9)); + if (legacy_speed == (0 << 9)) + vars->line_speed = ELINK_SPEED_10; + else if (legacy_speed == (1 << 9)) + vars->line_speed = ELINK_SPEED_100; + else if (legacy_speed == (2 << 9)) + vars->line_speed = ELINK_SPEED_1000; + else { /* Should not happen: Treat as link down */ + vars->line_speed = 0; + link_up = 0; + } + + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_LEGACY_MII_CTRL, + &mii_ctrl); + /* For IEEE testing, check for a fake link. */ + link_up |= ((mii_ctrl & 0x3040) == 0x40); + } + + if (link_up) { + if (legacy_status & (1 << 8)) + vars->duplex = DUPLEX_FULL; + else + vars->duplex = DUPLEX_HALF; + + PMD_DRV_LOG(DEBUG, + "Link is up in %dMbps, is_duplex_full= %d", + vars->line_speed, + (vars->duplex == DUPLEX_FULL)); + /* Check legacy speed AN resolution */ + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_LEGACY_MII_STATUS, + &val); + if (val & (1 << 5)) + vars->link_status |= + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, + &val); + if ((val & (1 << 0)) == 0) + vars->link_status |= + LINK_STATUS_PARALLEL_DETECTION_USED; + } + } + if (link_up) { + PMD_DRV_LOG(DEBUG, "BNX2X848x3: link speed is %d", + vars->line_speed); + elink_ext_phy_resolve_fc(phy, params, vars); + + /* Read LP advertised speeds */ + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LP, &val); + if (val & (1 << 5)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; + if (val & (1 << 6)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; + if (val & (1 << 7)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; + if (val & (1 << 8)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; + if (val & (1 << 9)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; + + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_1000T_STATUS, &val); + + if (val & (1 << 10)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; + if (val & (1 << 11)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_MASTER_STATUS, &val); + + if (val & (1 << 11)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + + /* Determine if EEE was negotiated */ + if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) + elink_eee_an_resolve(phy, params, vars); + } + + return link_up; +} + +static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str, + uint16_t * len) +{ + elink_status_t status = ELINK_STATUS_OK; + uint32_t spirom_ver; + spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); + status = elink_format_ver(spirom_ver, str, len); + return status; +} + +static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) +{ + elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); + elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); +} + +static void elink_8481_link_reset(struct elink_phy *phy, + struct elink_params *params) +{ + elink_cl45_write(params->sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); + elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); +} + +static void elink_848x3_link_reset(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port; + uint16_t val16; + + if (!(CHIP_IS_E1x(sc))) + port = SC_PATH(sc); + else + port = params->port; + + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + } else { + elink_cl45_read(sc, phy, + MDIO_CTL_DEVAD, + MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); + val16 |= MDIO_84833_SUPER_ISOLATE; + elink_cl45_write(sc, phy, + MDIO_CTL_DEVAD, + MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); + } +} + +static void elink_848xx_set_link_led(struct elink_phy *phy, + struct elink_params *params, uint8_t mode) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val; + __rte_unused uint8_t port; + + if (!(CHIP_IS_E1x(sc))) + port = SC_PATH(sc); + else + port = params->port; + + switch (mode) { + case ELINK_LED_MODE_OFF: + + PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OFF", port); + + if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == + SHARED_HW_CFG_LED_EXTPHY1) { + + /* Set LED masks */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, 0x0); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED2_MASK, 0x0); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED3_MASK, 0x0); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED5_MASK, 0x0); + + } else { + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, 0x0); + } + break; + case ELINK_LED_MODE_FRONT_PANEL_OFF: + + PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE FRONT PANEL OFF", port); + + if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == + SHARED_HW_CFG_LED_EXTPHY1) { + + /* Set LED masks */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, 0x0); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED2_MASK, 0x0); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED3_MASK, 0x0); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED5_MASK, 0x20); + + } else { + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, 0x0); + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { + /* Disable MI_INT interrupt before setting LED4 + * source to constant off. + */ + if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + + params->port * 4) & + ELINK_NIG_MASK_MI_INT) { + params->link_flags |= + ELINK_LINK_FLAGS_INT_DISABLED; + + elink_bits_dis(sc, + NIG_REG_MASK_INTERRUPT_PORT0 + + params->port * 4, + ELINK_NIG_MASK_MI_INT); + } + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_SIGNAL_MASK, + 0x0); + } + } + break; + case ELINK_LED_MODE_ON: + + PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE ON", port); + + if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == + SHARED_HW_CFG_LED_EXTPHY1) { + /* Set control reg */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + val &= 0x8000; + val |= 0x2492; + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, val); + + /* Set LED masks */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, 0x0); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED2_MASK, 0x20); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED3_MASK, 0x20); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED5_MASK, 0x0); + } else { + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, 0x20); + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { + /* Disable MI_INT interrupt before setting LED4 + * source to constant on. + */ + if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + + params->port * 4) & + ELINK_NIG_MASK_MI_INT) { + params->link_flags |= + ELINK_LINK_FLAGS_INT_DISABLED; + + elink_bits_dis(sc, + NIG_REG_MASK_INTERRUPT_PORT0 + + params->port * 4, + ELINK_NIG_MASK_MI_INT); + } + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_SIGNAL_MASK, + 0x20); + } + } + break; + + case ELINK_LED_MODE_OPER: + + PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OPER", port); + + if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == + SHARED_HW_CFG_LED_EXTPHY1) { + + /* Set control reg */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + + if (!((val & + MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) + >> + MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) + { + PMD_DRV_LOG(DEBUG, "Setting LINK_SIGNAL"); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, + 0xa492); + } + + /* Set LED masks */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, 0x10); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED2_MASK, 0x80); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED3_MASK, 0x98); + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED5_MASK, 0x40); + + } else { + /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED + * sources are all wired through LED1, rather than only + * 10G in other modes. + */ + val = ((params->hw_led_mode << + SHARED_HW_CFG_LED_MODE_SHIFT) == + SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; + + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, val); + + /* Tell LED3 to blink on source */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + val &= ~(7 << 6); + val |= (1 << 6); /* A83B[8:6]= 1 */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, val); + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { + /* Restore LED4 source to external link, + * and re-enable interrupts. + */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_SIGNAL_MASK, + 0x40); + if (params->link_flags & + ELINK_LINK_FLAGS_INT_DISABLED) { + elink_link_int_enable(params); + params->link_flags &= + ~ELINK_LINK_FLAGS_INT_DISABLED; + } + } + } + break; + } + + /* This is a workaround for E3+84833 until autoneg + * restart is fixed in f/w + */ + if (CHIP_IS_E3(sc)) { + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); + } +} + +/******************************************************************/ +/* 54618SE PHY SECTION */ +/******************************************************************/ +static void elink_54618se_specific_func(struct elink_phy *phy, + struct elink_params *params, + uint32_t action) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t temp; + switch (action) { + case ELINK_PHY_INIT: + /* Configure LED4: set to INTR (0x6). */ + /* Accessing shadow register 0xe. */ + elink_cl22_write(sc, phy, + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_LED_SEL2); + elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); + temp &= ~(0xf << 4); + temp |= (0x6 << 4); + elink_cl22_write(sc, phy, + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_WR_ENA | temp); + /* Configure INTR based on link status change. */ + elink_cl22_write(sc, phy, + MDIO_REG_INTR_MASK, + ~MDIO_REG_INTR_MASK_LINK_STATUS); + break; + } +} + +static elink_status_t elink_54618se_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t port; + uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; + uint32_t cfg_pin; + + PMD_DRV_LOG(DEBUG, "54618SE cfg init"); + DELAY(1000 * 1); + + /* This works with E3 only, no need to check the chip + * before determining the port. + */ + port = params->port; + + cfg_pin = (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + e3_cmn_pin_cfg)) & + PORT_HW_CFG_E3_PHY_RESET_MASK) >> + PORT_HW_CFG_E3_PHY_RESET_SHIFT; + + /* Drive pin high to bring the GPHY out of reset. */ + elink_set_cfg_pin(sc, cfg_pin, 1); + + /* wait for GPHY to reset */ + DELAY(1000 * 50); + + /* reset phy */ + elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000); + elink_wait_reset_complete(sc, phy, params); + + /* Wait for GPHY to reset */ + DELAY(1000 * 50); + + elink_54618se_specific_func(phy, params, ELINK_PHY_INIT); + /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ + elink_cl22_write(sc, phy, + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); + elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); + temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; + elink_cl22_write(sc, phy, + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_WR_ENA | temp); + + /* Set up fc */ + /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ + elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); + fc_val = 0; + if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) + fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; + + if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) + fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; + + /* Read all advertisement */ + elink_cl22_read(sc, phy, 0x09, &an_1000_val); + + elink_cl22_read(sc, phy, 0x04, &an_10_100_val); + + elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val); + + /* Disable forced speed */ + autoneg_val &= + ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13)); + an_10_100_val &= + ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) | + (1 << 11)); + + if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || + (phy->req_line_speed == ELINK_SPEED_1000)) { + an_1000_val |= (1 << 8); + autoneg_val |= (1 << 9 | 1 << 12); + if (phy->req_duplex == DUPLEX_FULL) + an_1000_val |= (1 << 9); + PMD_DRV_LOG(DEBUG, "Advertising 1G"); + } else + an_1000_val &= ~((1 << 8) | (1 << 9)); + + elink_cl22_write(sc, phy, 0x09, an_1000_val); + elink_cl22_read(sc, phy, 0x09, &an_1000_val); + + /* Advertise 10/100 link speed */ + if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { + an_10_100_val |= (1 << 5); + autoneg_val |= (1 << 9 | 1 << 12); + PMD_DRV_LOG(DEBUG, "Advertising 10M-HD"); + } + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { + an_10_100_val |= (1 << 6); + autoneg_val |= (1 << 9 | 1 << 12); + PMD_DRV_LOG(DEBUG, "Advertising 10M-FD"); + } + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { + an_10_100_val |= (1 << 7); + autoneg_val |= (1 << 9 | 1 << 12); + PMD_DRV_LOG(DEBUG, "Advertising 100M-HD"); + } + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { + an_10_100_val |= (1 << 8); + autoneg_val |= (1 << 9 | 1 << 12); + PMD_DRV_LOG(DEBUG, "Advertising 100M-FD"); + } + } + + /* Only 10/100 are allowed to work in FORCE mode */ + if (phy->req_line_speed == ELINK_SPEED_100) { + autoneg_val |= (1 << 13); + /* Enabled AUTO-MDIX when autoneg is disabled */ + elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0)); + PMD_DRV_LOG(DEBUG, "Setting 100M force"); + } + if (phy->req_line_speed == ELINK_SPEED_10) { + /* Enabled AUTO-MDIX when autoneg is disabled */ + elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0)); + PMD_DRV_LOG(DEBUG, "Setting 10M force"); + } + + if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { + elink_status_t rc; + + elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS, + MDIO_REG_GPHY_EXP_ACCESS_TOP | + MDIO_REG_GPHY_EXP_TOP_2K_BUF); + elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); + temp &= 0xfffe; + elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); + + rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); + if (rc != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers"); + elink_eee_disable(phy, params, vars); + } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && + (phy->req_duplex == DUPLEX_FULL) && + (elink_eee_calc_timer(params) || + !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) { + /* Need to advertise EEE only when requested, + * and either no LPI assertion was requested, + * or it was requested and a valid timer was set. + * Also notice full duplex is required for EEE. + */ + elink_eee_advertise(phy, params, vars, + SHMEM_EEE_1G_ADV); + } else { + PMD_DRV_LOG(DEBUG, "Don't Advertise 1GBase-T EEE"); + elink_eee_disable(phy, params, vars); + } + } else { + vars->eee_status &= ~SHMEM_EEE_1G_ADV << + SHMEM_EEE_SUPPORTED_SHIFT; + + if (phy->flags & ELINK_FLAGS_EEE) { + /* Handle legacy auto-grEEEn */ + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) { + temp = 6; + PMD_DRV_LOG(DEBUG, "Enabling Auto-GrEEEn"); + } else { + temp = 0; + PMD_DRV_LOG(DEBUG, "Don't Adv. EEE"); + } + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_EEE_ADV, temp); + } + } + + elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val); + + if (phy->req_duplex == DUPLEX_FULL) + autoneg_val |= (1 << 8); + + elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val); + + return ELINK_STATUS_OK; +} + +static void elink_5461x_set_link_led(struct elink_phy *phy, + struct elink_params *params, uint8_t mode) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t temp; + + elink_cl22_write(sc, phy, + MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1); + elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); + temp &= 0xff00; + + PMD_DRV_LOG(DEBUG, "54618x set link led (mode=%x)", mode); + switch (mode) { + case ELINK_LED_MODE_FRONT_PANEL_OFF: + case ELINK_LED_MODE_OFF: + temp |= 0x00ee; + break; + case ELINK_LED_MODE_OPER: + temp |= 0x0001; + break; + case ELINK_LED_MODE_ON: + temp |= 0x00ff; + break; + default: + break; + } + elink_cl22_write(sc, phy, + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_WR_ENA | temp); + return; +} + +static void elink_54618se_link_reset(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t cfg_pin; + uint8_t port; + + /* In case of no EPIO routed to reset the GPHY, put it + * in low power mode. + */ + elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800); + /* This works with E3 only, no need to check the chip + * before determining the port. + */ + port = params->port; + cfg_pin = (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + e3_cmn_pin_cfg)) & + PORT_HW_CFG_E3_PHY_RESET_MASK) >> + PORT_HW_CFG_E3_PHY_RESET_SHIFT; + + /* Drive pin low to put GPHY in reset. */ + elink_set_cfg_pin(sc, cfg_pin, 0); +} + +static uint8_t elink_54618se_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val; + uint8_t link_up = 0; + uint16_t legacy_status, legacy_speed; + + /* Get speed operation status */ + elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status); + PMD_DRV_LOG(DEBUG, "54618SE read_status: 0x%x", legacy_status); + + /* Read status to clear the PHY interrupt. */ + elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val); + + link_up = ((legacy_status & (1 << 2)) == (1 << 2)); + + if (link_up) { + legacy_speed = (legacy_status & (7 << 8)); + if (legacy_speed == (7 << 8)) { + vars->line_speed = ELINK_SPEED_1000; + vars->duplex = DUPLEX_FULL; + } else if (legacy_speed == (6 << 8)) { + vars->line_speed = ELINK_SPEED_1000; + vars->duplex = DUPLEX_HALF; + } else if (legacy_speed == (5 << 8)) { + vars->line_speed = ELINK_SPEED_100; + vars->duplex = DUPLEX_FULL; + } + /* Omitting 100Base-T4 for now */ + else if (legacy_speed == (3 << 8)) { + vars->line_speed = ELINK_SPEED_100; + vars->duplex = DUPLEX_HALF; + } else if (legacy_speed == (2 << 8)) { + vars->line_speed = ELINK_SPEED_10; + vars->duplex = DUPLEX_FULL; + } else if (legacy_speed == (1 << 8)) { + vars->line_speed = ELINK_SPEED_10; + vars->duplex = DUPLEX_HALF; + } else /* Should not happen */ + vars->line_speed = 0; + + PMD_DRV_LOG(DEBUG, + "Link is up in %dMbps, is_duplex_full= %d", + vars->line_speed, (vars->duplex == DUPLEX_FULL)); + + /* Check legacy speed AN resolution */ + elink_cl22_read(sc, phy, 0x01, &val); + if (val & (1 << 5)) + vars->link_status |= + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + elink_cl22_read(sc, phy, 0x06, &val); + if ((val & (1 << 0)) == 0) + vars->link_status |= + LINK_STATUS_PARALLEL_DETECTION_USED; + + PMD_DRV_LOG(DEBUG, "BNX2X54618SE: link speed is %d", + vars->line_speed); + + elink_ext_phy_resolve_fc(phy, params, vars); + + if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { + /* Report LP advertised speeds */ + elink_cl22_read(sc, phy, 0x5, &val); + + if (val & (1 << 5)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; + if (val & (1 << 6)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; + if (val & (1 << 7)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; + if (val & (1 << 8)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; + if (val & (1 << 9)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; + + elink_cl22_read(sc, phy, 0xa, &val); + if (val & (1 << 10)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; + if (val & (1 << 11)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + + if ((phy->flags & ELINK_FLAGS_EEE) && + elink_eee_has_cap(params)) + elink_eee_an_resolve(phy, params, vars); + } + } + return link_up; +} + +static void elink_54618se_config_loopback(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t val; + uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; + + PMD_DRV_LOG(DEBUG, "2PMA/PMD ext_phy_loopback: 54618se"); + + /* Enable master/slave manual mmode and set to master */ + /* mii write 9 [bits set 11 12] */ + elink_cl22_write(sc, phy, 0x09, 3 << 11); + + /* forced 1G and disable autoneg */ + /* set val [mii read 0] */ + /* set val [expr $val & [bits clear 6 12 13]] */ + /* set val [expr $val | [bits set 6 8]] */ + /* mii write 0 $val */ + elink_cl22_read(sc, phy, 0x00, &val); + val &= ~((1 << 6) | (1 << 12) | (1 << 13)); + val |= (1 << 6) | (1 << 8); + elink_cl22_write(sc, phy, 0x00, val); + + /* Set external loopback and Tx using 6dB coding */ + /* mii write 0x18 7 */ + /* set val [mii read 0x18] */ + /* mii write 0x18 [expr $val | [bits set 10 15]] */ + elink_cl22_write(sc, phy, 0x18, 7); + elink_cl22_read(sc, phy, 0x18, &val); + elink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15)); + + /* This register opens the gate for the UMAC despite its name */ + REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1); + + /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame + * length used by the MAC receive logic to check frames. + */ + REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); +} + +/******************************************************************/ +/* SFX7101 PHY SECTION */ +/******************************************************************/ +static void elink_7101_config_loopback(struct elink_phy *phy, + struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + /* SFX7101_XGXS_TEST1 */ + elink_cl45_write(sc, phy, + MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); +} + +static elink_status_t elink_7101_config_init(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + uint16_t fw_ver1, fw_ver2, val; + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LASI indication"); + + /* Restore normal power mode */ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + /* HW reset */ + elink_ext_phy_hw_reset(sc, params->port); + elink_wait_reset_complete(sc, phy, params); + + elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); + PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LED to blink on traffic"); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3)); + + elink_ext_phy_set_pause(params, phy, vars); + /* Restart autoneg */ + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); + val |= 0x200; + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); + + /* Save spirom version */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); + elink_save_spirom_version(sc, params->port, + (uint32_t) (fw_ver1 << 16 | fw_ver2), + phy->ver_addr); + return ELINK_STATUS_OK; +} + +static uint8_t elink_7101_read_status(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t link_up; + uint16_t val1, val2; + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + PMD_DRV_LOG(DEBUG, "10G-base-T LASI status 0x%x->0x%x", val2, val1); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); + elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); + PMD_DRV_LOG(DEBUG, "10G-base-T PMA status 0x%x->0x%x", val2, val1); + link_up = ((val1 & 4) == 4); + /* If link is up print the AN outcome of the SFX7101 PHY */ + if (link_up) { + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, + &val2); + vars->line_speed = ELINK_SPEED_10000; + vars->duplex = DUPLEX_FULL; + PMD_DRV_LOG(DEBUG, "SFX7101 AN status 0x%x->Master=%x", + val2, (val2 & (1 << 14))); + elink_ext_phy_10G_an_resolve(sc, phy, vars); + elink_ext_phy_resolve_fc(phy, params, vars); + + /* Read LP advertised speeds */ + if (val2 & (1 << 11)) + vars->link_status |= + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + } + return link_up; +} + +static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str, + uint16_t * len) +{ + if (*len < 5) + return ELINK_STATUS_ERROR; + str[0] = (spirom_ver & 0xFF); + str[1] = (spirom_ver & 0xFF00) >> 8; + str[2] = (spirom_ver & 0xFF0000) >> 16; + str[3] = (spirom_ver & 0xFF000000) >> 24; + str[4] = '\0'; + *len -= 5; + return ELINK_STATUS_OK; +} + +static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) +{ + /* Low power mode is controlled by GPIO 2 */ + elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); + /* The PHY reset is controlled by GPIO 1 */ + elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); +} + +static void elink_7101_set_link_led(struct elink_phy *phy, + struct elink_params *params, uint8_t mode) +{ + uint16_t val = 0; + struct bnx2x_softc *sc = params->sc; + switch (mode) { + case ELINK_LED_MODE_FRONT_PANEL_OFF: + case ELINK_LED_MODE_OFF: + val = 2; + break; + case ELINK_LED_MODE_ON: + val = 1; + break; + case ELINK_LED_MODE_OPER: + val = 0; + break; + } + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val); +} + +/******************************************************************/ +/* STATIC PHY DECLARATION */ +/******************************************************************/ + +static const struct elink_phy phy_null = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, + .addr = 0, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = 0, + .media_type = ELINK_ETH_PHY_NOT_PRESENT, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) NULL, + .read_status = (read_status_t) NULL, + .link_reset = (link_reset_t) NULL, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) NULL, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_serdes = { + .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, + .addr = 0xff, + .def_md_devad = 0, + .flags = 0, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_2500baseX_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_xgxs_config_init, + .read_status = (read_status_t) elink_link_settings_status, + .link_reset = (link_reset_t) elink_int_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) NULL, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_xgxs = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, + .addr = 0xff, + .def_md_devad = 0, + .flags = 0, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_2500baseX_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_CX4, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_xgxs_config_init, + .read_status = (read_status_t) elink_link_settings_status, + .link_reset = (link_reset_t) elink_int_link_reset, + .config_loopback = (config_loopback_t) elink_set_xgxs_loopback, + .format_fw_ver = (format_fw_ver_t) NULL, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) elink_xgxs_specific_func +}; + +static const struct elink_phy phy_warpcore = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_TX_ERROR_CHECK, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_20000baseKR2_Full | + ELINK_SUPPORTED_20000baseMLD2_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_UNSPECIFIED, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + /* req_duplex = */ 0, + /* rsrv = */ 0, + .config_init = (config_init_t) elink_warpcore_config_init, + .read_status = (read_status_t) elink_warpcore_read_status, + .link_reset = (link_reset_t) elink_warpcore_link_reset, + .config_loopback = (config_loopback_t) elink_set_warpcore_loopback, + .format_fw_ver = (format_fw_ver_t) NULL, + .hw_reset = (hw_reset_t) elink_warpcore_hw_reset, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_7101 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_7101_config_init, + .read_status = (read_status_t) elink_7101_read_status, + .link_reset = (link_reset_t) elink_common_ext_link_reset, + .config_loopback = (config_loopback_t) elink_7101_config_loopback, + .format_fw_ver = (format_fw_ver_t) elink_7101_format_ver, + .hw_reset = (hw_reset_t) elink_7101_hw_reset, + .set_link_led = (set_link_led_t) elink_7101_set_link_led, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_8073 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073, + .addr = 0xff, + .def_md_devad = 0, + .flags = 0, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_2500baseX_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_KR, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_8073_config_init, + .read_status = (read_status_t) elink_8073_read_status, + .link_reset = (link_reset_t) elink_8073_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_format_ver, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) elink_8073_specific_func +}; + +static const struct elink_phy phy_8705 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_XFP_FIBER, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_8705_config_init, + .read_status = (read_status_t) elink_8705_read_status, + .link_reset = (link_reset_t) elink_common_ext_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_null_format_ver, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_8706 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_8706_config_init, + .read_status = (read_status_t) elink_8706_read_status, + .link_reset = (link_reset_t) elink_common_ext_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_format_ver, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_8726 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_NOT_PRESENT, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_8726_config_init, + .read_status = (read_status_t) elink_8726_read_status, + .link_reset = (link_reset_t) elink_8726_link_reset, + .config_loopback = (config_loopback_t) elink_8726_config_loopback, + .format_fw_ver = (format_fw_ver_t) elink_format_ver, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) NULL, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_8727 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_NOT_PRESENT, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_8727_config_init, + .read_status = (read_status_t) elink_8727_read_status, + .link_reset = (link_reset_t) elink_8727_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_format_ver, + .hw_reset = (hw_reset_t) elink_8727_hw_reset, + .set_link_led = (set_link_led_t) elink_8727_set_link_led, + .phy_specific_func = (phy_specific_func_t) elink_8727_specific_func +}; + +static const struct elink_phy phy_8481 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_8481_config_init, + .read_status = (read_status_t) elink_848xx_read_status, + .link_reset = (link_reset_t) elink_8481_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, + .hw_reset = (hw_reset_t) elink_8481_hw_reset, + .set_link_led = (set_link_led_t) elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t) NULL +}; + +static const struct elink_phy phy_84823 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_848x3_config_init, + .read_status = (read_status_t) elink_848xx_read_status, + .link_reset = (link_reset_t) elink_848x3_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func +}; + +static const struct elink_phy phy_84833 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL | + ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_848x3_config_init, + .read_status = (read_status_t) elink_848xx_read_status, + .link_reset = (link_reset_t) elink_848x3_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, + .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy, + .set_link_led = (set_link_led_t) elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func +}; + +static const struct elink_phy phy_84834 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t) elink_848x3_config_init, + .read_status = (read_status_t) elink_848xx_read_status, + .link_reset = (link_reset_t) elink_848x3_link_reset, + .config_loopback = (config_loopback_t) NULL, + .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, + .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy, + .set_link_led = (set_link_led_t) elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func +}; + +static const struct elink_phy phy_54618se = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + /* req_duplex = */ 0, + /* rsrv = */ 0, + .config_init = (config_init_t) elink_54618se_config_init, + .read_status = (read_status_t) elink_54618se_read_status, + .link_reset = (link_reset_t) elink_54618se_link_reset, + .config_loopback = (config_loopback_t) elink_54618se_config_loopback, + .format_fw_ver = (format_fw_ver_t) NULL, + .hw_reset = (hw_reset_t) NULL, + .set_link_led = (set_link_led_t) elink_5461x_set_link_led, + .phy_specific_func = (phy_specific_func_t) elink_54618se_specific_func +}; + +/*****************************************************************/ +/* */ +/* Populate the phy according. Main function: elink_populate_phy */ +/* */ +/*****************************************************************/ + +static void elink_populate_preemphasis(struct bnx2x_softc *sc, + uint32_t shmem_base, + struct elink_phy *phy, uint8_t port, + uint8_t phy_index) +{ + /* Get the 4 lanes xgxs config rx and tx */ + uint32_t rx = 0, tx = 0, i; + for (i = 0; i < 2; i++) { + /* INT_PHY and ELINK_EXT_PHY1 share the same value location in + * the shmem. When num_phys is greater than 1, than this value + * applies only to ELINK_EXT_PHY1 + */ + if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) { + rx = REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + xgxs_config_rx[i << 1])); + + tx = REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + xgxs_config_tx[i << 1])); + } else { + rx = REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + xgxs_config2_rx[i << 1])); + + tx = REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + xgxs_config2_rx[i << 1])); + } + + phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff); + phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); + + phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff); + phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); + } +} + +static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc, + uint32_t shmem_base, uint8_t phy_index, + uint8_t port) +{ + uint32_t ext_phy_config = 0; + switch (phy_index) { + case ELINK_EXT_PHY1: + ext_phy_config = REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + external_phy_config)); + break; + case ELINK_EXT_PHY2: + ext_phy_config = REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + external_phy_config2)); + break; + default: + PMD_DRV_LOG(DEBUG, "Invalid phy_index %d", phy_index); + return ELINK_STATUS_ERROR; + } + + return ext_phy_config; +} + +static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, + uint32_t shmem_base, uint8_t port, + struct elink_phy *phy) +{ + uint32_t phy_addr; + __rte_unused uint32_t chip_id; + uint32_t switch_cfg = (REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info. + port_feature_config[port]. + link_config)) & + PORT_FEATURE_CONNECTED_SWITCH_MASK); + chip_id = + (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | + ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); + + PMD_DRV_LOG(DEBUG, ":chip_id = 0x%x", chip_id); + if (USES_WARPCORE(sc)) { + uint32_t serdes_net_if; + phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); + *phy = phy_warpcore; + if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) + phy->flags |= ELINK_FLAGS_4_PORT_MODE; + else + phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; + /* Check Dual mode */ + serdes_net_if = (REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + default_cfg)) & + PORT_HW_CFG_NET_SERDES_IF_MASK); + /* Set the appropriate supported and flags indications per + * interface type of the chip + */ + switch (serdes_net_if) { + case PORT_HW_CFG_NET_SERDES_IF_SGMII: + phy->supported &= (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause); + phy->media_type = ELINK_ETH_PHY_BASE_T; + break; + case PORT_HW_CFG_NET_SERDES_IF_XFI: + phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause); + phy->media_type = ELINK_ETH_PHY_XFP_FIBER; + break; + case PORT_HW_CFG_NET_SERDES_IF_SFI: + phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause); + phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; + break; + case PORT_HW_CFG_NET_SERDES_IF_KR: + phy->media_type = ELINK_ETH_PHY_KR; + phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause); + break; + case PORT_HW_CFG_NET_SERDES_IF_DXGXS: + phy->media_type = ELINK_ETH_PHY_KR; + phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; + phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause); + break; + case PORT_HW_CFG_NET_SERDES_IF_KR2: + phy->media_type = ELINK_ETH_PHY_KR; + phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; + phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause); + phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; + break; + default: + PMD_DRV_LOG(DEBUG, "Unknown WC interface type 0x%x", + serdes_net_if); + break; + } + + /* Enable MDC/MDIO work-around for E3 A0 since free running MDC + * was not set as expected. For B0, ECO will be enabled so there + * won't be an issue there + */ + if (CHIP_REV(sc) == CHIP_REV_Ax) + phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; + else + phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; + } else { + switch (switch_cfg) { + case ELINK_SWITCH_CFG_1G: + phy_addr = REG_RD(sc, + NIG_REG_SERDES0_CTRL_PHY_ADDR + + port * 0x10); + *phy = phy_serdes; + break; + case ELINK_SWITCH_CFG_10G: + phy_addr = REG_RD(sc, + NIG_REG_XGXS0_CTRL_PHY_ADDR + + port * 0x18); + *phy = phy_xgxs; + break; + default: + PMD_DRV_LOG(DEBUG, "Invalid switch_cfg"); + return ELINK_STATUS_ERROR; + } + } + phy->addr = (uint8_t) phy_addr; + phy->mdio_ctrl = elink_get_emac_base(sc, + SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, + port); + if (CHIP_IS_E2(sc)) + phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; + else + phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; + + PMD_DRV_LOG(DEBUG, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x", + port, phy->addr, phy->mdio_ctrl); + + elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY); + return ELINK_STATUS_OK; +} + +static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc, + uint8_t phy_index, + uint32_t shmem_base, + uint32_t shmem2_base, + uint8_t port, + struct elink_phy *phy) +{ + uint32_t ext_phy_config, phy_type, config2; + uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; + ext_phy_config = elink_get_ext_phy_config(sc, shmem_base, + phy_index, port); + phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); + /* Select the phy type */ + switch (phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073: + mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; + *phy = phy_8073; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705: + *phy = phy_8705; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706: + *phy = phy_8706; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: + mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; + *phy = phy_8726; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC: + /* BNX2X8727_NOC => BNX2X8727 no over current */ + mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; + *phy = phy_8727; + phy->flags |= ELINK_FLAGS_NOC; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: + mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; + *phy = phy_8727; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481: + *phy = phy_8481; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823: + *phy = phy_84823; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833: + *phy = phy_84833; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834: + *phy = phy_84834; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE: + *phy = phy_54618se; + if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) + phy->flags |= ELINK_FLAGS_EEE; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: + *phy = phy_7101; + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: + *phy = phy_null; + return ELINK_STATUS_ERROR; + default: + *phy = phy_null; + /* In case external PHY wasn't found */ + if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && + (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) + return ELINK_STATUS_ERROR; + return ELINK_STATUS_OK; + } + + phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); + elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index); + + /* The shmem address of the phy version is located on different + * structures. In case this structure is too old, do not set + * the address + */ + config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region, + dev_info.shared_hw_config. + config2)); + if (phy_index == ELINK_EXT_PHY1) { + phy->ver_addr = shmem_base + offsetof(struct shmem_region, + port_mb[port]. + ext_phy_fw_version); + + /* Check specific mdc mdio settings */ + if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) + mdc_mdio_access = config2 & + SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; + } else { + uint32_t size = REG_RD(sc, shmem2_base); + + if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) { + phy->ver_addr = shmem2_base + + offsetof(struct shmem2_region, + ext_phy_fw_version2[port]); + } + /* Check specific mdc mdio settings */ + if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) + mdc_mdio_access = (config2 & + SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) + >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - + SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); + } + phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port); + + if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) && + (phy->ver_addr)) { + /* Remove 100Mb link supported for BNX2X84833/4 when phy fw + * version lower than or equal to 1.39 + */ + uint32_t raw_ver = REG_RD(sc, phy->ver_addr); + if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1)) + phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full); + } + + PMD_DRV_LOG(DEBUG, "phy_type 0x%x port %d found in index %d", + phy_type, port, phy_index); + PMD_DRV_LOG(DEBUG, " addr=0x%x, mdio_ctl=0x%x", + phy->addr, phy->mdio_ctrl); + return ELINK_STATUS_OK; +} + +static elink_status_t elink_populate_phy(struct bnx2x_softc *sc, + uint8_t phy_index, uint32_t shmem_base, + uint32_t shmem2_base, uint8_t port, + struct elink_phy *phy) +{ + elink_status_t status = ELINK_STATUS_OK; + phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; + if (phy_index == ELINK_INT_PHY) + return elink_populate_int_phy(sc, shmem_base, port, phy); + status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base, + port, phy); + return status; +} + +static void elink_phy_def_cfg(struct elink_params *params, + struct elink_phy *phy, uint8_t phy_index) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t link_config; + /* Populate the default phy configuration for MF mode */ + if (phy_index == ELINK_EXT_PHY2) { + link_config = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_feature_config + [params->port].link_config2)); + phy->speed_cap_mask = + REG_RD(sc, + params->shmem_base + offsetof(struct shmem_region, + dev_info.port_hw_config + [params->port]. + speed_capability_mask2)); + } else { + link_config = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_feature_config + [params->port].link_config)); + phy->speed_cap_mask = + REG_RD(sc, + params->shmem_base + offsetof(struct shmem_region, + dev_info.port_hw_config + [params->port]. + speed_capability_mask)); + } + + PMD_DRV_LOG(DEBUG, + "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x", + phy_index, link_config, phy->speed_cap_mask); + + phy->req_duplex = DUPLEX_FULL; + switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { + case PORT_FEATURE_LINK_SPEED_10M_HALF: + phy->req_duplex = DUPLEX_HALF; + case PORT_FEATURE_LINK_SPEED_10M_FULL: + phy->req_line_speed = ELINK_SPEED_10; + break; + case PORT_FEATURE_LINK_SPEED_100M_HALF: + phy->req_duplex = DUPLEX_HALF; + case PORT_FEATURE_LINK_SPEED_100M_FULL: + phy->req_line_speed = ELINK_SPEED_100; + break; + case PORT_FEATURE_LINK_SPEED_1G: + phy->req_line_speed = ELINK_SPEED_1000; + break; + case PORT_FEATURE_LINK_SPEED_2_5G: + phy->req_line_speed = ELINK_SPEED_2500; + break; + case PORT_FEATURE_LINK_SPEED_10G_CX4: + phy->req_line_speed = ELINK_SPEED_10000; + break; + default: + phy->req_line_speed = ELINK_SPEED_AUTO_NEG; + break; + } + + switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { + case PORT_FEATURE_FLOW_CONTROL_AUTO: + phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; + break; + case PORT_FEATURE_FLOW_CONTROL_TX: + phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX; + break; + case PORT_FEATURE_FLOW_CONTROL_RX: + phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX; + break; + case PORT_FEATURE_FLOW_CONTROL_BOTH: + phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH; + break; + default: + phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; + break; + } +} + +uint32_t elink_phy_selection(struct elink_params *params) +{ + uint32_t phy_config_swapped, prio_cfg; + uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; + + phy_config_swapped = params->multi_phy_config & + PORT_HW_CFG_PHY_SWAPPED_ENABLED; + + prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK; + + if (phy_config_swapped) { + switch (prio_cfg) { + case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: + return_cfg = + PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; + break; + case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: + return_cfg = + PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; + break; + case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: + return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; + break; + case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: + return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; + break; + } + } else + return_cfg = prio_cfg; + + return return_cfg; +} + +elink_status_t elink_phy_probe(struct elink_params * params) +{ + uint8_t phy_index, actual_phy_idx; + uint32_t phy_config_swapped, sync_offset, media_types; + struct bnx2x_softc *sc = params->sc; + struct elink_phy *phy; + params->num_phys = 0; + PMD_DRV_LOG(DEBUG, "Begin phy probe"); +#ifdef ELINK_INCLUDE_EMUL + if (CHIP_REV_IS_EMUL(sc)) + return ELINK_STATUS_OK; +#endif + phy_config_swapped = params->multi_phy_config & + PORT_HW_CFG_PHY_SWAPPED_ENABLED; + + for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) { + actual_phy_idx = phy_index; + if (phy_config_swapped) { + if (phy_index == ELINK_EXT_PHY1) + actual_phy_idx = ELINK_EXT_PHY2; + else if (phy_index == ELINK_EXT_PHY2) + actual_phy_idx = ELINK_EXT_PHY1; + } + PMD_DRV_LOG(DEBUG, "phy_config_swapped %x, phy_index %x," + " actual_phy_idx %x", phy_config_swapped, + phy_index, actual_phy_idx); + phy = ¶ms->phy[actual_phy_idx]; + if (elink_populate_phy(sc, phy_index, params->shmem_base, + params->shmem2_base, params->port, + phy) != ELINK_STATUS_OK) { + params->num_phys = 0; + PMD_DRV_LOG(DEBUG, "phy probe failed in phy index %d", + phy_index); + for (phy_index = ELINK_INT_PHY; + phy_index < ELINK_MAX_PHYS; phy_index++) + *phy = phy_null; + return ELINK_STATUS_ERROR; + } + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) + break; + + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) + phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; + + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_MT_SUPPORT)) + phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; + + sync_offset = params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port].media_type); + media_types = REG_RD(sc, sync_offset); + + /* Update media type for non-PMF sync only for the first time + * In case the media type changes afterwards, it will be updated + * using the update_status function + */ + if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << + (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * + actual_phy_idx))) == 0) { + media_types |= ((phy->media_type & + PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << + (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * + actual_phy_idx)); + } + REG_WR(sc, sync_offset, media_types); + + elink_phy_def_cfg(params, phy, phy_index); + params->num_phys++; + } + + PMD_DRV_LOG(DEBUG, "End phy probe. #phys found %x", params->num_phys); + return ELINK_STATUS_OK; +} + +#ifdef ELINK_INCLUDE_EMUL +static elink_status_t elink_init_e3_emul_mac(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->line_speed = params->req_line_speed[0]; + /* In case link speed is auto, set speed the highest as possible */ + if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) { + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) + vars->line_speed = ELINK_SPEED_2500; + else if (elink_is_4_port_mode(sc)) + vars->line_speed = ELINK_SPEED_10000; + else + vars->line_speed = ELINK_SPEED_20000; + } + if (vars->line_speed < ELINK_SPEED_10000) { + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) { + PMD_DRV_LOG(DEBUG, "Invalid line speed %d while UMAC is" + " disabled!", params->req_line_speed[0]); + return ELINK_STATUS_ERROR; + } + switch (vars->line_speed) { + case ELINK_SPEED_10: + vars->link_status = ELINK_LINK_10TFD; + break; + case ELINK_SPEED_100: + vars->link_status = ELINK_LINK_100TXFD; + break; + case ELINK_SPEED_1000: + vars->link_status = ELINK_LINK_1000TFD; + break; + case ELINK_SPEED_2500: + vars->link_status = ELINK_LINK_2500TFD; + break; + default: + PMD_DRV_LOG(DEBUG, "Invalid line speed %d for UMAC", + vars->line_speed); + return ELINK_STATUS_ERROR; + } + vars->link_status |= LINK_STATUS_LINK_UP; + + if (params->loopback_mode == ELINK_LOOPBACK_UMAC) + elink_umac_enable(params, vars, 1); + else + elink_umac_enable(params, vars, 0); + } else { + /* Link speed >= 10000 requires XMAC enabled */ + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) { + PMD_DRV_LOG(DEBUG, "Invalid line speed %d while XMAC is" + " disabled!", params->req_line_speed[0]); + return ELINK_STATUS_ERROR; + } + /* Check link speed */ + switch (vars->line_speed) { + case ELINK_SPEED_10000: + vars->link_status = ELINK_LINK_10GTFD; + break; + case ELINK_SPEED_20000: + vars->link_status = ELINK_LINK_20GTFD; + break; + default: + PMD_DRV_LOG(DEBUG, "Invalid line speed %d for XMAC", + vars->line_speed); + return ELINK_STATUS_ERROR; + } + vars->link_status |= LINK_STATUS_LINK_UP; + if (params->loopback_mode == ELINK_LOOPBACK_XMAC) + elink_xmac_enable(params, vars, 1); + else + elink_xmac_enable(params, vars, 0); + } + return ELINK_STATUS_OK; +} + +static elink_status_t elink_init_emul(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + if (CHIP_IS_E3(sc)) { + if (elink_init_e3_emul_mac(params, vars) != ELINK_STATUS_OK) + return ELINK_STATUS_ERROR; + } else { + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) { + vars->line_speed = ELINK_SPEED_1000; + vars->link_status = (LINK_STATUS_LINK_UP | + ELINK_LINK_1000XFD); + if (params->loopback_mode == ELINK_LOOPBACK_EMAC) + elink_emac_enable(params, vars, 1); + else + elink_emac_enable(params, vars, 0); + } else { + vars->line_speed = ELINK_SPEED_10000; + vars->link_status = (LINK_STATUS_LINK_UP | + ELINK_LINK_10GTFD); + if (params->loopback_mode == ELINK_LOOPBACK_BMAC) + elink_bmac_enable(params, vars, 1, 1); + else + elink_bmac_enable(params, vars, 0, 1); + } + } + vars->link_up = 1; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + + if (CHIP_IS_E1x(sc)) + elink_pbf_update(params, vars->flow_ctrl, vars->line_speed); + /* Disable drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + + /* update shared memory */ + elink_update_mng(params, vars->link_status); + return ELINK_STATUS_OK; +} +#endif +#ifdef ELINK_INCLUDE_FPGA +static elink_status_t elink_init_fpga(struct elink_params *params, + struct elink_vars *vars) +{ + /* Enable on E1.5 FPGA */ + struct bnx2x_softc *sc = params->sc; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | ELINK_FLOW_CTRL_RX); + vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | + LINK_STATUS_RX_FLOW_CONTROL_ENABLED); + if (CHIP_IS_E3(sc)) { + vars->line_speed = params->req_line_speed[0]; + switch (vars->line_speed) { + case ELINK_SPEED_AUTO_NEG: + vars->line_speed = ELINK_SPEED_2500; + case ELINK_SPEED_2500: + vars->link_status = ELINK_LINK_2500TFD; + break; + case ELINK_SPEED_1000: + vars->link_status = ELINK_LINK_1000XFD; + break; + case ELINK_SPEED_100: + vars->link_status = ELINK_LINK_100TXFD; + break; + case ELINK_SPEED_10: + vars->link_status = ELINK_LINK_10TFD; + break; + default: + PMD_DRV_LOG(DEBUG, "Invalid link speed %d", + params->req_line_speed[0]); + return ELINK_STATUS_ERROR; + } + vars->link_status |= LINK_STATUS_LINK_UP; + if (params->loopback_mode == ELINK_LOOPBACK_UMAC) + elink_umac_enable(params, vars, 1); + else + elink_umac_enable(params, vars, 0); + } else { + vars->line_speed = ELINK_SPEED_10000; + vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD); + if (params->loopback_mode == ELINK_LOOPBACK_EMAC) + elink_emac_enable(params, vars, 1); + else + elink_emac_enable(params, vars, 0); + } + vars->link_up = 1; + + if (CHIP_IS_E1x(sc)) + elink_pbf_update(params, vars->flow_ctrl, vars->line_speed); + /* Disable drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + + /* Update shared memory */ + elink_update_mng(params, vars->link_status); + return ELINK_STATUS_OK; +} +#endif +static void elink_init_bmac_loopback(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->link_up = 1; + vars->line_speed = ELINK_SPEED_10000; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_BMAC; + + vars->phy_flags = PHY_XGXS_FLAG; + + elink_xgxs_deassert(params); + + /* Set bmac loopback */ + elink_bmac_enable(params, vars, 1, 1); + + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); +} + +static void elink_init_emac_loopback(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->link_up = 1; + vars->line_speed = ELINK_SPEED_1000; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_EMAC; + + vars->phy_flags = PHY_XGXS_FLAG; + + elink_xgxs_deassert(params); + /* Set bmac loopback */ + elink_emac_enable(params, vars, 1); + elink_emac_program(params, vars); + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); +} + +static void elink_init_xmac_loopback(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->link_up = 1; + if (!params->req_line_speed[0]) + vars->line_speed = ELINK_SPEED_10000; + else + vars->line_speed = params->req_line_speed[0]; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_XMAC; + vars->phy_flags = PHY_XGXS_FLAG; + /* Set WC to loopback mode since link is required to provide clock + * to the XMAC in 20G mode + */ + elink_set_aer_mmd(params, ¶ms->phy[0]); + elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0); + params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY], + params); + + elink_xmac_enable(params, vars, 1); + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); +} + +static void elink_init_umac_loopback(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->link_up = 1; + vars->line_speed = ELINK_SPEED_1000; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_UMAC; + vars->phy_flags = PHY_XGXS_FLAG; + elink_umac_enable(params, vars, 1); + + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); +} + +static void elink_init_xgxs_loopback(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; + vars->link_up = 1; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->duplex = DUPLEX_FULL; + if (params->req_line_speed[0] == ELINK_SPEED_1000) + vars->line_speed = ELINK_SPEED_1000; + else if ((params->req_line_speed[0] == ELINK_SPEED_20000) || + (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) + vars->line_speed = ELINK_SPEED_20000; + else + vars->line_speed = ELINK_SPEED_10000; + + if (!USES_WARPCORE(sc)) + elink_xgxs_deassert(params); + elink_link_initialize(params, vars); + + if (params->req_line_speed[0] == ELINK_SPEED_1000) { + if (USES_WARPCORE(sc)) + elink_umac_enable(params, vars, 0); + else { + elink_emac_program(params, vars); + elink_emac_enable(params, vars, 0); + } + } else { + if (USES_WARPCORE(sc)) + elink_xmac_enable(params, vars, 0); + else + elink_bmac_enable(params, vars, 0, 1); + } + + if (params->loopback_mode == ELINK_LOOPBACK_XGXS) { + /* Set 10G XGXS loopback */ + int_phy->config_loopback(int_phy, params); + } else { + /* Set external phy loopback */ + uint8_t phy_index; + for (phy_index = ELINK_EXT_PHY1; + phy_index < params->num_phys; phy_index++) + if (params->phy[phy_index].config_loopback) + params->phy[phy_index].config_loopback(¶ms-> + phy + [phy_index], + params); + } + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + + elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); +} + +void elink_set_rx_filter(struct elink_params *params, uint8_t en) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t val = en * 0x1F; + + /* Open / close the gate between the NIG and the BRB */ + if (!CHIP_IS_E1x(sc)) + val |= en * 0x20; + REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val); + + REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3); + + REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : + NIG_REG_LLH0_BRB1_NOT_MCP), en); +} + +static elink_status_t elink_avoid_link_flap(struct elink_params *params, + struct elink_vars *vars) +{ + uint32_t phy_idx; + uint32_t dont_clear_stat, lfa_sts; + struct bnx2x_softc *sc = params->sc; + + /* Sync the link parameters */ + elink_link_status_update(params, vars); + + /* + * The module verification was already done by previous link owner, + * so this call is meant only to get warning message + */ + + for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { + struct elink_phy *phy = ¶ms->phy[phy_idx]; + if (phy->phy_specific_func) { + PMD_DRV_LOG(DEBUG, "Calling PHY specific func"); + phy->phy_specific_func(phy, params, ELINK_PHY_INIT); + } + if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || + (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) || + (phy->media_type == ELINK_ETH_PHY_DA_TWINAX)) + elink_verify_sfp_module(phy, params); + } + lfa_sts = REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, lfa_sts)); + + dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; + + /* Re-enable the NIG/MAC */ + if (CHIP_IS_E3(sc)) { + if (!dont_clear_stat) { + REG_WR(sc, GRCBASE_MISC + + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_MSTAT0 << + params->port)); + REG_WR(sc, GRCBASE_MISC + + MISC_REGISTERS_RESET_REG_2_SET, + (MISC_REGISTERS_RESET_REG_2_MSTAT0 << + params->port)); + } + if (vars->line_speed < ELINK_SPEED_10000) + elink_umac_enable(params, vars, 0); + else + elink_xmac_enable(params, vars, 0); + } else { + if (vars->line_speed < ELINK_SPEED_10000) + elink_emac_enable(params, vars, 0); + else + elink_bmac_enable(params, vars, 0, !dont_clear_stat); + } + + /* Increment LFA count */ + lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | + (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> + LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) + << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); + /* Clear link flap reason */ + lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; + + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, lfa_sts), lfa_sts); + + /* Disable NIG DRAIN */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + + /* Enable interrupts */ + elink_link_int_enable(params); + return ELINK_STATUS_OK; +} + +static void elink_cannot_avoid_link_flap(struct elink_params *params, + struct elink_vars *vars, + int lfa_status) +{ + uint32_t lfa_sts, cfg_idx, tmp_val; + struct bnx2x_softc *sc = params->sc; + + elink_link_reset(params, vars, 1); + + if (!params->lfa_base) + return; + /* Store the new link parameters */ + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, req_duplex), + params->req_duplex[0] | (params->req_duplex[1] << 16)); + + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, req_flow_ctrl), + params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); + + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, req_line_speed), + params->req_line_speed[0] | (params->req_line_speed[1] << 16)); + + for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, + speed_cap_mask[cfg_idx]), + params->speed_cap_mask[cfg_idx]); + } + + tmp_val = REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, additional_config)); + tmp_val &= ~REQ_FC_AUTO_ADV_MASK; + tmp_val |= params->req_fc_auto_adv; + + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, additional_config), tmp_val); + + lfa_sts = REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, lfa_sts)); + + /* Clear the "Don't Clear Statistics" bit, and set reason */ + lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; + + /* Set link flap reason */ + lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; + lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << + LFA_LINK_FLAP_REASON_OFFSET); + + /* Increment link flap counter */ + lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | + (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> + LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) + << LINK_FLAP_COUNT_OFFSET)); + REG_WR(sc, params->lfa_base + + offsetof(struct shmem_lfa, lfa_sts), lfa_sts); + /* Proceed with regular link initialization */ +} + +elink_status_t elink_phy_init(struct elink_params *params, + struct elink_vars *vars) +{ + int lfa_status; + struct bnx2x_softc *sc = params->sc; + PMD_DRV_LOG(DEBUG, "Phy Initialization started"); + PMD_DRV_LOG(DEBUG, "(1) req_speed %d, req_flowctrl %d", + params->req_line_speed[0], params->req_flow_ctrl[0]); + PMD_DRV_LOG(DEBUG, "(2) req_speed %d, req_flowctrl %d", + params->req_line_speed[1], params->req_flow_ctrl[1]); + PMD_DRV_LOG(DEBUG, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv); + vars->link_status = 0; + vars->phy_link_up = 0; + vars->link_up = 0; + vars->line_speed = 0; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_NONE; + vars->phy_flags = 0; + vars->check_kr2_recovery_cnt = 0; + params->link_flags = ELINK_PHY_INITIALIZED; + /* Driver opens NIG-BRB filters */ + elink_set_rx_filter(params, 1); + /* Check if link flap can be avoided */ + lfa_status = elink_check_lfa(params); + + if (lfa_status == 0) { + PMD_DRV_LOG(DEBUG, "Link Flap Avoidance in progress"); + return elink_avoid_link_flap(params, vars); + } + + PMD_DRV_LOG(DEBUG, "Cannot avoid link flap lfa_sta=0x%x", lfa_status); + elink_cannot_avoid_link_flap(params, vars, lfa_status); + + /* Disable attentions */ + elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4, + (ELINK_NIG_MASK_XGXS0_LINK_STATUS | + ELINK_NIG_MASK_XGXS0_LINK10G | + ELINK_NIG_MASK_SERDES0_LINK_STATUS | + ELINK_NIG_MASK_MI_INT)); +#ifdef ELINK_INCLUDE_EMUL + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)) +#endif + + elink_emac_init(params); + + if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) + vars->link_status |= LINK_STATUS_PFC_ENABLED; + + if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) { + PMD_DRV_LOG(DEBUG, "No phy found for initialization !!"); + return ELINK_STATUS_ERROR; + } + set_phy_vars(params, vars); + + PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys); +#ifdef ELINK_INCLUDE_FPGA + if (CHIP_REV_IS_FPGA(sc)) { + return elink_init_fpga(params, vars); + } else +#endif +#ifdef ELINK_INCLUDE_EMUL + if (CHIP_REV_IS_EMUL(sc)) { + return elink_init_emul(params, vars); + } else +#endif + switch (params->loopback_mode) { + case ELINK_LOOPBACK_BMAC: + elink_init_bmac_loopback(params, vars); + break; + case ELINK_LOOPBACK_EMAC: + elink_init_emac_loopback(params, vars); + break; + case ELINK_LOOPBACK_XMAC: + elink_init_xmac_loopback(params, vars); + break; + case ELINK_LOOPBACK_UMAC: + elink_init_umac_loopback(params, vars); + break; + case ELINK_LOOPBACK_XGXS: + case ELINK_LOOPBACK_EXT_PHY: + elink_init_xgxs_loopback(params, vars); + break; + default: + if (!CHIP_IS_E3(sc)) { + if (params->switch_cfg == ELINK_SWITCH_CFG_10G) + elink_xgxs_deassert(params); + else + elink_serdes_deassert(sc, params->port); + } + elink_link_initialize(params, vars); + DELAY(1000 * 30); + elink_link_int_enable(params); + break; + } + elink_update_mng(params, vars->link_status); + + elink_update_mng_eee(params, vars->eee_status); + return ELINK_STATUS_OK; +} + +static elink_status_t elink_link_reset(struct elink_params *params, + struct elink_vars *vars, + uint8_t reset_ext_phy) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t phy_index, port = params->port, clear_latch_ind = 0; + PMD_DRV_LOG(DEBUG, "Resetting the link of port %d", port); + /* Disable attentions */ + vars->link_status = 0; + elink_update_mng(params, vars->link_status); + vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | + SHMEM_EEE_ACTIVE_BIT); + elink_update_mng_eee(params, vars->eee_status); + elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, + (ELINK_NIG_MASK_XGXS0_LINK_STATUS | + ELINK_NIG_MASK_XGXS0_LINK10G | + ELINK_NIG_MASK_SERDES0_LINK_STATUS | + ELINK_NIG_MASK_MI_INT)); + + /* Activate nig drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1); + + /* Disable nig egress interface */ + if (!CHIP_IS_E3(sc)) { + REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0); + REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0); + } +#ifdef ELINK_INCLUDE_EMUL + /* Stop BigMac rx */ + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC)) +#endif + if (!CHIP_IS_E3(sc)) + elink_set_bmac_rx(sc, port, 0); +#ifdef ELINK_INCLUDE_EMUL + /* Stop XMAC/UMAC rx */ + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)) +#endif + if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) { + elink_set_xmac_rxtx(params, 0); + elink_set_umac_rxtx(params, 0); + } + /* Disable emac */ + if (!CHIP_IS_E3(sc)) + REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0); + + DELAY(1000 * 10); + /* The PHY reset is controlled by GPIO 1 + * Hold it as vars low + */ + /* Clear link led */ + elink_set_mdio_emac_per_phy(sc, params); + elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); + + if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) { + for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; + phy_index++) { + if (params->phy[phy_index].link_reset) { + elink_set_aer_mmd(params, + ¶ms->phy[phy_index]); + params->phy[phy_index].link_reset(¶ms-> + phy + [phy_index], + params); + } + if (params->phy[phy_index].flags & + ELINK_FLAGS_REARM_LATCH_SIGNAL) + clear_latch_ind = 1; + } + } + + if (clear_latch_ind) { + /* Clear latching indication */ + elink_rearm_latch_signal(sc, port, 0); + elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4, + 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); + } +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + if (!CHIP_REV_IS_SLOW(sc)) +#endif + if (params->phy[ELINK_INT_PHY].link_reset) + params->phy[ELINK_INT_PHY].link_reset(¶ms-> + phy + [ELINK_INT_PHY], + params); + + /* Disable nig ingress interface */ + if (!CHIP_IS_E3(sc)) { + /* Reset BigMac */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0); + REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0); + } else { + uint32_t xmac_base = + (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + elink_set_xumac_nig(params, 0, 0); + if (REG_RD(sc, MISC_REG_RESET_REG_2) & + MISC_REGISTERS_RESET_REG_2_XMAC) + REG_WR(sc, xmac_base + XMAC_REG_CTRL, + XMAC_CTRL_REG_SOFT_RESET); + } + vars->link_up = 0; + vars->phy_flags = 0; + return ELINK_STATUS_OK; +} + +elink_status_t elink_lfa_reset(struct elink_params * params, + struct elink_vars * vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->link_up = 0; + vars->phy_flags = 0; + params->link_flags &= ~ELINK_PHY_INITIALIZED; + if (!params->lfa_base) + return elink_link_reset(params, vars, 1); + /* + * Activate NIG drain so that during this time the device won't send + * anything while it is unable to response. + */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1); + + /* + * Close gracefully the gate from BMAC to NIG such that no half packets + * are passed. + */ + if (!CHIP_IS_E3(sc)) + elink_set_bmac_rx(sc, params->port, 0); + + if (CHIP_IS_E3(sc)) { + elink_set_xmac_rxtx(params, 0); + elink_set_umac_rxtx(params, 0); + } + /* Wait 10ms for the pipe to clean up */ + DELAY(1000 * 10); + + /* Clean the NIG-BRB using the network filters in a way that will + * not cut a packet in the middle. + */ + elink_set_rx_filter(params, 0); + + /* + * Re-open the gate between the BMAC and the NIG, after verifying the + * gate to the BRB is closed, otherwise packets may arrive to the + * firmware before driver had initialized it. The target is to achieve + * minimum management protocol down time. + */ + if (!CHIP_IS_E3(sc)) + elink_set_bmac_rx(sc, params->port, 1); + + if (CHIP_IS_E3(sc)) { + elink_set_xmac_rxtx(params, 1); + elink_set_umac_rxtx(params, 1); + } + /* Disable NIG drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + return ELINK_STATUS_OK; +} + +/****************************************************************************/ +/* Common function */ +/****************************************************************************/ +static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + __rte_unused uint32_t chip_id) +{ + struct elink_phy phy[PORT_MAX]; + struct elink_phy *phy_blk[PORT_MAX]; + uint16_t val; + int8_t port = 0; + int8_t port_of_path = 0; + uint32_t swap_val, swap_override; + swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); + swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); + port ^= (swap_val && swap_override); + elink_ext_phy_hw_reset(sc, port); + /* PART1 - Reset both phys */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + uint32_t shmem_base, shmem2_base; + /* In E2, same phy is using for port0 of the two paths */ + if (CHIP_IS_E1x(sc)) { + shmem_base = shmem_base_path[0]; + shmem2_base = shmem2_base_path[0]; + port_of_path = port; + } else { + shmem_base = shmem_base_path[port]; + shmem2_base = shmem2_base_path[port]; + port_of_path = 0; + } + + /* Extract the ext phy address for the port */ + if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, + port_of_path, &phy[port]) != + ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "populate_phy failed"); + return ELINK_STATUS_ERROR; + } + /* Disable attentions */ + elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + + port_of_path * 4, + (ELINK_NIG_MASK_XGXS0_LINK_STATUS | + ELINK_NIG_MASK_XGXS0_LINK10G | + ELINK_NIG_MASK_SERDES0_LINK_STATUS | + ELINK_NIG_MASK_MI_INT)); + + /* Need to take the phy out of low power mode in order + * to write to access its registers + */ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); + + /* Reset the phy */ + elink_cl45_write(sc, &phy[port], + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); + } + + /* Add delay of 150ms after reset */ + DELAY(1000 * 150); + + if (phy[PORT_0].addr & 0x1) { + phy_blk[PORT_0] = &(phy[PORT_1]); + phy_blk[PORT_1] = &(phy[PORT_0]); + } else { + phy_blk[PORT_0] = &(phy[PORT_0]); + phy_blk[PORT_1] = &(phy[PORT_1]); + } + + /* PART2 - Download firmware to both phys */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + if (CHIP_IS_E1x(sc)) + port_of_path = port; + else + port_of_path = 0; + + PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x", + phy_blk[port]->addr); + if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], + port_of_path)) + return ELINK_STATUS_ERROR; + + /* Only set bit 10 = 1 (Tx power down) */ + elink_cl45_read(sc, phy_blk[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, &val); + + /* Phase1 of TX_POWER_DOWN reset */ + elink_cl45_write(sc, phy_blk[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10)); + } + + /* Toggle Transmitter: Power down and then up with 600ms delay + * between + */ + DELAY(1000 * 600); + + /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + /* Phase2 of POWER_DOWN_RESET */ + /* Release bit 10 (Release Tx power down) */ + elink_cl45_read(sc, phy_blk[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, &val); + + elink_cl45_write(sc, phy_blk[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, + (val & (~(1 << 10)))); + DELAY(1000 * 15); + + /* Read modify write the SPI-ROM version select register */ + elink_cl45_read(sc, phy_blk[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_EDC_FFE_MAIN, &val); + elink_cl45_write(sc, phy_blk[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12))); + + /* set GPIO2 back to LOW */ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + } + return ELINK_STATUS_OK; +} + +static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc, + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + __rte_unused uint32_t chip_id) +{ + uint32_t val; + int8_t port; + struct elink_phy phy; + /* Use port1 because of the static port-swap */ + /* Enable the module detection interrupt */ + val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN); + val |= ((1 << MISC_REGISTERS_GPIO_3) | + (1 << + (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); + REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); + + elink_ext_phy_hw_reset(sc, 0); + DELAY(1000 * 5); + for (port = 0; port < PORT_MAX; port++) { + uint32_t shmem_base, shmem2_base; + + /* In E2, same phy is using for port0 of the two paths */ + if (CHIP_IS_E1x(sc)) { + shmem_base = shmem_base_path[0]; + shmem2_base = shmem2_base_path[0]; + } else { + shmem_base = shmem_base_path[port]; + shmem2_base = shmem2_base_path[port]; + } + /* Extract the ext phy address for the port */ + if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, + port, &phy) != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "populate phy failed"); + return ELINK_STATUS_ERROR; + } + + /* Reset phy */ + elink_cl45_write(sc, &phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); + + /* Set fault module detected LED on */ + elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0, + MISC_REGISTERS_GPIO_HIGH, port); + } + + return ELINK_STATUS_OK; +} + +static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc, + uint32_t shmem_base, uint8_t * io_gpio, + uint8_t * io_port) +{ + + uint32_t phy_gpio_reset = REG_RD(sc, shmem_base + + offsetof(struct shmem_region, + dev_info. + port_hw_config[PORT_0]. + default_cfg)); + switch (phy_gpio_reset) { + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: + *io_gpio = 0; + *io_port = 0; + break; + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: + *io_gpio = 1; + *io_port = 0; + break; + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: + *io_gpio = 2; + *io_port = 0; + break; + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: + *io_gpio = 3; + *io_port = 0; + break; + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: + *io_gpio = 0; + *io_port = 1; + break; + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: + *io_gpio = 1; + *io_port = 1; + break; + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: + *io_gpio = 2; + *io_port = 1; + break; + case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: + *io_gpio = 3; + *io_port = 1; + break; + default: + /* Don't override the io_gpio and io_port */ + break; + } +} + +static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc, + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + __rte_unused uint32_t chip_id) +{ + int8_t port, reset_gpio; + uint32_t swap_val, swap_override; + struct elink_phy phy[PORT_MAX]; + struct elink_phy *phy_blk[PORT_MAX]; + int8_t port_of_path; + swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); + swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); + + reset_gpio = MISC_REGISTERS_GPIO_1; + port = 1; + + /* Retrieve the reset gpio/port which control the reset. + * Default is GPIO1, PORT1 + */ + elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0], + (uint8_t *) & reset_gpio, + (uint8_t *) & port); + + /* Calculate the port based on port swap */ + port ^= (swap_val && swap_override); + + /* Initiate PHY reset */ + elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, + port); + DELAY(1000 * 1); + elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, + port); + + DELAY(1000 * 5); + + /* PART1 - Reset both phys */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + uint32_t shmem_base, shmem2_base; + + /* In E2, same phy is using for port0 of the two paths */ + if (CHIP_IS_E1x(sc)) { + shmem_base = shmem_base_path[0]; + shmem2_base = shmem2_base_path[0]; + port_of_path = port; + } else { + shmem_base = shmem_base_path[port]; + shmem2_base = shmem2_base_path[port]; + port_of_path = 0; + } + + /* Extract the ext phy address for the port */ + if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, + port_of_path, &phy[port]) != + ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "populate phy failed"); + return ELINK_STATUS_ERROR; + } + /* disable attentions */ + elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + + port_of_path * 4, + (ELINK_NIG_MASK_XGXS0_LINK_STATUS | + ELINK_NIG_MASK_XGXS0_LINK10G | + ELINK_NIG_MASK_SERDES0_LINK_STATUS | + ELINK_NIG_MASK_MI_INT)); + + /* Reset the phy */ + elink_cl45_write(sc, &phy[port], + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); + } + + /* Add delay of 150ms after reset */ + DELAY(1000 * 150); + if (phy[PORT_0].addr & 0x1) { + phy_blk[PORT_0] = &(phy[PORT_1]); + phy_blk[PORT_1] = &(phy[PORT_0]); + } else { + phy_blk[PORT_0] = &(phy[PORT_0]); + phy_blk[PORT_1] = &(phy[PORT_1]); + } + /* PART2 - Download firmware to both phys */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + if (CHIP_IS_E1x(sc)) + port_of_path = port; + else + port_of_path = 0; + PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x", + phy_blk[port]->addr); + if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], + port_of_path)) + return ELINK_STATUS_ERROR; + /* Disable PHY transmitter output */ + elink_cl45_write(sc, phy_blk[port], + MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1); + + } + return ELINK_STATUS_OK; +} + +static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc, + uint32_t shmem_base_path[], + __rte_unused uint32_t + shmem2_base_path[], + __rte_unused uint8_t + phy_index, uint32_t chip_id) +{ + uint8_t reset_gpios; + reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id); + elink_cb_gpio_mult_write(sc, reset_gpios, + MISC_REGISTERS_GPIO_OUTPUT_LOW); + DELAY(10); + elink_cb_gpio_mult_write(sc, reset_gpios, + MISC_REGISTERS_GPIO_OUTPUT_HIGH); + PMD_DRV_LOG(DEBUG, "84833 reset pulse on pin values 0x%x", reset_gpios); + return ELINK_STATUS_OK; +} + +static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc, + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + uint32_t ext_phy_type, + uint32_t chip_id) +{ + elink_status_t rc = ELINK_STATUS_OK; + + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073: + rc = elink_8073_common_init_phy(sc, shmem_base_path, + shmem2_base_path, + phy_index, chip_id); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC: + rc = elink_8727_common_init_phy(sc, shmem_base_path, + shmem2_base_path, + phy_index, chip_id); + break; + + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: + /* GPIO1 affects both ports, so there's need to pull + * it for single port alone + */ + rc = elink_8726_common_init_phy(sc, shmem_base_path, + shmem2_base_path, + phy_index, chip_id); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834: + /* GPIO3's are linked, and so both need to be toggled + * to obtain required 2us pulse. + */ + rc = elink_84833_common_init_phy(sc, shmem_base_path, + shmem2_base_path, + phy_index, chip_id); + break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: + rc = ELINK_STATUS_ERROR; + break; + default: + PMD_DRV_LOG(DEBUG, + "ext_phy 0x%x common init not required", + ext_phy_type); + break; + } + + if (rc != ELINK_STATUS_OK) + elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized," + // " Port %d", + + return rc; +} + +elink_status_t elink_common_init_phy(struct bnx2x_softc * sc, + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint32_t chip_id, + __rte_unused uint8_t one_port_enabled) +{ + elink_status_t rc = ELINK_STATUS_OK; + uint32_t phy_ver, val; + uint8_t phy_index = 0; + uint32_t ext_phy_type, ext_phy_config; +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc)) + return ELINK_STATUS_OK; +#endif + + elink_set_mdio_clk(sc, GRCBASE_EMAC0); + elink_set_mdio_clk(sc, GRCBASE_EMAC1); + PMD_DRV_LOG(DEBUG, "Begin common phy init"); + if (CHIP_IS_E3(sc)) { + /* Enable EPIO */ + val = REG_RD(sc, MISC_REG_GEN_PURP_HWG); + REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1); + } + /* Check if common init was already done */ + phy_ver = REG_RD(sc, shmem_base_path[0] + + offsetof(struct shmem_region, + port_mb[PORT_0].ext_phy_fw_version)); + if (phy_ver) { + PMD_DRV_LOG(DEBUG, "Not doing common init; phy ver is 0x%x", + phy_ver); + return ELINK_STATUS_OK; + } + + /* Read the ext_phy_type for arbitrary port(0) */ + for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; + phy_index++) { + ext_phy_config = elink_get_ext_phy_config(sc, + shmem_base_path[0], + phy_index, 0); + ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); + rc |= elink_ext_phy_common_init(sc, shmem_base_path, + shmem2_base_path, + phy_index, ext_phy_type, + chip_id); + } + return rc; +} + +static void elink_check_over_curr(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t cfg_pin; + uint8_t port = params->port; + uint32_t pin_val; + + cfg_pin = (REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port]. + e3_cmn_pin_cfg1)) & + PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> + PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; + + /* Ignore check if no external input PIN available */ + if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK) + return; + + if (!pin_val) { + if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { + elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has" + // " been detected and the power to " + // "that SFP+ module has been removed" + // " to prevent failure of the card." + // " Please remove the SFP+ module and" + // " restart the system to clear this" + // " error.", + vars->phy_flags |= PHY_OVER_CURRENT_FLAG; + elink_warpcore_power_module(params, 0); + } + } else + vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; +} + +/* Returns 0 if no change occured since last check; 1 otherwise. */ +static uint8_t elink_analyze_link_error(struct elink_params *params, + struct elink_vars *vars, + uint32_t status, uint32_t phy_flag, + uint32_t link_flag, uint8_t notify) +{ + struct bnx2x_softc *sc = params->sc; + /* Compare new value with previous value */ + uint8_t led_mode; + uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0; + + if ((status ^ old_status) == 0) + return 0; + + /* If values differ */ + switch (phy_flag) { + case PHY_HALF_OPEN_CONN_FLAG: + PMD_DRV_LOG(DEBUG, "Analyze Remote Fault"); + break; + case PHY_SFP_TX_FAULT_FLAG: + PMD_DRV_LOG(DEBUG, "Analyze TX Fault"); + break; + default: + PMD_DRV_LOG(DEBUG, "Analyze UNKNOWN"); + } + PMD_DRV_LOG(DEBUG, "Link changed:[%x %x]->%x", vars->link_up, + old_status, status); + + /* a. Update shmem->link_status accordingly + * b. Update elink_vars->link_up + */ + if (status) { + vars->link_status &= ~LINK_STATUS_LINK_UP; + vars->link_status |= link_flag; + vars->link_up = 0; + vars->phy_flags |= phy_flag; + + /* activate nig drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1); + /* Set LED mode to off since the PHY doesn't know about these + * errors + */ + led_mode = ELINK_LED_MODE_OFF; + } else { + vars->link_status |= LINK_STATUS_LINK_UP; + vars->link_status &= ~link_flag; + vars->link_up = 1; + vars->phy_flags &= ~phy_flag; + led_mode = ELINK_LED_MODE_OPER; + + /* Clear nig drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + } + elink_sync_link(params, vars); + /* Update the LED according to the link state */ + elink_set_led(params, vars, led_mode, ELINK_SPEED_10000); + + /* Update link status in the shared memory */ + elink_update_mng(params, vars->link_status); + + /* C. Trigger General Attention */ + vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT; + if (notify) + elink_cb_notify_link_changed(sc); + + return 1; +} + +/****************************************************************************** +* Description: +* This function checks for half opened connection change indication. +* When such change occurs, it calls the elink_analyze_link_error +* to check if Remote Fault is set or cleared. Reception of remote fault +* status message in the MAC indicates that the peer's MAC has detected +* a fault, for example, due to break in the TX side of fiber. +* +******************************************************************************/ +static elink_status_t elink_check_half_open_conn(struct elink_params *params, + struct elink_vars *vars, + uint8_t notify) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t lss_status = 0; + uint32_t mac_base; + /* In case link status is physically up @ 10G do */ + if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || + (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4))) + return ELINK_STATUS_OK; + + if (CHIP_IS_E3(sc) && + (REG_RD(sc, MISC_REG_RESET_REG_2) & + (MISC_REGISTERS_RESET_REG_2_XMAC))) { + /* Check E3 XMAC */ + /* Note that link speed cannot be queried here, since it may be + * zero while link is down. In case UMAC is active, LSS will + * simply not be set + */ + mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + + /* Clear stick bits (Requires rising edge) */ + REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); + REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, + XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | + XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); + if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS)) + lss_status = 1; + + elink_analyze_link_error(params, vars, lss_status, + PHY_HALF_OPEN_CONN_FLAG, + LINK_STATUS_NONE, notify); + } else if (REG_RD(sc, MISC_REG_RESET_REG_2) & + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { + /* Check E1X / E2 BMAC */ + uint32_t lss_status_reg; + uint32_t wb_data[2]; + mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : + NIG_REG_INGRESS_BMAC0_MEM; + /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ + if (CHIP_IS_E2(sc)) + lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; + else + lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; + + REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2); + lss_status = (wb_data[0] > 0); + + elink_analyze_link_error(params, vars, lss_status, + PHY_HALF_OPEN_CONN_FLAG, + LINK_STATUS_NONE, notify); + } + return ELINK_STATUS_OK; +} + +static void elink_sfp_tx_fault_detection(struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t cfg_pin, value = 0; + uint8_t led_change, port = params->port; + + /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ + cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, + dev_info. + port_hw_config + [port]. + e3_cmn_pin_cfg)) & + PORT_HW_CFG_E3_TX_FAULT_MASK) >> + PORT_HW_CFG_E3_TX_FAULT_SHIFT; + + if (elink_get_cfg_pin(sc, cfg_pin, &value)) { + PMD_DRV_LOG(DEBUG, "Failed to read pin 0x%02x", cfg_pin); + return; + } + + led_change = elink_analyze_link_error(params, vars, value, + PHY_SFP_TX_FAULT_FLAG, + LINK_STATUS_SFP_TX_FAULT, 1); + + if (led_change) { + /* Change TX_Fault led, set link status for further syncs */ + uint8_t led_mode; + + if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { + led_mode = MISC_REGISTERS_GPIO_HIGH; + vars->link_status |= LINK_STATUS_SFP_TX_FAULT; + } else { + led_mode = MISC_REGISTERS_GPIO_LOW; + vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; + } + + /* If module is unapproved, led should be on regardless */ + if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { + PMD_DRV_LOG(DEBUG, "Change TX_Fault LED: ->%x", + led_mode); + elink_set_e3_module_fault_led(params, led_mode); + } + } +} + +static void elink_kr2_recovery(struct elink_params *params, + struct elink_vars *vars, struct elink_phy *phy) +{ + PMD_DRV_LOG(DEBUG, "KR2 recovery"); + + elink_warpcore_enable_AN_KR2(phy, params, vars); + elink_warpcore_restart_AN_KR(phy, params); +} + +static void elink_check_kr2_wa(struct elink_params *params, + struct elink_vars *vars, struct elink_phy *phy) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t base_page, next_page, not_kr2_device, lane; + int sigdet; + + /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery + * Since some switches tend to reinit the AN process and clear the + * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled + * and recovered many times + */ + if (vars->check_kr2_recovery_cnt > 0) { + vars->check_kr2_recovery_cnt--; + return; + } + + sigdet = elink_warpcore_get_sigdet(phy, params); + if (!sigdet) { + if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { + elink_kr2_recovery(params, vars, phy); + PMD_DRV_LOG(DEBUG, "No sigdet"); + } + return; + } + + lane = elink_get_warpcore_lane(params); + CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, + MDIO_AER_BLOCK_AER_REG, lane); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_LP_AUTO_NEG, &base_page); + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_LP_AUTO_NEG2, &next_page); + elink_set_aer_mmd(params, phy); + + /* CL73 has not begun yet */ + if (base_page == 0) { + if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { + elink_kr2_recovery(params, vars, phy); + PMD_DRV_LOG(DEBUG, "No BP"); + } + return; + } + + /* In case NP bit is not set in the BasePage, or it is set, + * but only KX is advertised, declare this link partner as non-KR2 + * device. + */ + not_kr2_device = (((base_page & 0x8000) == 0) || + (((base_page & 0x8000) && + ((next_page & 0xe0) == 0x2)))); + + /* In case KR2 is already disabled, check if we need to re-enable it */ + if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { + if (!not_kr2_device) { + PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, + next_page); + elink_kr2_recovery(params, vars, phy); + } + return; + } + /* KR2 is enabled, but not KR2 device */ + if (not_kr2_device) { + /* Disable KR2 on both lanes */ + PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, next_page); + elink_disable_kr2(params, vars, phy); + /* Restart AN on leading lane */ + elink_warpcore_restart_AN_KR(phy, params); + return; + } +} + +void elink_period_func(struct elink_params *params, struct elink_vars *vars) +{ + uint16_t phy_idx; + struct bnx2x_softc *sc = params->sc; + for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { + if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { + elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); + if (elink_check_half_open_conn(params, vars, 1) != + ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "Fault detection failed"); + } + break; + } + } + + if (CHIP_IS_E3(sc)) { + struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; + elink_set_aer_mmd(params, phy); + if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) && + (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) + elink_check_kr2_wa(params, vars, phy); + elink_check_over_curr(params, vars); + if (vars->rx_tx_asic_rst) + elink_warpcore_config_runtime(phy, params, vars); + + if ((REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port]. + default_cfg)) + & PORT_HW_CFG_NET_SERDES_IF_MASK) == + PORT_HW_CFG_NET_SERDES_IF_SFI) { + if (elink_is_sfp_module_plugged(params)) { + elink_sfp_tx_fault_detection(phy, params, vars); + } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) { + /* Clean trail, interrupt corrects the leds */ + vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; + vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; + /* Update link status in the shared memory */ + elink_update_mng(params, vars->link_status); + } + } + } +} + +uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, + uint32_t shmem_base, + uint32_t shmem2_base, uint8_t port) +{ + uint8_t phy_index, fan_failure_det_req = 0; + struct elink_phy phy; + for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; + phy_index++) { + if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, + port, &phy) + != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "populate phy failed"); + return 0; + } + fan_failure_det_req |= (phy.flags & + ELINK_FLAGS_FAN_FAILURE_DET_REQ); + } + return fan_failure_det_req; +} + +void elink_hw_reset_phy(struct elink_params *params) +{ + uint8_t phy_index; + struct bnx2x_softc *sc = params->sc; + elink_update_mng(params, 0); + elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4, + (ELINK_NIG_MASK_XGXS0_LINK_STATUS | + ELINK_NIG_MASK_XGXS0_LINK10G | + ELINK_NIG_MASK_SERDES0_LINK_STATUS | + ELINK_NIG_MASK_MI_INT)); + + for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) { + if (params->phy[phy_index].hw_reset) { + params->phy[phy_index].hw_reset(¶ms->phy[phy_index], + params); + params->phy[phy_index] = phy_null; + } + } +} + +void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars, + __rte_unused uint32_t chip_id, uint32_t shmem_base, + uint32_t shmem2_base, uint8_t port) +{ + uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index; + uint32_t val; + uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset; + if (CHIP_IS_E3(sc)) { + if (elink_get_mod_abs_int_cfg(sc, + shmem_base, + port, + &gpio_num, + &gpio_port) != ELINK_STATUS_OK) + return; + } else { + struct elink_phy phy; + for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; + phy_index++) { + if (elink_populate_phy(sc, phy_index, shmem_base, + shmem2_base, port, &phy) + != ELINK_STATUS_OK) { + PMD_DRV_LOG(DEBUG, "populate phy failed"); + return; + } + if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) { + gpio_num = MISC_REGISTERS_GPIO_3; + gpio_port = port; + break; + } + } + } + + if (gpio_num == 0xff) + return; + + /* Set GPIO3 to trigger SFP+ module insertion/removal */ + elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, + gpio_port); + + swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); + swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); + gpio_port ^= (swap_val && swap_override); + + vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << + (gpio_num + (gpio_port << 2)); + + sync_offset = shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port].aeu_int_mask); + REG_WR(sc, sync_offset, vars->aeu_int_mask); + + PMD_DRV_LOG(DEBUG, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x", + gpio_num, gpio_port, vars->aeu_int_mask); + + if (port == 0) + offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; + else + offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; + + /* Open appropriate AEU for interrupts */ + aeu_mask = REG_RD(sc, offset); + aeu_mask |= vars->aeu_int_mask; + REG_WR(sc, offset, aeu_mask); + + /* Enable the GPIO to trigger interrupt */ + val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN); + val |= 1 << (gpio_num + (gpio_port << 2)); + REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); +} diff --git a/lib/librte_pmd_bnx2x/elink.h b/lib/librte_pmd_bnx2x/elink.h new file mode 100644 index 0000000..eff40bf --- /dev/null +++ b/lib/librte_pmd_bnx2x/elink.h @@ -0,0 +1,609 @@ +/*- + * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. + * + * Eric Davis + * David Christensen + * Gary Zambrano + * + * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ELINK_H +#define ELINK_H + +#define ELINK_DEBUG + + + + + + +/***********************************************************/ +/* CLC Call backs functions */ +/***********************************************************/ +/* CLC device structure */ +struct bnx2x_softc; + +extern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr); +extern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val); + +/* mode - 0( LOW ) /1(HIGH)*/ +extern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc, + uint16_t gpio_num, + uint8_t mode, uint8_t port); +extern uint8_t elink_cb_gpio_mult_write(struct bnx2x_softc *sc, + uint8_t pins, + uint8_t mode); + +extern uint32_t elink_cb_gpio_read(struct bnx2x_softc *sc, uint16_t gpio_num, uint8_t port); +extern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc, + uint16_t gpio_num, + uint8_t mode, uint8_t port); + +extern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param); + +/* This function is called every 1024 bytes downloading of phy firmware. +Driver can use it to print to screen indication for download progress */ +extern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total); + +/* Each log type has its own parameters */ +typedef enum elink_log_id { + ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */ + ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */ + ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */ + ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */ + ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */ +}elink_log_id_t; + +typedef enum elink_status { + ELINK_STATUS_OK = 0, + ELINK_STATUS_ERROR, + ELINK_STATUS_TIMEOUT, + ELINK_STATUS_NO_LINK, + ELINK_STATUS_INVALID_IMAGE, + ELINK_OP_NOT_SUPPORTED = 122 +} elink_status_t; +extern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...); +extern void elink_cb_load_warpcore_microcode(void); + +extern void elink_cb_notify_link_changed(struct bnx2x_softc *sc); + +#define ELINK_EVENT_LOG_LEVEL_ERROR 1 +#define ELINK_EVENT_LOG_LEVEL_WARNING 2 +#define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1 +#define ELINK_EVENT_ID_SFP_POWER_FAULT 2 + +#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) +/* Debug prints */ + +/***********************************************************/ +/* Defines */ +/***********************************************************/ +#define ELINK_DEFAULT_PHY_DEV_ADDR 3 +#define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5 + + +#define DUPLEX_FULL 1 +#define DUPLEX_HALF 2 + +#define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO +#define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX +#define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX +#define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH +#define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE + +#define ELINK_NET_SERDES_IF_XFI 1 +#define ELINK_NET_SERDES_IF_SFI 2 +#define ELINK_NET_SERDES_IF_KR 3 +#define ELINK_NET_SERDES_IF_DXGXS 4 + +#define ELINK_SPEED_AUTO_NEG 0 +#define ELINK_SPEED_10 10 +#define ELINK_SPEED_100 100 +#define ELINK_SPEED_1000 1000 +#define ELINK_SPEED_2500 2500 +#define ELINK_SPEED_10000 10000 +#define ELINK_SPEED_20000 20000 + +#define ELINK_I2C_DEV_ADDR_A0 0xa0 +#define ELINK_I2C_DEV_ADDR_A2 0xa2 + +#define ELINK_SFP_EEPROM_PAGE_SIZE 16 +#define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14 +#define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16 +#define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25 +#define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3 +#define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28 +#define ELINK_SFP_EEPROM_PART_NO_SIZE 16 +#define ELINK_SFP_EEPROM_REVISION_ADDR 0x38 +#define ELINK_SFP_EEPROM_REVISION_SIZE 4 +#define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44 +#define ELINK_SFP_EEPROM_SERIAL_SIZE 16 +#define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ +#define ELINK_SFP_EEPROM_DATE_SIZE 6 +#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c +#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1 +#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2) +#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e +#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1 + +#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e +#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f + +#define ELINK_PWR_FLT_ERR_MSG_LEN 250 + +#define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \ + ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) +#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \ + (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ + PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) +#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \ + ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) + +/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ +#define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) +/* Single Media board contains single external phy */ +#define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2) +/* Dual Media board contains two external phy with different media */ +#define ELINK_DUAL_MEDIA(params) (params->num_phys == 3) + +#define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF +#define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00 +#define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 +#define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16 +#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ + ELINK_FW_PARAM_PHY_ADDR_MASK) +#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ + ELINK_FW_PARAM_PHY_TYPE_MASK) +#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ + ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \ + ELINK_FW_PARAM_MDIO_CTRL_OFFSET) +#define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ + (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET) + + +#define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 +#define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250 + +#define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) + +#define ELINK_BMAC_CONTROL_RX_ENABLE 2 +/***********************************************************/ +/* Structs */ +/***********************************************************/ +#define ELINK_INT_PHY 0 +#define ELINK_EXT_PHY1 1 +#define ELINK_EXT_PHY2 2 +#define ELINK_MAX_PHYS 3 + +/* Same configuration is shared between the XGXS and the first external phy */ +#define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1) +#define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \ + 0 : (_phy_idx - 1)) +/***********************************************************/ +/* elink_phy struct */ +/* Defines the required arguments and function per phy */ +/***********************************************************/ +struct elink_vars; +struct elink_params; +struct elink_phy; + +typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params, + struct elink_vars *vars); +typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params, + struct elink_vars *vars); +typedef void (*link_reset_t)(struct elink_phy *phy, + struct elink_params *params); +typedef void (*config_loopback_t)(struct elink_phy *phy, + struct elink_params *params); +typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len); +typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params); +typedef void (*set_link_led_t)(struct elink_phy *phy, + struct elink_params *params, uint8_t mode); +typedef void (*phy_specific_func_t)(struct elink_phy *phy, + struct elink_params *params, uint32_t action); +struct elink_reg_set { + uint8_t devad; + uint16_t reg; + uint16_t val; +}; + +struct elink_phy { + uint32_t type; + + /* Loaded during init */ + uint8_t addr; + uint8_t def_md_devad; + uint16_t flags; + /* No Over-Current detection */ +#define ELINK_FLAGS_NOC (1<<1) + /* Fan failure detection required */ +#define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2) + /* Initialize first the XGXS and only then the phy itself */ +#define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3) +#define ELINK_FLAGS_WC_DUAL_MODE (1<<4) +#define ELINK_FLAGS_4_PORT_MODE (1<<5) +#define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6) +#define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7) +#define ELINK_FLAGS_MDC_MDIO_WA (1<<8) +#define ELINK_FLAGS_DUMMY_READ (1<<9) +#define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10) +#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11) +#define ELINK_FLAGS_TX_ERROR_CHECK (1<<12) +#define ELINK_FLAGS_EEE (1<<13) +#define ELINK_FLAGS_TEMPERATURE (1<<14) +#define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15) + + /* preemphasis values for the rx side */ + uint16_t rx_preemphasis[4]; + + /* preemphasis values for the tx side */ + uint16_t tx_preemphasis[4]; + + /* EMAC address for access MDIO */ + uint32_t mdio_ctrl; + + uint32_t supported; +#define ELINK_SUPPORTED_10baseT_Half (1<<0) +#define ELINK_SUPPORTED_10baseT_Full (1<<1) +#define ELINK_SUPPORTED_100baseT_Half (1<<2) +#define ELINK_SUPPORTED_100baseT_Full (1<<3) +#define ELINK_SUPPORTED_1000baseT_Full (1<<4) +#define ELINK_SUPPORTED_2500baseX_Full (1<<5) +#define ELINK_SUPPORTED_10000baseT_Full (1<<6) +#define ELINK_SUPPORTED_TP (1<<7) +#define ELINK_SUPPORTED_FIBRE (1<<8) +#define ELINK_SUPPORTED_Autoneg (1<<9) +#define ELINK_SUPPORTED_Pause (1<<10) +#define ELINK_SUPPORTED_Asym_Pause (1<<11) +#define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21) +#define ELINK_SUPPORTED_20000baseKR2_Full (1<<22) + + uint32_t media_type; +#define ELINK_ETH_PHY_UNSPECIFIED 0x0 +#define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1 +#define ELINK_ETH_PHY_XFP_FIBER 0x2 +#define ELINK_ETH_PHY_DA_TWINAX 0x3 +#define ELINK_ETH_PHY_BASE_T 0x4 +#define ELINK_ETH_PHY_SFP_1G_FIBER 0x5 +#define ELINK_ETH_PHY_KR 0xf0 +#define ELINK_ETH_PHY_CX4 0xf1 +#define ELINK_ETH_PHY_NOT_PRESENT 0xff + + /* The address in which version is located*/ + uint32_t ver_addr; + + uint16_t req_flow_ctrl; + + uint16_t req_line_speed; + + uint32_t speed_cap_mask; + + uint16_t req_duplex; + uint16_t rsrv; + /* Called per phy/port init, and it configures LASI, speed, autoneg, + duplex, flow control negotiation, etc. */ + config_init_t config_init; + + /* Called due to interrupt. It determines the link, speed */ + read_status_t read_status; + + /* Called when driver is unloading. Should reset the phy */ + link_reset_t link_reset; + + /* Set the loopback configuration for the phy */ + config_loopback_t config_loopback; + + /* Format the given raw number into str up to len */ + format_fw_ver_t format_fw_ver; + + /* Reset the phy (both ports) */ + hw_reset_t hw_reset; + + /* Set link led mode (on/off/oper)*/ + set_link_led_t set_link_led; + + /* PHY Specific tasks */ + phy_specific_func_t phy_specific_func; +#define ELINK_DISABLE_TX 1 +#define ELINK_ENABLE_TX 2 +#define ELINK_PHY_INIT 3 +}; + +/* Inputs parameters to the CLC */ +struct elink_params { + + uint8_t port; + + /* Default / User Configuration */ + uint8_t loopback_mode; +#define ELINK_LOOPBACK_NONE 0 +#define ELINK_LOOPBACK_EMAC 1 +#define ELINK_LOOPBACK_BMAC 2 +#define ELINK_LOOPBACK_XGXS 3 +#define ELINK_LOOPBACK_EXT_PHY 4 +#define ELINK_LOOPBACK_EXT 5 +#define ELINK_LOOPBACK_UMAC 6 +#define ELINK_LOOPBACK_XMAC 7 + + /* Device parameters */ + uint8_t mac_addr[6]; + + uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE]; + uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE]; + + uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ + + /* shmem parameters */ + uint32_t shmem_base; + uint32_t shmem2_base; + uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; + uint32_t switch_cfg; +#define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH +#define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH +#define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT + + uint32_t lane_config; + + /* Phy register parameter */ + uint32_t chip_id; + + /* features */ + uint32_t feature_config_flags; +#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) +#define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1) +#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) +#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) +#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4) +#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5) +#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6) +#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7) +#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8) +#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9) +#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10) +#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11) +#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12) +#define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13) +#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14) + + /* Will be populated during common init */ + struct elink_phy phy[ELINK_MAX_PHYS]; + + /* Will be populated during common init */ + uint8_t num_phys; + + uint8_t rsrv; + + /* Used to configure the EEE Tx LPI timer, has several modes of + * operation, according to bits 29:28 - + * 2'b00: Timer will be configured by nvram, output will be the value + * from nvram. + * 2'b01: Timer will be configured by nvram, output will be in + * microseconds. + * 2'b10: bits 1:0 contain an nvram value which will be used instead + * of the one located in the nvram. Output will be that value. + * 2'b11: bits 19:0 contain the idle timer in microseconds; output + * will be in microseconds. + * Bits 31:30 should be 2'b11 in order for EEE to be enabled. + */ + uint32_t eee_mode; +#define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00) +#define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100) +#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000) +#define ELINK_EEE_MODE_NVRAM_MASK (0x3) +#define ELINK_EEE_MODE_TIMER_MASK (0xfffff) +#define ELINK_EEE_MODE_OUTPUT_TIME (1<<28) +#define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29) +#define ELINK_EEE_MODE_ENABLE_LPI (1<<30) +#define ELINK_EEE_MODE_ADV_LPI (1<<31) + + uint16_t hw_led_mode; /* part of the hw_config read from the shmem */ + uint32_t multi_phy_config; + + /* Device pointer passed to all callback functions */ + struct bnx2x_softc *sc; + uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when + req_flow_ctrl is set to AUTO */ + uint16_t link_flags; +#define ELINK_LINK_FLAGS_INT_DISABLED (1<<0) +#define ELINK_PHY_INITIALIZED (1<<1) + uint32_t lfa_base; +}; + +/* Output parameters */ +struct elink_vars { + uint8_t phy_flags; +#define PHY_XGXS_FLAG (1<<0) +#define PHY_SGMII_FLAG (1<<1) +#define PHY_PHYSICAL_LINK_FLAG (1<<2) +#define PHY_HALF_OPEN_CONN_FLAG (1<<3) +#define PHY_OVER_CURRENT_FLAG (1<<4) +#define PHY_SFP_TX_FAULT_FLAG (1<<5) + + uint8_t mac_type; +#define ELINK_MAC_TYPE_NONE 0 +#define ELINK_MAC_TYPE_EMAC 1 +#define ELINK_MAC_TYPE_BMAC 2 +#define ELINK_MAC_TYPE_UMAC 3 +#define ELINK_MAC_TYPE_XMAC 4 + + uint8_t phy_link_up; /* internal phy link indication */ + uint8_t link_up; + + uint16_t line_speed; + uint16_t duplex; + + uint16_t flow_ctrl; + uint16_t ieee_fc; + + /* The same definitions as the shmem parameter */ + uint32_t link_status; + uint32_t eee_status; + uint8_t fault_detected; + uint8_t check_kr2_recovery_cnt; +#define ELINK_CHECK_KR2_RECOVERY_CNT 5 + uint16_t periodic_flags; +#define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001 + + uint32_t aeu_int_mask; + uint8_t rx_tx_asic_rst; + uint8_t turn_to_run_wc_rt; + uint16_t rsrv2; + /* The same definitions as the shmem2 parameter */ + uint32_t link_attr_sync; +}; + +/***********************************************************/ +/* Functions */ +/***********************************************************/ +elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars); + +/* Reset the link. Should be called when driver or interface goes down + Before calling phy firmware upgrade, the reset_ext_phy should be set + to 0 */ +elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars); +/* elink_link_update should be called upon link interrupt */ +elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars); + +/* Reads the link_status from the shmem, + and update the link vars accordingly */ +void elink_link_status_update(struct elink_params *input, + struct elink_vars *output); + +/* Set/Unset the led + Basically, the CLC takes care of the led for the link, but in case one needs + to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to + blink the led, and ELINK_LED_MODE_OFF to set the led off.*/ +elink_status_t elink_set_led(struct elink_params *params, + struct elink_vars *vars, uint8_t mode, uint32_t speed); +#define ELINK_LED_MODE_OFF 0 +#define ELINK_LED_MODE_ON 1 +#define ELINK_LED_MODE_OPER 2 +#define ELINK_LED_MODE_FRONT_PANEL_OFF 3 + +/* elink_handle_module_detect_int should be called upon module detection + interrupt */ +void elink_handle_module_detect_int(struct elink_params *params); + +/* One-time initialization for external phy after power up */ +elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled); + +void elink_hw_reset_phy(struct elink_params *params); + +/* Check swap bit and adjust PHY order */ +uint32_t elink_phy_selection(struct elink_params *params); + +/* Probe the phys on board, and populate them in "params" */ +elink_status_t elink_phy_probe(struct elink_params *params); + +/* Checks if fan failure detection is required on one of the phys on board */ +uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, uint32_t shmem_base, + uint32_t shmem2_base, uint8_t port); + +/* Open / close the gate between the NIG and the BRB */ +void elink_set_rx_filter(struct elink_params *params, uint8_t en); + +/* DCBX structs */ + +/* Number of maximum COS per chip */ +#define ELINK_DCBX_E2E3_MAX_NUM_COS (2) +#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6) +#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3) +#define ELINK_DCBX_E3B0_MAX_NUM_COS ( \ + ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \ + ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1)) + +#define ELINK_DCBX_MAX_NUM_COS ( \ + ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \ + ELINK_DCBX_E2E3_MAX_NUM_COS)) + +/* PFC port configuration params */ +struct elink_nig_brb_pfc_port_params { + /* NIG */ + uint32_t pause_enable; + uint32_t llfc_out_en; + uint32_t llfc_enable; + uint32_t pkt_priority_to_cos; + uint8_t num_of_rx_cos_priority_mask; + uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS]; + uint32_t llfc_high_priority_classes; + uint32_t llfc_low_priority_classes; +}; + + +/* ETS port configuration params */ +struct elink_ets_bw_params { + uint8_t bw; +}; + +struct elink_ets_sp_params { + /** + * valid values are 0 - 5. 0 is highest strict priority. + * There can't be two COS's with the same pri. + */ + uint8_t pri; +}; + +enum elink_cos_state { + elink_cos_state_strict = 0, + elink_cos_state_bw = 1, +}; + +struct elink_ets_cos_params { + enum elink_cos_state state ; + union { + struct elink_ets_bw_params bw_params; + struct elink_ets_sp_params sp_params; + } params; +}; + +struct elink_ets_params { + uint8_t num_of_cos; /* Number of valid COS entries*/ + struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS]; +}; + +/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB + * when link is already up + */ +elink_status_t elink_update_pfc(struct elink_params *params, + struct elink_vars *vars, + struct elink_nig_brb_pfc_port_params *pfc_params); + +void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars, + uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base, + uint8_t port); + +void elink_period_func(struct elink_params *params, struct elink_vars *vars); + +void elink_enable_pmd_tx(struct elink_params *params); + + + +#endif /* ELINK_H */ -- 2.1.4