From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 5289FC32A for ; Fri, 5 Jun 2015 07:22:44 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 04 Jun 2015 22:22:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,556,1427785200"; d="scan'208";a="582505475" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga003.jf.intel.com with ESMTP; 04 Jun 2015 22:22:43 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t555MfQg032668; Fri, 5 Jun 2015 13:22:41 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t555McVZ024407; Fri, 5 Jun 2015 13:22:40 +0800 Received: (from wenzhuol@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t555McTo024403; Fri, 5 Jun 2015 13:22:38 +0800 From: Wenzhuo Lu To: dev@dpdk.org Date: Fri, 5 Jun 2015 13:21:49 +0800 Message-Id: <1433481718-24253-18-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1433481718-24253-1-git-send-email-wenzhuo.lu@intel.com> References: <1433481718-24253-1-git-send-email-wenzhuo.lu@intel.com> Subject: [dpdk-dev] [PATCH 17/26] ixgbe/base: new simplified x550em init flow X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Jun 2015 05:22:45 -0000 The init flow is simplified. We no longer wait for the PHY FW init complete bit to be set as this bit is only set once by the PHY at power on and then cleared on the first read. So only the first instance of running SW (or possibly MAC FW) needs to initialize the PHY. The PHY initialization has been simplified and now only requires that the PHY FW be "un-stalled". SW no longer needs to put the PHY in low-power mode or enable the transceiver. Signed-off-by: Wenzhuo Lu --- drivers/net/ixgbe/base/ixgbe_x550.c | 85 +++++++++---------------------------- 1 file changed, 19 insertions(+), 66 deletions(-) diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index 34ea26f..a321594 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -1293,84 +1293,37 @@ s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) { u32 status; u16 reg; - u32 retries = 1; - - /* TODO: The number of attempts and delay between attempts is undefined */ - do { - /* decrement retries counter and exit if we hit 0 */ - if (retries < 1) { - ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, - "External PHY not yet finished resetting."); - return IXGBE_ERR_PHY; - } - retries--; - - usec_delay(0); - - status = hw->phy.ops.read_reg(hw, - IXGBE_MDIO_TX_VENDOR_ALARMS_3, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - ®); - - if (status != IXGBE_SUCCESS) - return status; - - /* Verify PHY FW reset has completed */ - } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1); - /* Set port to low power mode */ status = hw->phy.ops.read_reg(hw, - IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, - ®); - - if (status != IXGBE_SUCCESS) - return status; - - reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; - - status = hw->phy.ops.write_reg(hw, - IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, - reg); - - if (status != IXGBE_SUCCESS) - return status; - - /* Enable the transmitter */ - status = hw->phy.ops.read_reg(hw, - IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR, + IXGBE_MDIO_TX_VENDOR_ALARMS_3, IXGBE_MDIO_PMA_PMD_DEV_TYPE, ®); if (status != IXGBE_SUCCESS) return status; - reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE; - - status = hw->phy.ops.write_reg(hw, - IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - reg); - - if (status != IXGBE_SUCCESS) - return status; + /* If PHY FW reset completed bit is set then this is the first + * SW instance after a power on so the PHY FW must be un-stalled. + */ + if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { + status = hw->phy.ops.read_reg(hw, + IXGBE_MDIO_GLOBAL_RES_PR_10, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + ®); - /* Un-stall the PHY FW */ - status = hw->phy.ops.read_reg(hw, - IXGBE_MDIO_GLOBAL_RES_PR_10, - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, - ®); + if (status != IXGBE_SUCCESS) + return status; - if (status != IXGBE_SUCCESS) - return status; + reg &= ~IXGBE_MDIO_POWER_UP_STALL; - reg &= ~IXGBE_MDIO_POWER_UP_STALL; + status = hw->phy.ops.write_reg(hw, + IXGBE_MDIO_GLOBAL_RES_PR_10, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + reg); - status = hw->phy.ops.write_reg(hw, - IXGBE_MDIO_GLOBAL_RES_PR_10, - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, - reg); + if (status != IXGBE_SUCCESS) + return status; + } return status; } -- 1.9.3