From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from sclab-apps-2.localdomain (sc-fw1.tilera.com [12.218.212.162]) by dpdk.org (Postfix) with ESMTP id EC616C8D2 for ; Fri, 19 Jun 2015 21:15:10 +0200 (CEST) X-CheckPoint: {55846A3E-1-A3D4DA0C-C0000002} Received: by sclab-apps-2.localdomain (Postfix, from userid 1318) id 4432F22048B; Fri, 19 Jun 2015 12:15:10 -0700 (PDT) From: Cyril Chemparathy To: dev@dpdk.org Date: Fri, 19 Jun 2015 12:14:58 -0700 Message-Id: <1434741309-22415-1-git-send-email-cchemparathy@ezchip.com> X-Mailer: git-send-email 2.1.2 Subject: [dpdk-dev] [PATCH 00/11] Introducing the TILE-Gx platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Jun 2015 19:15:21 -0000 This series adds support for the EZchip TILE-Gx family of SoCs. The architecture port in itself is fairly straight forward due to its reliance on generics for the most part. In addition to adding TILE-Gx architecture specific code, this series includes a few cross-platform fixes for DPDK (cpuflags, SSE related, etc.), as well as minor extensions to to accomodate a wider range of hugepage sizes and configurable mempool element alignment boundaries. Cyril Chemparathy (11): test: limit x86 cpuflags checks to x86 builds hash: fix compilation on non-X86 platforms hash: check SSE flags only on x86 builds eal: allow empty compile time flags memzone: refactor rte_memzone_reserve() variants memzone: allow multiple pagesizes to be requested mempool: allow config override on element alignment tile: add page sizes for TILE-Gx/Mx platforms tile: initial TILE-Gx support. tile: Add TILE-Gx mPIPE poll mode driver. maintainers: claim responsibility for TILE-Gx platform MAINTAINERS | 4 + app/test/test_cpuflags.c | 6 +- config/defconfig_tile-tilegx-linuxapp-gcc | 73 + drivers/net/Makefile | 1 + drivers/net/mpipe/Makefile | 46 + drivers/net/mpipe/mpipe_tilegx.c | 1641 ++++++++++++++++++++ lib/librte_eal/common/eal_common_cpuflags.c | 5 +- lib/librte_eal/common/eal_common_memzone.c | 141 +- .../common/include/arch/tile/rte_atomic.h | 86 + .../common/include/arch/tile/rte_byteorder.h | 91 ++ .../common/include/arch/tile/rte_cpuflags.h | 85 + .../common/include/arch/tile/rte_cycles.h | 70 + .../common/include/arch/tile/rte_memcpy.h | 93 ++ .../common/include/arch/tile/rte_prefetch.h | 61 + .../common/include/arch/tile/rte_rwlock.h | 70 + .../common/include/arch/tile/rte_spinlock.h | 92 ++ lib/librte_eal/common/include/rte_memory.h | 16 +- lib/librte_eal/common/include/rte_memzone.h | 50 +- lib/librte_hash/rte_hash_crc.h | 2 + lib/librte_hash/rte_jhash.h | 3 +- lib/librte_mempool/rte_mempool.c | 16 +- lib/librte_mempool/rte_mempool.h | 6 + mk/arch/tile/rte.vars.mk | 39 + mk/machine/tilegx/rte.vars.mk | 57 + mk/rte.app.mk | 1 + 25 files changed, 2645 insertions(+), 110 deletions(-) create mode 100644 config/defconfig_tile-tilegx-linuxapp-gcc create mode 100644 drivers/net/mpipe/Makefile create mode 100644 drivers/net/mpipe/mpipe_tilegx.c create mode 100644 lib/librte_eal/common/include/arch/tile/rte_atomic.h create mode 100644 lib/librte_eal/common/include/arch/tile/rte_byteorder.h create mode 100644 lib/librte_eal/common/include/arch/tile/rte_cpuflags.h create mode 100644 lib/librte_eal/common/include/arch/tile/rte_cycles.h create mode 100644 lib/librte_eal/common/include/arch/tile/rte_memcpy.h create mode 100644 lib/librte_eal/common/include/arch/tile/rte_prefetch.h create mode 100644 lib/librte_eal/common/include/arch/tile/rte_rwlock.h create mode 100644 lib/librte_eal/common/include/arch/tile/rte_spinlock.h create mode 100644 mk/arch/tile/rte.vars.mk create mode 100644 mk/machine/tilegx/rte.vars.mk -- 2.1.2