DPDK patches and discussions
 help / color / mirror / Atom feed
From: Wenzhuo Lu <wenzhuo.lu@intel.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH 28/37] ixgbe/base: add new mac-dependent values for x540, x550
Date: Wed, 24 Jun 2015 11:26:17 +0800	[thread overview]
Message-ID: <1435116386-12010-29-git-send-email-wenzhuo.lu@intel.com> (raw)
In-Reply-To: <1435116386-12010-1-git-send-email-wenzhuo.lu@intel.com>

Add new values that vary by MAC type that are introduced in
x540, x550.
And remove some meaningless comments BTW.

Please note this patch hits a checkpatch errror.
"ERROR: Macros with complex values should be enclosed in parentheses
 #105: FILE: drivers/net/ixgbe/base/ixgbe_type.h:3337:"
We think it's not an error and the checkpatch is overly aggressive.
If we add the parentheses, it will broke our code and make it cannot
be compiled. We should ignore this error safely enough.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
---
 drivers/net/ixgbe/base/ixgbe_type.h | 72 ++++++++++++++++++++++++++++++-------
 1 file changed, 59 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index d4a91d8..74b76e2 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -166,18 +166,40 @@ POSSIBILITY OF SUCH DAMAGE.
 #define IXGBE_EXVET		0x05078
 
 /* NVM Registers */
-#define IXGBE_EEC	0x10010
-#define IXGBE_EERD	0x10014
-#define IXGBE_EEWR	0x10018
-#define IXGBE_FLA	0x1001C
+#define IXGBE_EEC		0x10010
+#define IXGBE_EEC_X540		IXGBE_EEC
+#define IXGBE_EEC_X550		IXGBE_EEC
+#define IXGBE_EEC_X550EM_x	IXGBE_EEC
+#define IXGBE_EEC_BY_MAC(_hw)	IXGBE_EEC
+
+#define IXGBE_EERD		0x10014
+#define IXGBE_EEWR		0x10018
+
+#define IXGBE_FLA		0x1001C
+#define IXGBE_FLA_X540		IXGBE_FLA
+#define IXGBE_FLA_X550		IXGBE_FLA
+#define IXGBE_FLA_X550EM_x	IXGBE_FLA
+#define IXGBE_FLA_BY_MAC(_hw)	IXGBE_FLA
+
 #define IXGBE_EEMNGCTL	0x10110
 #define IXGBE_EEMNGDATA	0x10114
 #define IXGBE_FLMNGCTL	0x10118
 #define IXGBE_FLMNGDATA	0x1011C
 #define IXGBE_FLMNGCNT	0x10120
 #define IXGBE_FLOP	0x1013C
-#define IXGBE_GRC	0x10200
-#define IXGBE_SRAMREL	0x10210
+
+#define IXGBE_GRC		0x10200
+#define IXGBE_GRC_X540		IXGBE_GRC
+#define IXGBE_GRC_X550		IXGBE_GRC
+#define IXGBE_GRC_X550EM_x	IXGBE_GRC
+#define IXGBE_GRC_BY_MAC(_hw)	IXGBE_GRC
+
+#define IXGBE_SRAMREL		0x10210
+#define IXGBE_SRAMREL_X540	IXGBE_SRAMREL
+#define IXGBE_SRAMREL_X550	IXGBE_SRAMREL
+#define IXGBE_SRAMREL_X550EM_x	IXGBE_SRAMREL
+#define IXGBE_SRAMREL_BY_MAC(_hw)	IXGBE_SRAMREL
+
 #define IXGBE_PHYDBG	0x10218
 
 /* General Receive Control */
@@ -1038,14 +1060,34 @@ struct ixgbe_dmac_config {
 #define IXGBE_GSCN_2		0x11028
 #define IXGBE_GSCN_3		0x1102C
 #define IXGBE_FACTPS		0x10150
+#define IXGBE_FACTPS_X540	IXGBE_FACTPS
+#define IXGBE_FACTPS_X550	IXGBE_FACTPS
+#define IXGBE_FACTPS_X550EM_x	IXGBE_FACTPS
+#define IXGBE_FACTPS_BY_MAC(_hw)	IXGBE_FACTPS
+
 #define IXGBE_PCIEANACTL	0x11040
 #define IXGBE_SWSM		0x10140
+#define IXGBE_SWSM_X540		IXGBE_SWSM
+#define IXGBE_SWSM_X550		IXGBE_SWSM
+#define IXGBE_SWSM_X550EM_x	IXGBE_SWSM
+#define IXGBE_SWSM_BY_MAC(_hw)	IXGBE_SWSM
+
 #define IXGBE_FWSM		0x10148
+#define IXGBE_FWSM_X540		IXGBE_FWSM
+#define IXGBE_FWSM_X550		IXGBE_FWSM
+#define IXGBE_FWSM_X550EM_x	IXGBE_FWSM
+#define IXGBE_FWSM_BY_MAC(_hw)	IXGBE_FWSM
+
+#define IXGBE_SWFW_SYNC		IXGBE_GSSR
+#define IXGBE_SWFW_SYNC_X540	IXGBE_SWFW_SYNC
+#define IXGBE_SWFW_SYNC_X550	IXGBE_SWFW_SYNC
+#define IXGBE_SWFW_SYNC_X550EM_x	IXGBE_SWFW_SYNC
+#define IXGBE_SWFW_SYNC_BY_MAC(_hw)	IXGBE_SWFW_SYNC
+
 #define IXGBE_GSSR		0x10160
 #define IXGBE_MREVID		0x11064
 #define IXGBE_DCA_ID		0x11070
 #define IXGBE_DCA_CTRL		0x11074
-#define IXGBE_SWFW_SYNC		IXGBE_GSSR
 
 /* PCI-E registers 82599-Specific */
 #define IXGBE_GCR_EXT		0x11050
@@ -3291,7 +3333,16 @@ union ixgbe_atr_hash_dword {
 	__be32 dword;
 };
 
-#define IXGBE_MVALS_INIT(m)    \
+
+#define IXGBE_MVALS_INIT(m)	\
+	IXGBE_CAT(EEC, m),		\
+	IXGBE_CAT(FLA, m),		\
+	IXGBE_CAT(GRC, m),		\
+	IXGBE_CAT(SRAMREL, m),		\
+	IXGBE_CAT(FACTPS, m),		\
+	IXGBE_CAT(SWSM, m),		\
+	IXGBE_CAT(SWFW_SYNC, m),	\
+	IXGBE_CAT(FWSM, m),		\
 	IXGBE_CAT(SDP0_GPIEN, m),	\
 	IXGBE_CAT(SDP1_GPIEN, m),	\
 	IXGBE_CAT(SDP2_GPIEN, m),	\
@@ -3339,11 +3390,6 @@ enum ixgbe_mac_type {
 	ixgbe_mac_82599_vf,
 	ixgbe_mac_X540,
 	ixgbe_mac_X540_vf,
-	/*
-	 * X550EM MAC type decoder:
-	 * ixgbe_mac_X550EM_x: "x" = Xeon
-	 * ixgbe_mac_X550EM_a: "a" = Atom
-	 */
 	ixgbe_mac_X550,
 	ixgbe_mac_X550EM_x,
 	ixgbe_mac_X550_vf,
-- 
1.9.3

  parent reply	other threads:[~2015-06-24  3:27 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-24  3:25 [dpdk-dev] [PATCH 00/37] update ixgbe base driver Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 01/37] ixgbe/base: update readme Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 02/37] ixgbe/base: update Low Power Link Up to use MAC ops link Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 03/37] ixgbe/base: fix 1G and 10G link stability for x550em SFP+ Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 04/37] ixgbe/base: update x550em SFP link setup Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 05/37] ixgbe/base: add shift define for EEE_SU.TEEE_DLY Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 06/37] ixgbe/base: add x550em identify SFP module support Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 07/37] ixgbe/base: fix potential warning Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 08/37] ixgbe/base: return err when SFP module is not present Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 09/37] ixgbe/base: power down the x550em PHY on overtemp events Wenzhuo Lu
2015-06-24  3:25 ` [dpdk-dev] [PATCH 10/37] ixgbe/base: restore advertised autoneg after setting LPLU Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 11/37] ixgbe/base: fix UniPHY link configuration Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 12/37] ixgbe/base: add macro for x550em bus speed fuse Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 13/37] ixgbe/base: add a new 82599 device ID Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 14/37] ixgbe/base: enable FEC when EEE is disabled Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 15/37] ixgbe/base: release semaphores in proper order Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 16/37] ixgbe/base: add wait helper for IOSF accesses Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 17/37] ixgbe/base: use a semaphore to serialize " Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 18/37] ixgbe/base: check for functional ucode Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 19/37] ixgbe/base: add KR/iXFI internal link mode support Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 20/37] ixgbe/base: check link again after getting speed Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 21/37] ixgbe/base: config MDIO clock for x550em Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 22/37] ixgbe/base: add support for led_on and led_off for X557 PHY LEDs Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 23/37] ixgbe/base: update EEE/FEC support for device X550EM_X_KR Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 24/37] ixgbe/base: introduce array of mac-type-dependent values Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 25/37] ixgbe/base: use mvals array for I2C_*_BY_MAC values Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 26/37] ixgbe/base: use mvals array for *_GPI*_BY_MAC values Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 27/37] ixgbe/base: use mvals array for CIA*_BY_MAC values Wenzhuo Lu
2015-06-24  3:26 ` Wenzhuo Lu [this message]
2015-06-24  3:26 ` [dpdk-dev] [PATCH 29/37] ixgbe/base: disable SW LPLU implementation for x557 V2 Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 30/37] ixgbe/base: remove FEC disablement for x550em Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 31/37] ixgbe/base: modify register definition code style Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 32/37] ixgbe/base: specific process for X550 and X550em when disabling PCIe master Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 33/37] ixgbe/base: fix flow control to be KR only Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 34/37] ixgbe/base: fix 5G and 2.5G speed description Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 35/37] ixgbe/base: force cs4227 LINE side to 10G SR mode Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 36/37] ixgbe/base: a minor optimization for max link up time Wenzhuo Lu
2015-06-24  3:26 ` [dpdk-dev] [PATCH 37/37] ixgbe/base: add support for new x550 PHY IDs Wenzhuo Lu
2015-06-25  1:24 ` [dpdk-dev] [PATCH 00/37] update ixgbe base driver Zhang, Helin
2015-06-26 11:27   ` Thomas Monjalon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1435116386-12010-29-git-send-email-wenzhuo.lu@intel.com \
    --to=wenzhuo.lu@intel.com \
    --cc=dev@dpdk.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).