From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <jmcnam2x@ecsmtp.ir.intel.com>
Received: from mga03.intel.com (mga03.intel.com [134.134.136.65])
by dpdk.org (Postfix) with ESMTP id AA05E5A59
for <dev@dpdk.org>; Thu, 2 Jul 2015 17:16:59 +0200 (CEST)
Received: from fmsmga002.fm.intel.com ([10.253.24.26])
by orsmga103.jf.intel.com with ESMTP; 02 Jul 2015 08:16:57 -0700
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.15,393,1432623600"; d="scan'208";a="754861335"
Received: from irvmail001.ir.intel.com ([163.33.26.43])
by fmsmga002.fm.intel.com with ESMTP; 02 Jul 2015 08:16:53 -0700
Received: from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com
[10.237.217.46])
by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id
t62FGp2B018925; Thu, 2 Jul 2015 16:16:51 +0100
Received: from sivswdev02.ir.intel.com (localhost [127.0.0.1])
by sivswdev02.ir.intel.com with ESMTP id t62FGpq8007088;
Thu, 2 Jul 2015 16:16:51 +0100
Received: (from jmcnam2x@localhost)
by sivswdev02.ir.intel.com with id t62FGpks007084;
Thu, 2 Jul 2015 16:16:51 +0100
From: John McNamara <john.mcnamara@intel.com>
To: dev@dpdk.org
Date: Thu, 2 Jul 2015 16:16:30 +0100
Message-Id: <1435850194-7024-4-git-send-email-john.mcnamara@intel.com>
X-Mailer: git-send-email 1.7.4.1
In-Reply-To: <1435850194-7024-1-git-send-email-john.mcnamara@intel.com>
References: <1435585344-26652-1-git-send-email-john.mcnamara@intel.com>
<1435850194-7024-1-git-send-email-john.mcnamara@intel.com>
Subject: [dpdk-dev] [PATCH v3 3/7] ixgbe: add support for ieee1588
timestamping
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: patches and discussions about DPDK <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
X-List-Received-Date: Thu, 02 Jul 2015 15:17:00 -0000
Add ixgbe support for new ethdev APIs to enable and read IEEE1588
PTP timestamps.
Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
drivers/net/ixgbe/ixgbe_ethdev.c | 122 +++++++++++++++++++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index f18550c..7a58bb3 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -116,6 +116,12 @@
#define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
+/* Additional timesync values. */
+#define IXGBE_TIMINCA_16NS_SHIFT 24
+#define IXGBE_TIMINCA_INCVALUE 16000000
+#define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
+ | IXGBE_TIMINCA_INCVALUE)
+
static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
static int ixgbe_dev_configure(struct rte_eth_dev *dev);
static int ixgbe_dev_start(struct rte_eth_dev *dev);
@@ -261,6 +267,14 @@ static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
struct ether_addr *mc_addr_set,
uint32_t nb_mc_addr);
+static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
+static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
+static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp,
+ uint32_t flags);
+static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp);
+
/*
* Define VF Stats MACRO for Non "cleared on read" register
*/
@@ -386,6 +400,10 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
.rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
.filter_ctrl = ixgbe_dev_filter_ctrl,
.set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
+ .timesync_enable = ixgbe_timesync_enable,
+ .timesync_disable = ixgbe_timesync_disable,
+ .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
+ .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
};
/*
@@ -4493,6 +4511,110 @@ ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
ixgbe_dev_addr_list_itr, TRUE);
}
+static int
+ixgbe_timesync_enable(struct rte_eth_dev *dev)
+{
+ struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t tsync_ctl;
+ uint32_t tsauxc;
+
+ /* Enable system time for platforms where it isn't on by default. */
+ tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
+ tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
+ IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
+
+ /* Start incrementing the register used to timestamp PTP packets. */
+ IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
+
+ /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
+ IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
+ (ETHER_TYPE_1588 |
+ IXGBE_ETQF_FILTER_EN |
+ IXGBE_ETQF_1588));
+
+ /* Enable timestamping of received PTP packets. */
+ tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
+ tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
+ IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
+
+ /* Enable timestamping of transmitted PTP packets. */
+ tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
+ tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
+ IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
+
+ return 0;
+}
+
+static int
+ixgbe_timesync_disable(struct rte_eth_dev *dev)
+{
+ struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t tsync_ctl;
+
+ /* Disable timestamping of transmitted PTP packets. */
+ tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
+ tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
+ IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
+
+ /* Disable timestamping of received PTP packets. */
+ tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
+ tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
+ IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
+
+ /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
+ IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
+
+ /* Stop incrementating the System Time registers. */
+ IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
+
+ return 0;
+}
+
+static int
+ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp,
+ uint32_t flags __rte_unused)
+{
+ struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t tsync_rxctl;
+ uint32_t rx_stmpl;
+ uint32_t rx_stmph;
+
+ tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
+ if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
+ return -EINVAL;
+
+ rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
+ rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
+
+ timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
+ timestamp->tv_nsec = 0;
+
+ return 0;
+}
+
+static int
+ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp)
+{
+ struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t tsync_txctl;
+ uint32_t tx_stmpl;
+ uint32_t tx_stmph;
+
+ tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
+ if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
+ return -EINVAL;
+
+ tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
+ tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
+
+ timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
+ timestamp->tv_nsec = 0;
+
+ return 0;
+}
+
static struct rte_driver rte_ixgbe_driver = {
.type = PMD_PDEV,
.init = rte_ixgbe_pmd_init,
--
1.8.1.4