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VI1PR02MB0813; 5:ZmpmF2txM9GKIpzGZybzZ/rcGoj900GkYNUmdeAtZuEBkl56egXwJR2uZFeBuGQXeTnW/BIvWC3lAmE8rAkGB9R23voi4JTgYy+XGet9MTDnjwvaMgvjFC7asnTSYV6rtPEfSfzBRFCpYZ168rMHZA==; 24:dmm+iIo8l9F7uhcYSnh2f7PkENncS/MfCxnBOGhd+/Ems0uu1FDHL0N6iPI42SpI4doasKTIAhlHVzmi9tRoAuPEsjGLURFZ3Y5lOPIZxCA=; 20:+f3uGDkbBDjlHIPBfPi/o9qiXbkhI0GH0t31t2TRFIeBPb9CldkTqu/5s2q6l+HacpzB3LmC2E4RNSEKfUX5Rw== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: ezchip.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2015 08:52:32.0474 (UTC) X-MS-Exchange-CrossTenant-Id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3; Ip=[124.207.145.166]; Helo=[bjgfarm-1.internal.tilera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR02MB0813 Subject: [dpdk-dev] [PATCH v3 03/12] hash: check SSE flags only on x86 builds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jul 2015 08:52:35 -0000 This is necessary because the required CPU flags may not be defined on other architectures. Change-Id: I14d3f9f625b2e7567123f1c97095f8d06abd674b Signed-off-by: Zhigang Lu --- lib/librte_hash/rte_hash_crc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h index abdbd9a..1f6f5bf 100644 --- a/lib/librte_hash/rte_hash_crc.h +++ b/lib/librte_hash/rte_hash_crc.h @@ -425,12 +425,14 @@ static inline void rte_hash_crc_set_alg(uint8_t alg) { switch (alg) { +#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64) case CRC32_SSE42_x64: if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) alg = CRC32_SSE42; case CRC32_SSE42: if (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2)) alg = CRC32_SW; +#endif case CRC32_SW: crc32_alg = alg; default: -- 2.1.2