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DB5PR02MB0806; 5:fzMFt4m588bCPDMWRFbRJDQ+fnGek2S/goB+sn73v3ogmcv7dQuFW7TIvOcjaltUsP8L75V0gtNfs8LOOK5fgSrwvnZTP63MwB1TW+jilwQqi2i/G2oiWLnP16jxHVGuIviow4F2mi8Kow8tbtHAzw==; 24:6TEpewsJtKQfY8Ga6M48yx9tpkOgAqbT1I67arLCW363WDFz/JOtCfzxNqxSm/Ymngu0av5ww+xZsdrRr7n4I6IOoe5WfIgpM7eXVun/Xgw=; 20:Q7Rq5yD+4CVCt8BMBO6whqODS+WYo6oXUidwZAgVb152usskJqrmJcql9oZfVv9W8jSymZYW9PtM5BTh6FzFsg== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: ezchip.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2015 08:53:17.6930 (UTC) X-MS-Exchange-CrossTenant-Id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3; Ip=[124.207.145.166]; Helo=[bjgfarm-1.internal.tilera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR02MB0806 Subject: [dpdk-dev] [PATCH v3 08/12] mempool: allow config override on element alignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jul 2015 08:53:20 -0000 On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware buffer manager require a 128-byte alignment. With this change, we allow configuration based override of the element alignment, and default to RTE_CACHE_LINE_SIZE if left unspecified. Change-Id: I9cd789d92b0bc9c8f44a633de59bb04d45d927a7 Signed-off-by: Zhigang Lu --- lib/librte_mempool/rte_mempool.c | 16 +++++++++------- lib/librte_mempool/rte_mempool.h | 6 ++++++ 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c index 02699a1..8e185c5 100644 --- a/lib/librte_mempool/rte_mempool.c +++ b/lib/librte_mempool/rte_mempool.c @@ -120,10 +120,10 @@ static unsigned optimize_object_size(unsigned obj_size) nrank = 1; /* process new object size */ - new_obj_size = (obj_size + RTE_CACHE_LINE_MASK) / RTE_CACHE_LINE_SIZE; + new_obj_size = (obj_size + RTE_MEMPOOL_ALIGN_MASK) / RTE_MEMPOOL_ALIGN; while (get_gcd(new_obj_size, nrank * nchan) != 1) new_obj_size++; - return new_obj_size * RTE_CACHE_LINE_SIZE; + return new_obj_size * RTE_MEMPOOL_ALIGN; } static void @@ -267,7 +267,7 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags, #endif if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0) sz->header_size = RTE_ALIGN_CEIL(sz->header_size, - RTE_CACHE_LINE_SIZE); + RTE_MEMPOOL_ALIGN); /* trailer contains the cookie in debug mode */ sz->trailer_size = 0; @@ -281,9 +281,9 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags, if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0) { sz->total_size = sz->header_size + sz->elt_size + sz->trailer_size; - sz->trailer_size += ((RTE_CACHE_LINE_SIZE - - (sz->total_size & RTE_CACHE_LINE_MASK)) & - RTE_CACHE_LINE_MASK); + sz->trailer_size += ((RTE_MEMPOOL_ALIGN - + (sz->total_size & RTE_MEMPOOL_ALIGN_MASK)) & + RTE_MEMPOOL_ALIGN_MASK); } /* @@ -498,7 +498,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size, * cache-aligned */ private_data_size = (private_data_size + - RTE_CACHE_LINE_MASK) & (~RTE_CACHE_LINE_MASK); + RTE_MEMPOOL_ALIGN_MASK) & (~RTE_MEMPOOL_ALIGN_MASK); if (! rte_eal_has_hugepages()) { /* @@ -525,6 +525,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size, * enough to hold mempool header and metadata plus mempool objects. */ mempool_size = MEMPOOL_HEADER_SIZE(mp, pg_num) + private_data_size; + mempool_size = RTE_ALIGN_CEIL(mempool_size, RTE_MEMPOOL_ALIGN); if (vaddr == NULL) mempool_size += (size_t)objsz.total_size * n; @@ -580,6 +581,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size, /* calculate address of the first element for continuous mempool. */ obj = (char *)mp + MEMPOOL_HEADER_SIZE(mp, pg_num) + private_data_size; + obj = RTE_PTR_ALIGN_CEIL(obj, RTE_MEMPOOL_ALIGN); /* populate address translation fields. */ mp->pg_num = pg_num; diff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_mempool.h index 6d4ce9a..ee67ce7 100644 --- a/lib/librte_mempool/rte_mempool.h +++ b/lib/librte_mempool/rte_mempool.h @@ -142,6 +142,12 @@ struct rte_mempool_objsz { /** Mempool over one chunk of physically continuous memory */ #define MEMPOOL_PG_NUM_DEFAULT 1 +#ifndef RTE_MEMPOOL_ALIGN +#define RTE_MEMPOOL_ALIGN RTE_CACHE_LINE_SIZE +#endif + +#define RTE_MEMPOOL_ALIGN_MASK (RTE_MEMPOOL_ALIGN - 1) + /** * Mempool object header structure * -- 2.1.2