From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 30AAFC332 for ; Thu, 9 Jul 2015 15:30:25 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 09 Jul 2015 06:30:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,440,1432623600"; d="scan'208";a="761254588" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga002.jf.intel.com with ESMTP; 09 Jul 2015 06:30:23 -0700 Received: from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com [10.237.217.46]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id t69DUM03010604; Thu, 9 Jul 2015 14:30:22 +0100 Received: from sivswdev02.ir.intel.com (localhost [127.0.0.1]) by sivswdev02.ir.intel.com with ESMTP id t69DUMc7014034; Thu, 9 Jul 2015 14:30:22 +0100 Received: (from jmcnam2x@localhost) by sivswdev02.ir.intel.com with id t69DUMwk014030; Thu, 9 Jul 2015 14:30:22 +0100 From: John McNamara To: dev@dpdk.org Date: Thu, 9 Jul 2015 14:30:16 +0100 Message-Id: <1436448620-13972-4-git-send-email-john.mcnamara@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1436448620-13972-1-git-send-email-john.mcnamara@intel.com> References: <1436448620-13972-1-git-send-email-john.mcnamara@intel.com> Subject: [dpdk-dev] [PATCH v4 3/7] e1000: add support for ieee1588 timestamping X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Jul 2015 13:30:26 -0000 Add e1000/igb support for new ethdev APIs to enable and read IEEE1588 PTP timestamps. Signed-off-by: John McNamara --- drivers/net/e1000/igb_ethdev.c | 115 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index 11e8ab8..eb97218 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -76,6 +76,12 @@ #define IGB_8_BIT_WIDTH CHAR_BIT #define IGB_8_BIT_MASK UINT8_MAX +/* Additional timesync values. */ +#define E1000_ETQF_FILTER_1588 3 +#define E1000_TIMINCA_INCVALUE 16000000 +#define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \ + | E1000_TIMINCA_INCVALUE) + static int eth_igb_configure(struct rte_eth_dev *dev); static int eth_igb_start(struct rte_eth_dev *dev); static void eth_igb_stop(struct rte_eth_dev *dev); @@ -199,6 +205,13 @@ static int eth_igb_filter_ctrl(struct rte_eth_dev *dev, static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addr_set, uint32_t nb_mc_addr); +static int igb_timesync_enable(struct rte_eth_dev *dev); +static int igb_timesync_disable(struct rte_eth_dev *dev); +static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp, + uint32_t flags); +static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp); /* * Define VF Stats MACRO for Non "cleared on read" register @@ -276,6 +289,10 @@ static const struct eth_dev_ops eth_igb_ops = { .rss_hash_conf_get = eth_igb_rss_hash_conf_get, .filter_ctrl = eth_igb_filter_ctrl, .set_mc_addr_list = eth_igb_set_mc_addr_list, + .timesync_enable = igb_timesync_enable, + .timesync_disable = igb_timesync_disable, + .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp, + .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp, }; /* @@ -3663,6 +3680,104 @@ eth_igb_set_mc_addr_list(struct rte_eth_dev *dev, return 0; } +static int +igb_timesync_enable(struct rte_eth_dev *dev) +{ + struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t tsync_ctl; + + /* Start incrementing the register used to timestamp PTP packets. */ + E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT); + + /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ + E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), + (ETHER_TYPE_1588 | + E1000_ETQF_FILTER_ENABLE | + E1000_ETQF_1588)); + + /* Enable timestamping of received PTP packets. */ + tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); + tsync_ctl |= E1000_TSYNCRXCTL_ENABLED; + E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl); + + /* Enable Timestamping of transmitted PTP packets. */ + tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); + tsync_ctl |= E1000_TSYNCTXCTL_ENABLED; + E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl); + + return 0; +} + +static int +igb_timesync_disable(struct rte_eth_dev *dev) +{ + struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t tsync_ctl; + + /* Disable timestamping of transmitted PTP packets. */ + tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); + tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED; + E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl); + + /* Disable timestamping of received PTP packets. */ + tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); + tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED; + E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl); + + /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ + E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0); + + /* Stop incrementating the System Time registers. */ + E1000_WRITE_REG(hw, E1000_TIMINCA, 0); + + return 0; +} + +static int +igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp, + uint32_t flags __rte_unused) +{ + struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t tsync_rxctl; + uint32_t rx_stmpl; + uint32_t rx_stmph; + + tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL); + if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0) + return -EINVAL; + + rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL); + rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH); + + timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl); + timestamp->tv_nsec = 0; + + return 0; +} + +static int +igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev, + struct timespec *timestamp) +{ + struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t tsync_txctl; + uint32_t tx_stmpl; + uint32_t tx_stmph; + + tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL); + if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0) + return -EINVAL; + + tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL); + tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH); + + timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl); + timestamp->tv_nsec = 0; + + return 0; +} + static struct rte_driver pmd_igb_drv = { .type = PMD_PDEV, .init = rte_igb_pmd_init, -- 1.8.1.4