[dpdk-dev] [PATCH v4 0/7] ethdev: add support for ieee1588 timestamping

[dpdk-dev] [PATCH v4 0/7] ethdev: add support for ieee1588 timestamping

[John McNamara]

This patchset adds ethdev API to enable and read IEEE1588/802.1AS PTP
timestamps from devices that support it. The following functions are added:

    rte_eth_timesync_enable()
    rte_eth_timesync_disable()
    rte_eth_timesync_read_rx_timestamp()
    rte_eth_timesync_read_tx_timestamp()

The "ieee1588" forwarding mode in testpmd is also refactored to demonstrate
the new API and to clean up the code.

Adds support for igb, ixgbe and i40e.

V4:
* Added timesync field to end of mbuf to pass IEEE1588 registers and flags.
  Removed previous ABI deprecation notice.

V3:
* Fixed issued with version.map.

V2:
* Added i40e support.

* Renamed ethdev functions from rte_eth_ieee15888_*() to rte_eth_timesync_*()
  since 802.1AS can be supported through the same interfaces.

V1:
* Initial version for igb and ixgbe.


John McNamara (7):
  ethdev: add support for ieee1588 timestamping
  mbuf: add field for ieee1588 timesync index
  e1000: add support for ieee1588 timestamping
  ixgbe: add support for ieee1588 timestamping
  i40e: add support for ieee1588 timestamping
  app/testpmd: refactor ieee1588 forwarding
  doc: document ieee1588 forwarding mode

 app/test-pmd/ieee1588fwd.c                  | 466 ++--------------------------
 doc/guides/testpmd_app_ug/run_app.rst       |   2 +-
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |   2 +
 drivers/net/e1000/igb_ethdev.c              | 115 +++++++
 drivers/net/i40e/i40e_ethdev.c              | 143 +++++++++
 drivers/net/i40e/i40e_rxtx.c                |  40 ++-
 drivers/net/ixgbe/ixgbe_ethdev.c            | 122 ++++++++
 lib/librte_ether/rte_ethdev.c               |  70 ++++-
 lib/librte_ether/rte_ethdev.h               |  90 +++++-
 lib/librte_ether/rte_ether_version.map      |   4 +
 lib/librte_mbuf/rte_mbuf.h                  |   3 +
 11 files changed, 614 insertions(+), 443 deletions(-)

--
1.8.1.4

[dpdk-dev] [PATCH v4 1/7] ethdev: add support for ieee1588 timestamping

[John McNamara]

Add ethdev API to enable and read IEEE1588/802.1AS PTP timestamps
from devices that support it. The following functions are added:

    rte_eth_timesync_enable()
    rte_eth_timesync_disable()
    rte_eth_timesync_read_rx_timestamp()
    rte_eth_timesync_read_tx_timestamp()

Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
 lib/librte_ether/rte_ethdev.c          | 70 +++++++++++++++++++++++++-
 lib/librte_ether/rte_ethdev.h          | 90 +++++++++++++++++++++++++++++++++-
 lib/librte_ether/rte_ether_version.map |  4 ++
 3 files changed, 162 insertions(+), 2 deletions(-)

diff --git a/lib/librte_ether/rte_ethdev.c b/lib/librte_ether/rte_ethdev.c
index 44d41b8..9ba0e24 100644
--- a/lib/librte_ether/rte_ethdev.c
+++ b/lib/librte_ether/rte_ethdev.c
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -3304,3 +3304,71 @@ rte_eth_dev_set_mc_addr_list(uint8_t port_id,
 	FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP);
 	return dev->dev_ops->set_mc_addr_list(dev, mc_addr_set, nb_mc_addr);
 }
+
+int
+rte_eth_timesync_enable(uint8_t port_id)
+{
+	struct rte_eth_dev *dev;
+
+	if (!rte_eth_dev_is_valid_port(port_id)) {
+		PMD_DEBUG_TRACE("Invalid port_id=%d\n", port_id);
+		return -ENODEV;
+	}
+
+	dev = &rte_eth_devices[port_id];
+
+	FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP);
+	return (*dev->dev_ops->timesync_enable)(dev);
+}
+
+int
+rte_eth_timesync_disable(uint8_t port_id)
+{
+	struct rte_eth_dev *dev;
+
+	if (!rte_eth_dev_is_valid_port(port_id)) {
+		PMD_DEBUG_TRACE("Invalid port_id=%d\n", port_id);
+		return -ENODEV;
+	}
+
+	dev = &rte_eth_devices[port_id];
+
+	FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP);
+	return (*dev->dev_ops->timesync_disable)(dev);
+}
+
+int
+rte_eth_timesync_read_rx_timestamp(uint8_t port_id, struct timespec *timestamp,
+				   uint32_t flags)
+{
+	struct rte_eth_dev *dev;
+
+	if (!rte_eth_dev_is_valid_port(port_id)) {
+		PMD_DEBUG_TRACE("Invalid port_id=%d\n", port_id);
+		return -ENODEV;
+	}
+
+	dev = &rte_eth_devices[port_id];
+
+	FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp,
+			    -ENOTSUP);
+	return (*dev->dev_ops->timesync_read_rx_timestamp)(dev, timestamp,
+							   flags);
+}
+
+int
+rte_eth_timesync_read_tx_timestamp(uint8_t port_id, struct timespec *timestamp)
+{
+	struct rte_eth_dev *dev;
+
+	if (!rte_eth_dev_is_valid_port(port_id)) {
+		PMD_DEBUG_TRACE("Invalid port_id=%d\n", port_id);
+		return -ENODEV;
+	}
+
+	dev = &rte_eth_devices[port_id];
+
+	FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp,
+			    -ENOTSUP);
+	return (*dev->dev_ops->timesync_read_tx_timestamp)(dev, timestamp);
+}
diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h
index 438d59a..79bde89 100644
--- a/lib/librte_ether/rte_ethdev.h
+++ b/lib/librte_ether/rte_ethdev.h
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -1240,6 +1240,21 @@ typedef int (*eth_set_mc_addr_list_t)(struct rte_eth_dev *dev,
 				      uint32_t nb_mc_addr);
 /**< @internal set the list of multicast addresses on an Ethernet device */
 
+typedef int (*eth_timesync_enable_t)(struct rte_eth_dev *dev);
+/**< @internal Function used to enable IEEE1588/802.1AS timestamping. */
+
+typedef int (*eth_timesync_disable_t)(struct rte_eth_dev *dev);
+/**< @internal Function used to disable IEEE1588/802.1AS timestamping. */
+
+typedef int (*eth_timesync_read_rx_timestamp_t)(struct rte_eth_dev *dev,
+						struct timespec *timestamp,
+						uint32_t flags);
+/**< @internal Function used to read an RX IEEE1588/802.1AS timestamp. */
+
+typedef int (*eth_timesync_read_tx_timestamp_t)(struct rte_eth_dev *dev,
+						struct timespec *timestamp);
+/**< @internal Function used to read a TX IEEE1588/802.1AS timestamp. */
+
 #ifdef RTE_NIC_BYPASS
 
 enum {
@@ -1398,6 +1413,15 @@ struct eth_dev_ops {
 	rss_hash_conf_get_t rss_hash_conf_get;
 	eth_filter_ctrl_t              filter_ctrl;          /**< common filter control*/
 	eth_set_mc_addr_list_t set_mc_addr_list; /**< set list of mcast addrs */
+
+	/** Turn IEEE1588/802.1AS timestamping on. */
+	eth_timesync_enable_t timesync_enable;
+	/** Turn IEEE1588/802.1AS timestamping off. */
+	eth_timesync_disable_t timesync_disable;
+	/** Read the IEEE1588/802.1AS RX timestamp. */
+	eth_timesync_read_rx_timestamp_t timesync_read_rx_timestamp;
+	/** Read the IEEE1588/802.1AS TX timestamp. */
+	eth_timesync_read_tx_timestamp_t timesync_read_tx_timestamp;
 };
 
 /**
@@ -3647,4 +3671,68 @@ int rte_eth_dev_set_mc_addr_list(uint8_t port_id,
 				 struct ether_addr *mc_addr_set,
 				 uint32_t nb_mc_addr);
 
+
+/**
+ * Enable IEEE1588/802.1AS timestamping for an Ethernet device.
+ *
+ * @param port_id
+ *   The port identifier of the Ethernet device.
+ *
+ * @return
+ *   - 0: Success.
+ *   - -ENODEV: The port ID is invalid.
+ *   - -ENOTSUP: The function is not supported by the Ethernet driver.
+ */
+extern int rte_eth_timesync_enable(uint8_t port_id);
+
+/**
+ * Disable IEEE1588/802.1AS timestamping for an Ethernet device.
+ *
+ * @param port_id
+ *   The port identifier of the Ethernet device.
+ *
+ * @return
+ *   - 0: Success.
+ *   - -ENODEV: The port ID is invalid.
+ *   - -ENOTSUP: The function is not supported by the Ethernet driver.
+ */
+extern int rte_eth_timesync_disable(uint8_t port_id);
+
+/**
+ * Read an IEEE1588/802.1AS RX timestamp from an Ethernet device.
+ *
+ * @param port_id
+ *   The port identifier of the Ethernet device.
+ * @param timestamp
+ *   Pointer to the timestamp struct.
+ * @param flags
+ *   Device specific flags. Used to pass the RX timesync register index to
+ *   i40e. Unused in igb/ixgbe, pass 0 instead.
+ *
+ * @return
+ *   - 0: Success.
+ *   - -EINVAL: No timestamp is available.
+ *   - -ENODEV: The port ID is invalid.
+ *   - -ENOTSUP: The function is not supported by the Ethernet driver.
+ */
+extern int rte_eth_timesync_read_rx_timestamp(uint8_t port_id,
+					      struct timespec *timestamp,
+					      uint32_t flags);
+
+/**
+ * Read an IEEE1588/802.1AS TX timestamp from an Ethernet device.
+ *
+ * @param port_id
+ *   The port identifier of the Ethernet device.
+ * @param timestamp
+ *   Pointer to the timestamp struct.
+ *
+ * @return
+ *   - 0: Success.
+ *   - -EINVAL: No timestamp is available.
+ *   - -ENODEV: The port ID is invalid.
+ *   - -ENOTSUP: The function is not supported by the Ethernet driver.
+ */
+extern int rte_eth_timesync_read_tx_timestamp(uint8_t port_id,
+					      struct timespec *timestamp);
 #endif /* _RTE_ETHDEV_H_ */
diff --git a/lib/librte_ether/rte_ether_version.map b/lib/librte_ether/rte_ether_version.map
index e3c8fa1..39baf11 100644
--- a/lib/librte_ether/rte_ether_version.map
+++ b/lib/librte_ether/rte_ether_version.map
@@ -110,5 +110,9 @@ DPDK_2.1 {
 	global:
 
 	rte_eth_dev_set_mc_addr_list;
+	rte_eth_timesync_disable;
+	rte_eth_timesync_enable;
+	rte_eth_timesync_read_rx_timestamp;
+	rte_eth_timesync_read_tx_timestamp;
 
 } DPDK_2.0;
-- 
1.8.1.4

[dpdk-dev] [PATCH v4 2/7] mbuf: add field for ieee1588 timesync index

[John McNamara]

Add mbuf field to store the IEEE1588 RX register index and other flags.

Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
 lib/librte_mbuf/rte_mbuf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h
index 80419df..d5895ea 100644
--- a/lib/librte_mbuf/rte_mbuf.h
+++ b/lib/librte_mbuf/rte_mbuf.h
@@ -339,6 +339,9 @@ struct rte_mbuf {
 	/** Size of the application private data. In case of an indirect
 	 * mbuf, it stores the direct mbuf private data size. */
 	uint16_t priv_size;
+
+	/** Timesync flags for use with IEEE1588. */
+	uint16_t timesync;
 } __rte_cache_aligned;
 
 static inline uint16_t rte_pktmbuf_priv_size(struct rte_mempool *mp);
-- 
1.8.1.4

[dpdk-dev] [PATCH v4 3/7] e1000: add support for ieee1588 timestamping

[John McNamara]

Add e1000/igb support for new ethdev APIs to enable and read
IEEE1588 PTP timestamps.

Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
 drivers/net/e1000/igb_ethdev.c | 115 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 11e8ab8..eb97218 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -76,6 +76,12 @@
 #define IGB_8_BIT_WIDTH  CHAR_BIT
 #define IGB_8_BIT_MASK   UINT8_MAX
 
+/* Additional timesync values. */
+#define E1000_ETQF_FILTER_1588 3
+#define E1000_TIMINCA_INCVALUE 16000000
+#define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
+				| E1000_TIMINCA_INCVALUE)
+
 static int  eth_igb_configure(struct rte_eth_dev *dev);
 static int  eth_igb_start(struct rte_eth_dev *dev);
 static void eth_igb_stop(struct rte_eth_dev *dev);
@@ -199,6 +205,13 @@ static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 				    struct ether_addr *mc_addr_set,
 				    uint32_t nb_mc_addr);
+static int igb_timesync_enable(struct rte_eth_dev *dev);
+static int igb_timesync_disable(struct rte_eth_dev *dev);
+static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+					  struct timespec *timestamp,
+					  uint32_t flags);
+static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+					  struct timespec *timestamp);
 
 /*
  * Define VF Stats MACRO for Non "cleared on read" register
@@ -276,6 +289,10 @@ static const struct eth_dev_ops eth_igb_ops = {
 	.rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 	.filter_ctrl          = eth_igb_filter_ctrl,
 	.set_mc_addr_list     = eth_igb_set_mc_addr_list,
+	.timesync_enable      = igb_timesync_enable,
+	.timesync_disable     = igb_timesync_disable,
+	.timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
+	.timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 };
 
 /*
@@ -3663,6 +3680,104 @@ eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 	return 0;
 }
 
+static int
+igb_timesync_enable(struct rte_eth_dev *dev)
+{
+	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_ctl;
+
+	/* Start incrementing the register used to timestamp PTP packets. */
+	E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
+
+	/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
+	E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
+			(ETHER_TYPE_1588 |
+			 E1000_ETQF_FILTER_ENABLE |
+			 E1000_ETQF_1588));
+
+	/* Enable timestamping of received PTP packets. */
+	tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
+	tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
+	E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
+
+	/* Enable Timestamping of transmitted PTP packets. */
+	tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
+	tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
+	E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
+
+	return 0;
+}
+
+static int
+igb_timesync_disable(struct rte_eth_dev *dev)
+{
+	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_ctl;
+
+	/* Disable timestamping of transmitted PTP packets. */
+	tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
+	tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
+	E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
+
+	/* Disable timestamping of received PTP packets. */
+	tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
+	tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
+	E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
+
+	/* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
+	E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
+
+	/* Stop incrementating the System Time registers. */
+	E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
+
+	return 0;
+}
+
+static int
+igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+			       struct timespec *timestamp,
+			       uint32_t flags __rte_unused)
+{
+	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_rxctl;
+	uint32_t rx_stmpl;
+	uint32_t rx_stmph;
+
+	tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
+	if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
+		return -EINVAL;
+
+	rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
+	rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
+
+	timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
+	timestamp->tv_nsec = 0;
+
+	return  0;
+}
+
+static int
+igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+			       struct timespec *timestamp)
+{
+	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_txctl;
+	uint32_t tx_stmpl;
+	uint32_t tx_stmph;
+
+	tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
+	if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
+		return -EINVAL;
+
+	tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
+	tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
+
+	timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
+	timestamp->tv_nsec = 0;
+
+	return  0;
+}
+
 static struct rte_driver pmd_igb_drv = {
 	.type = PMD_PDEV,
 	.init = rte_igb_pmd_init,
-- 
1.8.1.4

[dpdk-dev] [PATCH v4 4/7] ixgbe: add support for ieee1588 timestamping

[John McNamara]

Add ixgbe support for new ethdev APIs to enable and read IEEE1588
PTP timestamps.

Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
 drivers/net/ixgbe/ixgbe_ethdev.c | 122 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index b7a60b1..4015feb 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -118,6 +118,12 @@
 
 #define IXGBE_HKEY_MAX_INDEX 10
 
+/* Additional timesync values. */
+#define IXGBE_TIMINCA_16NS_SHIFT 24
+#define IXGBE_TIMINCA_INCVALUE   16000000
+#define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
+				  | IXGBE_TIMINCA_INCVALUE)
+
 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
@@ -263,6 +269,14 @@ static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 				      struct ether_addr *mc_addr_set,
 				      uint32_t nb_mc_addr);
 
+static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
+static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
+static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+					    struct timespec *timestamp,
+					    uint32_t flags);
+static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+					    struct timespec *timestamp);
+
 /*
  * Define VF Stats MACRO for Non "cleared on read" register
  */
@@ -388,6 +402,10 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 	.rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 	.filter_ctrl          = ixgbe_dev_filter_ctrl,
 	.set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
+	.timesync_enable      = ixgbe_timesync_enable,
+	.timesync_disable     = ixgbe_timesync_disable,
+	.timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
+	.timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 };
 
 /*
@@ -4514,6 +4532,110 @@ ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 					 ixgbe_dev_addr_list_itr, TRUE);
 }
 
+static int
+ixgbe_timesync_enable(struct rte_eth_dev *dev)
+{
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_ctl;
+	uint32_t tsauxc;
+
+	/* Enable system time for platforms where it isn't on by default. */
+	tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
+	tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
+	IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
+
+	/* Start incrementing the register used to timestamp PTP packets. */
+	IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
+
+	/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
+	IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
+			(ETHER_TYPE_1588 |
+			 IXGBE_ETQF_FILTER_EN |
+			 IXGBE_ETQF_1588));
+
+	/* Enable timestamping of received PTP packets. */
+	tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
+	tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
+	IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
+
+	/* Enable timestamping of transmitted PTP packets. */
+	tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
+	tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
+	IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
+
+	return 0;
+}
+
+static int
+ixgbe_timesync_disable(struct rte_eth_dev *dev)
+{
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_ctl;
+
+	/* Disable timestamping of transmitted PTP packets. */
+	tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
+	tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
+	IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
+
+	/* Disable timestamping of received PTP packets. */
+	tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
+	tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
+	IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
+
+	/* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
+	IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
+
+	/* Stop incrementating the System Time registers. */
+	IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
+
+	return 0;
+}
+
+static int
+ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+				 struct timespec *timestamp,
+				 uint32_t flags __rte_unused)
+{
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_rxctl;
+	uint32_t rx_stmpl;
+	uint32_t rx_stmph;
+
+	tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
+	if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
+		return -EINVAL;
+
+	rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
+	rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
+
+	timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
+	timestamp->tv_nsec = 0;
+
+	return  0;
+}
+
+static int
+ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+				 struct timespec *timestamp)
+{
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_txctl;
+	uint32_t tx_stmpl;
+	uint32_t tx_stmph;
+
+	tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
+	if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
+		return -EINVAL;
+
+	tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
+	tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
+
+	timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
+	timestamp->tv_nsec = 0;
+
+	return  0;
+}
+
 static struct rte_driver rte_ixgbe_driver = {
 	.type = PMD_PDEV,
 	.init = rte_ixgbe_pmd_init,
-- 
1.8.1.4

[dpdk-dev] [PATCH v4 5/7] i40e: add support for ieee1588 timestamping

[John McNamara]

Add ixgbe support for new ethdev APIs to enable and read IEEE1588/
802.1AS PTP timestamps.

Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 143 +++++++++++++++++++++++++++++++++++++++++
 drivers/net/i40e/i40e_rxtx.c   |  40 +++++++++++-
 2 files changed, 182 insertions(+), 1 deletion(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 5fb6b4c..db642a5 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -55,6 +55,7 @@
 #include "base/i40e_prototype.h"
 #include "base/i40e_adminq_cmd.h"
 #include "base/i40e_type.h"
+#include "base/i40e_register.h"
 #include "i40e_ethdev.h"
 #include "i40e_rxtx.h"
 #include "i40e_pf.h"
@@ -106,6 +107,12 @@
 	(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 	(1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 
+#define I40E_PTP_40GB_INCVAL  0x0199999999ULL
+#define I40E_PTP_10GB_INCVAL  0x0333333333ULL
+#define I40E_PTP_1GB_INCVAL   0x2000000000ULL
+#define I40E_PRTTSYN_TSYNENA  0x80000000
+#define I40E_PRTTSYN_TSYNTYPE 0x0e000000
+
 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 static int i40e_dev_configure(struct rte_eth_dev *dev);
 static int i40e_dev_start(struct rte_eth_dev *dev);
@@ -217,6 +224,14 @@ static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 			uint8_t sw_id, uint8_t on);
 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 
+static int i40e_timesync_enable(struct rte_eth_dev *dev);
+static int i40e_timesync_disable(struct rte_eth_dev *dev);
+static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+					   struct timespec *timestamp,
+					   uint32_t flags);
+static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+					   struct timespec *timestamp);
+
 static const struct rte_pci_id pci_id_i40e_map[] = {
 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 #include "rte_pci_dev_ids.h"
@@ -269,6 +284,10 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
 	.filter_ctrl                  = i40e_dev_filter_ctrl,
 	.mirror_rule_set              = i40e_mirror_rule_set,
 	.mirror_rule_reset            = i40e_mirror_rule_reset,
+	.timesync_enable              = i40e_timesync_enable,
+	.timesync_disable             = i40e_timesync_disable,
+	.timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
+	.timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 };
 
 static struct eth_driver rte_i40e_pmd = {
@@ -6086,3 +6105,127 @@ i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
 	}
 	return 0;
 }
+
+static int
+i40e_timesync_enable(struct rte_eth_dev *dev)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct rte_eth_link *link = &dev->data->dev_link;
+	uint32_t tsync_ctl_l;
+	uint32_t tsync_ctl_h;
+	uint32_t tsync_inc_l;
+	uint32_t tsync_inc_h;
+
+	switch (link->link_speed) {
+	case ETH_LINK_SPEED_40G:
+		tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
+		tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
+		break;
+	case ETH_LINK_SPEED_10G:
+		tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
+		tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
+		break;
+	case ETH_LINK_SPEED_1000:
+		tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
+		tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
+		break;
+	default:
+		tsync_inc_l = 0x0;
+		tsync_inc_h = 0x0;
+	}
+
+	/* Clear timesync registers. */
+	I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
+	I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
+	I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
+	I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
+	I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
+	I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
+	I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
+
+	/* Set the timesync increment value. */
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
+
+	/* Enable timestamping of PTP packets. */
+	tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
+	tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
+
+	tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
+	tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
+	tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
+
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
+
+	return 0;
+}
+
+static int
+i40e_timesync_disable(struct rte_eth_dev *dev)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t tsync_ctl_l;
+	uint32_t tsync_ctl_h;
+
+	/* Disable timestamping of transmitted PTP packets. */
+	tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
+	tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
+
+	tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
+	tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
+
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
+
+	/* Set the timesync increment value. */
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
+	I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
+
+	return 0;
+}
+
+static int
+i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+				struct timespec *timestamp, uint32_t flags)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t sync_status;
+	uint32_t rx_stmpl;
+	uint32_t rx_stmph;
+	uint32_t index = flags & 0x03;
+
+	sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
+	if ((sync_status & (1 << index)) == 0)
+		return -EINVAL;
+
+	rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
+	rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
+
+	timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
+	timestamp->tv_nsec = 0;
+
+	return  0;
+}
+
+static int
+i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+				struct timespec *timestamp)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint32_t sync_status;
+	uint32_t tx_stmpl;
+	uint32_t tx_stmph;
+
+	sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
+	if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
+		return -EINVAL;
+
+	tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
+	tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
+
+	timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
+	timestamp->tv_nsec = 0;
+
+	return  0;
+}
diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index 88b015d..c79160f 100644
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -185,7 +185,7 @@ i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 	static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 		0, /* PTYPE 0 */
 		0, /* PTYPE 1 */
-		0, /* PTYPE 2 */
+		PKT_RX_IEEE1588_PTP, /* PTYPE 2 */
 		0, /* PTYPE 3 */
 		0, /* PTYPE 4 */
 		0, /* PTYPE 5 */
@@ -741,7 +741,19 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 			if (pkt_flags & PKT_RX_FDIR)
 				pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 
+#ifdef RTE_LIBRTE_IEEE1588
+			uint16_t tsyn = (qword1
+					 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
+					   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
+					 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
+
+			if (tsyn & 0x04)
+				pkt_flags |= PKT_RX_IEEE1588_TMST;
+
+			mb->timesync = tsyn & 0x03;
+#endif
 			mb->ol_flags |= pkt_flags;
+
 		}
 
 		for (j = 0; j < I40E_LOOK_AHEAD; j++)
@@ -923,6 +935,7 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 		qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 		rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 				>> I40E_RXD_QW1_STATUS_SHIFT;
+
 		/* Check the DD bit first */
 		if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 			break;
@@ -980,6 +993,16 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 		if (pkt_flags & PKT_RX_FDIR)
 			pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 
+#ifdef RTE_LIBRTE_IEEE1588
+		uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
+					| I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
+					>> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
+
+		if (tsyn & 0x04)
+			pkt_flags |= PKT_RX_IEEE1588_TMST;
+
+		rxm->timesync = tsyn & 0x03;
+#endif
 		rxm->ol_flags |= pkt_flags;
 
 		rx_pkts[nb_rx++] = rxm;
@@ -1030,6 +1053,7 @@ i40e_recv_scattered_pkts(void *rx_queue,
 		qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 		rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 					I40E_RXD_QW1_STATUS_SHIFT;
+
 		/* Check the DD bit */
 		if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 			break;
@@ -1139,6 +1163,16 @@ i40e_recv_scattered_pkts(void *rx_queue,
 		if (pkt_flags & PKT_RX_FDIR)
 			pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 
+#ifdef RTE_LIBRTE_IEEE1588
+		uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
+					| I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
+					>> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
+
+		if (tsyn & 0x04)
+			pkt_flags |= PKT_RX_IEEE1588_TMST;
+
+		first_seg->timesync = tsyn & 0x03;
+#endif
 		first_seg->ol_flags |= pkt_flags;
 
 		/* Prefetch data of first segment, if configured to do so. */
@@ -2389,6 +2423,10 @@ i40e_tx_queue_init(struct i40e_tx_queue *txq)
 	tx_ctx.new_context = 1;
 	tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 	tx_ctx.qlen = txq->nb_tx_desc;
+
+#ifdef RTE_LIBRTE_IEEE1588
+	tx_ctx.timesync_ena = 1;
+#endif
 	tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
 	if (vsi->type == I40E_VSI_FDIR)
 		tx_ctx.fd_ena = TRUE;
-- 
1.8.1.4

[dpdk-dev] [PATCH v4 6/7] app/testpmd: refactor ieee1588 forwarding

[John McNamara]

Refactor the ieee1588_fwd mode in testpmd to use the new ethdev
APIs to enable and read IEEE1588 PTP timestamps.

Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
 app/test-pmd/ieee1588fwd.c | 466 +++------------------------------------------
 1 file changed, 27 insertions(+), 439 deletions(-)

diff --git a/app/test-pmd/ieee1588fwd.c b/app/test-pmd/ieee1588fwd.c
index dfbb185..069ee2e 100644
--- a/app/test-pmd/ieee1588fwd.c
+++ b/app/test-pmd/ieee1588fwd.c
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -31,39 +31,9 @@
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <stdarg.h>
-#include <stdio.h>
-#include <string.h>
-#include <errno.h>
-#include <stdint.h>
-#include <unistd.h>
-#include <inttypes.h>
 
-#include <sys/queue.h>
-#include <sys/stat.h>
-
-#include <rte_common.h>
-#include <rte_byteorder.h>
-#include <rte_log.h>
-#include <rte_debug.h>
 #include <rte_cycles.h>
-#include <rte_memory.h>
-#include <rte_memzone.h>
-#include <rte_launch.h>
-#include <rte_eal.h>
-#include <rte_per_lcore.h>
-#include <rte_lcore.h>
-#include <rte_atomic.h>
-#include <rte_branch_prediction.h>
-#include <rte_ring.h>
-#include <rte_memory.h>
-#include <rte_mempool.h>
-#include <rte_mbuf.h>
-#include <rte_interrupts.h>
-#include <rte_pci.h>
-#include <rte_ether.h>
 #include <rte_ethdev.h>
-#include <rte_string_fns.h>
 
 #include "testpmd.h"
 
@@ -77,6 +47,7 @@ struct ptpv2_msg {
 	uint8_t version; /**< must be 0x02 */
 	uint8_t unused[34];
 };
+
 #define PTP_SYNC_MESSAGE                0x0
 #define PTP_DELAY_REQ_MESSAGE           0x1
 #define PTP_PATH_DELAY_REQ_MESSAGE      0x2
@@ -108,393 +79,18 @@ struct ptpv2_msg {
  * is greater than the previous one.
  */
 
-/*
- * 1GbE 82576 Kawela registers used for IEEE1588 hardware support
- */
-#define IGBE_82576_ETQF(n) (0x05CB0 + (4 * (n)))
-#define IGBE_82576_ETQF_FILTER_ENABLE  (1 << 26)
-#define IGBE_82576_ETQF_1588_TIMESTAMP (1 << 30)
-
-#define IGBE_82576_TSYNCRXCTL  0x0B620
-#define IGBE_82576_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
-
-#define IGBE_82576_RXSTMPL     0x0B624
-#define IGBE_82576_RXSTMPH     0x0B628
-#define IGBE_82576_RXSATRL     0x0B62C
-#define IGBE_82576_RXSATRH     0x0B630
-#define IGBE_82576_TSYNCTXCTL  0x0B614
-#define IGBE_82576_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
-
-#define IGBE_82576_TXSTMPL     0x0B618
-#define IGBE_82576_TXSTMPH     0x0B61C
-#define IGBE_82576_SYSTIML     0x0B600
-#define IGBE_82576_SYSTIMH     0x0B604
-#define IGBE_82576_TIMINCA     0x0B608
-#define IGBE_82576_TIMADJL     0x0B60C
-#define IGBE_82576_TIMADJH     0x0B610
-#define IGBE_82576_TSAUXC      0x0B640
-#define IGBE_82576_TRGTTIML0   0x0B644
-#define IGBE_82576_TRGTTIMH0   0x0B648
-#define IGBE_82576_TRGTTIML1   0x0B64C
-#define IGBE_82576_TRGTTIMH1   0x0B650
-#define IGBE_82576_AUXSTMPL0   0x0B65C
-#define IGBE_82576_AUXSTMPH0   0x0B660
-#define IGBE_82576_AUXSTMPL1   0x0B664
-#define IGBE_82576_AUXSTMPH1   0x0B668
-#define IGBE_82576_TSYNCRXCFG  0x05F50
-#define IGBE_82576_TSSDP       0x0003C
-
-/*
- * 10GbE 82599 Niantic registers used for IEEE1588 hardware support
- */
-#define IXGBE_82599_ETQF(n) (0x05128 + (4 * (n)))
-#define IXGBE_82599_ETQF_FILTER_ENABLE  (1 << 31)
-#define IXGBE_82599_ETQF_1588_TIMESTAMP (1 << 30)
-
-#define IXGBE_82599_TSYNCRXCTL 0x05188
-#define IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE (1 << 4)
-
-#define IXGBE_82599_RXSTMPL    0x051E8
-#define IXGBE_82599_RXSTMPH    0x051A4
-#define IXGBE_82599_RXSATRL    0x051A0
-#define IXGBE_82599_RXSATRH    0x051A8
-#define IXGBE_82599_RXMTRL     0x05120
-#define IXGBE_82599_TSYNCTXCTL 0x08C00
-#define IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE (1 << 4)
-
-#define IXGBE_82599_TXSTMPL    0x08C04
-#define IXGBE_82599_TXSTMPH    0x08C08
-#define IXGBE_82599_SYSTIML    0x08C0C
-#define IXGBE_82599_SYSTIMH    0x08C10
-#define IXGBE_82599_TIMINCA    0x08C14
-#define IXGBE_82599_TIMADJL    0x08C18
-#define IXGBE_82599_TIMADJH    0x08C1C
-#define IXGBE_82599_TSAUXC     0x08C20
-#define IXGBE_82599_TRGTTIML0  0x08C24
-#define IXGBE_82599_TRGTTIMH0  0x08C28
-#define IXGBE_82599_TRGTTIML1  0x08C2C
-#define IXGBE_82599_TRGTTIMH1  0x08C30
-#define IXGBE_82599_AUXSTMPL0  0x08C3C
-#define IXGBE_82599_AUXSTMPH0  0x08C40
-#define IXGBE_82599_AUXSTMPL1  0x08C44
-#define IXGBE_82599_AUXSTMPH1  0x08C48
-
-/**
- * Mandatory ETQF register for IEEE1588 packets filter.
- */
-#define ETQF_FILTER_1588_REG 3
-
-/**
- * Recommended value for increment and period of
- * the Increment Attribute Register.
- */
-#define IEEE1588_TIMINCA_INIT ((0x02 << 24) | 0x00F42400)
-
-/**
- * Data structure with pointers to port-specific functions.
- */
-typedef void (*ieee1588_start_t)(portid_t pi); /**< Start IEEE1588 feature. */
-typedef void (*ieee1588_stop_t)(portid_t pi);  /**< Stop IEEE1588 feature.  */
-typedef int  (*tmst_read_t)(portid_t pi, uint64_t *tmst); /**< Read TMST regs */
-
-struct port_ieee1588_ops {
-	ieee1588_start_t ieee1588_start;
-	ieee1588_stop_t  ieee1588_stop;
-	tmst_read_t      rx_tmst_read;
-	tmst_read_t      tx_tmst_read;
-};
-
-/**
- * 1GbE 82576 IEEE1588 operations.
- */
-static void
-igbe_82576_ieee1588_start(portid_t pi)
-{
-	uint32_t tsync_ctl;
-
-	/*
-	 * Start incrementation of the System Time registers used to
-	 * timestamp PTP packets.
-	 */
-	port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, IEEE1588_TIMINCA_INIT);
-	port_id_pci_reg_write(pi, IGBE_82576_TSAUXC, 0);
-
-	/*
-	 * Enable L2 filtering of IEEE1588 Ethernet frame types.
-	 */
-	port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG),
-			      (ETHER_TYPE_1588 |
-			       IGBE_82576_ETQF_FILTER_ENABLE |
-			       IGBE_82576_ETQF_1588_TIMESTAMP));
-
-	/*
-	 * Enable timestamping of received PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
-	tsync_ctl |= IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
-	port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
-
-	/*
-	 * Enable Timestamping of transmitted PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
-	tsync_ctl |= IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
-	port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
-}
-
-static void
-igbe_82576_ieee1588_stop(portid_t pi)
-{
-	uint32_t tsync_ctl;
-
-	/*
-	 * Disable Timestamping of transmitted PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
-	tsync_ctl &= ~IGBE_82576_TSYNCTXCTL_TXTS_ENABLE;
-	port_id_pci_reg_write(pi, IGBE_82576_TSYNCTXCTL, tsync_ctl);
-
-	/*
-	 * Disable timestamping of received PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
-	tsync_ctl &= ~IGBE_82576_TSYNCRXCTL_RXTS_ENABLE;
-	port_id_pci_reg_write(pi, IGBE_82576_TSYNCRXCTL, tsync_ctl);
-
-	/*
-	 * Disable L2 filtering of IEEE1588 Ethernet types.
-	 */
-	port_id_pci_reg_write(pi, IGBE_82576_ETQF(ETQF_FILTER_1588_REG), 0);
-
-	/*
-	 * Stop incrementation of the System Time registers.
-	 */
-	port_id_pci_reg_write(pi, IGBE_82576_TIMINCA, 0);
-}
-
-/**
- * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
- * of a 1GbE 82576 port.
- *
- * @param pi
- *   The port identifier.
- *
- * @param tmst
- *   The address of a 64-bit variable to return the value of the RX timestamp.
- *
- * @return
- *  -1: the RXSTMPL and RXSTMPH registers of the port are not valid.
- *   0: the variable pointed to by the "tmst" parameter contains the value
- *      of the RXSTMPL and RXSTMPH registers of the port.
- */
-static int
-igbe_82576_rx_timestamp_read(portid_t pi, uint64_t *tmst)
-{
-	uint32_t tsync_rxctl;
-	uint32_t rx_stmpl;
-	uint32_t rx_stmph;
-
-	tsync_rxctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCRXCTL);
-	if ((tsync_rxctl & 0x01) == 0)
-		return (-1);
-
-	rx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPL);
-	rx_stmph = port_id_pci_reg_read(pi, IGBE_82576_RXSTMPH);
-	*tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
-	return (0);
-}
-
-/**
- * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
- * of a 1GbE 82576 port.
- *
- * @param pi
- *   The port identifier.
- *
- * @param tmst
- *   The address of a 64-bit variable to return the value of the TX timestamp.
- *
- * @return
- *  -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
- *   0: the variable pointed to by the "tmst" parameter contains the value
- *      of the TXSTMPL and TXSTMPH registers of the port.
- */
-static int
-igbe_82576_tx_timestamp_read(portid_t pi, uint64_t *tmst)
-{
-	uint32_t tsync_txctl;
-	uint32_t tx_stmpl;
-	uint32_t tx_stmph;
-
-	tsync_txctl = port_id_pci_reg_read(pi, IGBE_82576_TSYNCTXCTL);
-	if ((tsync_txctl & 0x01) == 0)
-		return (-1);
-
-	tx_stmpl = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPL);
-	tx_stmph = port_id_pci_reg_read(pi, IGBE_82576_TXSTMPH);
-	*tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
-	return (0);
-}
-
-static struct port_ieee1588_ops igbe_82576_ieee1588_ops = {
-	.ieee1588_start = igbe_82576_ieee1588_start,
-	.ieee1588_stop  = igbe_82576_ieee1588_stop,
-	.rx_tmst_read   = igbe_82576_rx_timestamp_read,
-	.tx_tmst_read   = igbe_82576_tx_timestamp_read,
-};
-
-/**
- * 10GbE 82599 IEEE1588 operations.
- */
-static void
-ixgbe_82599_ieee1588_start(portid_t pi)
-{
-	uint32_t tsync_ctl;
-
-	/*
-	 * Start incrementation of the System Time registers used to
-	 * timestamp PTP packets.
-	 */
-	port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, IEEE1588_TIMINCA_INIT);
-
-	/*
-	 * Enable L2 filtering of IEEE1588 Ethernet frame types.
-	 */
-	port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG),
-			      (ETHER_TYPE_1588 |
-			       IXGBE_82599_ETQF_FILTER_ENABLE |
-			       IXGBE_82599_ETQF_1588_TIMESTAMP));
-
-	/*
-	 * Enable timestamping of received PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
-	tsync_ctl |= IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
-	port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
-
-	/*
-	 * Enable Timestamping of transmitted PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
-	tsync_ctl |= IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
-	port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
-}
-
-static void
-ixgbe_82599_ieee1588_stop(portid_t pi)
-{
-	uint32_t tsync_ctl;
-
-	/*
-	 * Disable Timestamping of transmitted PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
-	tsync_ctl &= ~IXGBE_82599_TSYNCTXCTL_TXTS_ENABLE;
-	port_id_pci_reg_write(pi, IXGBE_82599_TSYNCTXCTL, tsync_ctl);
-
-	/*
-	 * Disable timestamping of received PTP packets.
-	 */
-	tsync_ctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
-	tsync_ctl &= ~IXGBE_82599_TSYNCRXCTL_RXTS_ENABLE;
-	port_id_pci_reg_write(pi, IXGBE_82599_TSYNCRXCTL, tsync_ctl);
-
-	/*
-	 * Disable L2 filtering of IEEE1588 Ethernet frame types.
-	 */
-	port_id_pci_reg_write(pi, IXGBE_82599_ETQF(ETQF_FILTER_1588_REG), 0);
-
-	/*
-	 * Stop incrementation of the System Time registers.
-	 */
-	port_id_pci_reg_write(pi, IXGBE_82599_TIMINCA, 0);
-}
-
-/**
- * Return the 64-bit value contained in the RX IEEE1588 timestamp registers
- * of a 10GbE 82599 port.
- *
- * @param pi
- *   The port identifier.
- *
- * @param tmst
- *   The address of a 64-bit variable to return the value of the TX timestamp.
- *
- * @return
- *  -1: the RX timestamp registers of the port are not valid.
- *   0: the variable pointed to by the "tmst" parameter contains the value
- *      of the RXSTMPL and RXSTMPH registers of the port.
- */
-static int
-ixgbe_82599_rx_timestamp_read(portid_t pi, uint64_t *tmst)
-{
-	uint32_t tsync_rxctl;
-	uint32_t rx_stmpl;
-	uint32_t rx_stmph;
-
-	tsync_rxctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCRXCTL);
-	if ((tsync_rxctl & 0x01) == 0)
-		return (-1);
-
-	rx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPL);
-	rx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_RXSTMPH);
-	*tmst = (uint64_t)(((uint64_t) rx_stmph << 32) | rx_stmpl);
-	return (0);
-}
-
-/**
- * Return the 64-bit value contained in the TX IEEE1588 timestamp registers
- * of a 10GbE 82599 port.
- *
- * @param pi
- *   The port identifier.
- *
- * @param tmst
- *   The address of a 64-bit variable to return the value of the TX timestamp.
- *
- * @return
- *  -1: the TXSTMPL and TXSTMPH registers of the port are not valid.
- *   0: the variable pointed to by the "tmst" parameter contains the value
- *      of the TXSTMPL and TXSTMPH registers of the port.
- */
-static int
-ixgbe_82599_tx_timestamp_read(portid_t pi, uint64_t *tmst)
-{
-	uint32_t tsync_txctl;
-	uint32_t tx_stmpl;
-	uint32_t tx_stmph;
-
-	tsync_txctl = port_id_pci_reg_read(pi, IXGBE_82599_TSYNCTXCTL);
-	if ((tsync_txctl & 0x01) == 0)
-		return (-1);
-
-	tx_stmpl = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPL);
-	tx_stmph = port_id_pci_reg_read(pi, IXGBE_82599_TXSTMPH);
-	*tmst = (uint64_t)(((uint64_t) tx_stmph << 32) | tx_stmpl);
-	return (0);
-}
-
-static struct port_ieee1588_ops ixgbe_82599_ieee1588_ops = {
-	.ieee1588_start = ixgbe_82599_ieee1588_start,
-	.ieee1588_stop  = ixgbe_82599_ieee1588_stop,
-	.rx_tmst_read   = ixgbe_82599_rx_timestamp_read,
-	.tx_tmst_read   = ixgbe_82599_tx_timestamp_read,
-};
-
 static void
-port_ieee1588_rx_timestamp_check(portid_t pi)
+port_ieee1588_rx_timestamp_check(portid_t pi, uint32_t index)
 {
-	struct port_ieee1588_ops *ieee_ops;
-	uint64_t rx_tmst;
+	struct timespec timestamp = {0, 0};
 
-	ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
-	if (ieee_ops->rx_tmst_read(pi, &rx_tmst) < 0) {
-		printf("Port %u: RX timestamp registers not valid\n",
+	if (rte_eth_timesync_read_rx_timestamp(pi, &timestamp, index) < 0) {
+		printf("Port %u RX timestamp registers not valid\n",
 		       (unsigned) pi);
 		return;
 	}
-	printf("Port %u RX timestamp value 0x%"PRIu64"\n",
-	       (unsigned) pi, rx_tmst);
+	printf("Port %u RX timestamp value %"PRIu64"\n",
+	       (unsigned) pi, timestamp.tv_sec);
 }
 
 #define MAX_TX_TMST_WAIT_MICROSECS 1000 /**< 1 milli-second */
@@ -502,26 +98,23 @@ port_ieee1588_rx_timestamp_check(portid_t pi)
 static void
 port_ieee1588_tx_timestamp_check(portid_t pi)
 {
-	struct port_ieee1588_ops *ieee_ops;
-	uint64_t tx_tmst;
-	unsigned wait_us;
+	struct timespec timestamp = {0, 0};
+	unsigned wait_us = 0;
 
-	ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
-	wait_us = 0;
-	while ((ieee_ops->tx_tmst_read(pi, &tx_tmst) < 0) &&
+	while ((rte_eth_timesync_read_tx_timestamp(pi, &timestamp) < 0) &&
 	       (wait_us < MAX_TX_TMST_WAIT_MICROSECS)) {
 		rte_delay_us(1);
 		wait_us++;
 	}
 	if (wait_us >= MAX_TX_TMST_WAIT_MICROSECS) {
-		printf("Port %u: TX timestamp registers not valid after"
+		printf("Port %u TX timestamp registers not valid after "
 		       "%u micro-seconds\n",
 		       (unsigned) pi, (unsigned) MAX_TX_TMST_WAIT_MICROSECS);
 		return;
 	}
-	printf("Port %u TX timestamp value 0x%"PRIu64" validated after "
+	printf("Port %u TX timestamp value %"PRIu64" validated after "
 	       "%u micro-second%s\n",
-	       (unsigned) pi, tx_tmst, wait_us,
+	       (unsigned) pi, timestamp.tv_sec, wait_us,
 	       (wait_us == 1) ? "" : "s");
 }
 
@@ -532,6 +125,7 @@ ieee1588_packet_fwd(struct fwd_stream *fs)
 	struct ether_hdr *eth_hdr;
 	struct ptpv2_msg *ptp_hdr;
 	uint16_t eth_type;
+	uint32_t timesync_index;
 
 	/*
 	 * Receive 1 packet at a time.
@@ -547,6 +141,7 @@ ieee1588_packet_fwd(struct fwd_stream *fs)
 	 */
 	eth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);
 	eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
+
 	if (! (mb->ol_flags & PKT_RX_IEEE1588_PTP)) {
 		if (eth_type == ETHER_TYPE_1588) {
 			printf("Port %u Received PTP packet not filtered"
@@ -562,7 +157,7 @@ ieee1588_packet_fwd(struct fwd_stream *fs)
 		return;
 	}
 	if (eth_type != ETHER_TYPE_1588) {
-		printf("Port %u Received NON PTP packet wrongly"
+		printf("Port %u Received NON PTP packet incorrectly"
 		       " detected by hardware\n",
 		       (unsigned) fs->rx_port);
 		rte_pktmbuf_free(mb);
@@ -573,8 +168,8 @@ ieee1588_packet_fwd(struct fwd_stream *fs)
 	 * Check that the received PTP packet is a PTP V2 packet of type
 	 * PTP_SYNC_MESSAGE.
 	 */
-	ptp_hdr = rte_pktmbuf_mtod_offset(mb, struct ptpv2_msg *,
-					  sizeof(struct ether_hdr));
+	ptp_hdr = (struct ptpv2_msg *) (rte_pktmbuf_mtod(mb, char *) +
+					sizeof(struct ether_hdr));
 	if (ptp_hdr->version != 0x02) {
 		printf("Port %u Received PTP V2 Ethernet frame with wrong PTP"
 		       " protocol version 0x%x (should be 0x02)\n",
@@ -584,7 +179,7 @@ ieee1588_packet_fwd(struct fwd_stream *fs)
 	}
 	if (ptp_hdr->msg_id != PTP_SYNC_MESSAGE) {
 		printf("Port %u Received PTP V2 Ethernet frame with unexpected"
-		       " messageID 0x%x (expected 0x0 - PTP_SYNC_MESSAGE)\n",
+		       " message ID 0x%x (expected 0x0 - PTP_SYNC_MESSAGE)\n",
 		       (unsigned) fs->rx_port, ptp_hdr->msg_id);
 		rte_pktmbuf_free(mb);
 		return;
@@ -604,8 +199,11 @@ ieee1588_packet_fwd(struct fwd_stream *fs)
 		return;
 	}
 
-	/* Check the RX timestamp */
-	port_ieee1588_rx_timestamp_check(fs->rx_port);
+	/* For i40e we need the timesync register index. It is ignored for the
+	 * other PMDs. */
+	timesync_index = mb->timesync & 0x3;
+	/* Read and check the RX timestamp. */
+	port_ieee1588_rx_timestamp_check(fs->rx_port, timesync_index);
 
 	/* Forward PTP packet with hardware TX timestamp */
 	mb->ol_flags |= PKT_TX_IEEE1588_TMST;
@@ -627,23 +225,13 @@ ieee1588_packet_fwd(struct fwd_stream *fs)
 static void
 port_ieee1588_fwd_begin(portid_t pi)
 {
-	struct port_ieee1588_ops *ieee_ops;
-
-	if (strcmp(ports[pi].dev_info.driver_name, "rte_igb_pmd") == 0)
-		ieee_ops = &igbe_82576_ieee1588_ops;
-	else
-		ieee_ops = &ixgbe_82599_ieee1588_ops;
-	ports[pi].fwd_ctx = ieee_ops;
-	(ieee_ops->ieee1588_start)(pi);
+	rte_eth_timesync_enable(pi);
 }
 
 static void
 port_ieee1588_fwd_end(portid_t pi)
 {
-	struct port_ieee1588_ops *ieee_ops;
-
-	ieee_ops = (struct port_ieee1588_ops *)ports[pi].fwd_ctx;
-	(ieee_ops->ieee1588_stop)(pi);
+	rte_eth_timesync_disable(pi);
 }
 
 struct fwd_engine ieee1588_fwd_engine = {
-- 
1.8.1.4

[dpdk-dev] [PATCH v4 7/7] doc: document ieee1588 forwarding mode

[John McNamara]

Document the optional ieee1588 forwarding mode.

Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
 doc/guides/testpmd_app_ug/run_app.rst       | 2 +-
 doc/guides/testpmd_app_ug/testpmd_funcs.rst | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/doc/guides/testpmd_app_ug/run_app.rst b/doc/guides/testpmd_app_ug/run_app.rst
index b29c176..54ae2b2 100644
--- a/doc/guides/testpmd_app_ug/run_app.rst
+++ b/doc/guides/testpmd_app_ug/run_app.rst
@@ -315,7 +315,7 @@ They must be separated from the EAL options, shown in the previous section, with
 
 *   --forward-mode=N
 
-    Set forwarding mode. (N: io|mac|mac_retry|mac_swap|flowgen|rxonly|txonly|csum|icmpecho)
+    Set forwarding mode. (N: io|mac|mac_retry|mac_swap|flowgen|rxonly|txonly|csum|icmpecho|ieee1588)
 
 *   --rss-ip
 
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 1d040cb..4652962 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -635,6 +635,8 @@ The available information categories are:
 
 *   icmpecho: receives a burst of packets, lookup for IMCP echo requests and, if any, send back ICMP echo replies.
 
+*   ieee1588: demonstrate L2 IEEE1588 V2 PTP timestamping for RX and TX. Requires ``CONFIG_RTE_LIBRTE_IEEE1588=y``.
+    Note: TX timestamping is only available in the "Full Featured" TX path. To force ``testpmd`` into this mode set ``--txqflags=0``.
 
 Example:
 
-- 
1.8.1.4

Re: [dpdk-dev] [PATCH v4 0/7] ethdev: add support for ieee1588 timestamping

[Thomas Monjalon]

2015-07-09 14:30, John McNamara:
> This patchset adds ethdev API to enable and read IEEE1588/802.1AS PTP
> timestamps from devices that support it. The following functions are added:
> 
>     rte_eth_timesync_enable()
>     rte_eth_timesync_disable()
>     rte_eth_timesync_read_rx_timestamp()
>     rte_eth_timesync_read_tx_timestamp()
> 
> The "ieee1588" forwarding mode in testpmd is also refactored to demonstrate
> the new API and to clean up the code.
> 
> Adds support for igb, ixgbe and i40e.
> 
> V4:
> * Added timesync field to end of mbuf to pass IEEE1588 registers and flags.
>   Removed previous ABI deprecation notice.
> 
> V3:
> * Fixed issued with version.map.
> 
> V2:
> * Added i40e support.
> 
> * Renamed ethdev functions from rte_eth_ieee15888_*() to rte_eth_timesync_*()
>   since 802.1AS can be supported through the same interfaces.
> 
> V1:
> * Initial version for igb and ixgbe.
> 
> 
> John McNamara (7):
>   ethdev: add support for ieee1588 timestamping
>   mbuf: add field for ieee1588 timesync index
>   e1000: add support for ieee1588 timestamping
>   ixgbe: add support for ieee1588 timestamping
>   i40e: add support for ieee1588 timestamping
>   app/testpmd: refactor ieee1588 forwarding
>   doc: document ieee1588 forwarding mode

Was previously acked by Wenzhuo except the new mbuf field.
Applied, thanks