From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f172.google.com (mail-pd0-f172.google.com [209.85.192.172]) by dpdk.org (Postfix) with ESMTP id EE7245A51 for ; Fri, 17 Jul 2015 02:33:16 +0200 (CEST) Received: by pdrg1 with SMTP id g1so52274895pdr.2 for ; Thu, 16 Jul 2015 17:33:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8HHtBueSHbglZiJJNF/WYGNOrNhizY9Ue5tAAbRiZQM=; b=Mmge7xadNEMn1OAQO+hmQp0IR7szmJPUyDWFAzXYJzTjekE7hcnxcm3rtDp4HqqSrO TkaPIflg2k0SA2APvhQo0rBU+GHpVqYR9ol01nshHJBIOULuvhPo/tmV5PMRGgUnzWa3 yHYweLFDNav0CyQRKJPK2/NMYvlmBBMiZSfvZ0rYAi1wOQFEN+HBFfLxuJpb9UmVaRF0 ZlKO5JNAolbhc//LxnuE6P9nHB9P93JXbjZtWQnWyUb78KZPi8h0bqEg6E9IKa3aY6e+ qyKi40qFfTgdIx+UQtaIpa4ziyxz2o3NjGcEkWMf1KwESXaNTCLKEegFLGEFvxG6zT6c xxlw== X-Gm-Message-State: ALoCoQmrqMO2RlAq57uEeUxla2B2ut+fhPRTqx8kA75yq5HNFnzoIj3YeK2BWa6SzMW7Izcc7jgV X-Received: by 10.70.125.129 with SMTP id mq1mr24095101pdb.19.1437093196252; Thu, 16 Jul 2015 17:33:16 -0700 (PDT) Received: from urahara.home.lan (static-50-53-82-155.bvtn.or.frontiernet.net. [50.53.82.155]) by smtp.gmail.com with ESMTPSA id ob15sm9176081pdb.40.2015.07.16.17.33.14 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Jul 2015 17:33:15 -0700 (PDT) From: Stephen Hemminger To: michael.qiu@intel.com, jing.d.chen@intel.com Date: Thu, 16 Jul 2015 17:33:22 -0700 Message-Id: <1437093202-30265-1-git-send-email-stephen@networkplumber.org> X-Mailer: git-send-email 2.1.4 Cc: dev@dpdk.org Subject: [dpdk-dev] [PATCH] fm10K: fix interrupt fault handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Jul 2015 00:33:17 -0000 The fm10k driver was reading the interrupt cause register but then using the interrupt mask register defines to look at the bits. The result is that if a fault happens, the driver would never clear the fault and would get into an infinite cycle of interrupts. Note: I don't work for Intel or have the hardware manuals (probably requires NDA anyway), but this looks logical and matches how the known working Linux driver handles these bits. Signed-off-by: Stephen Hemminger --- drivers/net/fm10k/fm10k_ethdev.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c index 493b6f9..665d852 100644 --- a/drivers/net/fm10k/fm10k_ethdev.c +++ b/drivers/net/fm10k/fm10k_ethdev.c @@ -1710,7 +1710,7 @@ fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr) const char *estr = "Unknown error"; /* Process PCA fault */ - if (eicr & FM10K_EIMR_PCA_FAULT) { + if (eicr & FM10K_EICR_PCA_FAULT) { err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault); if (err) goto error; @@ -1738,7 +1738,7 @@ fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr) } /* Process THI fault */ - if (eicr & FM10K_EIMR_THI_FAULT) { + if (eicr & FM10K_EICR_THI_FAULT) { err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault); if (err) goto error; @@ -1756,7 +1756,7 @@ fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr) } /* Process FUM fault */ - if (eicr & FM10K_EIMR_FUM_FAULT) { + if (eicr & FM10K_EICR_FUM_FAULT) { err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault); if (err) goto error; -- 2.1.4