From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id F20C18D3A for ; Fri, 23 Oct 2015 16:17:42 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 23 Oct 2015 07:17:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,186,1444719600"; d="scan'208";a="586676655" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by FMSMGA003.fm.intel.com with ESMTP; 23 Oct 2015 07:17:41 -0700 Received: from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com [10.237.217.46]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id t9NEHeOO002499; Fri, 23 Oct 2015 15:17:40 +0100 Received: from sivswdev02.ir.intel.com (localhost [127.0.0.1]) by sivswdev02.ir.intel.com with ESMTP id t9NEHeo2017765; Fri, 23 Oct 2015 15:17:40 +0100 Received: (from dhunt5@localhost) by sivswdev02.ir.intel.com with id t9NEHeQo017761; Fri, 23 Oct 2015 15:17:40 +0100 From: David Hunt To: dev@dpdk.org Date: Fri, 23 Oct 2015 15:17:11 +0100 Message-Id: <1445609833-17649-10-git-send-email-david.hunt@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1445609833-17649-1-git-send-email-david.hunt@intel.com> References: <1445609833-17649-1-git-send-email-david.hunt@intel.com> Cc: Benjamin Boren Subject: [dpdk-dev] [PATCH 09/11] lib: add armv8 rte_vect.h X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Oct 2015 14:17:43 -0000 From: Benjamin Boren Signed-off-by: Benjamin Boren Signed-off-by: David Hunt --- .../common/include/arch/arm64/rte_vect.h | 102 +++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_vect.h diff --git a/lib/librte_eal/common/include/arch/arm64/rte_vect.h b/lib/librte_eal/common/include/arch/arm64/rte_vect.h new file mode 100644 index 0000000..ceae710 --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm64/rte_vect.h @@ -0,0 +1,102 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Intel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_VECT_ARM64_H_ +#define _RTE_VECT_ARM64_H_ + +/** + * @file + * + * RTE SSE/AVX related header. + */ + + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef float32x4_t __m128; + +typedef int32x4_t __m128i; + +typedef __m128i xmm_t; + +#define XMM_SIZE (sizeof(xmm_t)) +#define XMM_MASK (XMM_SIZE - 1) + +typedef union rte_xmm { + xmm_t x; + uint8_t u8[XMM_SIZE / sizeof(uint8_t)]; + uint16_t u16[XMM_SIZE / sizeof(uint16_t)]; + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; + double pd[XMM_SIZE / sizeof(double)]; +} rte_xmm_t __aligned(16); + +#define _mm_srli_epi32(a, imm) { (__m128i)vshrq_n_u32((uint32x4_t)a, imm) } + +#define _mm_srli_si128(a, imm) { (__m128i)vextq_s8((int8x16_t)a, \ + vdupq_n_s8(0), (imm)) } + +static inline __m128i +_mm_set_epi32(int i3, int i2, int i1, int i0); +static inline int +_mm_cvtsi128_si64(__m128i a); + +static inline __m128i +_mm_set_epi32(int i3, int i2, int i1, int i0) +{ + int32_t __aligned(16) data[4] = { i0, i1, i2, i3 }; + return vld1q_s32(data); +} + +static inline int +_mm_cvtsi128_si64(__m128i a) +{ + return vgetq_lane_s64(a, 0); +} + +static inline __m128i +_mm_and_si128(__m128i a, __m128i b) +{ + return (__m128i)vandq_s32(a, b); +} + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_VECT_ARM64_H_*/ + -- 2.1.4