[dpdk-dev] [PATCH 00/11] add armv8 architecture support

[dpdk-dev] [PATCH 00/11] add armv8 architecture support

[David Hunt]

This patch provides support for the ARMv8 architecture. We hope that this will
encourage the ARM community to contribute PMDs for their SoCs to DPDK.

For now, we've added Intel engineers to the MAINTAINERS file. We would like to
encourage the ARM community to take over maintenance of this area in future,
and to further improve it.

ACL and LPM libraries have been disabled in the config due to their reliance
on SSE. 

This patch was tested on an Applied Micro X-Gene Mustang board (pcap only)

This patch was also tested with an Intel 82599 NIC on a Gigabyte MP30-AR0
passing traffic between the two NIC ports using testpmd.

Notes on DPDK configuration:

  Did not use igb_uio or kni so the following optionse were disabled in 
  config/common_linuxapp

  CONFIG_RTE_EAL_IGB_UIO=n
  CONFIG_RTE_LIBRTE_KNI=n
  CONFIG_RTE_KNI_KMOD=n

  make config T=arm64-native-linuxapp-gcc
  make install T=arm64-native-linuxapp-gcc
  
Notes on arm64 kernel configuration:

  Using Ubuntu 14.04 LTS with a 4.3.0-rc6 kernel (with modified PCI drivers),
  and uio_pci_generic.
  ARM64 kernels do not seem to have functional resource mapping of PCI memory
  (PCI_MMAP), so the pci driver needs to be patched to enable this. The
  symptom of this is when /sys/bus/pci/devices/0000:0X:00.Y directory is
  missing the resource0...N files for mmapping the device memory. Earlier
  kernels (3.13.x) had these files present, but mmap'ping resulted in a
  "Bus Error" when the NIC memory was accessed.
  However, during limited testing with a modified 4.3.0-rc6 kernel, we were
  able to mmap the NIC memory, and pass traffic between the two ports on a
  82599 NIC connected via fibre cable. 
  We have no plans to upstream a kernel patch for this and hope that
  someone more familiar with the arm architecture can create a proper patch
  and enable this functionality.

Benjamin Boren (11):
  lib: add armv8 rte_atomic.h
  lib: add armv8 rte_byteorder.h
  lib: add armv8 rte_cpuflags.h
  lib: add armv8 rte_cycles.h
  lib: add armv8 rte_memcpy.h
  lib: add armv8 rte_prefetch.h
  lib: add armv8 rte_rwlock.h
  lib: add armv8 rte_spinlock.h
  lib: add armv8 rte_vect.h
  mk: add makefile and config changes for armv8 architecture
  app: add armv8 cpuflags check to test_cpuflags application

 MAINTAINERS                                        |   6 +
 app/test/test_cpuflags.c                           |  17 ++
 config/defconfig_arm64-native-linuxapp-gcc         |  55 +++++
 .../common/include/arch/arm64/rte_atomic.h         | 269 +++++++++++++++++++++
 .../common/include/arch/arm64/rte_byteorder.h      | 157 ++++++++++++
 .../common/include/arch/arm64/rte_cpuflags.h       | 137 +++++++++++
 .../common/include/arch/arm64/rte_cycles.h         |  77 ++++++
 .../common/include/arch/arm64/rte_memcpy.h         | 266 ++++++++++++++++++++
 .../common/include/arch/arm64/rte_prefetch.h       |  61 +++++
 .../common/include/arch/arm64/rte_rwlock.h         |  70 ++++++
 .../common/include/arch/arm64/rte_spinlock.h       | 114 +++++++++
 .../common/include/arch/arm64/rte_vect.h           | 102 ++++++++
 mk/arch/arm64/rte.vars.mk                          |  58 +++++
 mk/machine/armv8-a/rte.vars.mk                     |  57 +++++
 mk/rte.cpuflags.mk                                 |   9 +
 15 files changed, 1455 insertions(+)
 create mode 100644 config/defconfig_arm64-native-linuxapp-gcc
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_atomic.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_byteorder.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_cpuflags.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_cycles.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_memcpy.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_prefetch.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_rwlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_spinlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_vect.h
 create mode 100644 mk/arch/arm64/rte.vars.mk
 create mode 100644 mk/machine/armv8-a/rte.vars.mk

-- 
2.1.4

[dpdk-dev] [PATCH 01/11] lib: add armv8 rte_atomic.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_atomic.h         | 269 +++++++++++++++++++++
 1 file changed, 269 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_atomic.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_atomic.h b/lib/librte_eal/common/include/arch/arm64/rte_atomic.h
new file mode 100644
index 0000000..c9e0dff
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_atomic.h
@@ -0,0 +1,269 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of Intel Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_ATOMIC_ARM64_H_
+#define _RTE_ATOMIC_ARM64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_atomic.h"
+
+/**
+ * @file
+ * Atomic Operations
+ *
+ * This file defines a API for atomic operations.
+ */
+
+/**
+ * General memory barrier.
+ *
+ * Guarantees that the LOAD and STORE operations generated before the
+ * barrier occur before the LOAD and STORE operations generated after.
+ */
+#define	rte_mb()  {asm volatile("dsb sy" : : : "memory"); }
+
+/**
+ * Write memory barrier.
+ *
+ * Guarantees that the STORE operations generated before the barrier
+ * occur before the STORE operations generated after.
+ */
+#define	rte_wmb() {asm volatile("dsb st" : : : "memory"); }
+
+/**
+ * Read memory barrier.
+ *
+ * Guarantees that the LOAD operations generated before the barrier
+ * occur before the LOAD operations generated after.
+ */
+#define	rte_rmb() {asm volatile("dsb ld" : : : "memory"); }
+
+
+
+/*------------------------- 16 bit atomic operations -------------------------*/
+
+#ifndef RTE_FORCE_INTRINSICS
+static inline int
+rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
+{
+	return __sync_bool_compare_and_swap(dst, exp, src);
+}
+
+static inline void
+rte_atomic16_inc(rte_atomic16_t *v)
+{
+	rte_atomic16_add(v, 1);
+}
+
+static inline void
+rte_atomic16_dec(rte_atomic16_t *v)
+{
+	rte_atomic16_sub(v, 1);
+}
+
+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
+{
+	return (__sync_add_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
+{
+	return (__sync_sub_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
+{
+	return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
+}
+
+
+/*------------------------- 32 bit atomic operations -------------------------*/
+
+static inline int
+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
+{
+	return __sync_bool_compare_and_swap(dst, exp, src);
+}
+
+static inline void
+rte_atomic32_inc(rte_atomic32_t *v)
+{
+	rte_atomic32_add(v, 1);
+}
+
+static inline void
+rte_atomic32_dec(rte_atomic32_t *v)
+{
+	rte_atomic32_sub(v, 1);
+}
+
+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
+{
+	return (__sync_add_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
+{
+	return (__sync_sub_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
+{
+	return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
+}
+
+/*------------------------- 64 bit atomic operations -------------------------*/
+
+static inline int
+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
+{
+	return __sync_bool_compare_and_swap(dst, exp, src);
+}
+
+static inline void
+rte_atomic64_init(rte_atomic64_t *v)
+{
+#ifdef __LP64__
+	v->cnt = 0;
+#else
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+					tmp, 0);
+	}
+#endif
+}
+
+static inline int64_t
+rte_atomic64_read(rte_atomic64_t *v)
+{
+#ifdef __LP64__
+	return v->cnt;
+#else
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		/* replace the value by itself */
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+					tmp, tmp);
+	}
+	return tmp;
+#endif
+}
+
+static inline void
+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
+{
+#ifdef __LP64__
+	v->cnt = new_value;
+#else
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+					tmp, new_value);
+	}
+#endif
+}
+
+static inline void
+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
+{
+	__sync_fetch_and_add(&v->cnt, inc);
+}
+
+static inline void
+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
+{
+	__sync_fetch_and_sub(&v->cnt, dec);
+}
+
+static inline void
+rte_atomic64_inc(rte_atomic64_t *v)
+{
+	rte_atomic64_add(v, 1);
+}
+
+static inline void
+rte_atomic64_dec(rte_atomic64_t *v)
+{
+	rte_atomic64_sub(v, 1);
+}
+
+static inline int64_t
+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
+{
+	return __sync_add_and_fetch(&v->cnt, inc);
+}
+
+static inline int64_t
+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
+{
+	return __sync_sub_and_fetch(&v->cnt, dec);
+}
+
+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
+{
+	return rte_atomic64_add_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
+{
+	return rte_atomic64_sub_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
+{
+	return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
+}
+
+static inline void rte_atomic64_clear(rte_atomic64_t *v)
+{
+	rte_atomic64_set(v, 0);
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ATOMIC_ARM64_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 02/11] lib: add armv8 rte_byteorder.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_byteorder.h      | 157 +++++++++++++++++++++
 1 file changed, 157 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_byteorder.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_byteorder.h b/lib/librte_eal/common/include/arch/arm64/rte_byteorder.h
new file mode 100644
index 0000000..c1bd56e
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_byteorder.h
@@ -0,0 +1,157 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Inspired from FreeBSD src/sys/powerpc/include/endian.h
+ * Copyright (c) 1987, 1991, 1993
+ * The Regents of the University of California.  All rights reserved.
+*/
+
+#ifndef _RTE_BYTEORDER_ARM_64_H_
+#define _RTE_BYTEORDER_ARM_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_byteorder.h"
+
+/*
+ * An architecture-optimized byte swap for a 16-bit value.
+ *
+ * Do not use this function directly. The preferred function is rte_bswap16().
+ */
+static inline uint16_t rte_arch_bswap16(uint16_t _x)
+{
+	register uint16_t x = _x;
+
+	asm volatile ("rev16 %[x1], %[x2]"
+			: [x1] "=r" (x)
+			: [x2] "r" (x));
+	return x;
+}
+
+/*
+ * An architecture-optimized byte swap for a 32-bit value.
+ *
+ * Do not use this function directly. The preferred function is rte_bswap32().
+ */
+static inline uint32_t rte_arch_bswap32(uint32_t _x)
+{
+	register uint32_t x = _x;
+
+	asm volatile ("rev32 %[x1], %[x2]"
+			: [x1] "=r" (x)
+			: [x2] "r" (x));
+	return x;
+}
+
+/*
+ * An architecture-optimized byte swap for a 64-bit value.
+ *
+  * Do not use this function directly. The preferred function is rte_bswap64().
+ */
+/* 64-bit mode */
+static inline uint64_t rte_arch_bswap64(uint64_t _x)
+{
+	register uint64_t x = _x;
+
+	asm volatile ("rev %[x1], %[x2]"
+			: [x1] "=r" (x)
+			: [x2] "r" (x));
+	return x;
+}
+
+#ifndef RTE_FORCE_INTRINSICS
+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?		\
+				   rte_constant_bswap16(x) :		\
+				   rte_arch_bswap16(x)))
+
+#define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ?		\
+				   rte_constant_bswap32(x) :		\
+				   rte_arch_bswap32(x)))
+
+#define rte_bswap64(x) ((uint64_t)(__builtin_constant_p(x) ?		\
+				   rte_constant_bswap64(x) :		\
+				   rte_arch_bswap64(x)))
+#else
+/*
+ * __builtin_bswap16 is only available gcc 4.8 and upwards
+ */
+#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)
+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?		\
+				   rte_constant_bswap16(x) :		\
+				   rte_arch_bswap16(x)))
+#endif
+#endif
+
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+#else /* RTE_BIG_ENDIAN */
+
+#define rte_cpu_to_le_16(x) rte_bswap16(x)
+#define rte_cpu_to_le_32(x) rte_bswap32(x)
+#define rte_cpu_to_le_64(x) rte_bswap64(x)
+
+#define rte_cpu_to_be_16(x) (x)
+#define rte_cpu_to_be_32(x) (x)
+#define rte_cpu_to_be_64(x) (x)
+
+#define rte_le_to_cpu_16(x) rte_bswap16(x)
+#define rte_le_to_cpu_32(x) rte_bswap32(x)
+#define rte_le_to_cpu_64(x) rte_bswap64(x)
+
+#define rte_be_to_cpu_16(x) (x)
+#define rte_be_to_cpu_32(x) (x)
+#define rte_be_to_cpu_64(x) (x)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_BYTEORDER_ARM_64_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 03/11] lib: add armv8 rte_cpuflags.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_cpuflags.h       | 137 +++++++++++++++++++++
 1 file changed, 137 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_cpuflags.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_cpuflags.h b/lib/librte_eal/common/include/arch/arm64/rte_cpuflags.h
new file mode 100644
index 0000000..b4dcf9d
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_cpuflags.h
@@ -0,0 +1,137 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_CPUFLAGS_ARM_64_H_
+#define _RTE_CPUFLAGS_ARM_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+
+#include "generic/rte_cpuflags.h"
+
+/* Symbolic values for the entries in the auxiliary table */
+#define AT_HWCAP  16
+#define AT_HWCAP2 26
+#define AT_PLATFORM 15
+
+/* software based registers */
+enum cpu_register_t {
+	REG_HWCAP = 0,
+	AARCH_MODE,
+};
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+	RTE_CPUFLAG_FP = 0,
+	RTE_CPUFLAG_ASIMD,
+	RTE_CPUFLAG_EVTSTRM,
+	RTE_CPUFLAG_AARCH64,
+	RTE_CPUFLAG_AARCH32,
+	/* The last item */
+	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
+};
+
+static const struct feature_entry cpu_feature_table[] = {
+	FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP,  0)
+	FEAT_DEF(ASIMD, 0x00000001, 0, REG_HWCAP,  1)
+	FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP,  2)
+	FEAT_DEF(AARCH64, 0x00000001, 0, AARCH_MODE, 3)
+	FEAT_DEF(AARCH32, 0x00000001, 0, AARCH_MODE, 4)
+};
+
+/*
+ * Read AUXV software register and get cpu features for Power
+ */
+static inline void
+rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
+	__attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
+{
+	int auxv_fd;
+	Elf64_auxv_t auxv;
+
+	auxv_fd = open("/proc/self/auxv", O_RDONLY);
+	assert(auxv_fd);
+	while (read(auxv_fd, &auxv,
+		sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) {
+		if (auxv.a_type == AT_HWCAP)
+			out[REG_HWCAP] = auxv.a_un.a_val;
+		if (auxv.a_type == AT_PLATFORM) {
+			if (strcmp((const char *)auxv.a_un.a_val,
+					"aarch64") == 0)
+				out[AARCH_MODE] = (1 << 3);
+			else if (strcmp((const char *)auxv.a_un.a_val,
+					"aarch32") == 0)
+				out[AARCH_MODE] =  (1 << 4);
+		}
+	}
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+static inline int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+	const struct feature_entry *feat;
+	cpuid_registers_t regs = {0};
+
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		/* Flag does not match anything in the feature tables */
+		return -ENOENT;
+
+	feat = &cpu_feature_table[feature];
+
+	if (!feat->leaf)
+		/* This entry in the table wasn't filled out! */
+		return -EFAULT;
+
+	/* get the cpuid leaf containing the desired feature */
+	rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
+
+	/* check if the feature is enabled */
+	return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CPUFLAGS_ARM_64_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 04/11] lib: add armv8 rte_cycles.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_cycles.h         | 77 ++++++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_cycles.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_cycles.h b/lib/librte_eal/common/include/arch/arm64/rte_cycles.h
new file mode 100644
index 0000000..60894c7
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_cycles.h
@@ -0,0 +1,77 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_CYCLES_ARM_64_H_
+#define _RTE_CYCLES_ARM_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static inline uint64_t
+rte_rdtsc(void)
+{
+	uint64_t tsc;
+
+	asm volatile("mrs %0, CNTVCT_EL0" : "=r" (tsc));
+
+#ifdef RTE_TIMER_MULTIPLIER
+	return tsc * RTE_TIMER_MULTIPLIER;
+#else
+	return tsc;
+#endif
+
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+	asm volatile("isb sy" :::);
+	return rte_rdtsc();
+}
+
+static inline uint64_t
+rte_get_tsc_cycles(void) { return rte_rdtsc(); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CYCLES_ARM_64_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 05/11] lib: add armv8 rte_memcpy.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_memcpy.h         | 266 +++++++++++++++++++++
 1 file changed, 266 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_memcpy.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_memcpy.h b/lib/librte_eal/common/include/arch/arm64/rte_memcpy.h
new file mode 100644
index 0000000..d413045
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_memcpy.h
@@ -0,0 +1,266 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_MEMCPY_ARM_64_H_
+#define _RTE_MEMCPY_ARM_64_H_
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+	asm volatile("LDP d0, d1, [%0]\n\t"
+		     "STP d0, d1, [%1]\n\t"
+		     : : "r" (src), "r" (dst) :
+	);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+	asm volatile("LDP q0, q1, [%0]\n\t"
+		     "STP q0, q1, [%1]\n\t"
+		     : : "r" (src), "r" (dst) :
+	);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+	asm volatile("LDP q0, q1, [%0]\n\t"
+		     "STP q0, q1, [%1]\n\t"
+		     "LDP d0, d1, [%0 , #32]\n\t"
+		     "STP d0, d1, [%1 , #32]\n\t"
+		     : : "r" (src), "r" (dst) :
+	);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+	asm volatile("LDP q0, q1, [%0]\n\t"
+		     "STP q0, q1, [%1]\n\t"
+		     "LDP q0, q1, [%0 , #32]\n\t"
+		     "STP q0, q1, [%1 , #32]\n\t"
+		     : : "r" (src), "r" (dst) :
+	);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+	asm volatile("LDP q0, q1, [%0]\n\t"
+		     "STP q0, q1, [%1]\n\t"
+		     "LDP q0, q1, [%0 , #32]\n\t"
+		     "STP q0, q1, [%1 , #32]\n\t"
+		     "LDP q0, q1, [%0 , #64]\n\t"
+		     "STP q0, q1, [%1 , #64]\n\t"
+		     "LDP q0, q1, [%0 , #96]\n\t"
+		     "STP q0, q1, [%1 , #96]\n\t"
+		     : : "r" (src), "r" (dst) :
+	);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+	asm volatile("LDP q0, q1, [%0]\n\t"
+		     "STP q0, q1, [%1]\n\t"
+		     "LDP q0, q1, [%0 , #32]\n\t"
+		     "STP q0, q1, [%1 , #32]\n\t"
+		     "LDP q0, q1, [%0 , #64]\n\t"
+		     "STP q0, q1, [%1 , #64]\n\t"
+		     "LDP q0, q1, [%0 , #96]\n\t"
+		     "STP q0, q1, [%1 , #96]\n\t"
+		     "LDP q0, q1, [%0 , #128]\n\t"
+		     "STP q0, q1, [%1 , #128]\n\t"
+		     "LDP q0, q1, [%0 , #160]\n\t"
+		     "STP q0, q1, [%1 , #160]\n\t"
+		     "LDP q0, q1, [%0 , #192]\n\t"
+		     "STP q0, q1, [%1 , #192]\n\t"
+		     "LDP q0, q1, [%0 , #224]\n\t"
+		     "STP q0, q1, [%1 , #224]\n\t"
+		     : : "r" (src), "r" (dst) :
+	);
+}
+/*
+static inline void
+	rte_mov16(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 16); }
+static inline void
+	rte_mov32(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 32); }
+static inline void
+	rte_mov64(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 64); }
+static inline void
+	rte_mov128(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 128); }
+static inline void
+	rte_mov256(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 256); }
+static inline void
+	rte_mov48(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 48); }
+*/
+#define rte_memcpy(dst, src, n)              \
+	({ (__builtin_constant_p(n)) ?       \
+	memcpy((dst), (src), (n)) :          \
+	rte_memcpy_func((dst), (src), (n)); })
+
+
+static inline void *
+rte_memcpy_func(void *dst, const void *src, size_t n)
+{
+	void *ret = dst;
+
+	/* We can't copy < 16 bytes using XMM registers so do it manually. */
+	if (n < 16) {
+		if (n & 0x01) {
+			*(uint8_t *)dst = *(const uint8_t *)src;
+			dst = (uint8_t *)dst + 1;
+			src = (const uint8_t *)src + 1;
+		}
+		if (n & 0x02) {
+			*(uint16_t *)dst = *(const uint16_t *)src;
+			dst = (uint16_t *)dst + 1;
+			src = (const uint16_t *)src + 1;
+		}
+		if (n & 0x04) {
+			*(uint32_t *)dst = *(const uint32_t *)src;
+			dst = (uint32_t *)dst + 1;
+			src = (const uint32_t *)src + 1;
+		}
+		if (n & 0x08)
+			*(uint64_t *)dst = *(const uint64_t *)src;
+		return ret;
+	}
+
+	/* Special fast cases for <= 128 bytes */
+	if (n <= 32) {
+		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+		rte_mov16((uint8_t *)dst - 16 + n,
+			(const uint8_t *)src - 16 + n);
+		return ret;
+	}
+
+	if (n <= 64) {
+		rte_mov32((uint8_t *)dst, (const uint8_t *)src);
+		rte_mov32((uint8_t *)dst - 32 + n,
+			(const uint8_t *)src - 32 + n);
+		return ret;
+	}
+
+	if (n <= 128) {
+		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+		rte_mov64((uint8_t *)dst - 64 + n,
+			(const uint8_t *)src - 64 + n);
+		return ret;
+	}
+
+	/*
+	 * For large copies > 128 bytes. This combination of 256, 64 and 16 byte
+	 * copies was found to be faster than doing 128 and 32 byte copies as
+	 * well.
+	 */
+	for ( ; n >= 256; n -= 256) {
+		rte_mov256((uint8_t *)dst, (const uint8_t *)src);
+		dst = (uint8_t *)dst + 256;
+		src = (const uint8_t *)src + 256;
+	}
+
+	/*
+	 * We split the remaining bytes (which will be less than 256) into
+	 * 64byte (2^6) chunks.
+	 * Using incrementing integers in the case labels of a switch statement
+	 * enourages the compiler to use a jump table. To get incrementing
+	 * integers, we shift the 2 relevant bits to the LSB position to first
+	 * get decrementing integers, and then subtract.
+	 */
+	switch (3 - (n >> 6)) {
+	case 0x00:
+		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+		n -= 64;
+		dst = (uint8_t *)dst + 64;
+		src = (const uint8_t *)src + 64;      /* fallthrough */
+	case 0x01:
+		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+		n -= 64;
+		dst = (uint8_t *)dst + 64;
+		src = (const uint8_t *)src + 64;      /* fallthrough */
+	case 0x02:
+		rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+		n -= 64;
+		dst = (uint8_t *)dst + 64;
+		src = (const uint8_t *)src + 64;      /* fallthrough */
+	default:
+		break;
+	}
+
+	/*
+	 * We split the remaining bytes (which will be less than 64) into
+	 * 16byte (2^4) chunks, using the same switch structure as above.
+	 */
+	switch (3 - (n >> 4)) {
+	case 0x00:
+		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+		n -= 16;
+		dst = (uint8_t *)dst + 16;
+		src = (const uint8_t *)src + 16;      /* fallthrough */
+	case 0x01:
+		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+		n -= 16;
+		dst = (uint8_t *)dst + 16;
+		src = (const uint8_t *)src + 16;      /* fallthrough */
+	case 0x02:
+		rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+		n -= 16;
+		dst = (uint8_t *)dst + 16;
+		src = (const uint8_t *)src + 16;      /* fallthrough */
+	default:
+		break;
+	}
+
+	/* Copy any remaining bytes, without going beyond end of buffers */
+	if (n != 0)
+		rte_mov16((uint8_t *)dst - 16 + n,
+			(const uint8_t *)src - 16 + n);
+	return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MEMCPY_ARM_64_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 06/11] lib: add armv8 rte_prefetch.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_prefetch.h       | 61 ++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_prefetch.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_prefetch.h b/lib/librte_eal/common/include/arch/arm64/rte_prefetch.h
new file mode 100644
index 0000000..b0d9170
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_prefetch.h
@@ -0,0 +1,61 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of Intel Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_PREFETCH_ARM_64_H_
+#define _RTE_PREFETCH_ARM_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_prefetch.h"
+/* May want to add PSTL1KEEP instructions for prefetch for ownership. */
+static inline void rte_prefetch0(const volatile void *p)
+{
+	asm volatile ("PRFM PLDL1KEEP, [%0]" : : "r" (p));
+}
+
+static inline void rte_prefetch1(const volatile void *p)
+{
+	asm volatile ("PRFM PLDL2KEEP, [%0]" : : "r" (p));
+}
+
+static inline void rte_prefetch2(const volatile void *p)
+{
+	asm volatile ("PRFM PLDL3KEEP, [%0]" : : "r" (p));
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PREFETCH_ARM_64_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 07/11] lib: add armv8 rte_rwlock.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_rwlock.h         | 70 ++++++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_rwlock.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_rwlock.h b/lib/librte_eal/common/include/arch/arm64/rte_rwlock.h
new file mode 100644
index 0000000..8f67a19
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_rwlock.h
@@ -0,0 +1,70 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) EZchip Semiconductor Ltd. 2015.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of EZchip Semiconductor nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_RWLOCK_TILE_H_
+#define _RTE_RWLOCK_TILE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_RWLOCK_TILE_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 08/11] lib: add armv8 rte_spinlock.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_spinlock.h       | 114 +++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_spinlock.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_spinlock.h b/lib/librte_eal/common/include/arch/arm64/rte_spinlock.h
new file mode 100644
index 0000000..64928ba
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_spinlock.h
@@ -0,0 +1,114 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of IBM Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _RTE_SPINLOCK_ARM_64_H_
+#define _RTE_SPINLOCK_ARM_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+/* Fixme: Use intrinsics to implement the spinlock on ARM64 architecture */
+
+#ifndef RTE_FORCE_INTRINSICS
+
+static inline void
+rte_spinlock_lock(rte_spinlock_t *sl)
+{
+	while (__sync_lock_test_and_set(&sl->locked, 1))
+		while (sl->locked)
+			rte_pause();
+}
+
+static inline void
+rte_spinlock_unlock(rte_spinlock_t *sl)
+{
+	__sync_lock_release(&sl->locked);
+}
+
+static inline int
+rte_spinlock_trylock(rte_spinlock_t *sl)
+{
+	return (__sync_lock_test_and_set(&sl->locked, 1) == 0);
+}
+
+#endif
+
+static inline int rte_tm_supported(void)
+{
+	return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+	return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+	return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_SPINLOCK_ARM_64_H_ */
-- 
2.1.4

[dpdk-dev] [PATCH 09/11] lib: add armv8 rte_vect.h

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 .../common/include/arch/arm64/rte_vect.h           | 102 +++++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_vect.h

diff --git a/lib/librte_eal/common/include/arch/arm64/rte_vect.h b/lib/librte_eal/common/include/arch/arm64/rte_vect.h
new file mode 100644
index 0000000..ceae710
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm64/rte_vect.h
@@ -0,0 +1,102 @@
+/*
+ *    BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of Intel Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_VECT_ARM64_H_
+#define _RTE_VECT_ARM64_H_
+
+/**
+ * @file
+ *
+ * RTE SSE/AVX related header.
+ */
+
+
+#include <arm_neon.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef float32x4_t __m128;
+
+typedef int32x4_t __m128i;
+
+typedef __m128i xmm_t;
+
+#define XMM_SIZE        (sizeof(xmm_t))
+#define XMM_MASK        (XMM_SIZE - 1)
+
+typedef union rte_xmm {
+	xmm_t    x;
+	uint8_t  u8[XMM_SIZE / sizeof(uint8_t)];
+	uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
+	uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
+	uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
+	double   pd[XMM_SIZE / sizeof(double)];
+} rte_xmm_t __aligned(16);
+
+#define _mm_srli_epi32(a, imm) { (__m128i)vshrq_n_u32((uint32x4_t)a, imm) }
+
+#define _mm_srli_si128(a, imm) { (__m128i)vextq_s8((int8x16_t)a, \
+					vdupq_n_s8(0), (imm)) }
+
+static inline  __m128i
+_mm_set_epi32(int i3, int i2, int i1, int i0);
+static inline int
+_mm_cvtsi128_si64(__m128i a);
+
+static inline  __m128i
+_mm_set_epi32(int i3, int i2, int i1, int i0)
+{
+	int32_t __aligned(16) data[4] = { i0, i1, i2, i3 };
+	return vld1q_s32(data);
+}
+
+static inline int
+_mm_cvtsi128_si64(__m128i a)
+{
+	return vgetq_lane_s64(a, 0);
+}
+
+static inline __m128i
+_mm_and_si128(__m128i a, __m128i b)
+{
+	return (__m128i)vandq_s32(a, b);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_VECT_ARM64_H_*/
+
-- 
2.1.4

[dpdk-dev] [PATCH 10/11] mk: add makefile and config changes for armv8 architecture

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 MAINTAINERS                                |  6 ++++
 config/defconfig_arm64-native-linuxapp-gcc | 55 ++++++++++++++++++++++++++++
 mk/arch/arm64/rte.vars.mk                  | 58 ++++++++++++++++++++++++++++++
 mk/machine/armv8-a/rte.vars.mk             | 57 +++++++++++++++++++++++++++++
 mk/rte.cpuflags.mk                         |  9 +++++
 5 files changed, 185 insertions(+)
 create mode 100644 config/defconfig_arm64-native-linuxapp-gcc
 create mode 100644 mk/arch/arm64/rte.vars.mk
 create mode 100644 mk/machine/armv8-a/rte.vars.mk

diff --git a/MAINTAINERS b/MAINTAINERS
index 080a8e8..93904ed 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -129,6 +129,12 @@ M: Bruce Richardson <bruce.richardson@intel.com>
 M: Konstantin Ananyev <konstantin.ananyev@intel.com>
 F: lib/librte_eal/common/include/arch/x86/
 
+Arm V8
+M: Ben Boren <ben.boren@intel.com>
+M: David Hunt <david.hunt@intel.com>
+M: Amrute Zende <amruta.zende@intel.com>
+F: lib/librte_eal/common/include/arch/arm64/
+
 Linux EAL (with overlaps)
 M: David Marchand <david.marchand@6wind.com>
 F: lib/librte_eal/linuxapp/Makefile
diff --git a/config/defconfig_arm64-native-linuxapp-gcc b/config/defconfig_arm64-native-linuxapp-gcc
new file mode 100644
index 0000000..302417f
--- /dev/null
+++ b/config/defconfig_arm64-native-linuxapp-gcc
@@ -0,0 +1,55 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+#   All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of Intel Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#include "common_linuxapp"
+
+CONFIG_RTE_MACHINE="armv8-a"
+
+CONFIG_RTE_ARCH="arm64"
+CONFIG_RTE_ARCH_ARM64=y
+CONFIG_RTE_ARCH_64=y
+
+CONFIG_RTE_TOOLCHAIN="gcc"
+CONFIG_RTE_TOOLCHAIN_GCC=y
+
+CONFIG_RTE_IXGBE_INC_VECTOR=n
+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
+CONFIG_RTE_LIBRTE_IVSHMEM=n
+CONFIG_RTE_LIBRTE_EAL_HOTPLUG=n
+
+CONFIG_RTE_LIBRTE_LPM=n
+CONFIG_RTE_LIBRTE_ACL=n
+CONFIG_RTE_LIBRTE_TABLE=n
+CONFIG_RTE_LIBRTE_PIPELINE=n
+
+# This is used to adjust the generic arm timer to align with the cpu cycle count.
+CONFIG_RTE_TIMER_MULTIPLIER=48
diff --git a/mk/arch/arm64/rte.vars.mk b/mk/arch/arm64/rte.vars.mk
new file mode 100644
index 0000000..9a148e1
--- /dev/null
+++ b/mk/arch/arm64/rte.vars.mk
@@ -0,0 +1,58 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of Intel Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#
+# arch:
+#
+#   - define ARCH variable (overridden by cmdline or by previous
+#     optional define in machine .mk)
+#   - define CROSS variable (overridden by cmdline or previous define
+#     in machine .mk)
+#   - define CPU_CFLAGS variable (overridden by cmdline or previous
+#     define in machine .mk)
+#   - define CPU_LDFLAGS variable (overridden by cmdline or previous
+#     define in machine .mk)
+#   - define CPU_ASFLAGS variable (overridden by cmdline or previous
+#     define in machine .mk)
+#   - may override any previously defined variable
+#
+# examples for CONFIG_RTE_ARCH: i686, x86_64, x86_64_32
+#
+
+ARCH  ?= arm64
+# common arch dir in eal headers
+ARCH_DIR := arm64
+CROSS ?=
+
+CPU_CFLAGS  ?= -flax-vector-conversions
+CPU_LDFLAGS ?=
+CPU_ASFLAGS ?=
+
+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS
diff --git a/mk/machine/armv8-a/rte.vars.mk b/mk/machine/armv8-a/rte.vars.mk
new file mode 100644
index 0000000..b785062
--- /dev/null
+++ b/mk/machine/armv8-a/rte.vars.mk
@@ -0,0 +1,57 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of Intel Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+MACHINE_CFLAGS += -march=armv8-a
diff --git a/mk/rte.cpuflags.mk b/mk/rte.cpuflags.mk
index f595cd0..7e7281c 100644
--- a/mk/rte.cpuflags.mk
+++ b/mk/rte.cpuflags.mk
@@ -106,6 +106,15 @@ ifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),)
 CPUFLAGS += VSX
 endif
 
+# ARMv8 CPU flags
+ifneq ($(filter $(AUTO_CPUFLAGS),__aarch64__),)
+CPUFLAGS += AARCH64
+endif
+
+ifneq ($(filter $(AUTO_CPUFLAGS),__aarch32__),)
+CPUFLAGS += AARCH32
+endif
+
 MACHINE_CFLAGS += $(addprefix -DRTE_MACHINE_CPUFLAG_,$(CPUFLAGS))
 
 # To strip whitespace
-- 
2.1.4

[dpdk-dev] [PATCH 11/11] app: add armv8 cpuflags check to test_cpuflags application

[David Hunt]

From: Benjamin Boren <Ben.Boren@intel.com>

Signed-off-by: Benjamin Boren <Ben.Boren@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
 app/test/test_cpuflags.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 5b92061..a498511 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -115,6 +115,23 @@ test_cpuflags(void)
 	CHECK_FOR_FLAG(RTE_CPUFLAG_ICACHE_SNOOP);
 #endif
 
+#ifdef RTE_ARCH_ARM64
+	printf("Checking for Floating Point:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_FP);
+
+	printf("Checking for Advanced SIMD (Neon):\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_ASIMD);
+
+	printf("Checking for Event Stream:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_EVTSTRM);
+
+	printf("Checking for ARM32 mode:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_AARCH32);
+
+	printf("Checking for ARM64 mode:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_AARCH64);
+#endif
+
 #if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)
 	printf("Check for SSE:\t\t");
 	CHECK_FOR_FLAG(RTE_CPUFLAG_SSE);
-- 
2.1.4

Re: [dpdk-dev] [PATCH 00/11] add armv8 architecture support

[Jan Viktorin]

Hello David,

thanks for this series. I'am sending few comments to the code as well.
Soon, I will have an ARMv8 board available so I will be able to test it.

Probably, we can just reinclude some headers from arm/ directory for
ARMv8 as they are not different.

Jan

On Fri, 23 Oct 2015 15:17:02 +0100
David Hunt <david.hunt@intel.com> wrote:

> This patch provides support for the ARMv8 architecture. We hope that this will
> encourage the ARM community to contribute PMDs for their SoCs to DPDK.
> 
> For now, we've added Intel engineers to the MAINTAINERS file. We would like to
> encourage the ARM community to take over maintenance of this area in future,
> and to further improve it.
> 
> ACL and LPM libraries have been disabled in the config due to their reliance
> on SSE. 
> 
> This patch was tested on an Applied Micro X-Gene Mustang board (pcap only)
> 
> This patch was also tested with an Intel 82599 NIC on a Gigabyte MP30-AR0
> passing traffic between the two NIC ports using testpmd.
> 
> Notes on DPDK configuration:
> 
>   Did not use igb_uio or kni so the following optionse were disabled in 
>   config/common_linuxapp
> 
>   CONFIG_RTE_EAL_IGB_UIO=n
>   CONFIG_RTE_LIBRTE_KNI=n
>   CONFIG_RTE_KNI_KMOD=n
> 
>   make config T=arm64-native-linuxapp-gcc
>   make install T=arm64-native-linuxapp-gcc
>   
> Notes on arm64 kernel configuration:
> 
>   Using Ubuntu 14.04 LTS with a 4.3.0-rc6 kernel (with modified PCI drivers),
>   and uio_pci_generic.
>   ARM64 kernels do not seem to have functional resource mapping of PCI memory
>   (PCI_MMAP), so the pci driver needs to be patched to enable this. The
>   symptom of this is when /sys/bus/pci/devices/0000:0X:00.Y directory is
>   missing the resource0...N files for mmapping the device memory. Earlier
>   kernels (3.13.x) had these files present, but mmap'ping resulted in a
>   "Bus Error" when the NIC memory was accessed.
>   However, during limited testing with a modified 4.3.0-rc6 kernel, we were
>   able to mmap the NIC memory, and pass traffic between the two ports on a
>   82599 NIC connected via fibre cable. 
>   We have no plans to upstream a kernel patch for this and hope that
>   someone more familiar with the arm architecture can create a proper patch
>   and enable this functionality.
> 
> Benjamin Boren (11):
>   lib: add armv8 rte_atomic.h
>   lib: add armv8 rte_byteorder.h
>   lib: add armv8 rte_cpuflags.h
>   lib: add armv8 rte_cycles.h
>   lib: add armv8 rte_memcpy.h
>   lib: add armv8 rte_prefetch.h
>   lib: add armv8 rte_rwlock.h
>   lib: add armv8 rte_spinlock.h
>   lib: add armv8 rte_vect.h
>   mk: add makefile and config changes for armv8 architecture
>   app: add armv8 cpuflags check to test_cpuflags application
> 
>  MAINTAINERS                                        |   6 +
>  app/test/test_cpuflags.c                           |  17 ++
>  config/defconfig_arm64-native-linuxapp-gcc         |  55 +++++
>  .../common/include/arch/arm64/rte_atomic.h         | 269 +++++++++++++++++++++
>  .../common/include/arch/arm64/rte_byteorder.h      | 157 ++++++++++++
>  .../common/include/arch/arm64/rte_cpuflags.h       | 137 +++++++++++
>  .../common/include/arch/arm64/rte_cycles.h         |  77 ++++++
>  .../common/include/arch/arm64/rte_memcpy.h         | 266 ++++++++++++++++++++
>  .../common/include/arch/arm64/rte_prefetch.h       |  61 +++++
>  .../common/include/arch/arm64/rte_rwlock.h         |  70 ++++++
>  .../common/include/arch/arm64/rte_spinlock.h       | 114 +++++++++
>  .../common/include/arch/arm64/rte_vect.h           | 102 ++++++++
>  mk/arch/arm64/rte.vars.mk                          |  58 +++++
>  mk/machine/armv8-a/rte.vars.mk                     |  57 +++++
>  mk/rte.cpuflags.mk                                 |   9 +
>  15 files changed, 1455 insertions(+)
>  create mode 100644 config/defconfig_arm64-native-linuxapp-gcc
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_atomic.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_byteorder.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_cpuflags.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_cycles.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_memcpy.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_prefetch.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_rwlock.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_spinlock.h
>  create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_vect.h
>  create mode 100644 mk/arch/arm64/rte.vars.mk
>  create mode 100644 mk/machine/armv8-a/rte.vars.mk
> 



-- 
   Jan Viktorin                  E-mail: Viktorin@RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic

Re: [dpdk-dev] [PATCH 10/11] mk: add makefile and config changes for armv8 architecture

[Jan Viktorin]

On Fri, 23 Oct 2015 15:17:12 +0100
David Hunt <david.hunt@intel.com> wrote:

>  
> +# ARMv8 CPU flags
> +ifneq ($(filter $(AUTO_CPUFLAGS),__aarch64__),)
> +CPUFLAGS += AARCH64
> +endif
> +
> +ifneq ($(filter $(AUTO_CPUFLAGS),__aarch32__),)
> +CPUFLAGS += AARCH32
> +endif
> +

I think, this should go with the ARMv7 series.

Jan

-- 
   Jan Viktorin                  E-mail: Viktorin@RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic

Re: [dpdk-dev] [PATCH 10/11] mk: add makefile and config changes for armv8 architecture

[Jan Viktorin]

On Fri, 23 Oct 2015 15:17:12 +0100
David Hunt <david.hunt@intel.com> wrote:

> +#     in machine .mk)
> +#   - define CPU_CFLAGS variable (overridden by cmdline or previous
> +#     define in machine .mk)
> +#   - define CPU_LDFLAGS variable (overridden by cmdline or previous
> +#     define in machine .mk)
> +#   - define CPU_ASFLAGS variable (overridden by cmdline or previous
> +#     define in machine .mk)
> +#   - may override any previously defined variable
> +#
> +# examples for CONFIG_RTE_ARCH: i686, x86_64, x86_64_32
> +#
> +
> +ARCH  ?= arm64
> +# common arch dir in eal headers
> +ARCH_DIR := arm64
> +CROSS ?=
> +
> +CPU_CFLAGS  ?= -flax-vector-conversions

What is the purpose of this flag?

from man gcc:

-flax-vector-conversions
  Allow implicit conversions between vectors with differing numbers of
  elements and/or incompatible element types. 
  This option should not be used for new code.
  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Jan

> +CPU_LDFLAGS ?=
> +CPU_ASFLAGS ?=
> +
> +export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS


-- 
   Jan Viktorin                  E-mail: Viktorin@RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic

Re: [dpdk-dev] [PATCH 05/11] lib: add armv8 rte_memcpy.h

[Jan Viktorin]

On Fri, 23 Oct 2015 15:17:07 +0100
David Hunt <david.hunt@intel.com> wrote:

> +		     "LDP q0, q1, [%0 , #192]\n\t"
> +		     "STP q0, q1, [%1 , #192]\n\t"
> +		     "LDP q0, q1, [%0 , #224]\n\t"
> +		     "STP q0, q1, [%1 , #224]\n\t"
> +		     : : "r" (src), "r" (dst) :
> +	);
> +}
> +/*
> +static inline void
> +	rte_mov16(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 16); }
> +static inline void
> +	rte_mov32(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 32); }
> +static inline void
> +	rte_mov64(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 64); }
> +static inline void
> +	rte_mov128(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 128); }
> +static inline void
> +	rte_mov256(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 256); }
> +static inline void
> +	rte_mov48(uint8_t *dst, const uint8_t *src) { memcpy(dst, src, 48); }
> +*/

I think, as this is commented out, it should be omitted from the patch.

Jan

> +#define rte_memcpy(dst, src, n)              \
> +	({ (__builtin_constant_p(n)) ?       \
> +	memcpy((dst), (src), (n)) :          \
> +	rte_memcpy_func((dst), (src), (n)); })
> +
> +


-- 
   Jan Viktorin                  E-mail: Viktorin@RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic

Re: [dpdk-dev] [PATCH 03/11] lib: add armv8 rte_cpuflags.h

[Jan Viktorin]

On Fri, 23 Oct 2015 15:17:05 +0100
David Hunt <david.hunt@intel.com> wrote:

> +#include "generic/rte_cpuflags.h"
> +
> +/* Symbolic values for the entries in the auxiliary table */
> +#define AT_HWCAP  16
> +#define AT_HWCAP2 26
> +#define AT_PLATFORM 15
> +
> +/* software based registers */
> +enum cpu_register_t {
> +	REG_HWCAP = 0,
> +	AARCH_MODE,
> +};
> +
> +/**
> + * Enumeration of all CPU features supported
> + */
> +enum rte_cpu_flag_t {
> +	RTE_CPUFLAG_FP = 0,
> +	RTE_CPUFLAG_ASIMD,
> +	RTE_CPUFLAG_EVTSTRM,
> +	RTE_CPUFLAG_AARCH64,
> +	RTE_CPUFLAG_AARCH32,

We detect ARCH32/64 on both ARMv7 and ARMv8. This is strange.

> +	/* The last item */
> +	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
> +};
> +
> +static const struct feature_entry cpu_feature_table[] = {
> +	FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP,  0)
> +	FEAT_DEF(ASIMD, 0x00000001, 0, REG_HWCAP,  1)
> +	FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP,  2)
> +	FEAT_DEF(AARCH64, 0x00000001, 0, AARCH_MODE, 3)
> +	FEAT_DEF(AARCH32, 0x00000001, 0, AARCH_MODE, 4)
> +};
> +

Is it possible to extend it in the same way as it is prepared for ARMv7
[1, 2]?

[1] https://github.com/RehiveTech/dpdk/commit/bd5f0480b60282cfcd0ef43ddf8896bef8a23bbb
[2] https://github.com/RehiveTech/dpdk/commit/e293c11770aefc1f58f0c0cca5efee02b21910ba

Perhaps, can we merge this with ARMv7 one (in a single file)? Do the
features overlap in a sane way?

Jan


-- 
   Jan Viktorin                  E-mail: Viktorin@RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic

Re: [dpdk-dev] [PATCH 09/11] lib: add armv8 rte_vect.h

[Jan Viktorin]

On Fri, 23 Oct 2015 15:17:11 +0100
David Hunt <david.hunt@intel.com> wrote:

> +
> +typedef float32x4_t __m128;
> +
> +typedef int32x4_t __m128i;
> +
> +typedef __m128i xmm_t;
> +
> +#define XMM_SIZE        (sizeof(xmm_t))
> +#define XMM_MASK        (XMM_SIZE - 1)
> +
> +typedef union rte_xmm {
> +	xmm_t    x;
> +	uint8_t  u8[XMM_SIZE / sizeof(uint8_t)];
> +	uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
> +	uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
> +	uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
> +	double   pd[XMM_SIZE / sizeof(double)];
> +} rte_xmm_t __aligned(16);
> +
> +#define _mm_srli_epi32(a, imm) { (__m128i)vshrq_n_u32((uint32x4_t)a, imm) }
> +
> +#define _mm_srli_si128(a, imm) { (__m128i)vextq_s8((int8x16_t)a, \
> +					vdupq_n_s8(0), (imm)) }
> +
> +static inline  __m128i
> +_mm_set_epi32(int i3, int i2, int i1, int i0);
> +static inline int
> +_mm_cvtsi128_si64(__m128i a);
> +
> +static inline  __m128i
> +_mm_set_epi32(int i3, int i2, int i1, int i0)
> +{
> +	int32_t __aligned(16) data[4] = { i0, i1, i2, i3 };
> +	return vld1q_s32(data);
> +}
> +
> +static inline int
> +_mm_cvtsi128_si64(__m128i a)
> +{
> +	return vgetq_lane_s64(a, 0);
> +}
> +
> +static inline __m128i
> +_mm_and_si128(__m128i a, __m128i b)
> +{
> +	return (__m128i)vandq_s32(a, b);
> +}
> +

What is the purpose of those wrappers? I mean, does it help to compile
some SSE-dependent libraries in DPDK for NEON?

Jan

-- 
   Jan Viktorin                  E-mail: Viktorin@RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic

Re: [dpdk-dev] [PATCH 10/11] mk: add makefile and config changes for armv8 architecture

[Jan Viktorin]

On Mon, 26 Oct 2015 17:22:01 +0100
Jan Viktorin <viktorin@rehivetech.com> wrote:

> On Fri, 23 Oct 2015 15:17:12 +0100
> David Hunt <david.hunt@intel.com> wrote:
> 
> >  
> > +# ARMv8 CPU flags
> > +ifneq ($(filter $(AUTO_CPUFLAGS),__aarch64__),)

I do not believe that this works. The function filter accepts
arguments swapped. I.e. first a pattern and then the list of
filtered data. I suppose, __aarch64__ is the pattern...

Jan

> > +CPUFLAGS += AARCH64
> > +endif
> > +
> > +ifneq ($(filter $(AUTO_CPUFLAGS),__aarch32__),)
> > +CPUFLAGS += AARCH32
> > +endif
> > +  
> 
> I think, this should go with the ARMv7 series.

> 
> Jan
> 



-- 
   Jan Viktorin                  E-mail: Viktorin@RehiveTech.com
   System Architect              Web:    www.RehiveTech.com
   RehiveTech
   Brno, Czech Republic