From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from wes1-so1.wedos.net (wes1-so1.wedos.net [46.28.106.15]) by dpdk.org (Postfix) with ESMTP id 3728A8D9E for ; Tue, 27 Oct 2015 20:16:17 +0100 (CET) Received: from pcviktorin.fit.vutbr.cz (pcviktorin.fit.vutbr.cz [147.229.13.147]) by wes1-so1.wedos.net (Postfix) with ESMTPSA id 3nljSJ6Hfxz3qn; Tue, 27 Oct 2015 20:16:16 +0100 (CET) From: Jan Viktorin To: dev@dpdk.org, David Hunt , David Marchand , "Ananyev, Konstantin" Date: Tue, 27 Oct 2015 20:13:49 +0100 Message-Id: <1445973229-22058-18-git-send-email-viktorin@rehivetech.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1445973229-22058-1-git-send-email-viktorin@rehivetech.com> References: <1445877458-31052-1-git-send-email-viktorin@rehivetech.com> <1445973229-22058-1-git-send-email-viktorin@rehivetech.com> Subject: [dpdk-dev] [PATCH v3 17/17] acl: handle when SSE 4.1 is unsupported X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Oct 2015 19:16:17 -0000 The main goal of this check is to avoid passing the -msse4.1 option to the GCC that does not support it (like arm toolchains). The ACL now builds for ARM. Signed-off-by: Jan Viktorin --- v2 -> v3: handle missing SSE as suggested by K. Ananyev --- lib/librte_acl/Makefile | 7 ++++++- lib/librte_acl/rte_acl.c | 19 +++++++++++++++++-- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile index 7a1cf8a..ed95f03 100644 --- a/lib/librte_acl/Makefile +++ b/lib/librte_acl/Makefile @@ -48,9 +48,14 @@ SRCS-$(CONFIG_RTE_LIBRTE_ACL) += rte_acl.c SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_bld.c SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_gen.c SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_scalar.c -SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c +CC_SSE4_1_SUPPORT := $(shell $(CC) -msse4.1 -dM -E - < /dev/null >/dev/null 2>&1 && echo 1) + +ifeq ($(CC_SSE4_1_SUPPORT),1) +SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c +CFLAGS_rte_acl.o += -DCC_SSE41_SUPPORT CFLAGS_acl_run_sse.o += -msse4.1 +endif # # If the compiler supports AVX2 instructions, diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c index d60219f..e7822de 100644 --- a/lib/librte_acl/rte_acl.c +++ b/lib/librte_acl/rte_acl.c @@ -42,6 +42,20 @@ static struct rte_tailq_elem rte_acl_tailq = { EAL_REGISTER_TAILQ(rte_acl_tailq) /* + * If the compiler doesn't support SSE instructions, + * then the dummy one would be used instead for SSE classify method. + */ +int __attribute__ ((weak)) +rte_acl_classify_sse(__rte_unused const struct rte_acl_ctx *ctx, + __rte_unused const uint8_t **data, + __rte_unused uint32_t *results, + __rte_unused uint32_t num, + __rte_unused uint32_t categories) +{ + return -ENOTSUP; +} + +/* * If the compiler doesn't support AVX2 instructions, * then the dummy one would be used instead for AVX2 classify method. */ @@ -97,10 +111,11 @@ rte_acl_init(void) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) alg = RTE_ACL_CLASSIFY_AVX2; else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1)) -#else + alg = RTE_ACL_CLASSIFY_SSE; +#elif defined (CC_SSE41_SUPPORT) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1)) -#endif alg = RTE_ACL_CLASSIFY_SSE; +#endif rte_acl_set_default_classify(alg); } -- 2.6.1