From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 55BC78E98 for ; Fri, 30 Oct 2015 09:03:43 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 30 Oct 2015 01:03:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,217,1444719600"; d="scan'208";a="590868485" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 30 Oct 2015 01:03:39 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t9U83bU0027694; Fri, 30 Oct 2015 16:03:37 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t9U83Y7Y002001; Fri, 30 Oct 2015 16:03:36 +0800 Received: (from jingche2@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9U83X9D001997; Fri, 30 Oct 2015 16:03:33 +0800 From: "Chen Jing D(Mark)" To: dev@dpdk.org Date: Fri, 30 Oct 2015 16:03:04 +0800 Message-Id: <1446192187-1890-12-git-send-email-jing.d.chen@intel.com> X-Mailer: git-send-email 1.7.12.2 In-Reply-To: <1446192187-1890-1-git-send-email-jing.d.chen@intel.com> References: <1446110173-13330-2-git-send-email-jing.d.chen@intel.com> <1446192187-1890-1-git-send-email-jing.d.chen@intel.com> Subject: [dpdk-dev] [PATCH v5 11/14] fm10k: introduce 2 funcs to reset TX queue and mbuf release X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Oct 2015 08:03:44 -0000 From: "Chen Jing D(Mark)" Add 2 funcs to reset TX queue and mbuf release when Vector TX applied. Signed-off-by: Chen Jing D(Mark) --- drivers/net/fm10k/fm10k_rxtx_vec.c | 68 ++++++++++++++++++++++++++++++++++++ 1 files changed, 68 insertions(+), 0 deletions(-) diff --git a/drivers/net/fm10k/fm10k_rxtx_vec.c b/drivers/net/fm10k/fm10k_rxtx_vec.c index 4515b26..06beca9 100644 --- a/drivers/net/fm10k/fm10k_rxtx_vec.c +++ b/drivers/net/fm10k/fm10k_rxtx_vec.c @@ -44,6 +44,11 @@ #pragma GCC diagnostic ignored "-Wcast-qual" #endif +static void +fm10k_tx_queue_release_mbufs_vec(struct fm10k_tx_queue *txq); +static void +fm10k_reset_tx_queue(struct fm10k_tx_queue *txq); + /* Handling the offload flags (olflags) field takes computation * time when receiving packets. Therefore we provide a flag to disable * the processing of the olflags field when they are not needed. This @@ -628,6 +633,17 @@ fm10k_recv_scattered_pkts_vec(void *rx_queue, &split_flags[i]); } +static const struct fm10k_txq_ops vec_txq_ops = { + .release_mbufs = fm10k_tx_queue_release_mbufs_vec, + .reset = fm10k_reset_tx_queue, +}; + +void __attribute__((cold)) +fm10k_txq_vec_setup(struct fm10k_tx_queue *txq) +{ + txq->ops = &vec_txq_ops; +} + static inline void vtx1(volatile struct fm10k_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags) @@ -777,3 +793,55 @@ fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, return nb_pkts; } + +static void __attribute__((cold)) +fm10k_tx_queue_release_mbufs_vec(struct fm10k_tx_queue *txq) +{ + unsigned i; + const uint16_t max_desc = (uint16_t)(txq->nb_desc - 1); + + if (txq->sw_ring == NULL || txq->nb_free == max_desc) + return; + + /* release the used mbufs in sw_ring */ + for (i = txq->next_dd - (txq->rs_thresh - 1); + i != txq->next_free; + i = (i + 1) & max_desc) + rte_pktmbuf_free_seg(txq->sw_ring[i]); + + txq->nb_free = max_desc; + + /* reset tx_entry */ + for (i = 0; i < txq->nb_desc; i++) + txq->sw_ring[i] = NULL; + + rte_free(txq->sw_ring); + txq->sw_ring = NULL; +} + +static void __attribute__((cold)) +fm10k_reset_tx_queue(struct fm10k_tx_queue *txq) +{ + static const struct fm10k_tx_desc zeroed_desc = {0}; + struct rte_mbuf **txe = txq->sw_ring; + uint16_t i; + + /* Zero out HW ring memory */ + for (i = 0; i < txq->nb_desc; i++) + txq->hw_ring[i] = zeroed_desc; + + /* Initialize SW ring entries */ + for (i = 0; i < txq->nb_desc; i++) + txe[i] = NULL; + + txq->next_dd = (uint16_t)(txq->rs_thresh - 1); + txq->next_rs = (uint16_t)(txq->rs_thresh - 1); + + txq->next_free = 0; + txq->nb_used = 0; + /* Always allow 1 descriptor to be un-allocated to avoid + * a H/W race condition + */ + txq->nb_free = (uint16_t)(txq->nb_desc - 1); + FM10K_PCI_REG_WRITE(txq->tail_ptr, 0); +} -- 1.7.7.6