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BLUPR0701MB1969; 5:1OlHdG2X1O4maNz0dhrXCy8g9JlVN01Cy0a18fHtwdYl6JVBDellPowd9Nl6SWlPTg96EN5KpkHsf3UxXcnNHngRD8xIZRowIJbH5EHBm//e0FaDpJcrXOSzs5ij8Bp/QXHaN1/MzHTgnb/hMO33jA==; 24:m9Mjrr6SYCo6zQWTcBDnUKp55hd00HBoC3tRgiS/lgrQOgkgJnMveXzZkEVViRDAXVIKUyJgXFInpcQ9TbkNs2c0QP/46Se3d5kobNNXks8=; 20:845ed37IU58tLZP957tYs9ZTsscb8auEv38USIMNo6UCTLfAcyXmJXeBWDqzMSy7yZJ2COWl8FLfRmmSWFyvrg== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2015 09:41:29.4599 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1969 X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1587; 2:Ya2kB7KSQApyKW1ni1YdKbcVCrAZyFdWhZWY8m2cg21GdqOLqWp4OHVY0oHzOjo09CXUqQvuHXBepOws7J8jEW2fNYcWKR3yoX8uKi6QxIxfQx1RmUgjnnl+mIzJe9coEjGgnriAR76YDyouvoWvZ66rJlaZw9lfhd6fBu9ErhE=; 23:gih22SM2jVxn4gxNJfLHjI3qHXwXSWgWeb3c2iv67j5Y8lDoe7W8jGdVSsSp1dqyYGY3WYop7B641lwh/crgHSvHSzdiatmbDKMmQ6mNBkwVhiiJln+yLvVKc+7S+BmJE+7zsKXEys0+TtopGsms0C+F1Ykk2AJJZjJgVTcCIIv/9iTaONQvm7A9OKtWeqI2 X-OriginatorOrg: caviumnetworks.com Subject: [dpdk-dev] [PATCH v3 04/14] eal: arm64: add armv8-a version of rte_cycles_64.h X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Nov 2015 09:41:33 -0000 cntcvt_el0 ticks are not based on cpu clk unlike rdtsc in x86. Its a fixed clock running based at constant speed. Though its a armv8-a implementer choice, typically it runs at 50 or 100 MHz Signed-off-by: Jerin Jacob --- .../common/include/arch/arm/rte_cycles.h | 4 ++ .../common/include/arch/arm/rte_cycles_64.h | 71 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles_64.h diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles.h b/lib/librte_eal/common/include/arch/arm/rte_cycles.h index b2372fa..a8009a0 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cycles.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles.h @@ -33,6 +33,10 @@ #ifndef _RTE_CYCLES_ARM_H_ #define _RTE_CYCLES_ARM_H_ +#ifdef RTE_ARCH_64 +#include +#else #include +#endif #endif /* _RTE_CYCLES_ARM_H_ */ diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h new file mode 100644 index 0000000..14f2612 --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h @@ -0,0 +1,71 @@ +/* + * BSD LICENSE + * + * Copyright (C) Cavium networks Ltd. 2015. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Cavium networks nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _RTE_CYCLES_ARM64_H_ +#define _RTE_CYCLES_ARM64_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_cycles.h" + +/** + * Read the time base register. + * + * @return + * The time base for this lcore. + */ +static inline uint64_t +rte_rdtsc(void) +{ + uint64_t tsc; + + asm volatile("mrs %0, cntvct_el0" : "=r" (tsc)); + return tsc; +} + +static inline uint64_t +rte_rdtsc_precise(void) +{ + rte_mb(); + return rte_rdtsc(); +} + +static inline uint64_t +rte_get_tsc_cycles(void) { return rte_rdtsc(); } + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_CYCLES_ARM64_H_ */ -- 1.9.3