From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 26F9695D7 for ; Mon, 16 Nov 2015 08:08:39 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 15 Nov 2015 23:08:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,301,1444719600"; d="scan'208";a="821018393" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga001.jf.intel.com with ESMTP; 15 Nov 2015 23:08:37 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id tAG78ZO0026999; Mon, 16 Nov 2015 15:08:35 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id tAG78Xg5010598; Mon, 16 Nov 2015 15:08:35 +0800 Received: (from wujingji@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id tAG78XYb010594; Mon, 16 Nov 2015 15:08:33 +0800 From: Jingjing Wu To: dev@dpdk.org Date: Mon, 16 Nov 2015 15:08:30 +0800 Message-Id: <1447657710-10563-1-git-send-email-jingjing.wu@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dpdk-dev] [PATCH] i40e: fix the write flush in vf driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Nov 2015 07:08:39 -0000 For i40e vf driver, should use I40EVF_WRITE_FLUSH to flush configuration but not I40E_WRITE_FLUSH. This patch fixed this issue. Fixes: be6c228d4da3 (i40evf: support Rx interrupt) Reported-by: Qian Xu Signed-off-by: Jingjing Wu --- drivers/net/i40e/i40e_ethdev_vf.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index 7ce8687..ea96f85 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -1700,7 +1700,7 @@ i40evf_enable_queues_intr(struct rte_eth_dev *dev) I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL01_INTENA_MASK | I40E_VFINT_DYN_CTL01_CLEARPBA_MASK); - I40E_WRITE_FLUSH(hw); + I40EVF_WRITE_FLUSH(hw); return; } @@ -1716,7 +1716,7 @@ i40evf_enable_queues_intr(struct rte_eth_dev *dev) I40E_VFINT_DYN_CTL01_INTENA_MASK | I40E_VFINT_DYN_CTL01_CLEARPBA_MASK); - I40E_WRITE_FLUSH(hw); + I40EVF_WRITE_FLUSH(hw); } static inline void @@ -1728,7 +1728,7 @@ i40evf_disable_queues_intr(struct rte_eth_dev *dev) if (!rte_intr_allow_others(intr_handle)) { I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0); - I40E_WRITE_FLUSH(hw); + I40EVF_WRITE_FLUSH(hw); return; } @@ -1740,7 +1740,7 @@ i40evf_disable_queues_intr(struct rte_eth_dev *dev) else I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0); - I40E_WRITE_FLUSH(hw); + I40EVF_WRITE_FLUSH(hw); } static int @@ -1770,7 +1770,7 @@ i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) (interval << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)); - I40E_WRITE_FLUSH(hw); + I40EVF_WRITE_FLUSH(hw); rte_intr_enable(&dev->pci_dev->intr_handle); @@ -1793,7 +1793,7 @@ i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) I40E_RX_VEC_START), 0); - I40E_WRITE_FLUSH(hw); + I40EVF_WRITE_FLUSH(hw); return 0; } -- 2.4.0