From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f177.google.com (mail-pf0-f177.google.com [209.85.192.177]) by dpdk.org (Postfix) with ESMTP id 978B691D6 for ; Fri, 4 Dec 2015 18:35:38 +0100 (CET) Received: by pfu207 with SMTP id 207so29202072pfu.2 for ; Fri, 04 Dec 2015 09:35:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mvista-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sErEkhwp3EK3xm/tWCQ6yo2fmYlxhz3ZxcqH90eBKEc=; b=0AmHxZTn7EVyJ6FDwnwKJUi+CdX5P2Jgm0a49+j/IV6wVPFVViOzuGgZKwDV2ccBCi 0DaG3fq9YA0ulk5jf7UveC4u9KKCsVYVOPYRmNjruILkzSm+/ksvyOaj4IbhhShW+OwS NP6A8INpxvOh5bVWPNxoBgUtVkiFYCXxdg7duwYIwGFZ5Iw4O4VfjfoNs0iQUTJ7/5A9 Wh5HyrKAmuXzvyyeebzrSOFa84Qr9ZP0Jt1K66UFd//1+kQK60HbUt0XoYG7AnnaOfHb 7pLl0BvPDrCfP496eBjEzpx0lihTPaM+A5zVi4rVI/wtPNZAEqgK+t94VRqeuKiiw5bK FjzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sErEkhwp3EK3xm/tWCQ6yo2fmYlxhz3ZxcqH90eBKEc=; b=gsEzgoEe4iqTEbvXTnz/CmOY81VAQhmSnU0dbaUP8m6z+6r3G3HMUJXH6f4z2pWBv4 AdmATKKycbLnkCmUt54TcS1O7HpFDs4v4L0o1Uj4U2lVDQPghc3pINHuO6IL7W5EN6MD xs8JGPRVSDdqFPanrekeZkX/IjMTgklispR4xqw2Mdv90tUuYKdu0XCNnVflswmqHJSg VuuEbfI6U/tayNdSkYIUmpEaSo4A8hmrnKECa4Wg6Dz0yMl2df+rSyeO9BZrTL3b2uWv IzZ5sEFg/4hHovSPr/k9aD/2yT7Y7MiIKLQQjj2PggbxAkVsont10Cnoa3mD9C5yzYsX xF1w== X-Gm-Message-State: ALoCoQnHSMd7zFoRSWE5crYLcrKoRCX0E7J1DTeRSoqRoXHOEVg+Luz2UA4Zq59FlcOk3FfD9Zlq X-Received: by 10.98.7.129 with SMTP id 1mr23245802pfh.70.1449250538039; Fri, 04 Dec 2015 09:35:38 -0800 (PST) Received: from rakeshk-OptiPlex-9020.mvista.com ([111.93.218.67]) by smtp.gmail.com with ESMTPSA id 134sm18365609pfa.30.2015.12.04.09.35.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Dec 2015 09:35:37 -0800 (PST) From: Santosh Shukla To: dev@dpdk.org Date: Fri, 4 Dec 2015 23:05:16 +0530 Message-Id: <1449250519-28372-4-git-send-email-sshukla@mvista.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449250519-28372-1-git-send-email-sshukla@mvista.com> References: <1449250519-28372-1-git-send-email-sshukla@mvista.com> Subject: [dpdk-dev] [PATCH 3/6] virtio: armv7/v8: Introdice api to emulate x86-style of PCI/ISA ioport access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Dec 2015 17:35:39 -0000 Currently virtio_pci address space accessed in x86-style of ioport apis example: {in,out}[bwl] and {in_p,out_p}[bwl]. Architecture like arm does IO access in memory-mapped way, as because they donot support direct IO instructions. So introducing a helper api for arm/arm64 who'll provide ioport access in x86-style. Also adding support for arm/arm64 in virtio_pci.h header file. Signed-off-by: Santosh Shukla --- drivers/net/virtio/virtio_pci.h | 15 ++ .../common/include/arch/arm/rte_isa_io.h | 212 ++++++++++++++++++++ 2 files changed, 227 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/arm/rte_isa_io.h diff --git a/drivers/net/virtio/virtio_pci.h b/drivers/net/virtio/virtio_pci.h index 47f722a..72f5f6a 100644 --- a/drivers/net/virtio/virtio_pci.h +++ b/drivers/net/virtio/virtio_pci.h @@ -40,9 +40,15 @@ #include #include #else + +#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64) +#include +#else /* !ARM64 , !ARM */ #include #endif +#endif + #include struct virtqueue; @@ -165,7 +171,11 @@ struct virtqueue; struct virtio_hw { struct virtqueue *cvq; +#if defined(RTE_ARCH_ARM64) + uint64_t io_base; +#else /* !ARM64 */ uint32_t io_base; +#endif uint32_t guest_features; uint32_t max_tx_queues; uint32_t max_rx_queues; @@ -226,8 +236,13 @@ outl_p(unsigned int data, unsigned int port) } #endif +#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64) +#define VIRTIO_PCI_REG_ADDR(hw, reg) \ + (unsigned long)((hw)->io_base + (reg)) +#else /* !ARM , !ARM64 */ #define VIRTIO_PCI_REG_ADDR(hw, reg) \ (unsigned short)((hw)->io_base + (reg)) +#endif #define VIRTIO_READ_REG_1(hw, reg) \ inb((VIRTIO_PCI_REG_ADDR((hw), (reg)))) diff --git a/lib/librte_eal/common/include/arch/arm/rte_isa_io.h b/lib/librte_eal/common/include/arch/arm/rte_isa_io.h new file mode 100644 index 0000000..14f806e --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm/rte_isa_io.h @@ -0,0 +1,212 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2015 Cavium Networks. All rights reserved. + * All rights reserved. + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * All rights reserved. + * + * ARM helper api to emulate x86-style of {in , out}[bwl] api used for + * accessing PCI/ISA IO address space. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * @File + * Currently virtio pci does IO access in x86-way i.e. IO_RESOURCE_IO way, It + * access the pci address space by port_number. The ARM doesn't have + * instructions for direct IO access. In ARM: IO's are memory mapped. + * + * Below helper api allow virtio_pci driver to access IO's for arm/arm64 arch + * in x86-style of apis example: {in , out}[bwl] and {in_p , out_p}[bwl]. + */ +#ifndef _RTE_ISA_IO_H_ +#define _RTE_ISA_IO_H_ + +#include +#include + +#if defined(RTE_ARCH_ARM) +/* + * Generic IO read/write api for arm: Refer TRM + */ +static inline void raw_writeb(uint8_t val, uint32_t addr) +{ + asm volatile("strb %0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writew(uint16_t val, uint32_t addr) +{ + asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writel(uint32_t val, uint32_t addr) +{ + asm volatile("str %0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline uint8_t raw_readb(uint32_t addr) +{ + uint8_t val; + asm volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint16_t raw_readw(uint32_t addr) +{ + uint16_t val; + asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint32_t raw_readl(uint32_t addr) +{ + uint32_t val; + asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +#elif defined(RTE_ARCH_ARM64) + +/* + * Generic IO read/write api for arm64: Refer TRM + */ +static inline void raw_writeb(uint8_t val, uint64_t addr) +{ + asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writew(uint16_t val, uint64_t addr) +{ + asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writel(uint32_t val, uint64_t addr) +{ + asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline uint8_t raw_readb(uint64_t addr) +{ + uint8_t val; + asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint16_t raw_readw(uint64_t addr) +{ + uint16_t val; + asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint32_t raw_readl(uint64_t addr) +{ + uint32_t val; + asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} +#else /* !ARM64 && !ARM */ + +#define raw_writeb(val, addr) +#define raw_writew(val, addr) +#define raw_writel(val, addr) +#define raw_readb(addr) +#define raw_readw(addr) +#define raw_readl(addr) + +#endif /* ARM64 or ARM */ + +/* Emulate x86-style of ioport api implementation for arm/arm64. Included API + * - {in, out}{b, w, l}() + * - {in_p, out_p} {b, w, l} () + * + * */ + +static inline uint8_t inb(unsigned long addr) +{ + return raw_readb(addr); +} + +static inline uint16_t inw(unsigned long addr) +{ + return raw_readw(addr); +} + +static inline uint32_t inl(unsigned long addr) +{ + return raw_readl(addr); +} + +static inline void outb(uint8_t value, unsigned long addr) +{ + raw_writeb(value, addr); +} + +static inline void outw(uint16_t value, unsigned long addr) +{ + raw_writew(value, addr); +} + +static inline void outl(uint32_t value, unsigned long addr) +{ + raw_writel(value, addr); +} + +static inline uint8_t inb_p(unsigned long addr) +{ + return inb(addr); +} + +static inline uint16_t inw_p(unsigned long addr) +{ + return inw(addr); +} + +static inline uint32_t inl_p(unsigned long addr) +{ + return inl(addr); +} + +static inline void outb_p(uint8_t value, unsigned long addr) +{ + outb(value, addr); +} + +static inline void outw_p(uint16_t value, unsigned long addr) +{ + outw(value, addr); +} + +static inline void outl_p(uint32_t value, unsigned long addr) +{ + outl(value, addr); +} + +#endif /* _RTE_ISA_IO_H_ */ -- 1.7.9.5