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From: Santosh Shukla <sshukla@mvista.com>
To: dev@dpdk.org
Date: Fri, 4 Dec 2015 23:05:16 +0530
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Subject: [dpdk-dev] [PATCH 3/6] virtio: armv7/v8: Introdice api to emulate
x86-style of PCI/ISA ioport access
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Currently virtio_pci address space accessed in x86-style of ioport apis example:
{in,out}[bwl] and {in_p,out_p}[bwl]. Architecture like arm does IO access in
memory-mapped way, as because they donot support direct IO instructions. So
introducing a helper api for arm/arm64 who'll provide ioport access in
x86-style.
Also adding support for arm/arm64 in virtio_pci.h header file.
Signed-off-by: Santosh Shukla <sshukla@mvista.com>
---
drivers/net/virtio/virtio_pci.h | 15 ++
.../common/include/arch/arm/rte_isa_io.h | 212 ++++++++++++++++++++
2 files changed, 227 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_isa_io.h
diff --git a/drivers/net/virtio/virtio_pci.h b/drivers/net/virtio/virtio_pci.h
index 47f722a..72f5f6a 100644
--- a/drivers/net/virtio/virtio_pci.h
+++ b/drivers/net/virtio/virtio_pci.h
@@ -40,9 +40,15 @@
#include <sys/types.h>
#include <machine/cpufunc.h>
#else
+
+#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64)
+#include <rte_isa_io.h>
+#else /* !ARM64 , !ARM */
#include <sys/io.h>
#endif
+#endif
+
#include <rte_ethdev.h>
struct virtqueue;
@@ -165,7 +171,11 @@ struct virtqueue;
struct virtio_hw {
struct virtqueue *cvq;
+#if defined(RTE_ARCH_ARM64)
+ uint64_t io_base;
+#else /* !ARM64 */
uint32_t io_base;
+#endif
uint32_t guest_features;
uint32_t max_tx_queues;
uint32_t max_rx_queues;
@@ -226,8 +236,13 @@ outl_p(unsigned int data, unsigned int port)
}
#endif
+#if defined(RTE_ARCH_ARM) || defined(RTE_ARCH_ARM64)
+#define VIRTIO_PCI_REG_ADDR(hw, reg) \
+ (unsigned long)((hw)->io_base + (reg))
+#else /* !ARM , !ARM64 */
#define VIRTIO_PCI_REG_ADDR(hw, reg) \
(unsigned short)((hw)->io_base + (reg))
+#endif
#define VIRTIO_READ_REG_1(hw, reg) \
inb((VIRTIO_PCI_REG_ADDR((hw), (reg))))
diff --git a/lib/librte_eal/common/include/arch/arm/rte_isa_io.h b/lib/librte_eal/common/include/arch/arm/rte_isa_io.h
new file mode 100644
index 0000000..14f806e
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_isa_io.h
@@ -0,0 +1,212 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Cavium Networks. All rights reserved.
+ * All rights reserved.
+ *
+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * ARM helper api to emulate x86-style of {in , out}[bwl] api used for
+ * accessing PCI/ISA IO address space.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * @File
+ * Currently virtio pci does IO access in x86-way i.e. IO_RESOURCE_IO way, It
+ * access the pci address space by port_number. The ARM doesn't have
+ * instructions for direct IO access. In ARM: IO's are memory mapped.
+ *
+ * Below helper api allow virtio_pci driver to access IO's for arm/arm64 arch
+ * in x86-style of apis example: {in , out}[bwl] and {in_p , out_p}[bwl].
+ */
+#ifndef _RTE_ISA_IO_H_
+#define _RTE_ISA_IO_H_
+
+#include <stdint.h>
+#include <inttypes.h>
+
+#if defined(RTE_ARCH_ARM)
+/*
+ * Generic IO read/write api for arm: Refer TRM
+ */
+static inline void raw_writeb(uint8_t val, uint32_t addr)
+{
+ asm volatile("strb %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void raw_writew(uint16_t val, uint32_t addr)
+{
+ asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void raw_writel(uint32_t val, uint32_t addr)
+{
+ asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline uint8_t raw_readb(uint32_t addr)
+{
+ uint8_t val;
+ asm volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+static inline uint16_t raw_readw(uint32_t addr)
+{
+ uint16_t val;
+ asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+static inline uint32_t raw_readl(uint32_t addr)
+{
+ uint32_t val;
+ asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#elif defined(RTE_ARCH_ARM64)
+
+/*
+ * Generic IO read/write api for arm64: Refer TRM
+ */
+static inline void raw_writeb(uint8_t val, uint64_t addr)
+{
+ asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void raw_writew(uint16_t val, uint64_t addr)
+{
+ asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void raw_writel(uint32_t val, uint64_t addr)
+{
+ asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline uint8_t raw_readb(uint64_t addr)
+{
+ uint8_t val;
+ asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+static inline uint16_t raw_readw(uint64_t addr)
+{
+ uint16_t val;
+ asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+static inline uint32_t raw_readl(uint64_t addr)
+{
+ uint32_t val;
+ asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+#else /* !ARM64 && !ARM */
+
+#define raw_writeb(val, addr)
+#define raw_writew(val, addr)
+#define raw_writel(val, addr)
+#define raw_readb(addr)
+#define raw_readw(addr)
+#define raw_readl(addr)
+
+#endif /* ARM64 or ARM */
+
+/* Emulate x86-style of ioport api implementation for arm/arm64. Included API
+ * - {in, out}{b, w, l}()
+ * - {in_p, out_p} {b, w, l} ()
+ *
+ * */
+
+static inline uint8_t inb(unsigned long addr)
+{
+ return raw_readb(addr);
+}
+
+static inline uint16_t inw(unsigned long addr)
+{
+ return raw_readw(addr);
+}
+
+static inline uint32_t inl(unsigned long addr)
+{
+ return raw_readl(addr);
+}
+
+static inline void outb(uint8_t value, unsigned long addr)
+{
+ raw_writeb(value, addr);
+}
+
+static inline void outw(uint16_t value, unsigned long addr)
+{
+ raw_writew(value, addr);
+}
+
+static inline void outl(uint32_t value, unsigned long addr)
+{
+ raw_writel(value, addr);
+}
+
+static inline uint8_t inb_p(unsigned long addr)
+{
+ return inb(addr);
+}
+
+static inline uint16_t inw_p(unsigned long addr)
+{
+ return inw(addr);
+}
+
+static inline uint32_t inl_p(unsigned long addr)
+{
+ return inl(addr);
+}
+
+static inline void outb_p(uint8_t value, unsigned long addr)
+{
+ outb(value, addr);
+}
+
+static inline void outw_p(uint16_t value, unsigned long addr)
+{
+ outw(value, addr);
+}
+
+static inline void outl_p(uint32_t value, unsigned long addr)
+{
+ outl(value, addr);
+}
+
+#endif /* _RTE_ISA_IO_H_ */
--
1.7.9.5