From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id BB2E08D39 for ; Thu, 10 Dec 2015 11:44:30 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP; 10 Dec 2015 02:44:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,407,1444719600"; d="scan'208";a="615765012" Received: from shilc102.sh.intel.com ([10.239.39.44]) by FMSMGA003.fm.intel.com with ESMTP; 10 Dec 2015 02:44:30 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shilc102.sh.intel.com with ESMTP id tBAAiPw6010879; Thu, 10 Dec 2015 18:44:25 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id tBAAiN9l030714; Thu, 10 Dec 2015 18:44:25 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id tBAAiNiB030710; Thu, 10 Dec 2015 18:44:23 +0800 From: Helin Zhang To: dev@dpdk.org Date: Thu, 10 Dec 2015 18:44:22 +0800 Message-Id: <1449744262-30679-1-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dpdk-dev] [PATCH] i40e: fix issue of setting input set for (double) vlan X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Dec 2015 10:44:31 -0000 It corrects the input set values to be set for vlan or double vlan. Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director") Signed-off-by: Helin Zhang --- drivers/net/i40e/i40e_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 7e03a1f..22b240c 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -207,9 +207,9 @@ /* Source MAC address */ #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL /* VLAN tag in the outer L2 header */ -#define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000000800000ULL +#define I40E_REG_INSET_L2_OUTER_VLAN 0x0080000000000000ULL /* VLAN tag in the inner L2 header */ -#define I40E_REG_INSET_L2_INNER_VLAN 0x0000000001000000ULL +#define I40E_REG_INSET_L2_INNER_VLAN 0x0100000000000000ULL /* Source IPv4 address */ #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL /* Destination IPv4 address */ -- 1.9.3