From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id DDFD08D35 for ; Mon, 18 Jan 2016 11:08:38 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 18 Jan 2016 02:08:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,312,1449561600"; d="scan'208";a="729395986" Received: from unknown (HELO dpdk5.sh.intel.com) ([10.239.129.244]) by orsmga003.jf.intel.com with ESMTP; 18 Jan 2016 02:08:37 -0800 From: Zhihong Wang To: dev@dpdk.org Date: Sun, 17 Jan 2016 22:05:10 -0500 Message-Id: <1453086314-30158-2-git-send-email-zhihong.wang@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1453086314-30158-1-git-send-email-zhihong.wang@intel.com> References: <1452752002-107586-1-git-send-email-zhihong.wang@intel.com> <1453086314-30158-1-git-send-email-zhihong.wang@intel.com> Subject: [dpdk-dev] [PATCH v2 1/5] lib/librte_eal: Identify AVX512 CPU flag X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2016 10:08:40 -0000 Read CPUID to check if AVX512 is supported by CPU. Signed-off-by: Zhihong Wang --- lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h index dd56553..89c0d9d 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h @@ -131,6 +131,7 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_ERMS, /**< ERMS */ RTE_CPUFLAG_INVPCID, /**< INVPCID */ RTE_CPUFLAG_RTM, /**< Transactional memory */ + RTE_CPUFLAG_AVX512F, /**< AVX512F */ /* (EAX 80000001h) ECX features */ RTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */ @@ -238,6 +239,7 @@ static const struct feature_entry cpu_feature_table[] = { FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) + FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4) -- 2.5.0