From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f42.google.com (mail-pa0-f42.google.com [209.85.220.42]) by dpdk.org (Postfix) with ESMTP id E666B8E8F for ; Tue, 19 Jan 2016 12:46:56 +0100 (CET) Received: by mail-pa0-f42.google.com with SMTP id uo6so436577601pac.1 for ; Tue, 19 Jan 2016 03:46:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mvista-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=08zELcqJbPcpksZ2aVv1vwJJQ4cOP5ljKt3yhfnjzCs=; b=GZkZG7vOgRH4E26rqw48n9ODdEc4pgRBpiF7OK8CGo8o7VfQ45vV0cFMQ2rMqRKfHA AZ+uVXPQuPxlU5hPCGCpLcs26KUmhLsrO98kU0EcwRudGCx60RVL/+816tKiBaV15BkD g6DwYkVrneZBbOgctnt5sARKkUcB5MaRxGCBJElg0sr01+VrW4bLo5vei7XdRyg1NMX+ vBpSSxstuLfWs+MDSLBHG14ewCSsqhP5rWJdZsdlZV++lPR8GFFkJbGvBU2+358r6f24 yv2XPlZcU3qz67OPXiru0jm8spC09TC/Vt64Qyx+k5H4nzU5u7zHpKONDifiGasjfE+y XebA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=08zELcqJbPcpksZ2aVv1vwJJQ4cOP5ljKt3yhfnjzCs=; b=UB+GjrWhfkJR3bFAuz11et6P/npNoe7aQY7HsgSv0QG1j8vNG2B8OCaOE34AgtkjLX f1E2zunCqJKH/blclQFAcdVFJHbYNnwJjnd57hTd+4l+Im6E5ERqt9Ntcs2c4SCtiitr 6VPymESAxwu+ph3gvgOrUAKac86EutImA1VsqNSL2HUmivhE7yMuT7+CuLFxr7tF6yJn 0QXNa9tHdhp8sLbbRTxCV51i72q/Y0dgcQ7vdFMRh3Bnw5qAfqWASjmlw5aduadJip8E JmDv4gsTAmPj80VaX2rkuEi9cFtIK/EG8qX0HgFyIPo/vC8t+qOXrrEDVOV88MXmP6Yv 3y8g== X-Gm-Message-State: ALoCoQkduwm6TPmvdMVzMjW2DbS6zFHU02dfKHATVRsHZWFbC6RKc9HkgRuGCLdC9EHWskTgQqTRt6nEt31NRxh53oCCK2k6cw== X-Received: by 10.66.234.200 with SMTP id ug8mr43753838pac.129.1453204016375; Tue, 19 Jan 2016 03:46:56 -0800 (PST) Received: from santosh-Latitude-E5530-non-vPro.mvista.com ([111.93.218.67]) by smtp.gmail.com with ESMTPSA id 75sm41014170pfj.20.2016.01.19.03.46.53 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Jan 2016 03:46:55 -0800 (PST) From: Santosh Shukla To: dev@dpdk.org Date: Tue, 19 Jan 2016 17:16:08 +0530 Message-Id: <1453203972-24855-8-git-send-email-sshukla@mvista.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1453203972-24855-1-git-send-email-sshukla@mvista.com> References: <1453203972-24855-1-git-send-email-sshukla@mvista.com> Subject: [dpdk-dev] [PATCH v5 07/11] virtio: pci: extend virtio pci rw api for vfio interface X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jan 2016 11:46:57 -0000 So far virtio handle rw access for uio / ioport interface, This patch to extend the support for vfio interface. Applicable for virtio 0.95 spec. Signed-off-by: Santosh Shukla --- v4--> v5: - Replaced virtio_rd/wr_1/2/4() macro implementation with inline function, per Yuan review commment. drivers/net/virtio/virtio_pci.c | 110 ++++++++++++++++++++++++++++++++++----- 1 file changed, 97 insertions(+), 13 deletions(-) diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c index a9f179f..0c29f1d 100644 --- a/drivers/net/virtio/virtio_pci.c +++ b/drivers/net/virtio/virtio_pci.c @@ -40,6 +40,7 @@ #include "virtio_pci.h" #include "virtio_logs.h" #include "virtqueue.h" +#include "virtio_vfio_rw.h" /* * Following macros are derieved from linux/pci_regs.h, however, @@ -49,24 +50,107 @@ #define PCI_CAPABILITY_LIST 0x34 #define PCI_CAP_ID_VNDR 0x09 - #define VIRTIO_PCI_REG_ADDR(hw, reg) \ (unsigned short)((hw)->io_base + (reg)) -#define VIRTIO_READ_REG_1(hw, reg) \ - inb((VIRTIO_PCI_REG_ADDR((hw), (reg)))) -#define VIRTIO_WRITE_REG_1(hw, reg, value) \ - outb_p((unsigned char)(value), (VIRTIO_PCI_REG_ADDR((hw), (reg)))) +static inline uint8_t +virtio_read_reg_1(struct virtio_hw *hw, uint64_t reg_offset) +{ + uint8_t ret; + struct rte_pci_device *dev; + + dev = hw->dev; + if (dev->kdrv == RTE_KDRV_VFIO) + ioport_inb(dev, reg_offset, &ret); + else + ret = inb(VIRTIO_PCI_REG_ADDR(hw, reg_offset)); + + return ret; +} + +static inline uint16_t +virtio_read_reg_2(struct virtio_hw *hw, uint64_t reg_offset) +{ + uint16_t ret; + struct rte_pci_device *dev; + + dev = hw->dev; + if (dev->kdrv == RTE_KDRV_VFIO) + ioport_inw(dev, reg_offset, &ret); + else + ret = inw(VIRTIO_PCI_REG_ADDR(hw, reg_offset)); + + return ret; +} + +static inline uint32_t +virtio_read_reg_4(struct virtio_hw *hw, uint64_t reg_offset) +{ + uint32_t ret; + struct rte_pci_device *dev; + + dev = hw->dev; + if (dev->kdrv == RTE_KDRV_VFIO) + ioport_inl(dev, reg_offset, &ret); + else + ret = inl(VIRTIO_PCI_REG_ADDR(hw, reg_offset)); + + return ret; +} + +static inline void +virtio_write_reg_1(struct virtio_hw *hw, uint64_t reg_offset, uint8_t value) +{ + struct rte_pci_device *dev; + + dev = hw->dev; + if (dev->kdrv == RTE_KDRV_VFIO) + ioport_outb_p(dev, reg_offset, value); + else + outb_p((unsigned char)value, + VIRTIO_PCI_REG_ADDR(hw, reg_offset)); +} + +static inline void +virtio_write_reg_2(struct virtio_hw *hw, uint64_t reg_offset, uint16_t value) +{ + struct rte_pci_device *dev; + + dev = hw->dev; + if (dev->kdrv == RTE_KDRV_VFIO) + ioport_outw_p(dev, reg_offset, value); + else + outw_p((unsigned short)value, + VIRTIO_PCI_REG_ADDR(hw, reg_offset)); +} + +static inline void +virtio_write_reg_4(struct virtio_hw *hw, uint64_t reg_offset, uint32_t value) +{ + struct rte_pci_device *dev; + + dev = hw->dev; + if (dev->kdrv == RTE_KDRV_VFIO) + ioport_outl_p(dev, reg_offset, value); + else + outl_p((unsigned int)value, + VIRTIO_PCI_REG_ADDR(hw, reg_offset)); +} + +#define VIRTIO_READ_REG_1(hw, reg) \ + virtio_read_reg_1((hw), (reg)) +#define VIRTIO_WRITE_REG_1(hw, reg, value) \ + virtio_write_reg_1((hw), (reg), (value)) -#define VIRTIO_READ_REG_2(hw, reg) \ - inw((VIRTIO_PCI_REG_ADDR((hw), (reg)))) -#define VIRTIO_WRITE_REG_2(hw, reg, value) \ - outw_p((unsigned short)(value), (VIRTIO_PCI_REG_ADDR((hw), (reg)))) +#define VIRTIO_READ_REG_2(hw, reg) \ + virtio_read_reg_2((hw), (reg)) +#define VIRTIO_WRITE_REG_2(hw, reg, value) \ + virtio_write_reg_2((hw), (reg), (value)) -#define VIRTIO_READ_REG_4(hw, reg) \ - inl((VIRTIO_PCI_REG_ADDR((hw), (reg)))) -#define VIRTIO_WRITE_REG_4(hw, reg, value) \ - outl_p((unsigned int)(value), (VIRTIO_PCI_REG_ADDR((hw), (reg)))) +#define VIRTIO_READ_REG_4(hw, reg) \ + virtio_read_reg_4((hw), (reg)) +#define VIRTIO_WRITE_REG_4(hw, reg, value) \ + virtio_write_reg_4((hw), (reg), (value)) static void legacy_read_dev_config(struct virtio_hw *hw, uint64_t offset, -- 1.7.9.5