[dpdk-dev] [PATCH v1 1/3] drivers/net/i40e: Add ethdev functions

[Remy Horton <remy.horton@intel.com>]

Implements driver support for dumping of EEPROM and registers,
and the settngs of MAC address.

Signed-off-by: Remy Horton <remy.horton@intel.com>
---
 doc/guides/rel_notes/release_2_3.rst |   5 +
 drivers/net/i40e/i40e_ethdev.c       | 130 +++++-
 drivers/net/i40e/i40e_regs.h         | 814 +++++++++++++++++++++++++++++++++++
 3 files changed, 947 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/i40e/i40e_regs.h

diff --git a/doc/guides/rel_notes/release_2_3.rst b/doc/guides/rel_notes/release_2_3.rst
index 99de186..2ac48dd 100644
--- a/doc/guides/rel_notes/release_2_3.rst
+++ b/doc/guides/rel_notes/release_2_3.rst
@@ -4,6 +4,11 @@ DPDK Release 2.3
 New Features
 ------------
 
+* **i40e: Added ethdev support functions.**
+
+  Implemented driver functions for Register dumping, EEPROM dumping, and
+  setting of MAC address.
+
 
 Resolved Issues
 ---------------
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index bf6220d..2f39358 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
+ *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -61,6 +61,7 @@
 #include "i40e_ethdev.h"
 #include "i40e_rxtx.h"
 #include "i40e_pf.h"
+#include "i40e_regs.h"
 
 /* Maximun number of MAC addresses */
 #define I40E_NUM_MACADDR_MAX       64
@@ -414,6 +415,22 @@ static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 					  uint16_t queue_id);
 
+static int i40e_get_reg_length(struct rte_eth_dev *dev);
+
+static int i40e_get_regs(struct rte_eth_dev *dev,
+			 struct rte_dev_reg_info *regs);
+
+static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
+
+static int i40e_get_eeprom(struct rte_eth_dev *dev,
+			   struct rte_dev_eeprom_info *eeprom);
+
+static int i40e_set_eeprom(struct rte_eth_dev *dev,
+			   struct rte_dev_eeprom_info *eeprom);
+
+static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
+				      struct ether_addr *mac_addr);
+
 
 static const struct rte_pci_id pci_id_i40e_map[] = {
 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
@@ -482,6 +499,12 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
 	.timesync_adjust_time         = i40e_timesync_adjust_time,
 	.timesync_read_time           = i40e_timesync_read_time,
 	.timesync_write_time          = i40e_timesync_write_time,
+	.get_reg_length	              = i40e_get_reg_length,
+	.get_reg                      = i40e_get_regs,
+	.get_eeprom_length            = i40e_get_eeprom_length,
+	.get_eeprom                   = i40e_get_eeprom,
+	.set_eeprom                   = i40e_set_eeprom,
+	.mac_addr_set                 = i40e_set_default_mac_addr,
 };
 
 /* store statistics names and its offset in stats structure */
@@ -8077,7 +8100,6 @@ i40e_parse_dcb_configure(struct rte_eth_dev *dev,
 	return 0;
 }
 
-
 static enum i40e_status_code
 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
 			      struct i40e_aqc_vsi_properties_data *info,
@@ -8532,3 +8554,107 @@ i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
 
 	return 0;
 }
+
+static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
+{
+	int idx_group = 0;
+	int idx_entry;
+	int count = 0;
+	const struct reg_info *reg_group;
+
+	while ((reg_group = i40e_regs[idx_group++])) {
+		idx_entry = 0;
+		while ((reg_group[idx_entry].count))
+			count += reg_group[idx_entry++].count + 1;
+	}
+
+	return count;
+}
+
+static inline int
+i40e_read_regs(struct i40e_hw *hw, const struct reg_info *reg,
+	       uint32_t *reg_buf)
+{
+	unsigned int i;
+
+	for (i = 0; i < reg->count; i++)
+		reg_buf[i] = I40E_READ_REG(hw,
+			reg->base_addr + i * reg->stride);
+	return reg->count;
+}
+
+static int i40e_get_regs(struct rte_eth_dev *dev,
+			 struct rte_dev_reg_info *regs)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	int idx_group = 0;
+	int idx_entry = 0;
+	int len_data = 0;
+	uint32_t *ptr_data = regs->data;
+	const struct reg_info *reg_group;
+
+	/* Only support doing full dump */
+	if (regs->offset != 0 && 0)
+		return -ENOTSUP;
+
+	while ((reg_group = i40e_regs[idx_group])) {
+		idx_entry = 0;
+		while (reg_group[idx_entry].count != 0) {
+			len_data += i40e_read_regs(hw,
+				&reg_group[idx_entry],
+				&ptr_data[len_data]);
+			idx_entry++;
+		}
+		idx_group++;
+	}
+
+	return 0;
+}
+
+static int i40e_get_eeprom_length(__rte_unused struct rte_eth_dev *dev)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+	/* Convert word count to byte count */
+	return hw->nvm.sr_size << 1;
+}
+
+static int i40e_get_eeprom(__rte_unused struct rte_eth_dev *dev,
+			   __rte_unused struct rte_dev_eeprom_info *eeprom)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	uint16_t *data = eeprom->data;
+	uint16_t offset, length, cnt_words;
+	int ret_code;
+
+	offset = eeprom->offset >> 1;
+	length = eeprom->length >> 1;
+	cnt_words = length;
+
+	if (offset > hw->nvm.sr_size ||
+		offset + length > hw->nvm.sr_size)
+		return -EINVAL;
+
+	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
+
+	ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
+	if (ret_code != I40E_SUCCESS || cnt_words != length)
+		return -EIO;
+
+	return 0;
+}
+
+static int i40e_set_eeprom(__rte_unused struct rte_eth_dev *dev,
+			   __rte_unused struct rte_dev_eeprom_info *eeprom)
+{
+	return -ENOTSUP;
+}
+
+static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
+				      struct ether_addr *mac_addr)
+{
+	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+	/* Flags: 0x3 updates port address */
+	i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
+}
diff --git a/drivers/net/i40e/i40e_regs.h b/drivers/net/i40e/i40e_regs.h
new file mode 100644
index 0000000..43b7167
--- /dev/null
+++ b/drivers/net/i40e/i40e_regs.h
@@ -0,0 +1,814 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of Intel Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IX40E_REGS_H_
+#define _IX40E_REGS_H_
+
+#include "base/i40e_register.h"
+
+struct reg_info {
+	uint32_t base_addr;
+	uint32_t count;
+	uint32_t stride;
+	const char *name;
+} reg_info;
+
+static const struct reg_info i40e_regs_pf_gen[] = {
+	{I40E_VFGEN_RSTAT1(0), I40E_VFGEN_RSTAT1_MAX_INDEX + 1, 4,
+	 "I40E_VFGEN_RSTAT1"},
+	{I40E_GL_FWSTS, 1, 4, "I40E_GL_FWSTS"},
+	{I40E_PFGEN_STATE, 1, 4, "I40E_PFGEN_STATE"},
+	{I40E_GLGEN_LED_CTL, 1, 4, "I40E_GLGEN_LED_CTL"},
+	{I40E_GLGEN_GPIO_CTL(0), I40E_GLGEN_GPIO_CTL_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_GPIO_CTL"},
+	{I40E_GLGEN_GPIO_SET, 1, 4, "I40E_GLGEN_GPIO_SET"},
+	{I40E_GLGEN_GPIO_STAT, 1, 4, "I40E_GLGEN_GPIO_STAT"},
+	{I40E_GLGEN_GPIO_TRANSIT, 1, 4, "I40E_GLGEN_GPIO_TRANSIT"},
+	{I40E_GLGEN_MSCA(0), I40E_GLGEN_MSCA_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_MSCA"},
+	{I40E_GLGEN_MSRWD(0), I40E_GLGEN_MSRWD_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_MSRWD"},
+	{I40E_GLGEN_I2CPARAMS(0), I40E_GLGEN_I2CPARAMS_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_I2CPARAMS"},
+	{I40E_GLVFGEN_TIMER, 1, 4, "I40E_GLVFGEN_TIMER"},
+	{I40E_GLGEN_MDIO_CTRL(0), I40E_GLGEN_MDIO_CTRL_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_MDIO_CTRL"},
+	{I40E_GLGEN_MDIO_I2C_SEL(0), I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_MDIO_I2C_SEL"},
+	{I40E_GLGEN_I2CCMD(0), I40E_GLGEN_I2CCMD_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_I2CCMD"},
+	{I40E_VSIGEN_RSTAT(0), I40E_VSIGEN_RSTAT_MAX_INDEX + 1, 4,
+	 "I40E_VSIGEN_RSTAT"},
+	{I40E_VSIGEN_RTRIG(0), I40E_VSIGEN_RTRIG_MAX_INDEX + 1, 4,
+	 "I40E_VSIGEN_RTRIG"},
+	{I40E_VPGEN_VFRSTAT(0), I40E_VPGEN_VFRSTAT_MAX_INDEX + 1, 4,
+	 "I40E_VPGEN_VFRSTAT"},
+	{I40E_VPGEN_VFRTRIG(0), I40E_VPGEN_VFRTRIG_MAX_INDEX + 1, 4,
+	 "I40E_VPGEN_VFRTRIG"},
+	{I40E_PFGEN_CTRL, 1, 4, "I40E_PFGEN_CTRL"},
+	{I40E_PFGEN_DRUN, 1, 4, "I40E_PFGEN_DRUN"},
+	{I40E_GLGEN_VFLRSTAT(0), I40E_GLGEN_VFLRSTAT_MAX_INDEX + 1, 4,
+	 "I40E_GLGEN_VFLRSTAT"},
+	{I40E_GLGEN_STAT, 1, 4, "I40E_GLGEN_STAT"},
+	{I40E_PRTGEN_STATUS, 1, 4, "I40E_PRTGEN_STATUS"},
+	{I40E_PRTGEN_CNF, 1, 4, "I40E_PRTGEN_CNF"},
+	{I40E_PRTGEN_CNF2, 1, 4, "I40E_PRTGEN_CNF2"},
+	{I40E_GLGEN_RSTCTL, 1, 4, "I40E_GLGEN_RSTCTL"},
+	{I40E_GLGEN_CLKSTAT, 1, 4, "I40E_GLGEN_CLKSTAT"},
+	{I40E_GLGEN_RTRIG, 1, 4, "I40E_GLGEN_RTRIG"},
+	{I40E_GLGEN_RSTAT, 1, 4, "I40E_GLGEN_RSTAT"},
+	{I40E_GLGEN_PCIFCNCNT, 1, 4, "I40E_GLGEN_PCIFCNCNT"},
+	{I40E_PFGEN_PORTNUM, 1, 4, "I40E_PFGEN_PORTNUM"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_pci[] = {
+	{I40E_PF_FUNC_RID, 1, 4, "I40E_PF_FUNC_RID"},
+	{I40E_PF_PCI_CIAA, 1, 4, "I40E_PF_PCI_CIAA"},
+	{I40E_PF_PCI_CIAD, 1, 4, "I40E_PF_PCI_CIAD"},
+	{I40E_PFPCI_FACTPS, 1, 4, "I40E_PFPCI_FACTPS"},
+	{I40E_PFPCI_VMINDEX, 1, 4, "I40E_PFPCI_VMINDEX"},
+	{I40E_PFPCI_VMPEND, 1, 4, "I40E_PFPCI_VMPEND"},
+	{I40E_GLPCI_DREVID, 1, 4, "I40E_GLPCI_DREVID"},
+	{I40E_GLPCI_BYTCTH, 1, 4, "I40E_GLPCI_BYTCTH"},
+	{I40E_GLPCI_BYTCTL, 1, 4, "I40E_GLPCI_BYTCTL"},
+	{I40E_GLPCI_GSCL_1, 1, 4, "I40E_GLPCI_GSCL_1"},
+	{I40E_GLPCI_GSCL_2, 1, 4, "I40E_GLPCI_GSCL_2"},
+	{I40E_GLPCI_GSCL_5_8(0), I40E_GLPCI_GSCL_5_8_MAX_INDEX + 1, 4,
+	 "I40E_GLPCI_GSCL_5_8"},
+	{I40E_GLPCI_GSCN_0_3(0), I40E_GLPCI_GSCN_0_3_MAX_INDEX + 1, 4,
+	 "I40E_GLPCI_GSCN_0_3"},
+	{I40E_GLPCI_PKTCT, 1, 4, "I40E_GLPCI_PKTCT"},
+	{I40E_GLPCI_PQ_MAX_USED_SPC, 1, 4, "I40E_GLPCI_PQ_MAX_USED_SPC"},
+	{I40E_GLPCI_PM_MUX_NPQ, 1, 4, "I40E_GLPCI_PM_MUX_NPQ"},
+	{I40E_GLPCI_PM_MUX_PFB, 1, 4, "I40E_GLPCI_PM_MUX_PFB"},
+	{I40E_GLPCI_SPARE_BITS_0, 1, 4, "I40E_GLPCI_SPARE_BITS_0"},
+	{I40E_GLPCI_SPARE_BITS_1, 1, 4, "I40E_GLPCI_SPARE_BITS_1"},
+	{I40E_PFPCI_VF_FLUSH_DONE, 1, 4, "I40E_PFPCI_VF_FLUSH_DONE"},
+	{I40E_PFPCI_PF_FLUSH_DONE, 1, 4, "I40E_PFPCI_PF_FLUSH_DONE"},
+	{I40E_PFPCI_VF_FLUSH_DONE1(0), I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX + 1,
+	 4,  "I40E_PFPCI_VF_FLUSH_DONE1"},
+	{I40E_PFPCI_VM_FLUSH_DONE, 1, 4, "I40E_PFPCI_VM_FLUSH_DONE"},
+	{I40E_PFPCI_CNF, 1, 4, "I40E_PFPCI_CNF"},
+	{I40E_PFPCI_DEVID, 1, 4, "I40E_PFPCI_DEVID"},
+	{I40E_PFPCI_SUBSYSID, 1, 4, "I40E_PFPCI_SUBSYSID"},
+	{I40E_PFPCI_FUNC, 1, 4, "I40E_PFPCI_FUNC"},
+	{I40E_PFPCI_FUNC2, 1, 4, "I40E_PFPCI_FUNC2"},
+	{I40E_PFPCI_STATUS1, 1, 4, "I40E_PFPCI_STATUS1"},
+	{I40E_PFPCI_PM, 1, 4, "I40E_PFPCI_PM"},
+	{I40E_PFPCI_CLASS, 1, 4, "I40E_PFPCI_CLASS"},
+	{I40E_GLTPH_CTRL, 1, 4, "I40E_GLTPH_CTRL"},
+	{I40E_GLPCI_LBARCTRL, 1, 4, "I40E_GLPCI_LBARCTRL"},
+	{I40E_GLPCI_SUBVENID, 1, 4, "I40E_GLPCI_SUBVENID"},
+	{I40E_GLPCI_PWRDATA, 1, 4, "I40E_GLPCI_PWRDATA"},
+	{I40E_GLPCI_CNF2, 1, 4, "I40E_GLPCI_CNF2"},
+	{I40E_GLPCI_SERH, 1, 4, "I40E_GLPCI_SERH"},
+	{I40E_GLPCI_SERL, 1, 4, "I40E_GLPCI_SERL"},
+	{I40E_GLPCI_CAPCTRL, 1, 4, "I40E_GLPCI_CAPCTRL"},
+	{I40E_GLPCI_CAPSUP, 1, 4, "I40E_GLPCI_CAPSUP"},
+	{I40E_GLPCI_LINKCAP, 1, 4, "I40E_GLPCI_LINKCAP"},
+	{I40E_GLPCI_PMSUP, 1, 4, "I40E_GLPCI_PMSUP"},
+	{I40E_GLPCI_REVID, 1, 4, "I40E_GLPCI_REVID"},
+	{I40E_GLPCI_VFSUP, 1, 4, "I40E_GLPCI_VFSUP"},
+	{I40E_GLPCI_CNF, 1, 4, "I40E_GLPCI_CNF"},
+	{I40E_GLPCI_UPADD, 1, 4, "I40E_GLPCI_UPADD"},
+	{I40E_GLPCI_VENDORID, 1, 4, "I40E_GLPCI_VENDORID"},
+	{0, 0, 0, NULL}
+	};
+
+static const struct reg_info i40e_regs_pf_mac[] = {
+	{I40E_PRTMAC_PCS_XAUI_SWAP_A, 1, 4, "I40E_PRTMAC_PCS_XAUI_SWAP_A"},
+	{I40E_PRTMAC_PCS_XAUI_SWAP_B, 1, 4, "I40E_PRTMAC_PCS_XAUI_SWAP_B"},
+	{I40E_PRTGL_SAH, 1, 4, "I40E_PRTGL_SAH"},
+	{I40E_PRTGL_SAL, 1, 4, "I40E_PRTGL_SAL"},
+	{I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE"},
+	{I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE"},
+	{I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP"},
+	{I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1"},
+	{I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2"},
+	{I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1"},
+	{I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2"},
+	{I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP"},
+	{I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP"},
+	{I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL"},
+	{I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(0),
+	 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX + 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA"},
+	{I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(0),
+	 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX + 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER"},
+	{I40E_PRTMAC_HSEC_CTL_TX_SA_PART1, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_TX_SA_PART1"},
+	{I40E_PRTMAC_HSEC_CTL_TX_SA_PART2, 1, 4,
+	 "I40E_PRTMAC_HSEC_CTL_TX_SA_PART2"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_power[] = {
+	{I40E_PRTPM_GC, 1, 4, "I40E_PRTPM_GC"},
+	{I40E_PRTPM_EEE_STAT, 1, 4, "I40E_PRTPM_EEE_STAT"},
+	{I40E_PRTPM_EEER, 1, 4, "I40E_PRTPM_EEER"},
+	{I40E_PRTPM_EEEC, 1, 4, "I40E_PRTPM_EEEC"},
+	{I40E_PRTPM_RLPIC, 1, 4, "I40E_PRTPM_RLPIC"},
+	{I40E_PRTPM_TLPIC, 1, 4, "I40E_PRTPM_TLPIC"},
+	{I40E_PRTPM_EEETXC, 1, 4, "I40E_PRTPM_EEETXC"},
+	{I40E_PRTPM_EEEFWD, 1, 4, "I40E_PRTPM_EEEFWD"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_wakeandproxy[] = {
+	{I40E_PFPM_FHFT_LENGTH(0), I40E_PFPM_FHFT_LENGTH_MAX_INDEX + 1, 4,
+	 "I40E_PFPM_FHFT_LENGTH"},
+	{I40E_PFPM_WUC, 1, 4, "I40E_PFPM_WUC"},
+	{I40E_PFPM_WUFC, 1, 4, "I40E_PFPM_WUFC"},
+	{I40E_PFPM_WUS, 1, 4, "I40E_PFPM_WUS"},
+	{I40E_PRTPM_FHFHR, 1, 4, "I40E_PRTPM_FHFHR"},
+	{I40E_GLPM_WUMC, 1, 4, "I40E_GLPM_WUMC"},
+	{I40E_PFPM_APM, 1, 4, "I40E_PFPM_APM"},
+	{I40E_PRTPM_SAL(0), I40E_PRTPM_SAL_MAX_INDEX + 1, 4, "I40E_PRTPM_SAL"},
+	{I40E_PRTPM_SAH(0), I40E_PRTPM_SAH_MAX_INDEX + 1, 4, "I40E_PRTPM_SAH"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_nvm[] = {
+	{I40E_GLNVM_ULD, 1, 4, "I40E_GLNVM_ULD"},
+	{I40E_GLNVM_PROTCSR(0), I40E_GLNVM_PROTCSR_MAX_INDEX + 1, 4,
+	 "I40E_GLNVM_PROTCSR"},
+	{I40E_GLNVM_GENS, 1, 4, "I40E_GLNVM_GENS"},
+	{I40E_GLNVM_FLASHID, 1, 4, "I40E_GLNVM_FLASHID"},
+	{I40E_GLNVM_FLA, 1, 4, "I40E_GLNVM_FLA"},
+	{I40E_GLNVM_SRCTL, 1, 4, "I40E_GLNVM_SRCTL"},
+	{I40E_GLNVM_SRDATA, 1, 4, "I40E_GLNVM_SRDATA"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_analyzer[] = {
+	{I40E_PRT_L2TAGSEN, 1, 4, "I40E_PRT_L2TAGSEN"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_switch[] = {
+	{I40E_GL_SWR_DEF_ACT_EN(0), I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX + 1, 4,
+	 "I40E_GL_SWR_DEF_ACT_EN"},
+	{I40E_GL_SWR_DEF_ACT(0), I40E_GL_SWR_DEF_ACT_MAX_INDEX + 1, 4,
+	 "I40E_GL_SWR_DEF_ACT"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_interrupt[] = {
+	{I40E_VFINT_ITRN(0, 0), 2048 * 3, 4, "I40E_VFINT_ITRN"},
+	{I40E_VFINT_DYN_CTLN(0), I40E_VFINT_DYN_CTLN_MAX_INDEX + 1, 4,
+	 "I40E_VFINT_DYN_CTLN"},
+	{I40E_VPINT_LNKLSTN(0), I40E_VPINT_LNKLSTN_MAX_INDEX + 1, 4,
+	 "I40E_VPINT_LNKLSTN"},
+	{I40E_VPINT_RATEN(0), I40E_VPINT_RATEN_MAX_INDEX + 1, 4,
+	 "I40E_VPINT_RATEN"},
+	{I40E_VFINT_ITR0(0, 0), 1024 * 3, 4, "I40E_VFINT_ITR0"},
+	{I40E_VFINT_STAT_CTL0(0), I40E_VFINT_STAT_CTL0_MAX_INDEX + 1, 4,
+	 "I40E_VFINT_STAT_CTL0"},
+	{I40E_VFINT_DYN_CTL0(0), I40E_VFINT_DYN_CTL0_MAX_INDEX + 1, 4,
+	 "I40E_VFINT_DYN_CTL0"},
+	{I40E_VPINT_LNKLST0(0), I40E_VPINT_LNKLST0_MAX_INDEX + 1, 4,
+	 "I40E_VPINT_LNKLST0"},
+	{I40E_VPINT_RATE0(0), I40E_VPINT_RATE0_MAX_INDEX + 1, 4,
+	 "I40E_VPINT_RATE0"},
+	{I40E_VFINT_ICR0(0), I40E_VFINT_ICR0_MAX_INDEX + 1, 4,
+	 "I40E_VFINT_ICR0"},
+	{I40E_VFINT_ICR0_ENA(0), I40E_VFINT_ICR0_ENA_MAX_INDEX + 1, 4,
+	 "I40E_VFINT_ICR0_ENA"},
+	{I40E_PFINT_ITRN(0, 0), 2048 * 3, 4, "I40E_PFINT_ITRN"},
+	{I40E_PFINT_DYN_CTLN(0), I40E_PFINT_DYN_CTLN_MAX_INDEX + 1, 4,
+	 "I40E_PFINT_DYN_CTLN"},
+	{I40E_PFINT_LNKLSTN(0), I40E_PFINT_LNKLSTN_MAX_INDEX + 1, 4,
+	 "I40E_PFINT_LNKLSTN"},
+	{I40E_PFINT_RATE0, 1, 4, "I40E_PFINT_RATE0"},
+	{I40E_PFINT_ICR0, 1, 4, "I40E_PFINT_ICR0"},
+	{I40E_PFINT_ICR0_ENA, 1, 4, "I40E_PFINT_ICR0_ENA"},
+	{I40E_QINT_RQCTL(0), I40E_QINT_RQCTL_MAX_INDEX + 1, 4,
+	 "I40E_QINT_RQCTL"},
+	{I40E_QINT_TQCTL(0), I40E_QINT_TQCTL_MAX_INDEX + 1, 4,
+	 "I40E_QINT_TQCTL"},
+	{I40E_PFGEN_PORTMDIO_NUM, 1, 4, "I40E_PFGEN_PORTMDIO_NUM"},
+	{I40E_PFINT_GPIO_ENA, 1, 4, "I40E_PFINT_GPIO_ENA"},
+	{I40E_EMPINT_GPIO_ENA, 1, 4, "I40E_EMPINT_GPIO_ENA"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_virtualpf[] = {
+	{I40E_VP_MDET_TX(0), I40E_VP_MDET_TX_MAX_INDEX + 1, 4,
+	 "I40E_VP_MDET_TX"},
+	{I40E_PF_MDET_TX, 1, 4, "I40E_PF_MDET_TX"},
+	{I40E_GL_MDET_TX, 1, 4, "I40E_GL_MDET_TX"},
+	{I40E_PF_MDET_RX, 1, 4, "I40E_PF_MDET_RX"},
+	{I40E_VP_MDET_RX(0), I40E_VP_MDET_RX_MAX_INDEX + 1, 4,
+	 "I40E_VP_MDET_RX"},
+	{I40E_GL_MDET_RX, 1, 4, "I40E_GL_MDET_RX"},
+	{I40E_PF_VT_PFALLOC, 1, 4, "I40E_PF_VT_PFALLOC"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_dcb[] = {
+	{I40E_PRTDCB_GENC, 1, 4, "I40E_PRTDCB_GENC"},
+	{I40E_PRTDCB_GENS, 1, 4, "I40E_PRTDCB_GENS"},
+	{I40E_GLDCB_GENC, 1, 4, "I40E_GLDCB_GENC"},
+	{I40E_PRTDCB_TETSC_TPB, 1, 4, "I40E_PRTDCB_TETSC_TPB"},
+	{I40E_PRTDCB_TDPMC, 1, 4, "I40E_PRTDCB_TDPMC"},
+	{I40E_PRTDCB_TCWSTC(0), I40E_PRTDCB_TCWSTC_MAX_INDEX + 1, 4,
+	 "I40E_PRTDCB_TCWSTC"},
+	{I40E_PRTDCB_TCPMC, 1, 4, "I40E_PRTDCB_TCPMC"},
+	{I40E_PRTDCB_TETSC_TCB, 1, 4, "I40E_PRTDCB_TETSC_TCB"},
+	{I40E_PRTDCB_RETSTCC(0), I40E_PRTDCB_RETSTCC_MAX_INDEX + 1, 4,
+	 "I40E_PRTDCB_RETSTCC"},
+	{I40E_PRTDCB_RPPMC, 1, 4, "I40E_PRTDCB_RPPMC"},
+	{I40E_PRTDCB_RETSC, 1, 4, "I40E_PRTDCB_RETSC"},
+	{I40E_PRTDCB_RUPTQ(0), I40E_PRTDCB_RUPTQ_MAX_INDEX + 1, 4,
+	 "I40E_PRTDCB_RUPTQ"},
+	{I40E_GLDCB_RUPTI, 1, 4, "I40E_GLDCB_RUPTI"},
+	{I40E_PRTDCB_TC2PFC, 1, 4, "I40E_PRTDCB_TC2PFC"},
+	{I40E_PRTDCB_RUP, 1, 4, "I40E_PRTDCB_RUP"},
+	{I40E_PRTDCB_MFLCN, 1, 4, "I40E_PRTDCB_MFLCN"},
+	{I40E_PRTDCB_TFCS, 1, 4, "I40E_PRTDCB_TFCS"},
+	{I40E_PRTDCB_FCTTVN(0), I40E_PRTDCB_FCTTVN_MAX_INDEX + 1, 4,
+	 "I40E_PRTDCB_FCTTVN"},
+	{I40E_PRTDCB_FCRTV, 1, 4, "I40E_PRTDCB_FCRTV"},
+	{I40E_PRTDCB_FCCFG, 1, 4, "I40E_PRTDCB_FCCFG"},
+	{I40E_PRTDCB_TPFCTS(0), I40E_PRTDCB_TPFCTS_MAX_INDEX + 1, 4,
+	 "I40E_PRTDCB_TPFCTS"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_rxbuf[] = {
+	{I40E_PRTRPB_DHW(0), I40E_PRTRPB_DHW_MAX_INDEX + 1, 4,
+	 "I40E_PRTRPB_DHW"},
+	{I40E_PRTRPB_DLW(0), I40E_PRTRPB_DLW_MAX_INDEX + 1, 4,
+	 "I40E_PRTRPB_DLW"},
+	{I40E_PRTRPB_DPS(0), I40E_PRTRPB_DPS_MAX_INDEX + 1, 4,
+	 "I40E_PRTRPB_DPS"},
+	{I40E_PRTRPB_SHT(0), I40E_PRTRPB_SHT_MAX_INDEX + 1, 4,
+	 "I40E_PRTRPB_SHT"},
+	{I40E_PRTRPB_SHW, 1, 4, "I40E_PRTRPB_SHW"},
+	{I40E_PRTRPB_SLT(0), I40E_PRTRPB_SLT_MAX_INDEX + 1, 4,
+	 "I40E_PRTRPB_SLT"},
+	{I40E_PRTRPB_SLW, 1, 4, "I40E_PRTRPB_SLW"},
+	{I40E_PRTRPB_SPS, 1, 4, "I40E_PRTRPB_SPS"},
+	{I40E_GLRPB_DPSS, 1, 4, "I40E_GLRPB_DPSS"},
+	{I40E_GLRPB_GHW, 1, 4, "I40E_GLRPB_GHW"},
+	{I40E_GLRPB_GLW, 1, 4, "I40E_GLRPB_GLW"},
+	{I40E_GLRPB_PHW, 1, 4, "I40E_GLRPB_PHW"},
+	{I40E_GLRPB_PLW, 1, 4, "I40E_GLRPB_PLW"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_hostcache[] = {
+	{I40E_PFHMC_SDCMD, 1, 4, "I40E_PFHMC_SDCMD"},
+	{I40E_PFHMC_SDDATALOW, 1, 4, "I40E_PFHMC_SDDATALOW"},
+	{I40E_PFHMC_SDDATAHIGH, 1, 4, "I40E_PFHMC_SDDATAHIGH"},
+	{I40E_PFHMC_PDINV, 1, 4, "I40E_PFHMC_PDINV"},
+	{I40E_PFHMC_ERRORINFO, 1, 4, "I40E_PFHMC_ERRORINFO"},
+	{I40E_PFHMC_ERRORDATA, 1, 4, "I40E_PFHMC_ERRORDATA"},
+	{I40E_GLHMC_SDPART(0), I40E_GLHMC_SDPART_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_SDPART"},
+	{I40E_GLHMC_LANTXOBJSZ, 1, 4, "I40E_GLHMC_LANTXOBJSZ"},
+	{I40E_GLHMC_LANQMAX, 1, 4, "I40E_GLHMC_LANQMAX"},
+	{I40E_GLHMC_LANRXOBJSZ, 1, 4, "I40E_GLHMC_LANRXOBJSZ"},
+	{I40E_GLHMC_FCOEDDPOBJSZ, 1, 4, "I40E_GLHMC_FCOEDDPOBJSZ"},
+	{I40E_GLHMC_FCOEMAX, 1, 4, "I40E_GLHMC_FCOEMAX"},
+	{I40E_GLHMC_FCOEFOBJSZ, 1, 4, "I40E_GLHMC_FCOEFOBJSZ"},
+	{I40E_GLHMC_FSIMCOBJSZ, 1, 4, "I40E_GLHMC_FSIMCOBJSZ"},
+	{I40E_GLHMC_FSIMCMAX, 1, 4, "I40E_GLHMC_FSIMCMAX"},
+	{I40E_GLHMC_FSIAVOBJSZ, 1, 4, "I40E_GLHMC_FSIAVOBJSZ"},
+	{I40E_GLHMC_FSIAVMAX, 1, 4, "I40E_GLHMC_FSIAVMAX"},
+	{I40E_GLHMC_FCOEFMAX, 1, 4, "I40E_GLHMC_FCOEFMAX"},
+	{I40E_GLHMC_FSIAVBASE(0), I40E_GLHMC_FSIAVBASE_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FSIAVBASE"},
+	{I40E_GLHMC_FSIAVCNT(0), I40E_GLHMC_FSIAVCNT_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FSIAVCNT"},
+	{I40E_GLHMC_FSIMCBASE(0), I40E_GLHMC_FSIMCBASE_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FSIMCBASE"},
+	{I40E_GLHMC_FSIMCCNT(0), I40E_GLHMC_FSIMCCNT_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FSIMCCNT"},
+	{I40E_GLHMC_LANTXBASE(0), I40E_GLHMC_LANTXBASE_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_LANTXBASE"},
+	{I40E_GLHMC_LANTXCNT(0), I40E_GLHMC_LANTXCNT_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_LANTXCNT"},
+	{I40E_GLHMC_LANRXBASE(0), I40E_GLHMC_LANRXBASE_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_LANRXBASE"},
+	{I40E_GLHMC_LANRXCNT(0), I40E_GLHMC_LANRXCNT_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_LANRXCNT"},
+	{I40E_GLHMC_FCOEDDPBASE(0), I40E_GLHMC_FCOEDDPBASE_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FCOEDDPBASE"},
+	{I40E_GLHMC_FCOEDDPCNT(0), I40E_GLHMC_FCOEDDPCNT_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FCOEDDPCNT"},
+	{I40E_GLHMC_FCOEFBASE(0), I40E_GLHMC_FCOEFBASE_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FCOEFBASE"},
+	{I40E_GLHMC_FCOEFCNT(0), I40E_GLHMC_FCOEFCNT_MAX_INDEX + 1, 4,
+	 "I40E_GLHMC_FCOEFCNT"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_context[] = {
+	{I40E_PFCM_LAN_ERRINFO, 1, 4, "I40E_PFCM_LAN_ERRINFO"},
+	{I40E_PFCM_LAN_ERRDATA, 1, 4, "I40E_PFCM_LAN_ERRDATA"},
+	{I40E_PFCM_LANCTXDATA(0), I40E_PFCM_LANCTXDATA_MAX_INDEX + 1, 4,
+	 "I40E_PFCM_LANCTXDATA"},
+	{I40E_PFCM_LANCTXCTL, 1, 4, "I40E_PFCM_LANCTXCTL"},
+	{I40E_PFCM_LANCTXSTAT, 1, 4, "I40E_PFCM_LANCTXSTAT"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_adminq[] = {
+	{I40E_PF_ATQBAL, 1, 4, "I40E_PF_ATQBAL"},
+	{I40E_GL_ATQBAL, 1, 4, "I40E_GL_ATQBAL"},
+	{I40E_PF_ARQBAL, 1, 4, "I40E_PF_ARQBAL"},
+	{I40E_GL_ARQBAL, 1, 4, "I40E_GL_ARQBAL"},
+	{I40E_PF_ATQBAH, 1, 4, "I40E_PF_ATQBAH"},
+	{I40E_GL_ATQBAH, 1, 4, "I40E_GL_ATQBAH"},
+	{I40E_PF_ARQBAH, 1, 4, "I40E_PF_ARQBAH"},
+	{I40E_GL_ARQBAH, 1, 4, "I40E_GL_ARQBAH"},
+	{I40E_PF_ATQLEN, 1, 4, "I40E_PF_ATQLEN"},
+	{I40E_GL_ATQLEN, 1, 4, "I40E_GL_ATQLEN"},
+	{I40E_PF_ARQLEN, 1, 4, "I40E_PF_ARQLEN"},
+	{I40E_PF_ATQH, 1, 4, "I40E_PF_ATQH"},
+	{I40E_GL_ATQH, 1, 4, "I40E_GL_ATQH"},
+	{I40E_PF_ARQH, 1, 4, "I40E_PF_ARQH"},
+	{I40E_GL_ARQH, 1, 4, "I40E_GL_ARQH"},
+	{I40E_PF_ATQT, 1, 4, "I40E_PF_ATQT"},
+	{I40E_GL_ATQT, 1, 4, "I40E_GL_ATQT"},
+	{I40E_GL_ARQT, 1, 4, "I40E_GL_ARQT"},
+	{I40E_PF_ARQT, 1, 4, "I40E_PF_ARQT"},
+	{I40E_VF_ATQBAL(0), I40E_VF_ATQBAL_MAX_INDEX + 1, 4, "I40E_VF_ATQBAL"},
+	{I40E_VF_ARQBAL(0), I40E_VF_ARQBAL_MAX_INDEX + 1, 4, "I40E_VF_ARQBAL"},
+	{I40E_VF_ATQBAH(0), I40E_VF_ATQBAH_MAX_INDEX + 1, 4, "I40E_VF_ATQBAH"},
+	{I40E_VF_ARQBAH(0), I40E_VF_ARQBAH_MAX_INDEX + 1, 4, "I40E_VF_ARQBAH"},
+	{I40E_VF_ATQLEN(0), I40E_VF_ATQLEN_MAX_INDEX + 1, 4, "I40E_VF_ATQLEN"},
+	{I40E_VF_ARQLEN(0), I40E_VF_ARQLEN_MAX_INDEX + 1, 4, "I40E_VF_ARQLEN"},
+	{I40E_VF_ATQH(0), I40E_VF_ATQH_MAX_INDEX + 1, 4, "I40E_VF_ATQH"},
+	{I40E_VF_ARQH(0), I40E_VF_ARQH_MAX_INDEX + 1, 4, "I40E_VF_ARQH"},
+	{I40E_VF_ATQT(0), I40E_VF_ATQT_MAX_INDEX + 1, 4, "I40E_VF_ATQT"},
+	{I40E_VF_ARQT(0), I40E_VF_ARQT_MAX_INDEX + 1, 4, "I40E_VF_ARQT"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_stats[] = {
+	{I40E_GLPRT_GORCL(0), I40E_GLPRT_GORCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_GORCL"},
+	{I40E_GLPRT_GORCH(0), I40E_GLPRT_GORCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_GORCH"},
+	{I40E_GLPRT_MLFC(0), I40E_GLPRT_MLFC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_MLFC"},
+	{I40E_GLPRT_MRFC(0), I40E_GLPRT_MRFC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_MRFC"},
+	{I40E_GLPRT_CRCERRS(0), I40E_GLPRT_CRCERRS_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_CRCERRS"},
+	{I40E_GLPRT_RLEC(0), I40E_GLPRT_RLEC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_RLEC"},
+	{I40E_GLPRT_ILLERRC(0), I40E_GLPRT_ILLERRC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_ILLERRC"},
+	{I40E_GLPRT_RUC(0), I40E_GLPRT_RUC_MAX_INDEX + 1, 4, "I40E_GLPRT_RUC"},
+	{I40E_GLPRT_ROC(0), I40E_GLPRT_ROC_MAX_INDEX + 1, 4, "I40E_GLPRT_ROC"},
+	{I40E_GLPRT_LXONRXC(0), I40E_GLPRT_LXONRXC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_LXONRXC"},
+	{I40E_GLPRT_LXOFFRXC(0), I40E_GLPRT_LXOFFRXC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_LXOFFRXC"},
+	{I40E_GLPRT_PXONRXC(0, 0), 32 * 8, 4, "I40E_GLPRT_PXONRXC"},
+	{I40E_GLPRT_PXOFFRXC(0, 0), 32 * 8, 4, "I40E_GLPRT_PXOFFRXC"},
+	{I40E_GLPRT_RXON2OFFCNT(0, 0), 32 * 8, 4, "I40E_GLPRT_RXON2OFFCNT"},
+	{I40E_GLPRT_PRC64L(0), I40E_GLPRT_PRC64L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC64L"},
+	{I40E_GLPRT_PRC64H(0), I40E_GLPRT_PRC64H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC64H"},
+	{I40E_GLPRT_PRC127L(0), I40E_GLPRT_PRC127L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC127L"},
+	{I40E_GLPRT_PRC127H(0), I40E_GLPRT_PRC127H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC127H"},
+	{I40E_GLPRT_PRC255L(0), I40E_GLPRT_PRC255L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC255L"},
+	{I40E_GLPRT_PRC255H(0), I40E_GLPRT_PRC255H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC255H"},
+	{I40E_GLPRT_PRC511L(0), I40E_GLPRT_PRC511L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC511L"},
+	{I40E_GLPRT_PRC511H(0), I40E_GLPRT_PRC511H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC511H"},
+	{I40E_GLPRT_PRC1023L(0), I40E_GLPRT_PRC1023L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC1023L"},
+	{I40E_GLPRT_PRC1023H(0), I40E_GLPRT_PRC1023H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC1023H"},
+	{I40E_GLPRT_PRC1522L(0), I40E_GLPRT_PRC1522L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC1522L"},
+	{I40E_GLPRT_PRC1522H(0), I40E_GLPRT_PRC1522H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC1522H"},
+	{I40E_GLPRT_PRC9522L(0), I40E_GLPRT_PRC9522L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC9522L"},
+	{I40E_GLPRT_PRC9522H(0), I40E_GLPRT_PRC9522H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PRC9522H"},
+	{I40E_GLPRT_RFC(0), I40E_GLPRT_RFC_MAX_INDEX + 1, 4, "I40E_GLPRT_RFC"},
+	{I40E_GLPRT_RJC(0), I40E_GLPRT_RJC_MAX_INDEX + 1, 4, "I40E_GLPRT_RJC"},
+	{I40E_GLPRT_UPRCL(0), I40E_GLPRT_UPRCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_UPRCL"},
+	{I40E_GLPRT_UPRCH(0), I40E_GLPRT_UPRCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_UPRCH"},
+	{I40E_GLPRT_MPRCL(0), I40E_GLPRT_MPRCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_MPRCL"},
+	{I40E_GLPRT_MPRCH(0), I40E_GLPRT_MPRCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_MPRCH"},
+	{I40E_GLPRT_BPRCL(0), I40E_GLPRT_BPRCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_BPRCL"},
+	{I40E_GLPRT_BPRCH(0), I40E_GLPRT_BPRCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_BPRCH"},
+	{I40E_GLPRT_RDPC(0), I40E_GLPRT_RDPC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_RDPC"},
+	{I40E_GLPRT_LDPC(0), I40E_GLPRT_LDPC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_LDPC"},
+	{I40E_GLPRT_RUPP(0), I40E_GLPRT_RUPP_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_RUPP"},
+	{I40E_GLPRT_GOTCL(0), I40E_GLPRT_GOTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_GOTCL"},
+	{I40E_GLPRT_GOTCH(0), I40E_GLPRT_GOTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_GOTCH"},
+	{I40E_GLPRT_PTC64L(0), I40E_GLPRT_PTC64L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC64L"},
+	{I40E_GLPRT_PTC64H(0), I40E_GLPRT_PTC64H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC64H"},
+	{I40E_GLPRT_PTC127L(0), I40E_GLPRT_PTC127L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC127L"},
+	{I40E_GLPRT_PTC127H(0), I40E_GLPRT_PTC127H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC127H"},
+	{I40E_GLPRT_PTC255L(0), I40E_GLPRT_PTC255L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC255L"},
+	{I40E_GLPRT_PTC255H(0), I40E_GLPRT_PTC255H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC255H"},
+	{I40E_GLPRT_PTC511L(0), I40E_GLPRT_PTC511L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC511L"},
+	{I40E_GLPRT_PTC511H(0), I40E_GLPRT_PTC511H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC511H"},
+	{I40E_GLPRT_PTC1023L(0), I40E_GLPRT_PTC1023L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC1023L"},
+	{I40E_GLPRT_PTC1023H(0), I40E_GLPRT_PTC1023H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC1023H"},
+	{I40E_GLPRT_PTC1522L(0), I40E_GLPRT_PTC1522L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC1522L"},
+	{I40E_GLPRT_PTC1522H(0), I40E_GLPRT_PTC1522H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC1522H"},
+	{I40E_GLPRT_PTC9522L(0), I40E_GLPRT_PTC9522L_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC9522L"},
+	{I40E_GLPRT_PTC9522H(0), I40E_GLPRT_PTC9522H_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_PTC9522H"},
+	{I40E_GLPRT_PXONTXC(0, 0), 32 * 8, 4, "I40E_GLPRT_PXONTXC"},
+	{I40E_GLPRT_PXOFFTXC(0, 0), 32 * 8, 4, "I40E_GLPRT_PXOFFTXC"},
+	{I40E_GLPRT_LXONTXC(0), I40E_GLPRT_LXONTXC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_LXONTXC"},
+	{I40E_GLPRT_LXOFFTXC(0), I40E_GLPRT_LXOFFTXC_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_LXOFFTXC"},
+	{I40E_GLPRT_UPTCL(0), I40E_GLPRT_UPTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_UPTCL"},
+	{I40E_GLPRT_UPTCH(0), I40E_GLPRT_UPTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_UPTCH"},
+	{I40E_GLPRT_MPTCL(0), I40E_GLPRT_MPTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_MPTCL"},
+	{I40E_GLPRT_MPTCH(0), I40E_GLPRT_MPTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_MPTCH"},
+	{I40E_GLPRT_BPTCL(0), I40E_GLPRT_BPTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_BPTCL"},
+	{I40E_GLPRT_BPTCH(0), I40E_GLPRT_BPTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_BPTCH"},
+	{I40E_GLPRT_TDOLD(0), I40E_GLPRT_TDOLD_MAX_INDEX + 1, 4,
+	 "I40E_GLPRT_TDOLD"},
+	{I40E_GLV_RDPC(0), I40E_GLV_RDPC_MAX_INDEX + 1, 4, "I40E_GLV_RDPC"},
+	{I40E_GL_FCOELAST(0), I40E_GL_FCOELAST_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOELAST"},
+	{I40E_GL_FCOEDDPC(0), I40E_GL_FCOEDDPC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDDPC"},
+	{I40E_GL_FCOECRC(0), I40E_GL_FCOECRC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOECRC"},
+	{I40E_GL_FCOEPRC(0), I40E_GL_FCOEPRC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEPRC"},
+	{I40E_GL_RXERR1_L(0), I40E_GL_RXERR1_L_MAX_INDEX + 1, 4,
+	 "I40E_GL_RXERR1_L"},
+	{I40E_GL_FCOEDIFEC(0), I40E_GL_FCOEDIFEC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDIFEC"},
+	{I40E_GL_RXERR2_L(0), I40E_GL_RXERR2_L_MAX_INDEX + 1, 4,
+	 "I40E_GL_RXERR2_L"},
+	{I40E_GL_FCOEDWRCH(0), I40E_GL_FCOEDWRCH_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDWRCH"},
+	{I40E_GL_FCOEDWRCL(0), I40E_GL_FCOEDWRCL_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDWRCL"},
+	{I40E_GL_FCOERPDC(0), I40E_GL_FCOERPDC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOERPDC"},
+	{I40E_GLV_GOTCL(0), I40E_GLV_GOTCL_MAX_INDEX + 1, 4, "I40E_GLV_GOTCL"},
+	{I40E_GLV_GOTCH(0), I40E_GLV_GOTCH_MAX_INDEX + 1, 4, "I40E_GLV_GOTCH"},
+	{I40E_GLSW_GOTCL(0), I40E_GLSW_GOTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_GOTCL"},
+	{I40E_GLSW_GOTCH(0), I40E_GLSW_GOTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_GOTCH"},
+	{I40E_GLVEBTC_TBCL(0, 0), 64 * 16, 4, "I40E_GLVEBTC_TBCL"},
+	{I40E_GLVEBTC_TBCH(0, 0), 64 * 16, 4, "I40E_GLVEBTC_TBCH"},
+	{I40E_GLVEBTC_TPCL(0, 0), 64 * 16, 4, "I40E_GLVEBTC_TPCL"},
+	{I40E_GLVEBTC_TPCH(0, 0), 64 * 16, 4, "I40E_GLVEBTC_TPCH"},
+	{I40E_GLV_UPTCL(0), I40E_GLV_UPTCL_MAX_INDEX + 1, 4, "I40E_GLV_UPTCL"},
+	{I40E_GLV_UPTCH(0), I40E_GLV_UPTCH_MAX_INDEX + 1, 4, "I40E_GLV_UPTCH"},
+	{I40E_GLV_MPTCL(0), I40E_GLV_MPTCL_MAX_INDEX + 1, 4, "I40E_GLV_MPTCL"},
+	{I40E_GLV_MPTCH(0), I40E_GLV_MPTCH_MAX_INDEX + 1, 4, "I40E_GLV_MPTCH"},
+	{I40E_GLV_BPTCL(0), I40E_GLV_BPTCL_MAX_INDEX + 1, 4, "I40E_GLV_BPTCL"},
+	{I40E_GLV_BPTCH(0), I40E_GLV_BPTCH_MAX_INDEX + 1, 4, "I40E_GLV_BPTCH"},
+	{I40E_GLSW_UPTCL(0), I40E_GLSW_UPTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_UPTCL"},
+	{I40E_GLSW_UPTCH(0), I40E_GLSW_UPTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_UPTCH"},
+	{I40E_GLSW_MPTCL(0), I40E_GLSW_MPTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_MPTCL"},
+	{I40E_GLSW_MPTCH(0), I40E_GLSW_MPTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_MPTCH"},
+	{I40E_GLSW_BPTCL(0), I40E_GLSW_BPTCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_BPTCL"},
+	{I40E_GLSW_BPTCH(0), I40E_GLSW_BPTCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_BPTCH"},
+	{I40E_GLV_TEPC(0), I40E_GLV_TEPC_MAX_INDEX + 1, 4, "I40E_GLV_TEPC"},
+	{I40E_GL_FCOEPTC(0), I40E_GL_FCOEPTC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEPTC"},
+	{I40E_GLSW_TDPC(0), I40E_GLSW_TDPC_MAX_INDEX + 1, 4, "I40E_GLSW_TDPC"},
+	{I40E_GL_FCOEDWTCL(0), I40E_GL_FCOEDWTCL_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDWTCL"},
+	{I40E_GL_FCOEDWTCH(0), I40E_GL_FCOEDWTCH_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDWTCH"},
+	{I40E_GL_FCOEDIXEC(0), I40E_GL_FCOEDIXEC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDIXEC"},
+	{I40E_GL_FCOEDIXVC(0), I40E_GL_FCOEDIXVC_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDIXVC"},
+	{I40E_GL_FCOEDIFTCL(0), I40E_GL_FCOEDIFTCL_MAX_INDEX + 1, 4,
+	 "I40E_GL_FCOEDIFTCL"},
+	{I40E_GLV_GORCL(0), I40E_GLV_GORCL_MAX_INDEX + 1, 4, "I40E_GLV_GORCL"},
+	{I40E_GLV_GORCH(0), I40E_GLV_GORCH_MAX_INDEX + 1, 4, "I40E_GLV_GORCH"},
+	{I40E_GLSW_GORCL(0), I40E_GLSW_GORCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_GORCL"},
+	{I40E_GLSW_GORCH(0), I40E_GLSW_GORCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_GORCH"},
+	{I40E_GLVEBVL_GORCL(0), I40E_GLVEBVL_GORCL_MAX_INDEX + 1, 4,
+	 "I40E_GLVEBVL_GORCL"},
+	{I40E_GLVEBVL_GORCH(0), I40E_GLVEBVL_GORCH_MAX_INDEX + 1, 4,
+	 "I40E_GLVEBVL_GORCH"},
+	{I40E_GLVEBTC_RBCL(0, 0), 64 * 16, 4, "I40E_GLVEBTC_RBCL"},
+	{I40E_GLVEBTC_RBCH(0, 0), 64 * 16, 4, "I40E_GLVEBTC_RBCH"},
+	{I40E_GLVEBTC_RPCL(0, 0), 64 * 16, 4, "I40E_GLVEBTC_RPCL"},
+	{I40E_GLVEBTC_RPCH(0, 0), 64 * 16, 4, "I40E_GLVEBTC_RPCH"},
+	{I40E_GLV_UPRCL(0), I40E_GLV_UPRCL_MAX_INDEX + 1, 4, "I40E_GLV_UPRCL"},
+	{I40E_GLV_UPRCH(0), I40E_GLV_UPRCH_MAX_INDEX + 1, 4, "I40E_GLV_UPRCH"},
+	{I40E_GLV_MPRCL(0), I40E_GLV_MPRCL_MAX_INDEX + 1, 4, "I40E_GLV_MPRCL"},
+	{I40E_GLV_MPRCH(0), I40E_GLV_MPRCH_MAX_INDEX + 1, 4, "I40E_GLV_MPRCH"},
+	{I40E_GLV_BPRCL(0), I40E_GLV_BPRCL_MAX_INDEX + 1, 4, "I40E_GLV_BPRCL"},
+	{I40E_GLV_BPRCH(0), I40E_GLV_BPRCH_MAX_INDEX + 1, 4, "I40E_GLV_BPRCH"},
+	{I40E_GLV_RUPP(0), I40E_GLV_RUPP_MAX_INDEX + 1, 4, "I40E_GLV_RUPP"},
+	{I40E_GLSW_UPRCL(0), I40E_GLSW_UPRCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_UPRCL"},
+	{I40E_GLSW_UPRCH(0), I40E_GLSW_UPRCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_UPRCH"},
+	{I40E_GLSW_MPRCL(0), I40E_GLSW_MPRCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_MPRCL"},
+	{I40E_GLSW_MPRCH(0), I40E_GLSW_MPRCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_MPRCH"},
+	{I40E_GLSW_BPRCL(0), I40E_GLSW_BPRCL_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_BPRCL"},
+	{I40E_GLSW_BPRCH(0), I40E_GLSW_BPRCH_MAX_INDEX + 1, 4,
+	 "I40E_GLSW_BPRCH"},
+	{I40E_GLSW_RUPP(0), I40E_GLSW_RUPP_MAX_INDEX + 1, 4, "I40E_GLSW_RUPP"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_lantxrx[] = {
+	{I40E_GLLAN_TSOMSK_F, 1, 4, "I40E_GLLAN_TSOMSK_F"},
+	{I40E_GLLAN_TSOMSK_L, 1, 4, "I40E_GLLAN_TSOMSK_L"},
+	{I40E_GLLAN_TSOMSK_M, 1, 4, "I40E_GLLAN_TSOMSK_M"},
+	{I40E_GL_RDPU_CNTRL, 1, 4, "I40E_GL_RDPU_CNTRL"},
+	{I40E_VPLAN_QTABLE(0, 0), 1024 * 16, 4, "I40E_VPLAN_QTABLE"},
+	{I40E_VPLAN_MAPENA(0), I40E_VPLAN_MAPENA_MAX_INDEX + 1, 4,
+		"I40E_VPLAN_MAPENA"},
+	{I40E_QTX_HEAD(0), I40E_QTX_HEAD_MAX_INDEX + 1, 4, "I40E_QTX_HEAD"},
+	{I40E_GLLAN_TXPRE_QDIS(0), I40E_GLLAN_TXPRE_QDIS_MAX_INDEX + 1, 4,
+		"I40E_GLLAN_TXPRE_QDIS"},
+	{I40E_QTX_ENA(0), I40E_QTX_ENA_MAX_INDEX + 1, 4, "I40E_QTX_ENA"},
+	{I40E_QTX_CTL(0), I40E_QTX_CTL_MAX_INDEX + 1, 4, "I40E_QTX_CTL"},
+	{I40E_QTX_TAIL(0), I40E_QTX_TAIL_MAX_INDEX + 1, 4, "I40E_QTX_TAIL"},
+	{I40E_QRX_ENA(0), I40E_QRX_ENA_MAX_INDEX + 1, 4, "I40E_QRX_ENA"},
+	{I40E_QRX_TAIL(0), I40E_QRX_TAIL_MAX_INDEX + 1, 4, "I40E_QRX_TAIL"},
+	{I40E_GLLAN_RCTL_0, 1, 4, "I40E_GLLAN_RCTL_0"},
+	{I40E_PFLAN_QALLOC, 1, 4, "I40E_PFLAN_QALLOC"},
+	{I40E_VSILAN_QTABLE(0, 0), 2048 * 8, 4, "I40E_VSILAN_QTABLE"},
+	{I40E_VSILAN_QBASE(0), I40E_VSILAN_QBASE_MAX_INDEX + 1, 4,
+		"I40E_VSILAN_QBASE"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_rxfilter[] = {
+	{I40E_VPQF_CTL(0), I40E_VPQF_CTL_MAX_INDEX + 1, 4, "I40E_VPQF_CTL"},
+	{I40E_PFQF_CTL_0, 1, 4, "I40E_PFQF_CTL_0"},
+	{I40E_PRTQF_FD_MSK(0, 0), 0x40 * 64, 4, "I40E_PRTQF_FD_MSK"},
+	{I40E_VSIQF_TCREGION(0, 0), 2048 * 4, 4, "I40E_VSIQF_TCREGION"},
+	{I40E_VSIQF_CTL(0), I40E_VSIQF_CTL_MAX_INDEX + 1, 4, "I40E_VSIQF_CTL"},
+	{I40E_VFQF_HLUT(0), I40E_VFQF_HLUT_MAX_INDEX + 1, 4, "I40E_VFQF_HLUT"},
+	{I40E_VFQF_HKEY(0), I40E_VFQF_HKEY_MAX_INDEX + 1, 4, "I40E_VFQF_HKEY"},
+	{I40E_VFQF_HREGION(0), I40E_VFQF_HREGION_MAX_INDEX + 1, 4,
+	 "I40E_VFQF_HREGION"},
+	{I40E_VFQF_HENA(0), I40E_VFQF_HENA_MAX_INDEX + 1, 4, "I40E_VFQF_HENA"},
+	{I40E_PFQF_HLUT(0), I40E_PFQF_HLUT_MAX_INDEX + 1, 4, "I40E_PFQF_HLUT"},
+	{I40E_PFQF_HKEY(0), I40E_PFQF_HKEY_MAX_INDEX + 1, 4, "I40E_PFQF_HKEY"},
+	{I40E_PFQF_HENA(0), I40E_PFQF_HENA_MAX_INDEX + 1, 4, "I40E_PFQF_HENA"},
+	{I40E_PFQF_CTL_1, 1, 4, "I40E_PFQF_CTL_1"},
+	{I40E_PFQF_FDALLOC, 1, 4, "I40E_PFQF_FDALLOC"},
+	{I40E_PFQF_FDSTAT, 1, 4, "I40E_PFQF_FDSTAT"},
+	{I40E_PRTQF_FD_FLXINSET(0), I40E_PRTQF_FD_FLXINSET_MAX_INDEX + 1, 4,
+	 "I40E_PRTQF_FD_FLXINSET"},
+	{I40E_PRTQF_FLX_PIT(0), I40E_PRTQF_FLX_PIT_MAX_INDEX + 1, 4,
+	 "I40E_PRTQF_FLX_PIT"},
+	{I40E_PRTQF_CTL_0, 1, 4, "I40E_PRTQF_CTL_0"},
+	{I40E_GLQF_PCNT(0), I40E_GLQF_PCNT_MAX_INDEX + 1, 4, "I40E_GLQF_PCNT"},
+	{I40E_GLQF_SWAP(0, 0), 64 * 8, 4, "I40E_GLQF_SWAP"},
+	{I40E_GLQF_CTL, 1, 4, "I40E_GLQF_CTL"},
+	{I40E_GLQF_FDCNT_0, 1, 4, "I40E_GLQF_FDCNT_0"},
+	{I40E_GLQF_HSYM(0), I40E_GLQF_HSYM_MAX_INDEX + 1, 4, "I40E_GLQF_HSYM"},
+	{I40E_GLQF_HKEY(0), I40E_GLQF_HKEY_MAX_INDEX + 1, 4, "I40E_GLQF_HKEY"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_ieee1588[] = {
+	{I40E_PRTTSYN_CTL1, 1, 4, "I40E_PRTTSYN_CTL1"},
+	{I40E_PRTTSYN_RXTIME_L(0), I40E_PRTTSYN_RXTIME_L_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_RXTIME_L"},
+	{I40E_PRTTSYN_RXTIME_H(0), I40E_PRTTSYN_RXTIME_H_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_RXTIME_H"},
+	{I40E_PRTTSYN_STAT_1, 1, 4, "I40E_PRTTSYN_STAT_1"},
+	{I40E_PRTTSYN_INC_L, 1, 4, "I40E_PRTTSYN_INC_L"},
+	{I40E_PRTTSYN_INC_H, 1, 4, "I40E_PRTTSYN_INC_H"},
+	{I40E_PRTTSYN_EVNT_L(0), I40E_PRTTSYN_EVNT_L_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_EVNT_L"},
+	{I40E_PRTTSYN_EVNT_H(0), I40E_PRTTSYN_EVNT_H_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_EVNT_H"},
+	{I40E_PRTTSYN_TIME_L, 1, 4, "I40E_PRTTSYN_TIME_L"},
+	{I40E_PRTTSYN_TIME_H, 1, 4, "I40E_PRTTSYN_TIME_H"},
+	{I40E_PRTTSYN_TGT_L(0), I40E_PRTTSYN_TGT_L_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_TGT_L"},
+	{I40E_PRTTSYN_TGT_H(0), I40E_PRTTSYN_TGT_H_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_TGT_H"},
+	{I40E_PRTTSYN_TXTIME_L, 1, 4, "I40E_PRTTSYN_TXTIME_L"},
+	{I40E_PRTTSYN_TXTIME_H, 1, 4, "I40E_PRTTSYN_TXTIME_H"},
+	{I40E_PRTTSYN_CTL0, 1, 4, "I40E_PRTTSYN_CTL0"},
+	{I40E_PRTTSYN_STAT_0, 1, 4, "I40E_PRTTSYN_STAT_0"},
+	{I40E_PRTTSYN_CLKO(0), I40E_PRTTSYN_CLKO_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_CLKO"},
+	{I40E_PRTTSYN_ADJ, 1, 4, "I40E_PRTTSYN_ADJ"},
+	{I40E_PRTTSYN_AUX_0(0), I40E_PRTTSYN_AUX_0_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_AUX_0"},
+	{I40E_PRTTSYN_AUX_1(0), I40E_PRTTSYN_AUX_1_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_AUX_1"},
+	{I40E_PRTTSYN_ADJ, 1, 4, "I40E_PRTTSYN_ADJ"},
+	{I40E_PRTTSYN_AUX_0(0), I40E_PRTTSYN_AUX_0_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_AUX_0"},
+	{I40E_PRTTSYN_AUX_1(0), I40E_PRTTSYN_AUX_1_MAX_INDEX + 1, 4,
+	 "I40E_PRTTSYN_AUX_1"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_fcoe[] = {
+	{I40E_GLFCOE_RCTL, 1, 4, "I40E_GLFCOE_RCTL"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info i40e_regs_pf_manage[] = {
+	{I40E_GL_FWRESETCNT, 1, 4, "I40E_GL_FWRESETCNT"},
+	{I40E_PRT_MNG_FTFT_MASK(0), I40E_PRT_MNG_FTFT_MASK_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_FTFT_MASK"},
+	{I40E_PRT_MNG_FTFT_LENGTH, 1, 4, "I40E_PRT_MNG_FTFT_LENGTH"},
+	{I40E_PRT_MNG_FTFT_DATA(0), I40E_PRT_MNG_FTFT_DATA_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_FTFT_DATA"},
+	{I40E_GL_MNG_HWARB_CTRL, 1, 4, "I40E_GL_MNG_HWARB_CTRL"},
+	{I40E_GL_MNG_FWSM, 1, 4, "I40E_GL_MNG_FWSM"},
+	{I40E_PRT_MNG_MIPAF6(0), I40E_PRT_MNG_MIPAF6_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MIPAF6"},
+	{I40E_PRT_MNG_MFUTP(0), I40E_PRT_MNG_MFUTP_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MFUTP"},
+	{I40E_PRT_MNG_MAVTV(0), I40E_PRT_MNG_MAVTV_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MAVTV"},
+	{I40E_PRT_MNG_MDEF(0), I40E_PRT_MNG_MDEF_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MDEF"},
+	{I40E_PRT_MNG_MDEF_EXT(0), I40E_PRT_MNG_MDEF_EXT_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MDEF_EXT"},
+	{I40E_PRT_MNG_MIPAF4(0), I40E_PRT_MNG_MIPAF4_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MIPAF4"},
+	{I40E_PRT_MNG_MMAL(0), I40E_PRT_MNG_MMAL_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MMAL"},
+	{I40E_PRT_MNG_MMAH(0), I40E_PRT_MNG_MMAH_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MMAH"},
+	{I40E_PRT_MNG_MDEFVSI(0), I40E_PRT_MNG_MDEFVSI_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_MDEFVSI"},
+	{I40E_PRT_MNG_METF(0), I40E_PRT_MNG_METF_MAX_INDEX + 1, 4,
+	 "I40E_PRT_MNG_METF"},
+	{I40E_PRT_MNG_MANC, 1, 4, "I40E_PRT_MNG_MANC"},
+	{I40E_PRT_MNG_MNGONLY, 1, 4, "I40E_PRT_MNG_MNGONLY"},
+	{I40E_PRT_MNG_MSFM, 1, 4, "I40E_PRT_MNG_MSFM"},
+	{0, 0, 0, NULL}
+};
+
+static const struct reg_info *i40e_regs[] = {
+	i40e_regs_pf_gen,
+	i40e_regs_pf_pci,
+	i40e_regs_pf_mac,
+	i40e_regs_pf_power,
+	i40e_regs_pf_wakeandproxy,
+	i40e_regs_pf_nvm,
+	i40e_regs_pf_analyzer,
+	i40e_regs_pf_switch,
+	i40e_regs_pf_interrupt,
+	i40e_regs_pf_virtualpf,
+	i40e_regs_pf_dcb,
+	i40e_regs_pf_rxbuf,
+	i40e_regs_pf_hostcache,
+	i40e_regs_pf_context,
+	i40e_regs_pf_adminq,
+	i40e_regs_pf_stats,
+	i40e_regs_pf_lantxrx,
+	i40e_regs_pf_rxfilter,
+	i40e_regs_pf_ieee1588,
+	i40e_regs_pf_fcoe,
+	i40e_regs_pf_manage,
+	NULL
+};
+
+#endif /* _IX40E_REGS_H_ */
-- 
2.5.0