From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by dpdk.org (Postfix) with ESMTP id 9E3D195C8 for ; Wed, 3 Feb 2016 00:11:43 +0100 (CET) Received: by mail-wm0-f49.google.com with SMTP id 128so140825966wmz.1 for ; Tue, 02 Feb 2016 15:11:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K2G1KBEtHbPIaQJSxN+PzkGM9i05nBUtqYr5G+2Vwl4=; b=gHyFXcWIfj48fU8x6Do756P2kbiBKzyU3Noe1VEqTYllMSvvPjR13cvmufECdTXEeu MyiDGFCTMts1UksCg8YWeD0F9fNDPbITaebOJHVfV7TKyU9HN30cFRlFoTrxTP+9jyHS Ja7OLUfwi+ilH6Z4m65fe3/tVrpb/iCcCOth8FXTrUTrIeZGmFF7OajZ9tBLjbg/dOay eVWkBaEZwrLsr/knFMYE4IjdLWgX9xHwC4Q7UXyJh6BkXrqq/moAKiYRaUrswLl7VVN+ KKoUE88MMN343B2ZI1bo32nGbjU1z/VatJt4c1ssoS9lyqELIAQ1+jHVjOTz0AqWibYo O1Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K2G1KBEtHbPIaQJSxN+PzkGM9i05nBUtqYr5G+2Vwl4=; b=jKgobs9L7AAsGZRyiupo5+lBSOS8wW7FZNLhhvknTVMvcnp4LhKUEIQkxPabfuy9AO 0cczvXnzCSoYXOTuAvMgi5iKK8iWeRzciqe7RYk3yeJj6rN60Hqo4VAacgTIGgPOCFNL BBUI3172tuAIfG/yyZ6ItEOogmP93HibuSf11UTxDgmXzpJPXA5zVGZJW0aVILl5EhUa gTla5iCpG4U+tyNi1SaobeUQvgy3bY8v52Jgu320/sflzgimv0S2MnHsbIO6VZdE9Tk8 FKdB3xiFqCPTu6Ff8gOCXwpH5NYcC5484Pl/5KExxmeahSSyuNh3JvcFkaCjyoVVOaD3 T1Iw== X-Gm-Message-State: AG10YOTWMP5550iCpDz0L3tn0Bz/piVwjo5ToQ8aS3fEzbqzhcjh3fSoL5MPHTp57uwTgcxK X-Received: by 10.194.57.100 with SMTP id h4mr36680161wjq.21.1454454703468; Tue, 02 Feb 2016 15:11:43 -0800 (PST) Received: from localhost.localdomain (136-92-190-109.dsl.ovh.fr. [109.190.92.136]) by smtp.gmail.com with ESMTPSA id lw7sm3588848wjb.19.2016.02.02.15.11.42 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Feb 2016 15:11:42 -0800 (PST) From: Thomas Monjalon To: david.marchand@6wind.com, ferruh.yigit@intel.com Date: Wed, 3 Feb 2016 00:10:24 +0100 Message-Id: <1454454626-4483-2-git-send-email-thomas.monjalon@6wind.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454453993-3903-1-git-send-email-thomas.monjalon@6wind.com> References: <1454453993-3903-1-git-send-email-thomas.monjalon@6wind.com> Cc: dev@dpdk.org, viktorin@rehivetech.com Subject: [dpdk-dev] [PATCH v1 3/5] eal/arm: adapt CPU flags check to the arch X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Feb 2016 23:11:43 -0000 The structure feature_entry does not need leaf/subleaf which were copied from x86 CPUID implementation. On x86, a valid flag is detected with the non-zero leaf value. This check is replaced by a check with a dummy "none" register. Signed-off-by: Thomas Monjalon --- lib/librte_eal/common/arch/arm/rte_cpuflags.c | 110 ++++++++++++-------------- 1 file changed, 50 insertions(+), 60 deletions(-) diff --git a/lib/librte_eal/common/arch/arm/rte_cpuflags.c b/lib/librte_eal/common/arch/arm/rte_cpuflags.c index 664f527..fba0a61 100644 --- a/lib/librte_eal/common/arch/arm/rte_cpuflags.c +++ b/lib/librte_eal/common/arch/arm/rte_cpuflags.c @@ -52,69 +52,66 @@ #endif enum cpu_register_t { - REG_HWCAP = 0, + REG_NONE = 0, + REG_HWCAP, REG_HWCAP2, + REG_MAX }; -typedef uint32_t cpuid_registers_t[4]; +typedef uint32_t hwcap_registers_t[REG_MAX]; -/** - * Struct to hold a processor feature entry - */ struct feature_entry { - uint32_t leaf; /**< cpuid leaf */ - uint32_t subleaf; /**< cpuid subleaf */ - uint32_t reg; /**< cpuid register */ - uint32_t bit; /**< cpuid register bit */ + uint32_t reg; + uint32_t bit; #define CPU_FLAG_NAME_MAX_LEN 64 - char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */ + char name[CPU_FLAG_NAME_MAX_LEN]; }; -#define FEAT_DEF(name, leaf, subleaf, reg, bit) \ - [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name }, +#define FEAT_DEF(name, reg, bit) \ + [RTE_CPUFLAG_##name] = {reg, bit, #name}, #ifdef RTE_ARCH_64 const struct feature_entry rte_cpu_feature_table[] = { - FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP, 0) - FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 1) - FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 2) - FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP, 3) - FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP, 4) - FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP, 5) - FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP, 6) - FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP, 7) - FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1) + FEAT_DEF(FP, REG_HWCAP, 0) + FEAT_DEF(NEON, REG_HWCAP, 1) + FEAT_DEF(EVTSTRM, REG_HWCAP, 2) + FEAT_DEF(AES, REG_HWCAP, 3) + FEAT_DEF(PMULL, REG_HWCAP, 4) + FEAT_DEF(SHA1, REG_HWCAP, 5) + FEAT_DEF(SHA2, REG_HWCAP, 6) + FEAT_DEF(CRC32, REG_HWCAP, 7) + FEAT_DEF(AARCH64, REG_PLATFORM, 1) }; #else const struct feature_entry rte_cpu_feature_table[] = { - FEAT_DEF(SWP, 0x00000001, 0, REG_HWCAP, 0) - FEAT_DEF(HALF, 0x00000001, 0, REG_HWCAP, 1) - FEAT_DEF(THUMB, 0x00000001, 0, REG_HWCAP, 2) - FEAT_DEF(A26BIT, 0x00000001, 0, REG_HWCAP, 3) - FEAT_DEF(FAST_MULT, 0x00000001, 0, REG_HWCAP, 4) - FEAT_DEF(FPA, 0x00000001, 0, REG_HWCAP, 5) - FEAT_DEF(VFP, 0x00000001, 0, REG_HWCAP, 6) - FEAT_DEF(EDSP, 0x00000001, 0, REG_HWCAP, 7) - FEAT_DEF(JAVA, 0x00000001, 0, REG_HWCAP, 8) - FEAT_DEF(IWMMXT, 0x00000001, 0, REG_HWCAP, 9) - FEAT_DEF(CRUNCH, 0x00000001, 0, REG_HWCAP, 10) - FEAT_DEF(THUMBEE, 0x00000001, 0, REG_HWCAP, 11) - FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 12) - FEAT_DEF(VFPv3, 0x00000001, 0, REG_HWCAP, 13) - FEAT_DEF(VFPv3D16, 0x00000001, 0, REG_HWCAP, 14) - FEAT_DEF(TLS, 0x00000001, 0, REG_HWCAP, 15) - FEAT_DEF(VFPv4, 0x00000001, 0, REG_HWCAP, 16) - FEAT_DEF(IDIVA, 0x00000001, 0, REG_HWCAP, 17) - FEAT_DEF(IDIVT, 0x00000001, 0, REG_HWCAP, 18) - FEAT_DEF(VFPD32, 0x00000001, 0, REG_HWCAP, 19) - FEAT_DEF(LPAE, 0x00000001, 0, REG_HWCAP, 20) - FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 21) - FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP2, 0) - FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP2, 1) - FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2) - FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3) - FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4) - FEAT_DEF(V7L, 0x00000001, 0, REG_PLATFORM, 0) + FEAT_DEF(SWP, REG_HWCAP, 0) + FEAT_DEF(HALF, REG_HWCAP, 1) + FEAT_DEF(THUMB, REG_HWCAP, 2) + FEAT_DEF(A26BIT, REG_HWCAP, 3) + FEAT_DEF(FAST_MULT, REG_HWCAP, 4) + FEAT_DEF(FPA, REG_HWCAP, 5) + FEAT_DEF(VFP, REG_HWCAP, 6) + FEAT_DEF(EDSP, REG_HWCAP, 7) + FEAT_DEF(JAVA, REG_HWCAP, 8) + FEAT_DEF(IWMMXT, REG_HWCAP, 9) + FEAT_DEF(CRUNCH, REG_HWCAP, 10) + FEAT_DEF(THUMBEE, REG_HWCAP, 11) + FEAT_DEF(NEON, REG_HWCAP, 12) + FEAT_DEF(VFPv3, REG_HWCAP, 13) + FEAT_DEF(VFPv3D16, REG_HWCAP, 14) + FEAT_DEF(TLS, REG_HWCAP, 15) + FEAT_DEF(VFPv4, REG_HWCAP, 16) + FEAT_DEF(IDIVA, REG_HWCAP, 17) + FEAT_DEF(IDIVT, REG_HWCAP, 18) + FEAT_DEF(VFPD32, REG_HWCAP, 19) + FEAT_DEF(LPAE, REG_HWCAP, 20) + FEAT_DEF(EVTSTRM, REG_HWCAP, 21) + FEAT_DEF(AES, REG_HWCAP2, 0) + FEAT_DEF(PMULL, REG_HWCAP2, 1) + FEAT_DEF(SHA1, REG_HWCAP2, 2) + FEAT_DEF(SHA2, REG_HWCAP2, 3) + FEAT_DEF(CRC32, REG_HWCAP2, 4) + FEAT_DEF(V7L, REG_PLATFORM, 0) }; #endif @@ -122,8 +119,7 @@ const struct feature_entry rte_cpu_feature_table[] = { * Read AUXV software register and get cpu features for ARM */ static void -rte_cpu_get_features(__attribute__((unused)) uint32_t leaf, - __attribute__((unused)) uint32_t subleaf, cpuid_registers_t out) +rte_cpu_get_features(hwcap_registers_t out) { int auxv_fd; #ifdef RTE_ARCH_64 @@ -157,22 +153,16 @@ int rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) { const struct feature_entry *feat; - cpuid_registers_t regs = {0}; + hwcap_registers_t regs = {0}; if (feature >= RTE_CPUFLAG_NUMFLAGS) - /* Flag does not match anything in the feature tables */ return -ENOENT; feat = &rte_cpu_feature_table[feature]; - - if (!feat->leaf) - /* This entry in the table wasn't filled out! */ + if (feat->reg == REG_NONE) return -EFAULT; - /* get the cpuid leaf containing the desired feature */ - rte_cpu_get_features(feat->leaf, feat->subleaf, regs); - - /* check if the feature is enabled */ + rte_cpu_get_features(regs); return (regs[feat->reg] >> feat->bit) & 1; } -- 2.7.0