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DB5PR02MB1013; 5:RWlET4sTmWVjeydzD/Hmhcg2d701uEm9t2VwbQCQ2lRXnToEdH+A+UFBJ5kBc+tkjHwaJL8oM5TuUsGsEGD1LXnhjhw+re1eEdin7oj6FzQJ1ErON50iFZ6eE/gqnXVRyC1ySihbF08WanGiJfZmiA==; 24:quSiuYXtkCtCbBstVFrcMi4OR8+RZ4+7BszhluW3C8ihUe/SsEGPaGsGuq0lvJpe/5CyIK7uvT3QmL/toA+nMWDVLN8bLFyFY6UP7U0VL9w= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: ezchip.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2016 04:04:33.9454 (UTC) X-MS-Exchange-CrossTenant-Id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3; Ip=[12.216.194.146]; Helo=[lab-14.internal.tilera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR02MB1013 Subject: [dpdk-dev] [PATCH v4 1/2] eal/tile: add rte_vect.h and enable CONFIG_RTE_LIBRTE_LPM X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Feb 2016 04:04:36 -0000 rte_vect.h was missing earlier thus LPM was disabled and l3fwd is not able to compile. This commit implements the vector api and enable LPM in the tilegx configuration by default. Signed-off-by: Liming Sun Acked-by: Zhigang Lu --- config/defconfig_tile-tilegx-linuxapp-gcc | 2 +- lib/librte_eal/common/include/arch/tile/rte_vect.h | 93 ++++++++++++++++++++++ 2 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 lib/librte_eal/common/include/arch/tile/rte_vect.h diff --git a/config/defconfig_tile-tilegx-linuxapp-gcc b/config/defconfig_tile-tilegx-linuxapp-gcc index fb61bcd..39794f6 100644 --- a/config/defconfig_tile-tilegx-linuxapp-gcc +++ b/config/defconfig_tile-tilegx-linuxapp-gcc @@ -64,7 +64,7 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n # This following libraries are not available on the tile architecture. # So they're turned off. -CONFIG_RTE_LIBRTE_LPM=n +CONFIG_RTE_LIBRTE_LPM=y CONFIG_RTE_LIBRTE_ACL=n CONFIG_RTE_LIBRTE_SCHED=n CONFIG_RTE_LIBRTE_PORT=n diff --git a/lib/librte_eal/common/include/arch/tile/rte_vect.h b/lib/librte_eal/common/include/arch/tile/rte_vect.h new file mode 100644 index 0000000..9afee70 --- /dev/null +++ b/lib/librte_eal/common/include/arch/tile/rte_vect.h @@ -0,0 +1,93 @@ +/* + * BSD LICENSE + * + * Copyright (C) EZchip Semiconductor Ltd. 2016. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of EZchip Semiconductor nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _RTE_VECT_H_ +#define _RTE_VECT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef __int128 __m128i; + +#define XMM_SIZE sizeof(__m128i) +#define XMM_MASK (XMM_SIZE - 1) + +typedef union rte_xmm { + __m128i x; + uint32_t u32[XMM_SIZE / sizeof(uint32_t)]; + uint64_t u64[XMM_SIZE / sizeof(uint64_t)]; +} rte_xmm_t; + +/* Extracts the low order 64-bit integer. */ +#define _mm_cvtsi128_si64(a) ((rte_xmm_t*)&a)->u64[0] + +/* Sets the 2 signed 64-bit integer values. */ +#define _mm_set_epi64x(i1, i0) ({ \ + rte_xmm_t m; \ + m.u64[0] = i0; \ + m.u64[1] = i1; \ + (m.x); \ +}) + +/* Sets the 4 signed 32-bit integer values. */ +#define _mm_set_epi32(i3, i2, i1, i0) ({ \ + rte_xmm_t m; \ + m.u32[0] = i0; \ + m.u32[1] = i1; \ + m.u32[2] = i2; \ + m.u32[3] = i3; \ + (m.x); \ +}) + +/* Shifts right the 4 32-bit integers by count bits with zeros. */ +#define _mm_srli_epi32(v, cnt) ({ \ + rte_xmm_t m; \ + m.u64[0] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[0], cnt); \ + m.u64[1] = __insn_v4shru(((rte_xmm_t*)&(v))->u64[1], cnt); \ + (m.x); \ +}) + +/* Shifts the 128-bit value in a right by imm bytes. */ +#define _mm_srli_si128(v, imm) ((v) >> (imm * sizeof(uint8_t))) + +/* Bitwise AND of the 128-bit value in a and the 128-bit value in b. */ +#define _mm_and_si128(a, b) ((a) & (b)) + +/* Loads 128-bit value. */ +#define _mm_loadu_si128(p) (*(p)) + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_VECT_H_ */ -- 1.8.3.1