From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 0560AC11C for ; Tue, 16 Feb 2016 09:21:09 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 16 Feb 2016 00:21:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,454,1449561600"; d="scan'208";a="915820065" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 16 Feb 2016 00:21:09 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u1G8L7A4004273; Tue, 16 Feb 2016 16:21:07 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u1G8L3pB028122; Tue, 16 Feb 2016 16:21:05 +0800 Received: (from wenzhuol@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u1G8L3FK028118; Tue, 16 Feb 2016 16:21:03 +0800 From: Wenzhuo Lu To: dev@dpdk.org Date: Tue, 16 Feb 2016 16:20:53 +0800 Message-Id: <1455610859-28079-2-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1455610859-28079-1-git-send-email-wenzhuo.lu@intel.com> References: <1454051035-25757-1-git-send-email-wenzhuo.lu@intel.com> <1455610859-28079-1-git-send-email-wenzhuo.lu@intel.com> Subject: [dpdk-dev] [PATCH v3 1/7] ixgbe: select pool by MAC when using double VLAN X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Feb 2016 08:21:10 -0000 On X550, as required by datasheet, E-tag packets are not expected when double VLAN are used. So modify the register PFVTCTL after enabling double VLAN to select pool by MAC but not MAC or E-tag. An introduction of E-tag: It's defined in IEEE802.1br. Please reference this website, http://www.ieee802.org/1/pages/802.1br.html. A brief description. E-tag means external tag, and it's a kind of l2 tunnel. It means a tag will be inserted in the l2 header. Like below, |31 24|23 16|15 8|7 0| 0| Destination MAC address | 4| Dest MAC address(cont.) | Src MAC address | 8| Source MAC address(cont.) | 12| E-tag Etherenet type (0x893f) | E-tag header | 16| E-tag header(cont.) | 20| VLAN Ethertype(optional) | VLAN header(optional) | 24| Original type | ...... | ...| ...... | The E-tag format is like below, |0 15|16 18|19 |20 31| | Ethertype - 0x893f | E-PCP |DEI| Ingress E-CID_base | |32 33|34 35|36 47|48 55 |56 63| | RSV | GRP |E-CID_base|Ingress_E-CID_ext| E-CID_ext | The Ingess_E-CID_ext and E-CID_ext are always zero for endpoints and are effectively reserved. The more details of E-tag is in IEEE 802.1BR. 802.1BR is used to replace 802.1Qbh. 802.1BR is a standard for Bridge Port Extension. It specifies the operation of Bridge Port Extenders, including management, protocols, and algorithms. Bridge Port Extenders operate in support of the MAC Service by Extended Bridges. The E-tag is added to l2 header to identify the VM channel and the virtual port. Signed-off-by: Wenzhuo Lu --- drivers/net/ixgbe/ixgbe_ethdev.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 4c4c6df..83df0c0 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -138,6 +138,8 @@ #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL +#define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 + static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev); static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); static int ixgbe_dev_configure(struct rte_eth_dev *dev); @@ -1725,6 +1727,14 @@ ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) ctrl |= IXGBE_EXTENDED_VLAN; IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); + /* Clear pooling mode of PFVTCTL. It's required by X550. */ + if (hw->mac.type == ixgbe_mac_X550 || + hw->mac.type == ixgbe_mac_X550EM_x) { + ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); + ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; + IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); + } + /* * VET EXT field in the EXVET register = 0x8100 by default * So no need to change. Same to VT field of DMATXCTL register -- 1.9.3