From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f169.google.com (mail-pf0-f169.google.com [209.85.192.169]) by dpdk.org (Postfix) with ESMTP id 10654C5A0 for ; Sun, 21 Feb 2016 15:18:31 +0100 (CET) Received: by mail-pf0-f169.google.com with SMTP id q63so77892537pfb.0 for ; Sun, 21 Feb 2016 06:18:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mvista-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9UmI7NNrd643N06jXuPbOepN+3CFrgTDxUZfhcW3M9U=; b=XyUFprlrQIrOwiWolIbqc/cGcJtwTVpA/YvXFjkCDWtOMy0I4gDONB9jWftL7NG4go IcuVljCc0su/5vmXctvEEOTcOMkzmCJzQ2/nZI0iyoc25+R2m7DNQDpfeTXGfZATOS3S 9lPfvakC7OeIndSTHveuQfH3LPCtI/g6XWLUWQM882IehpFT1mz1OdZgNDdSvxQAWe7D IucOrMYz8OX/SP+KwsfJhigt1VMsJefjpMW7RQZbB7NJXKacC46PySUdWzt1rdQj/nhl 64N3Cpu0t5g4b4xM2KD/1GgVrk46A3K+XGPwPS5r6fLLggbQ2DucXr2+VQEJCayr30hO qyCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9UmI7NNrd643N06jXuPbOepN+3CFrgTDxUZfhcW3M9U=; b=Pi1d+KJ2ZRxx2sZB6cDXvpqyGjLfhFD9KUKRTt4PnWsOd7JZ/GGrNG8Jkh/IE63ROV BCniJiucmdekcQKIHz6mL6OyoB16IMDc/7mv6ZzAgdDIaKXhqY/zfI8cpM6rwi3qnKDu sIFTl33jV1haWWRo9+i+szY1SVLHBkzBtUp2LD57gjb7VZ3XMppuGR5CiSr/DRm4+6oL ukvkuBk37aRLlenV52Hij5994Kx7XVr7IiEEX7JQTr1mptoLHu84FgrZnpN2Ipm1c8wd rpKLYwd7RXehx9kOMb1BW/iicSdgk0ZHkVTL9uDyL/yhlfNEZJChTw/wJ1F7Zw1s5oSI nKsw== X-Gm-Message-State: AG10YOSlFmkKfJAzDY/f0nZ3ta47BqeI2+ijaFwV71vwW+0XuDytNnc4j5+w5MytMuBGvvvm X-Received: by 10.98.66.75 with SMTP id p72mr31821740pfa.50.1456064310488; Sun, 21 Feb 2016 06:18:30 -0800 (PST) Received: from localhost.localdomain ([106.216.140.39]) by smtp.gmail.com with ESMTPSA id 3sm30255392pfn.59.2016.02.21.06.18.26 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 Feb 2016 06:18:29 -0800 (PST) From: Santosh Shukla To: dev@dpdk.org Date: Sun, 21 Feb 2016 19:48:01 +0530 Message-Id: <1456064281-4606-4-git-send-email-sshukla@mvista.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1456064281-4606-1-git-send-email-sshukla@mvista.com> References: <1454853068-14621-1-git-send-email-sshukla@mvista.com> <1456064281-4606-1-git-send-email-sshukla@mvista.com> Subject: [dpdk-dev] [PATCH v9 3/3] eal/linux: vfio: add pci ioport support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Feb 2016 14:18:31 -0000 Include vfio map/rd/wr support for pci ioport. Signed-off-by: Santosh Shukla Acked-by: Anatoly Burakov Acked-by: David Marchand --- v7: - This is enhancement patch for vfio map/rd/wr, rebased on top of David(s) - "Rework ioport for virtio" patchset. For more information about api, refer patch [1]. [1] http://dpdk.org/dev/patchwork/patch/10426/ v8: - Remove rte_pci_ioport malloc and rte_free()/unmap() func from v7. - removed umap from git header. v9: - renamed p->offset to p->base lib/librte_eal/linuxapp/eal/eal_pci_vfio.c | 36 ++++++++++++++++++---------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c b/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c index 4832313..4d29a0d 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c @@ -74,6 +74,7 @@ EAL_REGISTER_TAILQ(rte_vfio_tailq) #define VFIO_GROUP_FMT "/dev/vfio/%u" #define VFIO_NOIOMMU_GROUP_FMT "/dev/vfio/noiommu-%u" #define VFIO_GET_REGION_ADDR(x) ((uint64_t) x << 40ULL) +#define VFIO_GET_REGION_IDX(x) (x >> 40) /* per-process VFIO config */ static struct vfio_config vfio_cfg; @@ -999,30 +1000,41 @@ int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar, struct rte_pci_ioport *p) { - RTE_SET_USED(dev); - RTE_SET_USED(bar); - RTE_SET_USED(p); - return -1; + if (bar < VFIO_PCI_BAR0_REGION_INDEX || + bar > VFIO_PCI_BAR5_REGION_INDEX) { + RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar); + return -1; + } + + p->dev = dev; + p->base = VFIO_GET_REGION_ADDR(bar); + return 0; } void pci_vfio_ioport_read(struct rte_pci_ioport *p, void *data, size_t len, off_t offset) { - RTE_SET_USED(p); - RTE_SET_USED(data); - RTE_SET_USED(len); - RTE_SET_USED(offset); + const struct rte_intr_handle *intr_handle = &p->dev->intr_handle; + + if (pread64(intr_handle->vfio_dev_fd, data, + len, p->base + offset) <= 0) + RTE_LOG(ERR, EAL, + "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n", + VFIO_GET_REGION_IDX(p->base), (int)offset); } void pci_vfio_ioport_write(struct rte_pci_ioport *p, const void *data, size_t len, off_t offset) { - RTE_SET_USED(p); - RTE_SET_USED(data); - RTE_SET_USED(len); - RTE_SET_USED(offset); + const struct rte_intr_handle *intr_handle = &p->dev->intr_handle; + + if (pwrite64(intr_handle->vfio_dev_fd, data, + len, p->base + offset) <= 0) + RTE_LOG(ERR, EAL, + "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n", + VFIO_GET_REGION_IDX(p->base), (int)offset); } int -- 1.7.9.5