From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-f46.google.com (mail-lf0-f46.google.com [209.85.215.46]) by dpdk.org (Postfix) with ESMTP id 48ED8AA3C for ; Tue, 1 Mar 2016 17:46:43 +0100 (CET) Received: by mail-lf0-f46.google.com with SMTP id v124so24250725lff.0 for ; Tue, 01 Mar 2016 08:46:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3n7AzZx+zxsTdwOaD3Bfugr30nQpa+iR89Z/WKg+IdI=; b=BQrNeAZioQio3xnBTAuJkTldygQtbX1S4/nJ38rZHSwD0TZBW7l5fr44M9JckbPzbY YFf2C4VyXRRRqGvetdBJyKhTlQ3Np2eVzd+BmFiojAw1GWJ7qXp0sMpm941lQDK/h9HC Ph219BPCiVQq2qKp2tlSHr41csbdRmvc0NydRMw7gFFBUaGt7Ro6386XG/55O9LEkgvb ik6Lpef+mldqLDX1nCQBO/MFHLo26jieIhQD7t+QaIstkjEepGlOXMvia6ehxiG22M5j 2hbnA79oUocg9EPIUP4B1L7dFJA/SbVEnbeDqhwm8/RjULCBJFPgryMaqLPjuDAy6zSh PSuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3n7AzZx+zxsTdwOaD3Bfugr30nQpa+iR89Z/WKg+IdI=; b=XQM7+tnfenntSmsAVx836F84Njb4QKcrdfS7cyUoeJDjLdybUTxNQspRlisDnFetTg Gy5SscW/LWRXz/pA1ai/0HJGY8qDCuTgtQ0Gqq21Cs1L3pV149B6wxn1uQ60WpkNUrMP bOlL2SIv8MiZ9L/Mct/AwAqKmF2f90n6Hdeo17OOSqKE6PvNu2Kqy1wOknXWngFJGqWA ao0gMVgzVRJB8YBfnR+eNUyG1fTQ4MGJDx1lABP9I3Uttuku2Mvo9+rkfIXu+VcCsPw9 zhYS7gLZScJG5VhJJeMGw+YjmoImLHMHbbURkTCStVEFCrxwKqB6FdeFjpUXrtd/oX8W dh8g== X-Gm-Message-State: AD7BkJKlgYLfJ0bVetQCWH0sxXXZlrKmLzx9nVVXamBsNOevgYCYFFB6iz/D5F2+3aUWZg== X-Received: by 10.25.90.21 with SMTP id o21mr6578982lfb.166.1456850803013; Tue, 01 Mar 2016 08:46:43 -0800 (PST) Received: from anpa-dpdk-2.lab.semihalf.com (cardhu.semihalf.com. [213.17.239.108]) by smtp.gmail.com with ESMTPSA id m8sm4994426lfe.32.2016.03.01.08.46.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 01 Mar 2016 08:46:42 -0800 (PST) From: Jan Medala To: dev@dpdk.org Date: Tue, 1 Mar 2016 17:46:40 +0100 Message-Id: <1456850801-3737-4-git-send-email-jan@semihalf.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456850801-3737-1-git-send-email-jan@semihalf.com> References: <1456850801-3737-1-git-send-email-jan@semihalf.com> Cc: Evgeny Schemeilin , matua@amazon.com Subject: [dpdk-dev] [PATCH v4 3/4] ena: Amazon ENA communication layer for DPDK platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Mar 2016 16:46:43 -0000 Implementation of platform specific code for ENA communication layer. Signed-off-by: Evgeny Schemeilin Signed-off-by: Jan Medala Signed-off-by: Jakub Palider --- drivers/net/ena/base/ena_plat_dpdk.h | 208 +++++++++++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) create mode 100644 drivers/net/ena/base/ena_plat_dpdk.h diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h new file mode 100644 index 0000000..2d245ab --- /dev/null +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -0,0 +1,208 @@ +/*- +* BSD LICENSE +* +* Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* * Neither the name of copyright holder nor the names of its +* contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_ +#define DPDK_ENA_COM_ENA_PLAT_DPDK_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef rte_atomic32_t ena_atomic32_t; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef uint64_t dma_addr_t; +typedef void *ena_mem_handle_t; + +#define SZ_4K 4096 + +#define ENA_COM_OK 0 +#define ENA_COM_NO_MEM -ENOMEM +#define ENA_COM_INVAL -EINVAL +#define ENA_COM_NO_SPACE -ENOSPC +#define ENA_COM_NO_DEVICE -ENODEV +#define ENA_COM_PERMISSION -EPERM +#define ENA_COM_TIMER_EXPIRED -ETIME +#define ENA_COM_FAULT -EFAULT + +#define ____cacheline_aligned __rte_cache_aligned + +#define ENA_ABORT() abort() + +#define ENA_MSLEEP(x) rte_delay_ms(x) +#define ENA_UDELAY(x) rte_delay_us(x) + +#define memcpy_toio memcpy +#define wmb rte_wmb +#define rmb rte_wmb +#define mb rte_mb + +#define US_PER_S 1000000 +#define ENA_GET_SYSTEM_USECS() \ + (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz()) + +#define ENA_ASSERT(cond, format, arg...) \ + do { \ + if (unlikely(!(cond))) { \ + printf("Assertion failed on %s:%s:%d:" format, \ + __FILE__, __func__, __LINE__, ##arg); \ + rte_exit(EXIT_FAILURE, "ASSERTION FAILED\n"); \ + } \ + } while (0) + +#define max_t(type, x, y) ({ \ + type __max1 = (x); \ + type __max2 = (y); \ + __max1 > __max2 ? __max1 : __max2; }) + +#define ENA_MAX32(x, y) max_t(u32, (x), (y)) +#define ENA_MAX16(x, y) max_t(u16, (x), (y)) +#define ENA_MAX8(x, y) max_t(u8, (x), (y)) + +#define U64_C(x) x ## ULL +#define BIT(nr) (1UL << (nr)) +#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) +#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#define GENMASK_ULL(h, l) (((U64_C(1) << ((h) - (l) + 1)) - 1) << (l)) + +#ifdef RTE_LIBRTE_ENA_COM_DEBUG +#define ena_trc_dbg(format, arg...) \ + RTE_LOG(DEBUG, PMD, "[ENA_COM: %s] " format, __func__, ##arg) +#define ena_trc_info(format, arg...) \ + RTE_LOG(INFO, PMD, "[ENA_COM: %s] " format, __func__, ##arg) +#define ena_trc_warn(format, arg...) \ + RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg) +#define ena_trc_err(format, arg...) \ + RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg) +#else +#define ena_trc_dbg(format, arg...) do { } while (0) +#define ena_trc_info(format, arg...) do { } while (0) +#define ena_trc_warn(format, arg...) do { } while (0) +#define ena_trc_err(format, arg...) do { } while (0) +#endif /* RTE_LIBRTE_ENA_COM_DEBUG */ + +/* Spinlock related methods */ +#define ena_spinlock_t rte_spinlock_t +#define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock) +#define ENA_SPINLOCK_LOCK(spinlock, flags) ({(void)flags; rte_spinlock_lock(&spinlock); }) +#define ENA_SPINLOCK_UNLOCK(spinlock, flags) ({(void)flags; rte_spinlock_unlock(&(spinlock)); }) + +typedef struct { + pthread_cond_t cond; + pthread_mutex_t mutex; +} q_waitqueue_t; + +#define ena_wait_queue_t q_waitqueue_t + +#define ENA_WAIT_EVENT_INIT(waitqueue) \ + do { \ + pthread_mutex_init(&(waitqueue).mutex, NULL); \ + pthread_cond_init(&(waitqueue).cond, NULL); \ + } while (0) + +#define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ + do { \ + struct timespec wait; \ + struct timeval now; \ + unsigned long timeout_us; \ + gettimeofday(&now, NULL); \ + wait.tv_sec = now.tv_sec + timeout / 1000000UL; \ + timeout_us = timeout % 1000000UL; \ + wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ + pthread_mutex_lock(&waitevent.mutex); \ + pthread_cond_timedwait(&waitevent.cond, &waitevent.mutex, &wait); \ + pthread_mutex_unlock(&waitevent.mutex); \ + } while (0) +#define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond) +/* pthread condition doesn't need to be rearmed after usage */ +#define ENA_WAIT_EVENT_CLEAR(...) + +#define ena_wait_event_t ena_wait_queue_t +#define ENA_MIGHT_SLEEP() + +#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ + do { \ + const struct rte_memzone *mz; \ + char z_name[RTE_MEMZONE_NAMESIZE]; \ + (void)dmadev; (void)handle; \ + snprintf(z_name, sizeof(z_name), "ena_alloc_%d", ena_alloc_cnt++); \ + mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, 0); \ + virt = mz->addr; \ + phys = mz->phys_addr; \ + } while (0) +#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \ + ({(void)size; rte_free(virt); }) +#define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1) +#define ENA_MEM_FREE(dmadev, ptr) ({(void)dmadev; rte_free(ptr); }) + +static inline void writel(u32 value, volatile void *addr) +{ + *(volatile u32 *)addr = value; +} + +static inline u32 readl(const volatile void *addr) +{ + return *(const volatile u32 *)addr; +} + +#define ENA_REG_WRITE32(value, reg) writel((value), (reg)) +#define ENA_REG_READ32(reg) readl((reg)) + +#define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr) +#define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr) +#define ATOMIC32_SET(i32_ptr, val) rte_atomic32_set(i32_ptr, val) +#define ATOMIC32_READ(i32_ptr) rte_atomic32_read(i32_ptr) + +#define msleep(x) rte_delay_us(x * 1000) +#define udelay(x) rte_delay_us(x) + +#define MAX_ERRNO 4095 +#define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO) +#define ERR_PTR(error) ((void *)(long)error) +#define PTR_ERR(error) ((long)(void *)error) +#define might_sleep() + +#endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ -- 1.9.1