From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f47.google.com (mail-wm0-f47.google.com [74.125.82.47]) by dpdk.org (Postfix) with ESMTP id 783E32C22 for ; Tue, 8 Mar 2016 19:40:13 +0100 (CET) Received: by mail-wm0-f47.google.com with SMTP id n186so145293764wmn.1 for ; Tue, 08 Mar 2016 10:40:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WAPTq4HF6t8l2qlcqpq4HzEbO5YtRLCWM6PytfkS+V4=; b=xFLA0aF3n+U62/2cBL0n4hYi/D48z/7dKyny0adMhqJR749EKbP2160KET/DHOXLua kmql5o2gqW6hwwwDY1Ob9BfyEXBtrvbhJKHk8HQzfR84Sa9db+F6lsY71Ju87Y8Fbi2H 0atLBPEPzinxkBdMgKrcykKP3Klh53sh28Labi4beQxzgO1O9a8IcVIq4139yYJASWQX Q8Vs9EwweKEkKc0YizukfCP4LDWxfpO7ICoYHry00hj6YN+4wXs0oUelzhMQ9oosZ4Ow +08Ctuo53DswSBpn2eAYma8iMHIRDlvWfHlGUbBstLOKFy7/KZodBkf8LCHUpuO2Wd3P FV7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WAPTq4HF6t8l2qlcqpq4HzEbO5YtRLCWM6PytfkS+V4=; b=jJw9M023VLbLzgIru9ukexeEMf4+p3bDDQQyKXAlzz/aoPmqaT5L7mU95hdhMUr9A2 gT8PebSn9M23mWRK7WdLQ/eeg8oE76v3b9jy6wojXwI8erzCR3eKGrQllayeLQegvdEk h0APsQPmnLVOqs7ps/lId74fzI3YALvMuJnvhlglb2Tpnk056yhLUVKKDZyp8NAdP49y J63CijcXjf+Y1gJfqy91DaIslaXnOI+ECnwBh9YZLy3P98MX4loiW/wHJeJt1QHTuFZS E6grOXcr6D1RgrIcoCIJ9EIdenznRQRLqACCRzcbJfn2Cb1+MWi7uyJia7ViZlQTVHwn a5AQ== X-Gm-Message-State: AD7BkJJkAQ0ZFZQHONbHmBlkG2XdHmWtxd7InrdJJCXEvetD8QgoBDS/NzTd+6SDOIVxDTqU X-Received: by 10.194.190.6 with SMTP id gm6mr31225678wjc.115.1457462413348; Tue, 08 Mar 2016 10:40:13 -0800 (PST) Received: from XPS13.localdomain (171.36.101.84.rev.sfr.net. [84.101.36.171]) by smtp.gmail.com with ESMTPSA id d2sm2955883wjf.28.2016.03.08.10.40.12 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 08 Mar 2016 10:40:12 -0800 (PST) From: Thomas Monjalon To: helin.zhang@intel.com Date: Tue, 8 Mar 2016 19:38:29 +0100 Message-Id: <1457462311-16349-2-git-send-email-thomas.monjalon@6wind.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1457462311-16349-1-git-send-email-thomas.monjalon@6wind.com> References: <1456113585-15259-1-git-send-email-helin.zhang@intel.com> <1457462311-16349-1-git-send-email-thomas.monjalon@6wind.com> Cc: dev@dpdk.org Subject: [dpdk-dev] [PATCH v3 1/3] i40e: enable extended tag X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Mar 2016 18:40:13 -0000 From: Helin Zhang PCIe feature of 'Extended Tag' is important for 40G performance. It adds its enabling during each port initialization, to ensure the high performance. Signed-off-by: Helin Zhang --- doc/guides/linux_gsg/enable_func.rst | 3 ++ doc/guides/rel_notes/release_16_04.rst | 6 ++++ drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++++++++++++++-- 3 files changed, 71 insertions(+), 3 deletions(-) diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst index c3fa6d3..8cb3d79 100644 --- a/doc/guides/linux_gsg/enable_func.rst +++ b/doc/guides/linux_gsg/enable_func.rst @@ -208,6 +208,9 @@ Enabling extended_tag and setting ``max_read_request_size`` to small size such a ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE`` +* From release 16.04, ``extended_tag`` is enabled by default during port + initialization, users don't need to care about that anymore. + Use 16 Bytes RX Descriptor Size ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst index 24f15bf..96f144e 100644 --- a/doc/guides/rel_notes/release_16_04.rst +++ b/doc/guides/rel_notes/release_16_04.rst @@ -57,6 +57,12 @@ This section should contain new features added in this release. Sample format: * **Added vhost-user live migration support.** +* **Enabled PCI extended tag for i40e.** + + It enabled extended tag by checking and writing corresponding PCI config + space bytes, to boost the performance. In the meanwhile, it deprecated the + legacy way via reading/writing sysfile supported by kernel module igb_uio. + Resolved Issues --------------- diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index ef24122..7e68c61 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -273,6 +273,17 @@ #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL +/* PCI offset for querying capability */ +#define PCI_DEV_CAP_REG 0xA4 +/* PCI offset for enabling/disabling Extended Tag */ +#define PCI_DEV_CTRL_REG 0xA8 +/* Bit mask of Extended Tag capability */ +#define PCI_DEV_CAP_EXT_TAG_MASK 0x20 +/* Bit shift of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8 +/* Bit mask of Extended Tag enable/disable */ +#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT) + static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev); static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev); static int i40e_dev_configure(struct rte_eth_dev *dev); @@ -386,7 +397,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev, static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info); static void i40e_configure_registers(struct i40e_hw *hw); -static void i40e_hw_init(struct i40e_hw *hw); +static void i40e_hw_init(struct rte_eth_dev *dev); static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi); static int i40e_mirror_rule_set(struct rte_eth_dev *dev, struct rte_eth_mirror_conf *mirror_conf, @@ -765,7 +776,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) i40e_clear_hw(hw); /* Initialize the hardware */ - i40e_hw_init(hw); + i40e_hw_init(dev); /* Reset here to make sure all is clean for each PF */ ret = i40e_pf_reset(hw); @@ -7262,13 +7273,61 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev, } /* + * Check and enable Extended Tag. + * Enabling Extended Tag is important for 40G performance. + */ +static void +i40e_enable_extended_tag(struct rte_eth_dev *dev) +{ + uint32_t buf = 0; + int ret; + + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CAP_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CAP_REG); + return; + } + if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) { + PMD_DRV_LOG(ERR, "Does not support Extended Tag"); + return; + } + + buf = 0; + ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } + if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) { + PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled"); + return; + } + buf |= PCI_DEV_CTRL_EXT_TAG_MASK; + ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf), + PCI_DEV_CTRL_REG); + if (ret < 0) { + PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x", + PCI_DEV_CTRL_REG); + return; + } +} + +/* * As some registers wouldn't be reset unless a global hardware reset, * hardware initialization is needed to put those registers into an * expected initial state. */ static void -i40e_hw_init(struct i40e_hw *hw) +i40e_hw_init(struct rte_eth_dev *dev) { + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + i40e_enable_extended_tag(dev); + /* clear the PF Queue Filter control register */ I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0); -- 2.7.0