From: Tomasz Kulasek <tomaszx.kulasek@intel.com>
To: dev@dpdk.org
Cc: helin.zhang@intel.com, konstantin.ananyev@intel.com
Subject: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_rx
Date: Fri, 15 Apr 2016 15:39:09 +0200 [thread overview]
Message-ID: <1460727549-4380-1-git-send-email-tomaszx.kulasek@intel.com> (raw)
CID 13193 (#1 of 1): Bad bit shift operation (BAD_SHIFT)
large_shift: In expression 1 << pool, left shifting by more than 31 bits
has undefined behavior. The shift amount, pool, is at least 32.
This patch limits mask shift to be in range of 32 bit PFVFRE[1] register,
for pool > 31.
Fixes: fe3a45fd4104 ("ixgbe: add VMDq support")
Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com>
---
drivers/net/ixgbe/ixgbe_ethdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 3f1ebc1..f676a64 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -4401,7 +4401,7 @@ ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
reg = IXGBE_READ_REG(hw, addr);
- val = bit1 << pool;
+ val = bit1 << (pool & 0x01F);
if (on)
reg |= val;
--
1.7.9.5
next reply other threads:[~2016-04-15 13:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-15 13:39 Tomasz Kulasek [this message]
2016-04-18 1:57 ` Lu, Wenzhuo
2016-04-21 13:51 ` Bruce Richardson
2016-04-21 14:44 ` Kulasek, TomaszX
2016-04-21 15:28 ` Bruce Richardson
2016-04-22 13:27 ` Kulasek, TomaszX
2016-04-22 15:35 ` [dpdk-dev] [PATCH v2] ixgbe: fix bad shift operation in ixgbe_set_pool_rx/tx Tomasz Kulasek
2016-04-25 10:35 ` Bruce Richardson
2016-04-25 10:38 ` Bruce Richardson
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